Merge tag 'amd-drm-next-6.11-2024-06-07' of https://gitlab.freedesktop.org/agd5f...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 42794b1bbe5ad4c2a3aa0b0f0a0e717aa338f85e..75ece8a2f96b65d6f63733651d44a091d36b24f7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -688,6 +688,30 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
                return "UMSCH_MM_CMD_BUFFER";
        case AMDGPU_UCODE_ID_JPEG_RAM:
                return "JPEG";
+       case AMDGPU_UCODE_ID_SDMA_RS64:
+               return "RS64_SDMA";
+       case AMDGPU_UCODE_ID_CP_RS64_PFP:
+               return "RS64_PFP";
+       case AMDGPU_UCODE_ID_CP_RS64_ME:
+               return "RS64_ME";
+       case AMDGPU_UCODE_ID_CP_RS64_MEC:
+               return "RS64_MEC";
+       case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
+               return "RS64_PFP_P0_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
+               return "RS64_PFP_P1_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
+               return "RS64_ME_P0_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
+               return "RS64_ME_P1_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
+               return "RS64_MEC_P0_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
+               return "RS64_MEC_P1_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
+               return "RS64_MEC_P2_STACK";
+       case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
+               return "RS64_MEC_P3_STACK";
        default:
                return "UNKNOWN UCODE";
        }
@@ -797,6 +821,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
        const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
        const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
+       const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL;
        const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
        const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
        const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;
@@ -818,6 +843,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
        mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
        sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
+       sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode->fw->data;
        imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
        vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
        umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode->fw->data;
@@ -834,6 +860,11 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                        ucode_addr = (u8 *)ucode->fw->data +
                                le32_to_cpu(sdma_hdr->ctl_ucode_offset);
                        break;
+               case AMDGPU_UCODE_ID_SDMA_RS64:
+                       ucode->ucode_size = le32_to_cpu(sdmav3_hdr->ucode_size_bytes);
+                       ucode_addr = (u8 *)ucode->fw->data +
+                               le32_to_cpu(sdmav3_hdr->header.ucode_array_offset_bytes);
+                       break;
                case AMDGPU_UCODE_ID_CP_MEC1:
                case AMDGPU_UCODE_ID_CP_MEC2:
                        ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -