#include <drm/drmP.h>
#include "amdgpu.h"
-static int amdgpu_sched_prepare_job(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity,
- struct amd_sched_job *job)
+static struct fence *amdgpu_sched_dependency(struct amd_sched_job *job)
{
- int r = 0;
- struct amdgpu_cs_parser *sched_job;
- if (!job || !job->data) {
- DRM_ERROR("job is null\n");
- return -EINVAL;
- }
-
- sched_job = (struct amdgpu_cs_parser *)job->data;
- if (sched_job->prepare_job) {
- r = sched_job->prepare_job(sched_job);
- if (r) {
- DRM_ERROR("Prepare job error\n");
- schedule_work(&sched_job->job_work);
- }
- }
- return r;
+ struct amdgpu_job *sched_job = (struct amdgpu_job *)job;
+ return amdgpu_sync_get_fence(&sched_job->ibs->sync);
}
-static struct fence *amdgpu_sched_run_job(struct amd_gpu_scheduler *sched,
- struct amd_sched_entity *entity,
- struct amd_sched_job *job)
+static struct fence *amdgpu_sched_run_job(struct amd_sched_job *job)
{
- int r = 0;
- struct amdgpu_cs_parser *sched_job;
+ struct amdgpu_job *sched_job;
struct amdgpu_fence *fence;
+ int r;
- if (!job || !job->data) {
+ if (!job) {
DRM_ERROR("job is null\n");
return NULL;
}
- sched_job = (struct amdgpu_cs_parser *)job->data;
+ sched_job = (struct amdgpu_job *)job;
mutex_lock(&sched_job->job_lock);
r = amdgpu_ib_schedule(sched_job->adev,
sched_job->num_ibs,
sched_job->ibs,
- sched_job->filp);
+ sched_job->base.owner);
if (r)
goto err;
fence = amdgpu_fence_ref(sched_job->ibs[sched_job->num_ibs - 1].fence);
- if (sched_job->run_job) {
- r = sched_job->run_job(sched_job);
- if (r)
- goto err;
- }
-
- amd_sched_emit(entity, sched_job->ibs[sched_job->num_ibs - 1].sequence);
+ if (sched_job->free_job)
+ sched_job->free_job(sched_job);
mutex_unlock(&sched_job->job_lock);
return &fence->base;
err:
DRM_ERROR("Run job error\n");
mutex_unlock(&sched_job->job_lock);
- schedule_work(&sched_job->job_work);
+ job->sched->ops->process_job(job);
return NULL;
}
-static void amdgpu_sched_process_job(struct amd_gpu_scheduler *sched,
- struct amd_sched_job *job)
+static void amdgpu_sched_process_job(struct amd_sched_job *job)
{
- struct amdgpu_cs_parser *sched_job;
+ struct amdgpu_job *sched_job;
- if (!job || !job->data) {
+ if (!job) {
DRM_ERROR("job is null\n");
return;
}
- sched_job = (struct amdgpu_cs_parser *)job->data;
- schedule_work(&sched_job->job_work);
+ sched_job = (struct amdgpu_job *)job;
+ /* after processing job, free memory */
+ fence_put(&sched_job->base.s_fence->base);
+ kfree(sched_job);
}
struct amd_sched_backend_ops amdgpu_sched_ops = {
- .prepare_job = amdgpu_sched_prepare_job,
+ .dependency = amdgpu_sched_dependency,
.run_job = amdgpu_sched_run_job,
.process_job = amdgpu_sched_process_job
};
struct amdgpu_ring *ring,
struct amdgpu_ib *ibs,
unsigned num_ibs,
- int (*free_job)(struct amdgpu_cs_parser *),
+ int (*free_job)(struct amdgpu_job *),
void *owner,
struct fence **f)
{
int r = 0;
if (amdgpu_enable_scheduler) {
- uint64_t v_seq;
- struct amdgpu_cs_parser *sched_job =
- amdgpu_cs_parser_create(adev, owner, &adev->kernel_ctx,
- ibs, 1);
- if(!sched_job) {
+ struct amdgpu_job *job =
+ kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
+ if (!job)
return -ENOMEM;
+ job->base.sched = ring->scheduler;
+ job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity;
+ job->adev = adev;
+ job->ibs = ibs;
+ job->num_ibs = num_ibs;
+ job->base.owner = owner;
+ mutex_init(&job->job_lock);
+ job->free_job = free_job;
+ mutex_lock(&job->job_lock);
+ r = amd_sched_entity_push_job((struct amd_sched_job *)job);
+ if (r) {
+ mutex_unlock(&job->job_lock);
+ kfree(job);
+ return r;
}
- sched_job->free_job = free_job;
- v_seq = atomic64_inc_return(&adev->kernel_ctx.rings[ring->idx].entity.last_queued_v_seq);
- ibs[num_ibs - 1].sequence = v_seq;
- amd_sched_push_job(ring->scheduler,
- &adev->kernel_ctx.rings[ring->idx].entity,
- sched_job);
- r = amd_sched_wait_emit(
- &adev->kernel_ctx.rings[ring->idx].entity,
- v_seq,
- false,
- -1);
+ *f = fence_get(&job->base.s_fence->base);
+ mutex_unlock(&job->job_lock);
+ } else {
+ r = amdgpu_ib_schedule(adev, num_ibs, ibs, owner);
if (r)
- WARN(true, "emit timeout\n");
- } else
- r = amdgpu_ib_schedule(adev, 1, ibs, owner);
- if (r)
- return r;
- *f = &ibs[num_ibs - 1].fence->base;
+ return r;
+ *f = fence_get(&ibs[num_ibs - 1].fence->base);
+ }
+
return 0;
}