Merge drm/drm-next into drm-intel-next

[linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e915ec034c987105dc7696e672f8552fc2409077..65c155b141899b711f715046ca9bdfeb60ade1d7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4590,19 +4590,22 @@ enum {
 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2       (0 << 28)
 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3       (1 << 28)
 #define   EDP_Y_COORDINATE_ENABLE              REG_BIT(25) /* display 10, 11 and 12 */
+#define   EDP_PSR2_SU_SDP_SCANLINE             REG_BIT(25) /* display 13+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)           ((t) << 20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK         (0x1f << 20)
 #define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES    8
 #define   EDP_PSR2_IO_BUFFER_WAKE(lines)       ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
 #define   EDP_PSR2_IO_BUFFER_WAKE_MASK         (3 << 13)
 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES        5
-#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)   (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT    13
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)   (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)
 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK     (7 << 13)
 #define   EDP_PSR2_FAST_WAKE_MAX_LINES         8
 #define   EDP_PSR2_FAST_WAKE(lines)            ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
 #define   EDP_PSR2_FAST_WAKE_MASK              (3 << 11)
 #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES     5
-#define   TGL_EDP_PSR2_FAST_WAKE(lines)                (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
+#define   TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT     10
+#define   TGL_EDP_PSR2_FAST_WAKE(lines)                (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)
 #define   TGL_EDP_PSR2_FAST_WAKE_MASK          (7 << 10)
 #define   EDP_PSR2_TP2_TIME_500us              (0 << 8)
 #define   EDP_PSR2_TP2_TIME_100us              (1 << 8)
@@ -7751,7 +7754,7 @@ enum {
 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
 
 /* DMC */
-#define DMC_PROGRAM(i)         _MMIO(0x80000 + (i) * 4)
+#define DMC_PROGRAM(addr, i)   _MMIO((addr) + (i) * 4)
 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
 #define DMC_HTP_ADDR_SKL       0x00500034
 #define DMC_SSP_BASE           _MMIO(0x8F074)
@@ -8107,6 +8110,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE                (1 << 2)
 
 #define CHICKEN_PAR1_1                 _MMIO(0x42080)
+#define  IGNORE_KVMR_PIPE_A            REG_BIT(23)
 #define  KBL_ARB_FILL_SPARE_22         REG_BIT(22)
 #define  DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
 #define  SKL_DE_COMPRESSED_HASH_MODE   (1 << 15)
@@ -10365,6 +10369,14 @@ enum skl_power_gate {
 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
 /* See DP_MSA_MISC_* for the bit definitions */
 
+#define _TRANS_A_SET_CONTEXT_LATENCY           0x6007C
+#define _TRANS_B_SET_CONTEXT_LATENCY           0x6107C
+#define _TRANS_C_SET_CONTEXT_LATENCY           0x6207C
+#define _TRANS_D_SET_CONTEXT_LATENCY           0x6307C
+#define TRANS_SET_CONTEXT_LATENCY(tran)                _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
+#define  TRANS_SET_CONTEXT_LATENCY_MASK                REG_GENMASK(15, 0)
+#define  TRANS_SET_CONTEXT_LATENCY_VALUE(x)    REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
+
 /* LCPLL Control */
 #define LCPLL_CTL                      _MMIO(0x130040)
 #define  LCPLL_PLL_DISABLE             (1 << 31)