Merge tag 'acpi-part2-4.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux.git] / drivers / gpu / drm / amd / amdgpu / cik.c

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a296f7bbe57cbb0c768499a6c254e433d931773a..8e59e65efd448891fc9d84a7db6e1669c2b892eb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_BONAIRE:
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_golden_registers,
-                                                (const u32)ARRAY_SIZE(bonaire_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_golden_registers,
+                                                       ARRAY_SIZE(bonaire_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_golden_common_registers,
+                                                       ARRAY_SIZE(bonaire_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_golden_spm_registers,
+                                                       ARRAY_SIZE(bonaire_golden_spm_registers));
                break;
        case CHIP_KABINI:
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_registers,
+                                                       ARRAY_SIZE(kalindi_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_common_registers,
+                                                       ARRAY_SIZE(kalindi_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_spm_registers,
+                                                       ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
        case CHIP_MULLINS:
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                godavari_golden_registers,
-                                                (const u32)ARRAY_SIZE(godavari_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       godavari_golden_registers,
+                                                       ARRAY_SIZE(godavari_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_common_registers,
+                                                       ARRAY_SIZE(kalindi_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_spm_registers,
+                                                       ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
        case CHIP_KAVERI:
-               amdgpu_program_register_sequence(adev,
-                                                spectre_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                spectre_golden_registers,
-                                                (const u32)ARRAY_SIZE(spectre_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                spectre_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(spectre_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                spectre_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(spectre_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_golden_registers,
+                                                       ARRAY_SIZE(spectre_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_golden_common_registers,
+                                                       ARRAY_SIZE(spectre_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_golden_spm_registers,
+                                                       ARRAY_SIZE(spectre_golden_spm_registers));
                break;
        case CHIP_HAWAII:
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_mgcg_cgcg_init,
-                                                (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_golden_registers,
-                                                (const u32)ARRAY_SIZE(hawaii_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_golden_common_registers,
-                                                (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_golden_spm_registers,
-                                                (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(hawaii_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_golden_registers,
+                                                       ARRAY_SIZE(hawaii_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_golden_common_registers,
+                                                       ARRAY_SIZE(hawaii_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_golden_spm_registers,
+                                                       ARRAY_SIZE(hawaii_golden_spm_registers));
                break;
        default:
                break;
@@ -1246,7 +1246,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
        /* disable BM */
        pci_clear_master(adev->pdev);
        /* reset */
-       amdgpu_pci_config_reset(adev);
+       amdgpu_device_pci_config_reset(adev);
 
        udelay(100);
 
@@ -1866,7 +1866,7 @@ static int cik_common_early_init(void *handle)
 
        adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 
-       amdgpu_get_pcie_info(adev);
+       amdgpu_device_get_pcie_info(adev);
 
        return 0;
 }
@@ -1974,77 +1974,77 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_BONAIRE:
-               amdgpu_ip_block_add(adev, &cik_common_ip_block);
-               amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
-               amdgpu_ip_block_add(adev, &cik_ih_ip_block);
-               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+               amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+               amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display)
-                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
-                       amdgpu_ip_block_add(adev, &dm_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dm_ip_block);
 #endif
                else
-                       amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
-               amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
-               amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
-               amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
-               amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+               amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
                break;
        case CHIP_HAWAII:
-               amdgpu_ip_block_add(adev, &cik_common_ip_block);
-               amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
-               amdgpu_ip_block_add(adev, &cik_ih_ip_block);
-               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+               amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+               amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display)
-                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
-                       amdgpu_ip_block_add(adev, &dm_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dm_ip_block);
 #endif
                else
-                       amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
-               amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
-               amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
-               amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
-               amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
+               amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+               amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
                break;
        case CHIP_KAVERI:
-               amdgpu_ip_block_add(adev, &cik_common_ip_block);
-               amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
-               amdgpu_ip_block_add(adev, &cik_ih_ip_block);
-               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+               amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+               amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display)
-                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
-                       amdgpu_ip_block_add(adev, &dm_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dm_ip_block);
 #endif
                else
-                       amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
-               amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
-               amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
-               amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
-               amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
+               amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+               amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
                break;
        case CHIP_KABINI:
        case CHIP_MULLINS:
-               amdgpu_ip_block_add(adev, &cik_common_ip_block);
-               amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
-               amdgpu_ip_block_add(adev, &cik_ih_ip_block);
-               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
+               amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
+               amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
                if (adev->enable_virtual_display)
-                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
-                       amdgpu_ip_block_add(adev, &dm_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dm_ip_block);
 #endif
                else
-                       amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
-               amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
-               amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
-               amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
-               amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
+                       amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
+               amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
+               amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+               amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
                break;
        default:
                /* FIXME: not supported yet */