Merge tag 'drm-misc-next-2021-04-01' of git://anongit.freedesktop.org/drm/drm-misc...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_device.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c3552079bb8621e3628c4a219b28494aec562d75..0f82c5d212372354a2de059509f478e67c7c3fd7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -465,49 +465,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
        }
 }
 
-/**
- * amdgpu_io_rreg - read an IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- *
- * Returns the 32 bit value from the offset specified.
- */
-u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
-{
-       if (adev->in_pci_err_recovery)
-               return 0;
-
-       if ((reg * 4) < adev->rio_mem_size)
-               return ioread32(adev->rio_mem + (reg * 4));
-       else {
-               iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
-               return ioread32(adev->rio_mem + (mmMM_DATA * 4));
-       }
-}
-
-/**
- * amdgpu_io_wreg - write to an IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- * @v: 32 bit value to write to the register
- *
- * Writes the value specified to the offset specified.
- */
-void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
-{
-       if (adev->in_pci_err_recovery)
-               return;
-
-       if ((reg * 4) < adev->rio_mem_size)
-               iowrite32(v, adev->rio_mem + (reg * 4));
-       else {
-               iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
-               iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
-       }
-}
-
 /**
  * amdgpu_mm_rdoorbell - read a doorbell dword
  *
@@ -2513,6 +2470,11 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
        if (r)
                DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
 
+       /* For XGMI + passthrough configuration on arcturus, enable light SBR */
+       if (adev->asic_type == CHIP_ARCTURUS &&
+           amdgpu_passthrough(adev) &&
+           adev->gmc.xgmi.num_physical_nodes > 1)
+               smu_set_light_sbr(&adev->smu, true);
 
        if (adev->gmc.xgmi.num_physical_nodes > 1) {
                mutex_lock(&mgpu_info.mutex);
@@ -2778,7 +2740,6 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
                                }
                        }
                }
-               adev->ip_blocks[i].status.hw = false;
        }
 
        return 0;
@@ -3284,7 +3245,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
        /* mutex initialization are all done here so we
         * can recall function without having locking issues */
-       atomic_set(&adev->irq.ih.lock, 0);
        mutex_init(&adev->firmware.mutex);
        mutex_init(&adev->pm.mutex);
        mutex_init(&adev->gfx.gpu_clock_mutex);
@@ -3357,17 +3317,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
        DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
 
-       /* io port mapping */
-       for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-               if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
-                       adev->rio_mem_size = pci_resource_len(adev->pdev, i);
-                       adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
-                       break;
-               }
-       }
-       if (adev->rio_mem == NULL)
-               DRM_INFO("PCI I/O BAR is not found.\n");
-
        /* enable PCIE atomic ops */
        r = pci_enable_atomic_ops_to_root(adev->pdev,
                                          PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
@@ -3521,11 +3470,11 @@ fence_driver_init:
                        adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
                        adev->virt.ops = NULL;
                        r = -EAGAIN;
-                       goto failed;
+                       goto release_ras_con;
                }
                dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
                amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
-               goto failed;
+               goto release_ras_con;
        }
 
        dev_info(adev->dev,
@@ -3591,7 +3540,7 @@ fence_driver_init:
                if (r) {
                        dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
                        amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
-                       goto failed;
+                       goto release_ras_con;
                }
                /* must succeed. */
                amdgpu_ras_resume(adev);
@@ -3615,16 +3564,15 @@ fence_driver_init:
        if (amdgpu_device_cache_pci_state(adev->pdev))
                pci_restore_state(pdev);
 
-       /* Enable lightSBR on SMU in passthrough + xgmi configuration */
-       if (amdgpu_passthrough(adev) && adev->gmc.xgmi.num_physical_nodes > 1)
-               smu_set_light_sbr(&adev->smu, true);
-
        if (adev->gmc.xgmi.pending_reset)
                queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
                                   msecs_to_jiffies(AMDGPU_RESUME_MS));
 
        return 0;
 
+release_ras_con:
+       amdgpu_release_ras_context(adev);
+
 failed:
        amdgpu_vf_error_trans_all(adev);
        if (atpx)
@@ -3696,9 +3644,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
                vga_switcheroo_fini_domain_pm_ops(adev->dev);
        if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
                vga_client_register(adev->pdev, NULL, NULL, NULL);
-       if (adev->rio_mem)
-               pci_iounmap(adev->pdev, adev->rio_mem);
-       adev->rio_mem = NULL;
        iounmap(adev->rmmio);
        adev->rmmio = NULL;
        amdgpu_device_doorbell_fini(adev);