case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
- if (load_type != AMDGPU_FW_LOAD_SMU)
- pr_warning("%d is not supported on VI\n", load_type);
return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10:
case CHIP_RAVEN:
uint64_t fw_offset = 0;
int i;
struct amdgpu_firmware_info *ucode = NULL;
- const struct common_firmware_header *header = NULL;
/* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
for (i = 0; i < adev->firmware.max_ucodes; i++) {
ucode = &adev->firmware.ucode[i];
if (ucode->fw) {
- header = (const struct common_firmware_header *)ucode->fw->data;
amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
adev->firmware.fw_buf_ptr + fw_offset);
if (i == AMDGPU_UCODE_ID_CP_MEC1 &&