Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index f2da69adcd9d484388853109ae76de7bdd0dde3d..4769a18304d7a4435403ffce859902b25e70f816 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -171,8 +171,7 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre
 
        memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
        err_data.err_addr = &err_rec;
-       amdgpu_umc_fill_error_record(&err_data, address,
-                       (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
+       amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 
        if (amdgpu_bad_page_threshold != 0) {
                amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
@@ -356,8 +355,12 @@ static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
        case AMDGPU_RAS_BLOCK__SDMA:
                mask = GENMASK(adev->sdma.num_instances - 1, 0);
                break;
+       case AMDGPU_RAS_BLOCK__VCN:
+       case AMDGPU_RAS_BLOCK__JPEG:
+               mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
+               break;
        default:
-               mask = 0;
+               mask = inst_mask;
                break;
        }
 
@@ -486,7 +489,8 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
                ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
                break;
        case 2:
-               if ((data.inject.address >= adev->gmc.mc_vram_size) ||
+               if ((data.inject.address >= adev->gmc.mc_vram_size &&
+                   adev->gmc.mc_vram_size) ||
                    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
                        dev_warn(adev->dev, "RAS WARN: input address "
                                        "0x%llx is invalid.",
@@ -1487,6 +1491,7 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
 {
        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+       struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
        struct drm_minor  *minor = adev_to_drm(adev)->primary;
        struct dentry     *dir;
 
@@ -1497,6 +1502,7 @@ static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *
                            &amdgpu_ras_debugfs_eeprom_ops);
        debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
                           &con->bad_page_cnt_threshold);
+       debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
        debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
        debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
        debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
@@ -1681,8 +1687,7 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
                }
        }
 
-       if (!adev->gmc.xgmi.connected_to_cpu)
-               amdgpu_umc_poison_handler(adev, false);
+       amdgpu_umc_poison_handler(adev, false);
 
        if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
                poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
@@ -2310,7 +2315,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
        atomic_set(&con->in_recovery, 0);
        con->eeprom_control.bad_channel_bitmap = 0;
 
-       max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
+       max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
        amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
 
        /* Todo: During test the SMU might fail to read the eeprom through I2C
@@ -2447,11 +2452,10 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
 {
        adev->ras_hw_enabled = adev->ras_enabled = 0;
 
-       if (!adev->is_atom_fw ||
-           !amdgpu_ras_asic_supported(adev))
+       if (!amdgpu_ras_asic_supported(adev))
                return;
 
-       if (!adev->gmc.xgmi.connected_to_cpu) {
+       if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
                if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
                        dev_info(adev->dev, "MEM ECC is active.\n");
                        adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |