Merge tag 'mmc-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 59cc678de8c1570642afc2d488f63fbc179a1e99..1f61ed95727ce3083faa9036c0d05f2d16641a5c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -33,6 +33,8 @@
 #include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
 #include <linux/nospec.h>
+#include "hwmgr.h"
+#define WIDTH_4K 3840
 
 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
 
@@ -1642,6 +1644,19 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
            attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
                return 0;
 
+       /* Skip fan attributes on APU */
+       if ((adev->flags & AMD_IS_APU) &&
+           (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
+            attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
+            attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
+            attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
+            attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
+            attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
+            attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
+            attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
+            attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
+               return 0;
+
        /* Skip limit attributes if DPM is not enabled */
        if (!adev->pm.dpm_enabled &&
            (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
@@ -1956,6 +1971,17 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
                mutex_unlock(&adev->pm.mutex);
        }
+       /* enable/disable Low Memory PState for UVD (4k videos) */
+       if (adev->asic_type == CHIP_STONEY &&
+               adev->uvd.decode_image_width >= WIDTH_4K) {
+               struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+
+               if (hwmgr && hwmgr->hwmgr_func &&
+                   hwmgr->hwmgr_func->update_nbdpm_pstate)
+                       hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
+                                                              !enable,
+                                                              true);
+       }
 }
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
@@ -2129,7 +2155,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
 
        for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
                struct amdgpu_ring *ring = adev->rings[i];
-               if (ring && ring->ready)
+               if (ring && ring->sched.ready)
                        amdgpu_fence_wait_empty(ring);
        }