return -EINVAL;
}
flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
- if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
- size = size << AMDGPU_GDS_SHIFT;
- else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
- size = size << AMDGPU_GWS_SHIFT;
- else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
- size = size << AMDGPU_OA_SHIFT;
- else
- return -EINVAL;
+ /* GDS allocations must be DW aligned */
+ if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
+ size = ALIGN(size, 4);
}
- size = roundup(size, PAGE_SIZE);
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
r = amdgpu_bo_reserve(vm->root.base.bo, false);
return -EINVAL;
}
- if (args->va_address >= AMDGPU_VA_HOLE_START &&
- args->va_address < AMDGPU_VA_HOLE_END) {
+ if (args->va_address >= AMDGPU_GMC_HOLE_START &&
+ args->va_address < AMDGPU_GMC_HOLE_END) {
dev_dbg(&dev->pdev->dev,
"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
- args->va_address, AMDGPU_VA_HOLE_START,
- AMDGPU_VA_HOLE_END);
+ args->va_address, AMDGPU_GMC_HOLE_START,
+ AMDGPU_GMC_HOLE_END);
return -EINVAL;
}
- args->va_address &= AMDGPU_VA_HOLE_MASK;
+ args->va_address &= AMDGPU_GMC_HOLE_MASK;
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",