Merge tag 'regulator-fix-v4.16-suspend' of git://git.kernel.org/pub/scm/linux/kernel...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_virt.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 6738df836a70eb45c3643593c3c03dc700ed67f1..e7dfb7b44b4b42e9ae6f5a82bbdb72850badd03a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -24,6 +24,14 @@
 #include "amdgpu.h"
 #define MAX_KIQ_REG_WAIT       100000000 /* in usecs */
 
 #include "amdgpu.h"
 #define MAX_KIQ_REG_WAIT       100000000 /* in usecs */
 

+bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
+{
+       /* By now all MMIO pages except mailbox are blocked */
+       /* if blocking is enabled in hypervisor. Choose the */
+       /* SCRATCH_REG0 to test. */
+       return RREG32_NO_KIQ(0xc040) == 0xffffffff;
+}
+

 int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
 {
        int r;
 int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
 {
        int r;


@@ -39,6 +47,12 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
        return 0;
 }
 
        return 0;
 }
 

+void amdgpu_free_static_csa(struct amdgpu_device *adev) {
+       amdgpu_bo_free_kernel(&adev->virt.csa_obj,
+                                               &adev->virt.csa_vmid0_addr,
+                                               NULL);
+}
+

 /*
  * amdgpu_map_static_csa should be called during amdgpu_vm_init
  * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
 /*
  * amdgpu_map_static_csa should be called during amdgpu_vm_init
  * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"


@@ -107,8 +121,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
        adev->enable_virtual_display = true;
        adev->cg_flags = 0;
        adev->pg_flags = 0;
        adev->enable_virtual_display = true;
        adev->cg_flags = 0;
        adev->pg_flags = 0;

-
-       mutex_init(&adev->virt.lock_reset);

 }
 
 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 }
 
 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)


@@ -227,6 +239,22 @@ int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
        return 0;
 }
 
        return 0;
 }
 

+/**
+ * amdgpu_virt_wait_reset() - wait for reset gpu completed
+ * @amdgpu:    amdgpu device.
+ * Wait for GPU reset completed.
+ * Return: Zero if reset success, otherwise will return error.
+ */
+int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
+{
+       struct amdgpu_virt *virt = &adev->virt;
+
+       if (!virt->ops || !virt->ops->wait_reset)
+               return -EINVAL;
+
+       return virt->ops->wait_reset(adev);
+}
+

 /**
  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
  * @amdgpu:    amdgpu device.
 /**
  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
  * @amdgpu:    amdgpu device.


@@ -296,7 +324,6 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj,
 
 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 {
 
 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 {

-       uint32_t pf2vf_ver = 0;

        uint32_t pf2vf_size = 0;
        uint32_t checksum = 0;
        uint32_t checkval;
        uint32_t pf2vf_size = 0;
        uint32_t checksum = 0;
        uint32_t checkval;


@@ -309,9 +336,9 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
                adev->virt.fw_reserve.p_pf2vf =
                        (struct amdgim_pf2vf_info_header *)(
                        adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
                adev->virt.fw_reserve.p_pf2vf =
                        (struct amdgim_pf2vf_info_header *)(
                        adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);

-               pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version;

                AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
                AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
                AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
                AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);

+               AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);

 
                /* pf2vf message must be in 4K */
                if (pf2vf_size > 0 && pf2vf_size < 4096) {
 
                /* pf2vf message must be in 4K */
                if (pf2vf_size > 0 && pf2vf_size < 4096) {