]> Git Repo - linux.git/blobdiff - drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm...
[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_fence.c
index 2fa95aef74d5200449c94a0215f04be60e8cb184..008e1984b7e39b9d51a9021c0df5762d889d6506 100644 (file)
@@ -187,7 +187,7 @@ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
 
        seq = ++ring->fence_drv.sync_seq;
        amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
-                              seq, AMDGPU_FENCE_FLAG_INT);
+                              seq, 0);
 
        *s = seq;
 
@@ -391,9 +391,9 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
        ring->fence_drv.irq_type = irq_type;
        ring->fence_drv.initialized = true;
 
-       dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
-                "cpu addr 0x%p\n", ring->idx,
-                ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
+       dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
+               "cpu addr 0x%p\n", ring->idx,
+               ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
        return 0;
 }
 
@@ -410,7 +410,6 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
                                  unsigned num_hw_submission)
 {
-       long timeout;
        int r;
 
        /* Check that num_hw_submission is a power of two */
@@ -434,20 +433,9 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 
        /* No need to setup the GPU scheduler for KIQ ring */
        if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
-               timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
-               if (timeout == 0) {
-                       /*
-                        * FIXME:
-                        * Delayed workqueue cannot use it directly,
-                        * so the scheduler will not use delayed workqueue if
-                        * MAX_SCHEDULE_TIMEOUT is set.
-                        * Currently keep it simple and silly.
-                        */
-                       timeout = MAX_SCHEDULE_TIMEOUT;
-               }
-               r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
-                                  num_hw_submission,
-                                  timeout, ring->name);
+               r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
+                                  num_hw_submission, amdgpu_job_hang_limit,
+                                  msecs_to_jiffies(amdgpu_lockup_timeout), ring->name);
                if (r) {
                        DRM_ERROR("Failed to create scheduler on ring %s.\n",
                                  ring->name);
@@ -499,11 +487,11 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
                r = amdgpu_fence_wait_empty(ring);
                if (r) {
                        /* no need to trigger GPU reset as we are unloading */
-                       amdgpu_fence_driver_force_completion(adev);
+                       amdgpu_fence_driver_force_completion(ring);
                }
                amdgpu_irq_put(adev, ring->fence_drv.irq_src,
                               ring->fence_drv.irq_type);
-               amd_sched_fini(&ring->sched);
+               drm_sched_fini(&ring->sched);
                del_timer_sync(&ring->fence_drv.fallback_timer);
                for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
                        dma_fence_put(ring->fence_drv.fences[j]);
@@ -534,7 +522,7 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
                r = amdgpu_fence_wait_empty(ring);
                if (r) {
                        /* delay GPU reset to resume */
-                       amdgpu_fence_driver_force_completion(adev);
+                       amdgpu_fence_driver_force_completion(ring);
                }
 
                /* disable the interrupt */
@@ -571,30 +559,15 @@ void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_fence_driver_force_completion - force all fence waiter to complete
+ * amdgpu_fence_driver_force_completion - force signal latest fence of ring
  *
- * @adev: amdgpu device pointer
+ * @ring: fence of the ring to signal
  *
- * In case of GPU reset failure make sure no process keep waiting on fence
- * that will never complete.
  */
-void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
+void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 {
-       int i;
-
-       for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
-               struct amdgpu_ring *ring = adev->rings[i];
-               if (!ring || !ring->fence_drv.initialized)
-                       continue;
-
-               amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
-       }
-}
-
-void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring)
-{
-       if (ring)
-               amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
+       amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
+       amdgpu_fence_process(ring);
 }
 
 /*
@@ -709,25 +682,25 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
 }
 
 /**
- * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
+ * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
  *
  * Manually trigger a gpu reset at the next fence wait.
  */
-static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
+static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
 {
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        struct amdgpu_device *adev = dev->dev_private;
 
-       seq_printf(m, "gpu reset\n");
-       amdgpu_gpu_reset(adev);
+       seq_printf(m, "gpu recover\n");
+       amdgpu_device_gpu_recover(adev, NULL, true);
 
        return 0;
 }
 
 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
        {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
-       {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
+       {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
 };
 
 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
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