Merge tag 'ceph-for-5.11-rc1' of git://github.com/ceph/ceph-client

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_device.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 026789b466db9a83aed5be61f1e018a8edf7f9c4..79dd85f71fabc6d0604e5e5d7808a99f1372d120 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,6 +80,7 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS               2000
@@ -115,6 +116,8 @@ const char *amdgpu_asic_name[] = {
        "NAVI12",
        "SIENNA_CICHLID",
        "NAVY_FLOUNDER",
+       "VANGOGH",
+       "DIMGREY_CAVEFISH",
        "LAST",
 };
 
@@ -582,6 +585,7 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
  * @adev: amdgpu_device pointer
  * @pcie_index: mmio register offset
  * @pcie_data: mmio register offset
+ * @reg_addr: indirect register address to read from
  *
  * Returns the value of indirect register @reg_addr
  */
@@ -612,6 +616,7 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
  * @adev: amdgpu_device pointer
  * @pcie_index: mmio register offset
  * @pcie_data: mmio register offset
+ * @reg_addr: indirect register address to read from
  *
  * Returns the value of indirect register @reg_addr
  */
@@ -1373,13 +1378,6 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
 
        amdgpu_gmc_tmz_set(adev);
 
-       if (amdgpu_num_kcq == -1) {
-               amdgpu_num_kcq = 8;
-       } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
-               amdgpu_num_kcq = 8;
-               dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
-       }
-
        amdgpu_gmc_noretry_set(adev);
 
        return 0;
@@ -1786,6 +1784,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
        case CHIP_VEGA20:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
        default:
                return 0;
        case CHIP_VEGA10:
@@ -1820,6 +1819,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
        case CHIP_NAVI12:
                chip_name = "navi12";
                break;
+       case CHIP_VANGOGH:
+               chip_name = "vangogh";
+               break;
        }
 
        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -1994,7 +1996,12 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
        case  CHIP_NAVI12:
        case  CHIP_SIENNA_CICHLID:
        case  CHIP_NAVY_FLOUNDER:
-               adev->family = AMDGPU_FAMILY_NV;
+       case  CHIP_DIMGREY_CAVEFISH:
+       case CHIP_VANGOGH:
+               if (adev->asic_type == CHIP_VANGOGH)
+                       adev->family = AMDGPU_FAMILY_VGH;
+               else
+                       adev->family = AMDGPU_FAMILY_NV;
 
                r = nv_set_ip_blocks(adev);
                if (r)
@@ -2643,8 +2650,10 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
 {
        int i, r;
 
-       amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
-       amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+       if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) {
+               amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
+               amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+       }
 
        for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
                if (!adev->ip_blocks[i].status.valid)
@@ -2999,10 +3008,10 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
        case CHIP_NAVI14:
        case CHIP_NAVI12:
        case CHIP_RENOIR:
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_DIMGREY_CAVEFISH:
+       case CHIP_VANGOGH:
 #endif
                return amdgpu_dc != 0;
 #endif
@@ -3337,7 +3346,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
        /* this will fail for cards that aren't VGA class devices, just
         * ignore it */
-       vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
+       if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
+               vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
 
        if (amdgpu_device_supports_boco(ddev))
                boco = true;
@@ -3596,7 +3606,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
                vga_switcheroo_unregister_client(adev->pdev);
        if (amdgpu_device_supports_boco(adev_to_drm(adev)))
                vga_switcheroo_fini_domain_pm_ops(adev->dev);
-       vga_client_register(adev->pdev, NULL, NULL, NULL);
+       if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
+               vga_client_register(adev->pdev, NULL, NULL, NULL);
        if (adev->rio_mem)
                pci_iounmap(adev->pdev, adev->rio_mem);
        adev->rio_mem = NULL;
@@ -3699,8 +3710,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
        amdgpu_fence_driver_suspend(adev);
 
-       r = amdgpu_device_ip_suspend_phase2(adev);
-
+       if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev))
+               r = amdgpu_device_ip_suspend_phase2(adev);
+       else
+               amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
        /* evict remaining vram memory
         * This second call to evict vram is to evict the gart page table
         * using the CPU.
@@ -3731,6 +3744,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
        if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
                return 0;
 
+       if (amdgpu_acpi_is_s0ix_supported())
+               amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
+
        /* post card */
        if (amdgpu_device_need_post(adev)) {
                r = amdgpu_device_asic_init(adev);