ASoC: simple-card: Use snd_soc_of_parse_aux_devs()

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 50fe08bf2f727656d8680fa998795d490d6df218..bcce4c0be4623fd0b758c1078fe0b90a832f2deb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -86,7 +86,7 @@ void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
                amdgpu_ras_get_context(adev)->error_query_ready = ready;
 }
 
                amdgpu_ras_get_context(adev)->error_query_ready = ready;
 }
 

-bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
+static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)

 {
        if (adev && amdgpu_ras_get_context(adev))
                return amdgpu_ras_get_context(adev)->error_query_ready;
 {
        if (adev && amdgpu_ras_get_context(adev))
                return amdgpu_ras_get_context(adev)->error_query_ready;


@@ -318,6 +318,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
        case 2:
                if ((data.inject.address >= adev->gmc.mc_vram_size) ||
                    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
        case 2:
                if ((data.inject.address >= adev->gmc.mc_vram_size) ||
                    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {

+                       dev_warn(adev->dev, "RAS WARN: input address "
+                                       "0x%llx is invalid.",
+                                       data.inject.address);

                        ret = -EINVAL;
                        break;
                }
                        ret = -EINVAL;
                        break;
                }


@@ -502,7 +505,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 }
 /* obj end */
 
 }
 /* obj end */
 

-void amdgpu_ras_parse_status_code(struct amdgpu_device* adev,
+static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,

                                  const char*           invoke_type,
                                  const char*           block_name,
                                  enum ta_ras_status    ret)
                                  const char*           invoke_type,
                                  const char*           block_name,
                                  enum ta_ras_status    ret)


@@ -812,7 +815,7 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
 }
 
 /* Trigger XGMI/WAFL error */
 }
 
 /* Trigger XGMI/WAFL error */

-int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
+static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,

                                 struct ta_ras_trigger_error_input *block_info)
 {
        int ret;
                                 struct ta_ras_trigger_error_input *block_info)
 {
        int ret;


@@ -1615,7 +1618,7 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
        data = con->eh_data;
        save_count = data->count - control->num_recs;
        /* only new entries are saved */
        data = con->eh_data;
        save_count = data->count - control->num_recs;
        /* only new entries are saved */

-       if (save_count > 0)
+       if (save_count > 0) {

                if (amdgpu_ras_eeprom_process_recods(control,
                                                        &data->bps[control->num_recs],
                                                        true,
                if (amdgpu_ras_eeprom_process_recods(control,
                                                        &data->bps[control->num_recs],
                                                        true,


@@ -1624,6 +1627,9 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
                        return -EIO;
                }
 
                        return -EIO;
                }
 

+               dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
+       }
+

        return 0;
 }
 
        return 0;
 }
 


@@ -1914,9 +1920,8 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
        amdgpu_ras_check_supported(adev, &con->hw_supported,
                        &con->supported);
        if (!con->hw_supported) {
        amdgpu_ras_check_supported(adev, &con->hw_supported,
                        &con->supported);
        if (!con->hw_supported) {

-               amdgpu_ras_set_context(adev, NULL);
-               kfree(con);
-               return 0;
+               r = 0;
+               goto err_out;

        }
 
        con->features = 0;
        }
 
        con->features = 0;


@@ -1927,29 +1932,29 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
        if (adev->nbio.funcs->init_ras_controller_interrupt) {
                r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
                if (r)
        if (adev->nbio.funcs->init_ras_controller_interrupt) {
                r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
                if (r)

-                       return r;
+                       goto err_out;

        }
 
        if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
                r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
                if (r)
        }
 
        if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
                r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
                if (r)

-                       return r;
+                       goto err_out;

        }
 
        }
 

-       amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
-
-       if (amdgpu_ras_fs_init(adev))
-               goto fs_out;
+       if (amdgpu_ras_fs_init(adev)) {
+               r = -EINVAL;
+               goto err_out;
+       }

 
        dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
                        "hardware ability[%x] ras_mask[%x]\n",
                        con->hw_supported, con->supported);
        return 0;
 
        dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
                        "hardware ability[%x] ras_mask[%x]\n",
                        con->hw_supported, con->supported);
        return 0;

-fs_out:
+err_out:

        amdgpu_ras_set_context(adev, NULL);
        kfree(con);
 
        amdgpu_ras_set_context(adev, NULL);
        kfree(con);
 

-       return -EINVAL;
+       return r;

 }
 
 /* helper function to handle common stuff in ip late init phase */
 }
 
 /* helper function to handle common stuff in ip late init phase */


@@ -2129,3 +2134,14 @@ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
                amdgpu_ras_reset_gpu(adev);
        }
 }
                amdgpu_ras_reset_gpu(adev);
        }
 }

+
+bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
+{
+       if (adev->asic_type == CHIP_VEGA20 &&
+           adev->pm.fw_version <= 0x283400) {
+               return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
+                               amdgpu_ras_intr_triggered();
+       }
+
+       return false;
+}