Merge tag 'platform-drivers-x86-v4.13-2' of git://git.infradead.org/linux-platform...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gfx.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9b9ea6eb49c567186ab6b467584c1d96242169d9..1f279050d334323d9f7d0e536aaa0f9393543297 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -32,6 +32,21 @@ void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
 
 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
 
+int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
+                            struct amdgpu_ring *ring,
+                            struct amdgpu_irq_src *irq);
+
+void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
+                             struct amdgpu_irq_src *irq);
+
+void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
+int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
+                       unsigned hpd_size);
+
+int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
+                                  unsigned mqd_size);
+void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
+
 /**
  * amdgpu_gfx_create_bitmask - create a bitmask
  *
@@ -45,4 +60,34 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
        return (u32)((1ULL << bit_width) - 1);
 }
 
+static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev,
+                                         int mec, int pipe, int queue)
+{
+       int bit = 0;
+
+       bit += mec * adev->gfx.mec.num_pipe_per_mec
+               * adev->gfx.mec.num_queue_per_pipe;
+       bit += pipe * adev->gfx.mec.num_queue_per_pipe;
+       bit += queue;
+
+       return bit;
+}
+
+static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
+                                          int *mec, int *pipe, int *queue)
+{
+       *queue = bit % adev->gfx.mec.num_queue_per_pipe;
+       *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
+               % adev->gfx.mec.num_pipe_per_mec;
+       *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
+              / adev->gfx.mec.num_pipe_per_mec;
+
+}
+static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
+                                                  int mec, int pipe, int queue)
+{
+       return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
+                       adev->gfx.mec.queue_bitmap);
+}
+
 #endif