Merge tag 'drm-intel-next-fixes-2020-10-22' of git://anongit.freedesktop.org/drm...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_virt.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index f826945989c727a1a5b23fef67e7541e5d62c86f..8dd624c20f895ed8f5d57c17e85eb06e92a5fe0d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -24,6 +24,8 @@
 #ifndef AMDGPU_VIRT_H
 #define AMDGPU_VIRT_H
 
 #ifndef AMDGPU_VIRT_H
 #define AMDGPU_VIRT_H
 

+#include "amdgv_sriovmsg.h"
+

 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this GPU */
 #define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */
 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this GPU */
 #define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */


@@ -79,7 +81,10 @@ struct amdgpu_virt_fw_reserve {
        struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
        unsigned int checksum_key;
 };
        struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
        unsigned int checksum_key;
 };

+

 /*
 /*

+ * Legacy GIM header
+ *

  * Defination between PF and VF
  * Structures forcibly aligned to 4 to keep the same style as PF.
  */
  * Defination between PF and VF
  * Structures forcibly aligned to 4 to keep the same style as PF.
  */


@@ -101,15 +106,7 @@ enum AMDGIM_FEATURE_FLAG {
        AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
 };
 
        AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
 };
 

-struct amd_sriov_msg_pf2vf_info_header {
-       /* the total structure size in byte. */
-       uint32_t size;
-       /* version of this structure, written by the GIM */
-       uint32_t version;
-       /* reserved */
-       uint32_t reserved[2];
-} __aligned(4);
-struct  amdgim_pf2vf_info_v1 {
+struct amdgim_pf2vf_info_v1 {

        /* header contains size and version */
        struct amd_sriov_msg_pf2vf_info_header header;
        /* max_width * max_height */
        /* header contains size and version */
        struct amd_sriov_msg_pf2vf_info_header header;
        /* max_width * max_height */


@@ -128,54 +125,6 @@ struct  amdgim_pf2vf_info_v1 {
        unsigned int checksum;
 } __aligned(4);
 
        unsigned int checksum;
 } __aligned(4);
 

-struct  amdgim_pf2vf_info_v2 {
-       /* header contains size and version */
-       struct amd_sriov_msg_pf2vf_info_header header;
-       /* use private key from mailbox 2 to create chueksum */
-       uint32_t checksum;
-       /* The features flags of the GIM driver supports. */
-       uint32_t feature_flags;
-       /* max_width * max_height */
-       uint32_t uvd_enc_max_pixels_count;
-       /* 16x16 pixels/sec, codec independent */
-       uint32_t uvd_enc_max_bandwidth;
-       /* max_width * max_height */
-       uint32_t vce_enc_max_pixels_count;
-       /* 16x16 pixels/sec, codec independent */
-       uint32_t vce_enc_max_bandwidth;
-       /* Bad pages block position in BYTE */
-       uint32_t bp_block_offset_L;
-       uint32_t bp_block_offset_H;
-       /* Bad pages block size in BYTE */
-       uint32_t bp_block_size;
-       /* MEC FW position in kb from the start of VF visible frame buffer */
-       uint32_t mecfw_kboffset_L;
-       uint32_t mecfw_kboffset_H;
-       /* MEC FW size in KB */
-       uint32_t mecfw_ksize;
-       /* UVD FW position in kb from the start of VF visible frame buffer */
-       uint32_t uvdfw_kboffset_L;
-       uint32_t uvdfw_kboffset_H;
-       /* UVD FW size in KB */
-       uint32_t uvdfw_ksize;
-       /* VCE FW position in kb from the start of VF visible frame buffer */
-       uint32_t vcefw_kboffset_L;
-       uint32_t vcefw_kboffset_H;
-       /* VCE FW size in KB */
-       uint32_t vcefw_ksize;
-       uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (18 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 0)];
-} __aligned(4);
-
-
-struct amd_sriov_msg_vf2pf_info_header {
-       /* the total structure size in byte. */
-       uint32_t size;
-       /*version of this structure, written by the guest */
-       uint32_t version;
-       /* reserved */
-       uint32_t reserved[2];
-} __aligned(4);
-

 struct amdgim_vf2pf_info_v1 {
        /* header contains size and version */
        struct amd_sriov_msg_vf2pf_info_header header;
 struct amdgim_vf2pf_info_v1 {
        /* header contains size and version */
        struct amd_sriov_msg_vf2pf_info_header header;


@@ -237,31 +186,6 @@ struct amdgim_vf2pf_info_v2 {
        uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
 } __aligned(4);
 
        uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
 } __aligned(4);
 

-#define AMDGPU_FW_VRAM_VF2PF_VER 2
-typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
-
-#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
-       do { \
-               ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
-       } while (0)
-
-#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
-       do { \
-               (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
-       } while (0)
-
-#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
-       do { \
-               if (!adev->virt.fw_reserve.p_pf2vf) \
-                       *(val) = 0; \
-               else { \
-                       if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
-                               *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
-                       if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
-                               *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
-               } \
-       } while (0)
-

 struct amdgpu_virt_ras_err_handler_data {
        /* point to bad page records array */
        struct eeprom_table_record *bps;
 struct amdgpu_virt_ras_err_handler_data {
        /* point to bad page records array */
        struct eeprom_table_record *bps;


@@ -285,7 +209,7 @@ struct amdgpu_virt {
        struct work_struct              flr_work;
        struct amdgpu_mm_table          mm_table;
        const struct amdgpu_virt_ops    *ops;
        struct work_struct              flr_work;
        struct amdgpu_mm_table          mm_table;
        const struct amdgpu_virt_ops    *ops;

-       struct amdgpu_vf_error_buffer   vf_errors;
+       struct amdgpu_vf_error_buffer   vf_errors;

        struct amdgpu_virt_fw_reserve   fw_reserve;
        uint32_t gim_feature;
        uint32_t reg_access_mode;
        struct amdgpu_virt_fw_reserve   fw_reserve;
        uint32_t gim_feature;
        uint32_t reg_access_mode;


@@ -293,6 +217,10 @@ struct amdgpu_virt {
        bool tdr_debug;
        struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
        bool ras_init_done;
        bool tdr_debug;
        struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
        bool ras_init_done;

+
+       /* vf2pf message */
+       struct delayed_work vf2pf_work;
+       uint32_t vf2pf_update_interval_ms;

 };
 
 #define amdgpu_sriov_enabled(adev) \
 };
 
 #define amdgpu_sriov_enabled(adev) \


@@ -325,9 +253,9 @@ static inline bool is_virtual_machine(void)
 #define amdgpu_sriov_is_pp_one_vf(adev) \
        ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
 #define amdgpu_sriov_is_debug(adev) \
 #define amdgpu_sriov_is_pp_one_vf(adev) \
        ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
 #define amdgpu_sriov_is_debug(adev) \

-       ((!adev->in_gpu_reset) && adev->virt.tdr_debug)
+       ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)

 #define amdgpu_sriov_is_normal(adev) \
 #define amdgpu_sriov_is_normal(adev) \

-       ((!adev->in_gpu_reset) && (!adev->virt.tdr_debug))
+       ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))

 
 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
 
 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
 void amdgpu_virt_init_setting(struct amdgpu_device *adev);


@@ -341,11 +269,9 @@ void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);

-int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
-                                       unsigned int key,
-                                       unsigned int chksum);

 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);

+void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);

 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
 
 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
 
 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);