drm/amd/display: Remove last parts of timing_trace
[linux.git] / drivers / gpu / drm / amd / display / dc / resource / dcn20 / dcn20_resource.c
index 5e7cfa8e8ec93d5087879be2187946e9b357c5b6..189d0c85872e6fb584b9aa95ab02ac5412134c57 100644 (file)
@@ -706,7 +706,6 @@ static const struct resource_caps res_cap_nv14 = {
 static const struct dc_debug_options debug_defaults_drv = {
                .disable_dmcu = false,
                .force_abm_enable = false,
-               .timing_trace = false,
                .clock_trace = true,
                .disable_pplib_clock_request = true,
                .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
@@ -920,7 +919,7 @@ struct link_encoder *dcn20_link_encoder_create(
                kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
        int link_regs_id;
 
-       if (!enc20)
+       if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
                return NULL;
 
        link_regs_id =
@@ -2040,6 +2039,7 @@ bool dcn20_fast_validate_bw(
 {
        bool out = false;
        int split[MAX_PIPES] = { 0 };
+       bool merge[MAX_PIPES] = { false };
        int pipe_cnt, i, pipe_idx, vlevel;
 
        ASSERT(pipes);
@@ -2064,7 +2064,7 @@ bool dcn20_fast_validate_bw(
        if (vlevel > context->bw_ctx.dml.soc.num_states)
                goto validate_fail;
 
-       vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
+       vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
 
        /*initialize pipe_just_split_from to invalid idx*/
        for (i = 0; i < MAX_PIPES; i++)
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