rtc: Au1000 On-Chip Counter0-as-RTC driver.

[linux.git] / drivers / net / pasemi_mac.h

diff --git a/drivers/net/pasemi_mac.h b/drivers/net/pasemi_mac.h
index 8bee2a664c83760d12a897eb4230331f6e99c229..1a115ec60b531d4bf407f406716fc8ccf9ac72f0 100644 (file)
--- a/drivers/net/pasemi_mac.h
+++ b/drivers/net/pasemi_mac.h
@@ -26,7 +26,14 @@
 #include <linux/spinlock.h>
 #include <linux/phy.h>
 
+/* Must be a power of two */
+#define RX_RING_SIZE 2048
+#define TX_RING_SIZE 4096
+#define CS_RING_SIZE (TX_RING_SIZE*2)
+
+
 #define MAX_LRO_DESCRIPTORS 8
+#define MAX_CS 2
 
 struct pasemi_mac_txring {
        struct pasemi_dmachan chan; /* Must be first */
@@ -51,6 +58,15 @@ struct pasemi_mac_rxring {
        struct pasemi_mac *mac; /* Needed in intr handler */
 };
 
+struct pasemi_mac_csring {
+       struct pasemi_dmachan chan;
+       unsigned int    size;
+       unsigned int    next_to_fill;
+       int             events[2];
+       int             last_event;
+       int             fun;
+};
+
 struct pasemi_mac {
        struct net_device *netdev;
        struct pci_dev *pdev;
@@ -59,10 +75,13 @@ struct pasemi_mac {
        struct phy_device *phydev;
        struct napi_struct napi;
 
+       int             bufsz; /* RX ring buffer size */
+       int             last_cs;
+       int             num_cs;
+       u32             dma_if;
        u8              type;
 #define MAC_TYPE_GMAC  1
 #define MAC_TYPE_XAUI  2
-       u32     dma_if;
 
        u8              mac_addr[6];
 
@@ -73,6 +92,7 @@ struct pasemi_mac {
 
        struct pasemi_mac_txring *tx;
        struct pasemi_mac_rxring *rx;
+       struct pasemi_mac_csring *cs[MAX_CS];
        char            tx_irq_name[10];                /* "eth%d tx" */
        char            rx_irq_name[10];                /* "eth%d rx" */
        int     link;
@@ -89,6 +109,16 @@ struct pasemi_mac_buffer {
        dma_addr_t      dma;
 };
 
+#define TX_DESC(tx, num)       ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
+#define TX_DESC_INFO(tx, num)  ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
+#define RX_DESC(rx, num)       ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
+#define RX_DESC_INFO(rx, num)  ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
+#define RX_BUFF(rx, num)       ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
+#define CS_DESC(cs, num)       ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)])
+
+#define RING_USED(ring)        (((ring)->next_to_fill - (ring)->next_to_clean) \
+                               & ((ring)->size - 1))
+#define RING_AVAIL(ring)       ((ring->size) - RING_USED(ring))
 
 /* PCI register offsets and formats */
 
@@ -96,7 +126,11 @@ struct pasemi_mac_buffer {
 /* MAC CFG register offsets */
 enum {
        PAS_MAC_CFG_PCFG = 0x80,
+       PAS_MAC_CFG_MACCFG = 0x84,
+       PAS_MAC_CFG_ADR0 = 0x8c,
+       PAS_MAC_CFG_ADR1 = 0x90,
        PAS_MAC_CFG_TXP = 0x98,
+       PAS_MAC_CFG_RMON = 0x100,
        PAS_MAC_IPC_CHNL = 0x208,
 };
 
@@ -130,6 +164,18 @@ enum {
 #define PAS_MAC_CFG_PCFG_SPD_100M      0x00000001
 #define PAS_MAC_CFG_PCFG_SPD_1G                0x00000002
 #define PAS_MAC_CFG_PCFG_SPD_10G       0x00000003
+
+#define PAS_MAC_CFG_MACCFG_TXT_M       0x70000000
+#define PAS_MAC_CFG_MACCFG_TXT_S       28
+#define PAS_MAC_CFG_MACCFG_PRES_M      0x0f000000
+#define PAS_MAC_CFG_MACCFG_PRES_S      24
+#define PAS_MAC_CFG_MACCFG_MAXF_M      0x00ffff00
+#define PAS_MAC_CFG_MACCFG_MAXF_S      8
+#define PAS_MAC_CFG_MACCFG_MAXF(x)     (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \
+                                        PAS_MAC_CFG_MACCFG_MAXF_M)
+#define PAS_MAC_CFG_MACCFG_MINF_M      0x000000ff
+#define PAS_MAC_CFG_MACCFG_MINF_S      0
+
 #define PAS_MAC_CFG_TXP_FCF            0x01000000
 #define PAS_MAC_CFG_TXP_FCE            0x00800000
 #define PAS_MAC_CFG_TXP_FC             0x00400000
@@ -156,6 +202,8 @@ enum {
 #define PAS_MAC_CFG_TXP_TIFG(x)                (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
                                         PAS_MAC_CFG_TXP_TIFG_M)
 
+#define PAS_MAC_RMON(r)                        (0x100+(r)*4)
+
 #define PAS_MAC_IPC_CHNL_DCHNO_M       0x003f0000
 #define PAS_MAC_IPC_CHNL_DCHNO_S       16
 #define PAS_MAC_IPC_CHNL_DCHNO(x)      (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
@@ -165,4 +213,5 @@ enum {
 #define PAS_MAC_IPC_CHNL_BCH(x)                (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
                                         PAS_MAC_IPC_CHNL_BCH_M)
 
+
 #endif /* PASEMI_MAC_H */