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ARM: dts: imx6q: Align pin config nodes with bindings
[linux.git] / arch / arm / boot / dts / nxp / imx / imx6q-dmo-edmqmx6.dts
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts
index 9f7ac7158c465eb1cfa710cb3e1790d554927644..c5525b2c1dbd594ba79c6c95e9dfc6b64a87670d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts
@@ -283,138 +283,136 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
 
-       imx6q-dmo-edmqmx6 {
-               pinctrl_hog: hoggrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
-                               MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
-                       >;
-               };
+       pinctrl_hog: hoggrp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
+                       MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
+               >;
+       };
 
-               pinctrl_can1: can1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
-                               MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
-                       >;
-               };
+       pinctrl_can1: can1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
+                       MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
+               >;
+       };
 
-               pinctrl_ecspi5: ecspi5rp-1 {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO        0x80000000
-                               MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI         0x80000000
-                               MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK         0x80000000
-                               MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x80000000
-                       >;
-               };
+       pinctrl_ecspi5: ecspi5rp-1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO        0x80000000
+                       MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI         0x80000000
+                       MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK         0x80000000
+                       MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x80000000
+               >;
+       };
 
-               pinctrl_enet: enetgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
-                               MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
-                               MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
-                               MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
-                               MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
-                               MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
-                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
-                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
-                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
-                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
-                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
-                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
-                               MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
-                               MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
-                               MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
-                               MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0
-                               MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
-                       >;
-               };
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
+                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
+                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
+                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
+                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
+                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
+                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
+                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
+                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
+                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
+                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
+                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
+                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                       MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0
+                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+               >;
+       };
 
-               pinctrl_i2c1: i2c1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
-                               MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+               >;
+       };
 
-               pinctrl_i2c2: i2c2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
-                               MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
+                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+               >;
+       };
 
-               pinctrl_i2c3: i2c3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
-                               MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
-                       >;
-               };
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
+                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+               >;
+       };
 
-               pinctrl_pcie: pciegrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x100b1
-                       >;
-               };
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x100b1
+               >;
+       };
 
-               pinctrl_pfuze: pfuze100grp1 {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x80000000
-                       >;
-               };
+       pinctrl_pfuze: pfuze100grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x80000000
+               >;
+       };
 
-               pinctrl_stmpe1: stmpe1grp {
-                       fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
-               };
+       pinctrl_stmpe1: stmpe1grp {
+               fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
+       };
 
-               pinctrl_stmpe2: stmpe2grp {
-                       fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
-               };
+       pinctrl_stmpe2: stmpe2grp {
+               fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
+       };
 
-               pinctrl_uart1: uart1grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
-                               MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
-                       >;
-               };
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+               >;
+       };
 
-               pinctrl_uart2: uart2grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
-                               MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
-                       >;
-               };
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                       MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+               >;
+       };
 
-               pinctrl_usbotg: usbotggrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
-                       >;
-               };
+       pinctrl_usbotg: usbotggrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
+               >;
+       };
 
-               pinctrl_usdhc3: usdhc3grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
-                               MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
-                               MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
-                               MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
-                               MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
-                               MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
-                       >;
-               };
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+               >;
+       };
 
-               pinctrl_usdhc4: usdhc4grp {
-                       fsl,pins = <
-                               MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
-                               MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
-                               MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
-                               MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
-                               MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
-                               MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
-                               MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
-                               MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
-                               MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
-                               MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
-                       >;
-               };
+       pinctrl_usdhc4: usdhc4grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                       MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                       MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                       MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                       MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                       MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                       MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                       MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                       MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                       MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+               >;
        };
 };
 
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