Merge tag 'iommu-updates-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 5916cc25e28be5e8b2497e5b663da49f6c4b03d9..f55f72a37ca838d223cd9759ae6c8b2fddff0875 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -161,8 +161,38 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
                          le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
                DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
                          le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
-               DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
-                         le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
+               DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
+                         le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
+               if (version_minor == 1) {
+                       const struct rlc_firmware_header_v2_1 *v2_1 =
+                               container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
+                       DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
+                                 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
+                       DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
+                       DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
+                       DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
+                       DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
+                       DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
+                       DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
+                       DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
+                       DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
+                       DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
+                       DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
+                       DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
+                       DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
+                                 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
+               }
        } else {
                DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
        }
@@ -265,6 +295,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
        case CHIP_POLARIS10:
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
+       case CHIP_VEGAM:
                if (!load_type)
                        return AMDGPU_FW_LOAD_DIRECT;
                else
@@ -276,6 +307,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
                        return AMDGPU_FW_LOAD_DIRECT;
                else
                        return AMDGPU_FW_LOAD_PSP;
+       case CHIP_VEGA20:
+               return AMDGPU_FW_LOAD_DIRECT;
        default:
                DRM_ERROR("Unknown firmware load type\n");
        }
@@ -307,7 +340,10 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
            (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
             ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
             ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
-            ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
+            ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
+            ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
                ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
 
                memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
@@ -329,6 +365,18 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                                              le32_to_cpu(header->ucode_array_offset_bytes) +
                                              le32_to_cpu(cp_hdr->jt_offset) * 4),
                       ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
+               ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
+               memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
+                      ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
+               ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
+               memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
+                      ucode->ucode_size);
+       } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
+               ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
+               memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
+                      ucode->ucode_size);
        }
 
        return 0;