Merge tag 'for-5.13/libata-2021-04-27' of git://git.kernel.dk/linux-block

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_irq.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index afbbec82a289c8300cd823b0e41ed1dc221fb166..90f50561b43a9d707f1782bf79b6315bede7095a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -65,6 +65,41 @@
 
 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
 
 
 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
 

+const char *soc15_ih_clientid_name[] = {
+       "IH",
+       "SDMA2 or ACP",
+       "ATHUB",
+       "BIF",
+       "SDMA3 or DCE",
+       "SDMA4 or ISP",
+       "VMC1 or PCIE0",
+       "RLC",
+       "SDMA0",
+       "SDMA1",
+       "SE0SH",
+       "SE1SH",
+       "SE2SH",
+       "SE3SH",
+       "VCN1 or UVD1",
+       "THM",
+       "VCN or UVD",
+       "SDMA5 or VCE0",
+       "VMC",
+       "SDMA6 or XDMA",
+       "GRBM_CP",
+       "ATS",
+       "ROM_SMUIO",
+       "DF",
+       "SDMA7 or VCE1",
+       "PWR",
+       "reserved",
+       "UTCL2",
+       "EA",
+       "UTCL2LOG",
+       "MP0",
+       "MP1"
+};
+

 /**
  * amdgpu_hotplug_work_func - work handler for display hotplug event
  *
 /**
  * amdgpu_hotplug_work_func - work handler for display hotplug event
  *


@@ -164,13 +199,13 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
         * ack the interrupt if it is there
         */
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
         * ack the interrupt if it is there
         */
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {

-               if (adev->nbio.funcs &&
-                   adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
-                       adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
+               if (adev->nbio.ras_funcs &&
+                   adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring)
+                       adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev);

 
 

-               if (adev->nbio.funcs &&
-                   adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
-                       adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
+               if (adev->nbio.ras_funcs &&
+                   adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring)
+                       adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev);

        }
 
        return ret;
        }
 
        return ret;


@@ -347,11 +382,6 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
 
                        kfree(src->enabled_types);
                        src->enabled_types = NULL;
 
                        kfree(src->enabled_types);
                        src->enabled_types = NULL;

-                       if (src->data) {
-                               kfree(src->data);
-                               kfree(src);
-                               adev->irq.client[i].sources[j] = NULL;
-                       }

                }
                kfree(adev->irq.client[i].sources);
                adev->irq.client[i].sources = NULL;
                }
                kfree(adev->irq.client[i].sources);
                adev->irq.client[i].sources = NULL;


@@ -535,7 +565,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
                for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
                        struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
 
                for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
                        struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
 

-                       if (!src)
+                       if (!src || !src->funcs || !src->funcs->set)

                                continue;
                        for (k = 0; k < src->num_types; k++)
                                amdgpu_irq_update(adev, src, k);
                                continue;
                        for (k = 0; k < src->num_types; k++)
                                amdgpu_irq_update(adev, src, k);