arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <[email protected]>
  11  *   Avi Kivity   <[email protected]>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         u32 ldr_mode;
 149         struct page *avic_logical_id_table_page;
 150         struct page *avic_physical_id_table_page;
 151         struct hlist_node hnode;
 152
 153         struct kvm_sev_info sev_info;
 154 };
 155
 156 struct kvm_vcpu;
 157
 158 struct nested_state {
 159         struct vmcb *hsave;
 160         u64 hsave_msr;
 161         u64 vm_cr_msr;
 162         u64 vmcb;
 163
 164         /* These are the merged vectors */
 165         u32 *msrpm;
 166
 167         /* gpa pointers to the real vectors */
 168         u64 vmcb_msrpm;
 169         u64 vmcb_iopm;
 170
 171         /* A VMEXIT is required but not yet emulated */
 172         bool exit_required;
 173
 174         /* cache for intercepts of the guest */
 175         u32 intercept_cr;
 176         u32 intercept_dr;
 177         u32 intercept_exceptions;
 178         u64 intercept;
 179
 180         /* Nested Paging related state */
 181         u64 nested_cr3;
 182 };
 183
 184 #define MSRPM_OFFSETS   16
 185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 186
 187 /*
 188  * Set osvw_len to higher value when updated Revision Guides
 189  * are published and we know what the new status bits are
 190  */
 191 static uint64_t osvw_len = 4, osvw_status;
 192
 193 struct vcpu_svm {
 194         struct kvm_vcpu vcpu;
 195         struct vmcb *vmcb;
 196         unsigned long vmcb_pa;
 197         struct svm_cpu_data *svm_data;
 198         uint64_t asid_generation;
 199         uint64_t sysenter_esp;
 200         uint64_t sysenter_eip;
 201         uint64_t tsc_aux;
 202
 203         u64 msr_decfg;
 204
 205         u64 next_rip;
 206
 207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 208         struct {
 209                 u16 fs;
 210                 u16 gs;
 211                 u16 ldt;
 212                 u64 gs_base;
 213         } host;
 214
 215         u64 spec_ctrl;
 216         /*
 217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 218          * translated into the appropriate L2_CFG bits on the host to
 219          * perform speculative control.
 220          */
 221         u64 virt_spec_ctrl;
 222
 223         u32 *msrpm;
 224
 225         ulong nmi_iret_rip;
 226
 227         struct nested_state nested;
 228
 229         bool nmi_singlestep;
 230         u64 nmi_singlestep_guest_rflags;
 231
 232         unsigned int3_injected;
 233         unsigned long int3_rip;
 234
 235         /* cached guest cpuid flags for faster access */
 236         bool nrips_enabled      : 1;
 237
 238         u32 ldr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444 #ifdef CONFIG_KVM_AMD_SEV
 445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 446
 447         return sev->active;
 448 #else
 449         return false;
 450 #endif
 451 }
 452
 453 static inline int sev_get_asid(struct kvm *kvm)
 454 {
 455         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 456
 457         return sev->asid;
 458 }
 459
 460 static inline void mark_all_dirty(struct vmcb *vmcb)
 461 {
 462         vmcb->control.clean = 0;
 463 }
 464
 465 static inline void mark_all_clean(struct vmcb *vmcb)
 466 {
 467         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 468                                & ~VMCB_ALWAYS_DIRTY_MASK;
 469 }
 470
 471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 472 {
 473         vmcb->control.clean &= ~(1 << bit);
 474 }
 475
 476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 477 {
 478         return container_of(vcpu, struct vcpu_svm, vcpu);
 479 }
 480
 481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 482 {
 483         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 484         mark_dirty(svm->vmcb, VMCB_AVIC);
 485 }
 486
 487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 488 {
 489         struct vcpu_svm *svm = to_svm(vcpu);
 490         u64 *entry = svm->avic_physical_id_cache;
 491
 492         if (!entry)
 493                 return false;
 494
 495         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 496 }
 497
 498 static void recalc_intercepts(struct vcpu_svm *svm)
 499 {
 500         struct vmcb_control_area *c, *h;
 501         struct nested_state *g;
 502
 503         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 504
 505         if (!is_guest_mode(&svm->vcpu))
 506                 return;
 507
 508         c = &svm->vmcb->control;
 509         h = &svm->nested.hsave->control;
 510         g = &svm->nested;
 511
 512         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 513         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 514         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 515         c->intercept = h->intercept | g->intercept;
 516 }
 517
 518 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 519 {
 520         if (is_guest_mode(&svm->vcpu))
 521                 return svm->nested.hsave;
 522         else
 523                 return svm->vmcb;
 524 }
 525
 526 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 527 {
 528         struct vmcb *vmcb = get_host_vmcb(svm);
 529
 530         vmcb->control.intercept_cr |= (1U << bit);
 531
 532         recalc_intercepts(svm);
 533 }
 534
 535 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 536 {
 537         struct vmcb *vmcb = get_host_vmcb(svm);
 538
 539         vmcb->control.intercept_cr &= ~(1U << bit);
 540
 541         recalc_intercepts(svm);
 542 }
 543
 544 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 545 {
 546         struct vmcb *vmcb = get_host_vmcb(svm);
 547
 548         return vmcb->control.intercept_cr & (1U << bit);
 549 }
 550
 551 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 552 {
 553         struct vmcb *vmcb = get_host_vmcb(svm);
 554
 555         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 556                 | (1 << INTERCEPT_DR1_READ)
 557                 | (1 << INTERCEPT_DR2_READ)
 558                 | (1 << INTERCEPT_DR3_READ)
 559                 | (1 << INTERCEPT_DR4_READ)
 560                 | (1 << INTERCEPT_DR5_READ)
 561                 | (1 << INTERCEPT_DR6_READ)
 562                 | (1 << INTERCEPT_DR7_READ)
 563                 | (1 << INTERCEPT_DR0_WRITE)
 564                 | (1 << INTERCEPT_DR1_WRITE)
 565                 | (1 << INTERCEPT_DR2_WRITE)
 566                 | (1 << INTERCEPT_DR3_WRITE)
 567                 | (1 << INTERCEPT_DR4_WRITE)
 568                 | (1 << INTERCEPT_DR5_WRITE)
 569                 | (1 << INTERCEPT_DR6_WRITE)
 570                 | (1 << INTERCEPT_DR7_WRITE);
 571
 572         recalc_intercepts(svm);
 573 }
 574
 575 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 576 {
 577         struct vmcb *vmcb = get_host_vmcb(svm);
 578
 579         vmcb->control.intercept_dr = 0;
 580
 581         recalc_intercepts(svm);
 582 }
 583
 584 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 585 {
 586         struct vmcb *vmcb = get_host_vmcb(svm);
 587
 588         vmcb->control.intercept_exceptions |= (1U << bit);
 589
 590         recalc_intercepts(svm);
 591 }
 592
 593 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 594 {
 595         struct vmcb *vmcb = get_host_vmcb(svm);
 596
 597         vmcb->control.intercept_exceptions &= ~(1U << bit);
 598
 599         recalc_intercepts(svm);
 600 }
 601
 602 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 603 {
 604         struct vmcb *vmcb = get_host_vmcb(svm);
 605
 606         vmcb->control.intercept |= (1ULL << bit);
 607
 608         recalc_intercepts(svm);
 609 }
 610
 611 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 612 {
 613         struct vmcb *vmcb = get_host_vmcb(svm);
 614
 615         vmcb->control.intercept &= ~(1ULL << bit);
 616
 617         recalc_intercepts(svm);
 618 }
 619
 620 static inline bool vgif_enabled(struct vcpu_svm *svm)
 621 {
 622         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 623 }
 624
 625 static inline void enable_gif(struct vcpu_svm *svm)
 626 {
 627         if (vgif_enabled(svm))
 628                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 629         else
 630                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 631 }
 632
 633 static inline void disable_gif(struct vcpu_svm *svm)
 634 {
 635         if (vgif_enabled(svm))
 636                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 637         else
 638                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 639 }
 640
 641 static inline bool gif_set(struct vcpu_svm *svm)
 642 {
 643         if (vgif_enabled(svm))
 644                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 645         else
 646                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 647 }
 648
 649 static unsigned long iopm_base;
 650
 651 struct kvm_ldttss_desc {
 652         u16 limit0;
 653         u16 base0;
 654         unsigned base1:8, type:5, dpl:2, p:1;
 655         unsigned limit1:4, zero0:3, g:1, base2:8;
 656         u32 base3;
 657         u32 zero1;
 658 } __attribute__((packed));
 659
 660 struct svm_cpu_data {
 661         int cpu;
 662
 663         u64 asid_generation;
 664         u32 max_asid;
 665         u32 next_asid;
 666         u32 min_asid;
 667         struct kvm_ldttss_desc *tss_desc;
 668
 669         struct page *save_area;
 670         struct vmcb *current_vmcb;
 671
 672         /* index = sev_asid, value = vmcb pointer */
 673         struct vmcb **sev_vmcbs;
 674 };
 675
 676 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 677
 678 struct svm_init_data {
 679         int cpu;
 680         int r;
 681 };
 682
 683 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 684
 685 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 686 #define MSRS_RANGE_SIZE 2048
 687 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 688
 689 static u32 svm_msrpm_offset(u32 msr)
 690 {
 691         u32 offset;
 692         int i;
 693
 694         for (i = 0; i < NUM_MSR_MAPS; i++) {
 695                 if (msr < msrpm_ranges[i] ||
 696                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 697                         continue;
 698
 699                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 700                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 701
 702                 /* Now we have the u8 offset - but need the u32 offset */
 703                 return offset / 4;
 704         }
 705
 706         /* MSR not in any range */
 707         return MSR_INVALID;
 708 }
 709
 710 #define MAX_INST_SIZE 15
 711
 712 static inline void clgi(void)
 713 {
 714         asm volatile (__ex(SVM_CLGI));
 715 }
 716
 717 static inline void stgi(void)
 718 {
 719         asm volatile (__ex(SVM_STGI));
 720 }
 721
 722 static inline void invlpga(unsigned long addr, u32 asid)
 723 {
 724         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 725 }
 726
 727 static int get_npt_level(struct kvm_vcpu *vcpu)
 728 {
 729 #ifdef CONFIG_X86_64
 730         return PT64_ROOT_4LEVEL;
 731 #else
 732         return PT32E_ROOT_LEVEL;
 733 #endif
 734 }
 735
 736 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 737 {
 738         vcpu->arch.efer = efer;
 739         if (!npt_enabled && !(efer & EFER_LMA))
 740                 efer &= ~EFER_LME;
 741
 742         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 743         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 744 }
 745
 746 static int is_external_interrupt(u32 info)
 747 {
 748         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 749         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 750 }
 751
 752 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 753 {
 754         struct vcpu_svm *svm = to_svm(vcpu);
 755         u32 ret = 0;
 756
 757         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 758                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 759         return ret;
 760 }
 761
 762 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 763 {
 764         struct vcpu_svm *svm = to_svm(vcpu);
 765
 766         if (mask == 0)
 767                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 768         else
 769                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 770
 771 }
 772
 773 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 774 {
 775         struct vcpu_svm *svm = to_svm(vcpu);
 776
 777         if (svm->vmcb->control.next_rip != 0) {
 778                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 779                 svm->next_rip = svm->vmcb->control.next_rip;
 780         }
 781
 782         if (!svm->next_rip) {
 783                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 784                                 EMULATE_DONE)
 785                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 786                 return;
 787         }
 788         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 789                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 790                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 791
 792         kvm_rip_write(vcpu, svm->next_rip);
 793         svm_set_interrupt_shadow(vcpu, 0);
 794 }
 795
 796 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 797 {
 798         struct vcpu_svm *svm = to_svm(vcpu);
 799         unsigned nr = vcpu->arch.exception.nr;
 800         bool has_error_code = vcpu->arch.exception.has_error_code;
 801         bool reinject = vcpu->arch.exception.injected;
 802         u32 error_code = vcpu->arch.exception.error_code;
 803
 804         /*
 805          * If we are within a nested VM we'd better #VMEXIT and let the guest
 806          * handle the exception
 807          */
 808         if (!reinject &&
 809             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 810                 return;
 811
 812         kvm_deliver_exception_payload(&svm->vcpu);
 813
 814         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 815                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 816
 817                 /*
 818                  * For guest debugging where we have to reinject #BP if some
 819                  * INT3 is guest-owned:
 820                  * Emulate nRIP by moving RIP forward. Will fail if injection
 821                  * raises a fault that is not intercepted. Still better than
 822                  * failing in all cases.
 823                  */
 824                 skip_emulated_instruction(&svm->vcpu);
 825                 rip = kvm_rip_read(&svm->vcpu);
 826                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 827                 svm->int3_injected = rip - old_rip;
 828         }
 829
 830         svm->vmcb->control.event_inj = nr
 831                 | SVM_EVTINJ_VALID
 832                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 833                 | SVM_EVTINJ_TYPE_EXEPT;
 834         svm->vmcb->control.event_inj_err = error_code;
 835 }
 836
 837 static void svm_init_erratum_383(void)
 838 {
 839         u32 low, high;
 840         int err;
 841         u64 val;
 842
 843         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 844                 return;
 845
 846         /* Use _safe variants to not break nested virtualization */
 847         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 848         if (err)
 849                 return;
 850
 851         val |= (1ULL << 47);
 852
 853         low  = lower_32_bits(val);
 854         high = upper_32_bits(val);
 855
 856         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 857
 858         erratum_383_found = true;
 859 }
 860
 861 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 862 {
 863         /*
 864          * Guests should see errata 400 and 415 as fixed (assuming that
 865          * HLT and IO instructions are intercepted).
 866          */
 867         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 868         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 869
 870         /*
 871          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 872          * all osvw.status bits inside that length, including bit 0 (which is
 873          * reserved for erratum 298), are valid. However, if host processor's
 874          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 875          * be conservative here and therefore we tell the guest that erratum 298
 876          * is present (because we really don't know).
 877          */
 878         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 879                 vcpu->arch.osvw.status |= 1;
 880 }
 881
 882 static int has_svm(void)
 883 {
 884         const char *msg;
 885
 886         if (!cpu_has_svm(&msg)) {
 887                 printk(KERN_INFO "has_svm: %s\n", msg);
 888                 return 0;
 889         }
 890
 891         return 1;
 892 }
 893
 894 static void svm_hardware_disable(void)
 895 {
 896         /* Make sure we clean up behind us */
 897         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 898                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 899
 900         cpu_svm_disable();
 901
 902         amd_pmu_disable_virt();
 903 }
 904
 905 static int svm_hardware_enable(void)
 906 {
 907
 908         struct svm_cpu_data *sd;
 909         uint64_t efer;
 910         struct desc_struct *gdt;
 911         int me = raw_smp_processor_id();
 912
 913         rdmsrl(MSR_EFER, efer);
 914         if (efer & EFER_SVME)
 915                 return -EBUSY;
 916
 917         if (!has_svm()) {
 918                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 919                 return -EINVAL;
 920         }
 921         sd = per_cpu(svm_data, me);
 922         if (!sd) {
 923                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 924                 return -EINVAL;
 925         }
 926
 927         sd->asid_generation = 1;
 928         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 929         sd->next_asid = sd->max_asid + 1;
 930         sd->min_asid = max_sev_asid + 1;
 931
 932         gdt = get_current_gdt_rw();
 933         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 934
 935         wrmsrl(MSR_EFER, efer | EFER_SVME);
 936
 937         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 938
 939         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 940                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 941                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 942         }
 943
 944
 945         /*
 946          * Get OSVW bits.
 947          *
 948          * Note that it is possible to have a system with mixed processor
 949          * revisions and therefore different OSVW bits. If bits are not the same
 950          * on different processors then choose the worst case (i.e. if erratum
 951          * is present on one processor and not on another then assume that the
 952          * erratum is present everywhere).
 953          */
 954         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 955                 uint64_t len, status = 0;
 956                 int err;
 957
 958                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 959                 if (!err)
 960                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 961                                                       &err);
 962
 963                 if (err)
 964                         osvw_status = osvw_len = 0;
 965                 else {
 966                         if (len < osvw_len)
 967                                 osvw_len = len;
 968                         osvw_status |= status;
 969                         osvw_status &= (1ULL << osvw_len) - 1;
 970                 }
 971         } else
 972                 osvw_status = osvw_len = 0;
 973
 974         svm_init_erratum_383();
 975
 976         amd_pmu_enable_virt();
 977
 978         return 0;
 979 }
 980
 981 static void svm_cpu_uninit(int cpu)
 982 {
 983         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 984
 985         if (!sd)
 986                 return;
 987
 988         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 989         kfree(sd->sev_vmcbs);
 990         __free_page(sd->save_area);
 991         kfree(sd);
 992 }
 993
 994 static int svm_cpu_init(int cpu)
 995 {
 996         struct svm_cpu_data *sd;
 997         int r;
 998
 999         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1000         if (!sd)
1001                 return -ENOMEM;
1002         sd->cpu = cpu;
1003         r = -ENOMEM;
1004         sd->save_area = alloc_page(GFP_KERNEL);
1005         if (!sd->save_area)
1006                 goto err_1;
1007
1008         if (svm_sev_enabled()) {
1009                 r = -ENOMEM;
1010                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1011                                               sizeof(void *),
1012                                               GFP_KERNEL);
1013                 if (!sd->sev_vmcbs)
1014                         goto err_1;
1015         }
1016
1017         per_cpu(svm_data, cpu) = sd;
1018
1019         return 0;
1020
1021 err_1:
1022         kfree(sd);
1023         return r;
1024
1025 }
1026
1027 static bool valid_msr_intercept(u32 index)
1028 {
1029         int i;
1030
1031         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1032                 if (direct_access_msrs[i].index == index)
1033                         return true;
1034
1035         return false;
1036 }
1037
1038 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1039 {
1040         u8 bit_write;
1041         unsigned long tmp;
1042         u32 offset;
1043         u32 *msrpm;
1044
1045         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1046                                       to_svm(vcpu)->msrpm;
1047
1048         offset    = svm_msrpm_offset(msr);
1049         bit_write = 2 * (msr & 0x0f) + 1;
1050         tmp       = msrpm[offset];
1051
1052         BUG_ON(offset == MSR_INVALID);
1053
1054         return !!test_bit(bit_write,  &tmp);
1055 }
1056
1057 static void set_msr_interception(u32 *msrpm, unsigned msr,
1058                                  int read, int write)
1059 {
1060         u8 bit_read, bit_write;
1061         unsigned long tmp;
1062         u32 offset;
1063
1064         /*
1065          * If this warning triggers extend the direct_access_msrs list at the
1066          * beginning of the file
1067          */
1068         WARN_ON(!valid_msr_intercept(msr));
1069
1070         offset    = svm_msrpm_offset(msr);
1071         bit_read  = 2 * (msr & 0x0f);
1072         bit_write = 2 * (msr & 0x0f) + 1;
1073         tmp       = msrpm[offset];
1074
1075         BUG_ON(offset == MSR_INVALID);
1076
1077         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1078         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1079
1080         msrpm[offset] = tmp;
1081 }
1082
1083 static void svm_vcpu_init_msrpm(u32 *msrpm)
1084 {
1085         int i;
1086
1087         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1088
1089         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1090                 if (!direct_access_msrs[i].always)
1091                         continue;
1092
1093                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1094         }
1095 }
1096
1097 static void add_msr_offset(u32 offset)
1098 {
1099         int i;
1100
1101         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1102
1103                 /* Offset already in list? */
1104                 if (msrpm_offsets[i] == offset)
1105                         return;
1106
1107                 /* Slot used by another offset? */
1108                 if (msrpm_offsets[i] != MSR_INVALID)
1109                         continue;
1110
1111                 /* Add offset to list */
1112                 msrpm_offsets[i] = offset;
1113
1114                 return;
1115         }
1116
1117         /*
1118          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1119          * increase MSRPM_OFFSETS in this case.
1120          */
1121         BUG();
1122 }
1123
1124 static void init_msrpm_offsets(void)
1125 {
1126         int i;
1127
1128         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1129
1130         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1131                 u32 offset;
1132
1133                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1134                 BUG_ON(offset == MSR_INVALID);
1135
1136                 add_msr_offset(offset);
1137         }
1138 }
1139
1140 static void svm_enable_lbrv(struct vcpu_svm *svm)
1141 {
1142         u32 *msrpm = svm->msrpm;
1143
1144         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1145         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1146         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1147         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1148         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1149 }
1150
1151 static void svm_disable_lbrv(struct vcpu_svm *svm)
1152 {
1153         u32 *msrpm = svm->msrpm;
1154
1155         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1156         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1157         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1158         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1159         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1160 }
1161
1162 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1163 {
1164         svm->nmi_singlestep = false;
1165
1166         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1167                 /* Clear our flags if they were not set by the guest */
1168                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1169                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1170                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1171                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1172         }
1173 }
1174
1175 /* Note:
1176  * This hash table is used to map VM_ID to a struct kvm_svm,
1177  * when handling AMD IOMMU GALOG notification to schedule in
1178  * a particular vCPU.
1179  */
1180 #define SVM_VM_DATA_HASH_BITS   8
1181 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1182 static u32 next_vm_id = 0;
1183 static bool next_vm_id_wrapped = 0;
1184 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1185
1186 /* Note:
1187  * This function is called from IOMMU driver to notify
1188  * SVM to schedule in a particular vCPU of a particular VM.
1189  */
1190 static int avic_ga_log_notifier(u32 ga_tag)
1191 {
1192         unsigned long flags;
1193         struct kvm_svm *kvm_svm;
1194         struct kvm_vcpu *vcpu = NULL;
1195         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1196         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1197
1198         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1199
1200         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1201         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1202                 if (kvm_svm->avic_vm_id != vm_id)
1203                         continue;
1204                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1205                 break;
1206         }
1207         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1208
1209         /* Note:
1210          * At this point, the IOMMU should have already set the pending
1211          * bit in the vAPIC backing page. So, we just need to schedule
1212          * in the vcpu.
1213          */
1214         if (vcpu)
1215                 kvm_vcpu_wake_up(vcpu);
1216
1217         return 0;
1218 }
1219
1220 static __init int sev_hardware_setup(void)
1221 {
1222         struct sev_user_data_status *status;
1223         int rc;
1224
1225         /* Maximum number of encrypted guests supported simultaneously */
1226         max_sev_asid = cpuid_ecx(0x8000001F);
1227
1228         if (!max_sev_asid)
1229                 return 1;
1230
1231         /* Minimum ASID value that should be used for SEV guest */
1232         min_sev_asid = cpuid_edx(0x8000001F);
1233
1234         /* Initialize SEV ASID bitmap */
1235         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1236         if (!sev_asid_bitmap)
1237                 return 1;
1238
1239         status = kmalloc(sizeof(*status), GFP_KERNEL);
1240         if (!status)
1241                 return 1;
1242
1243         /*
1244          * Check SEV platform status.
1245          *
1246          * PLATFORM_STATUS can be called in any state, if we failed to query
1247          * the PLATFORM status then either PSP firmware does not support SEV
1248          * feature or SEV firmware is dead.
1249          */
1250         rc = sev_platform_status(status, NULL);
1251         if (rc)
1252                 goto err;
1253
1254         pr_info("SEV supported\n");
1255
1256 err:
1257         kfree(status);
1258         return rc;
1259 }
1260
1261 static void grow_ple_window(struct kvm_vcpu *vcpu)
1262 {
1263         struct vcpu_svm *svm = to_svm(vcpu);
1264         struct vmcb_control_area *control = &svm->vmcb->control;
1265         int old = control->pause_filter_count;
1266
1267         control->pause_filter_count = __grow_ple_window(old,
1268                                                         pause_filter_count,
1269                                                         pause_filter_count_grow,
1270                                                         pause_filter_count_max);
1271
1272         if (control->pause_filter_count != old)
1273                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1274
1275         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1276                                   control->pause_filter_count, old);
1277 }
1278
1279 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1280 {
1281         struct vcpu_svm *svm = to_svm(vcpu);
1282         struct vmcb_control_area *control = &svm->vmcb->control;
1283         int old = control->pause_filter_count;
1284
1285         control->pause_filter_count =
1286                                 __shrink_ple_window(old,
1287                                                     pause_filter_count,
1288                                                     pause_filter_count_shrink,
1289                                                     pause_filter_count);
1290         if (control->pause_filter_count != old)
1291                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1292
1293         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1294                                     control->pause_filter_count, old);
1295 }
1296
1297 static __init int svm_hardware_setup(void)
1298 {
1299         int cpu;
1300         struct page *iopm_pages;
1301         void *iopm_va;
1302         int r;
1303
1304         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1305
1306         if (!iopm_pages)
1307                 return -ENOMEM;
1308
1309         iopm_va = page_address(iopm_pages);
1310         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1311         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1312
1313         init_msrpm_offsets();
1314
1315         if (boot_cpu_has(X86_FEATURE_NX))
1316                 kvm_enable_efer_bits(EFER_NX);
1317
1318         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1319                 kvm_enable_efer_bits(EFER_FFXSR);
1320
1321         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1322                 kvm_has_tsc_control = true;
1323                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1324                 kvm_tsc_scaling_ratio_frac_bits = 32;
1325         }
1326
1327         /* Check for pause filtering support */
1328         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1329                 pause_filter_count = 0;
1330                 pause_filter_thresh = 0;
1331         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1332                 pause_filter_thresh = 0;
1333         }
1334
1335         if (nested) {
1336                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1337                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1338         }
1339
1340         if (sev) {
1341                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1342                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1343                         r = sev_hardware_setup();
1344                         if (r)
1345                                 sev = false;
1346                 } else {
1347                         sev = false;
1348                 }
1349         }
1350
1351         for_each_possible_cpu(cpu) {
1352                 r = svm_cpu_init(cpu);
1353                 if (r)
1354                         goto err;
1355         }
1356
1357         if (!boot_cpu_has(X86_FEATURE_NPT))
1358                 npt_enabled = false;
1359
1360         if (npt_enabled && !npt) {
1361                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1362                 npt_enabled = false;
1363         }
1364
1365         if (npt_enabled) {
1366                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1367                 kvm_enable_tdp();
1368         } else
1369                 kvm_disable_tdp();
1370
1371         if (avic) {
1372                 if (!npt_enabled ||
1373                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1374                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1375                         avic = false;
1376                 } else {
1377                         pr_info("AVIC enabled\n");
1378
1379                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1380                 }
1381         }
1382
1383         if (vls) {
1384                 if (!npt_enabled ||
1385                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1386                     !IS_ENABLED(CONFIG_X86_64)) {
1387                         vls = false;
1388                 } else {
1389                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1390                 }
1391         }
1392
1393         if (vgif) {
1394                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1395                         vgif = false;
1396                 else
1397                         pr_info("Virtual GIF supported\n");
1398         }
1399
1400         return 0;
1401
1402 err:
1403         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1404         iopm_base = 0;
1405         return r;
1406 }
1407
1408 static __exit void svm_hardware_unsetup(void)
1409 {
1410         int cpu;
1411
1412         if (svm_sev_enabled())
1413                 bitmap_free(sev_asid_bitmap);
1414
1415         for_each_possible_cpu(cpu)
1416                 svm_cpu_uninit(cpu);
1417
1418         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1419         iopm_base = 0;
1420 }
1421
1422 static void init_seg(struct vmcb_seg *seg)
1423 {
1424         seg->selector = 0;
1425         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1426                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1427         seg->limit = 0xffff;
1428         seg->base = 0;
1429 }
1430
1431 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1432 {
1433         seg->selector = 0;
1434         seg->attrib = SVM_SELECTOR_P_MASK | type;
1435         seg->limit = 0xffff;
1436         seg->base = 0;
1437 }
1438
1439 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1440 {
1441         struct vcpu_svm *svm = to_svm(vcpu);
1442
1443         if (is_guest_mode(vcpu))
1444                 return svm->nested.hsave->control.tsc_offset;
1445
1446         return vcpu->arch.tsc_offset;
1447 }
1448
1449 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1450 {
1451         struct vcpu_svm *svm = to_svm(vcpu);
1452         u64 g_tsc_offset = 0;
1453
1454         if (is_guest_mode(vcpu)) {
1455                 /* Write L1's TSC offset.  */
1456                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1457                                svm->nested.hsave->control.tsc_offset;
1458                 svm->nested.hsave->control.tsc_offset = offset;
1459         } else
1460                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1461                                            svm->vmcb->control.tsc_offset,
1462                                            offset);
1463
1464         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1465
1466         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1467 }
1468
1469 static void avic_init_vmcb(struct vcpu_svm *svm)
1470 {
1471         struct vmcb *vmcb = svm->vmcb;
1472         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1473         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1474         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1475         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1476
1477         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1478         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1479         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1480         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1481         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1482 }
1483
1484 static void init_vmcb(struct vcpu_svm *svm)
1485 {
1486         struct vmcb_control_area *control = &svm->vmcb->control;
1487         struct vmcb_save_area *save = &svm->vmcb->save;
1488
1489         svm->vcpu.arch.hflags = 0;
1490
1491         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1492         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1493         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1494         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1495         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1496         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1497         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1498                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1499
1500         set_dr_intercepts(svm);
1501
1502         set_exception_intercept(svm, PF_VECTOR);
1503         set_exception_intercept(svm, UD_VECTOR);
1504         set_exception_intercept(svm, MC_VECTOR);
1505         set_exception_intercept(svm, AC_VECTOR);
1506         set_exception_intercept(svm, DB_VECTOR);
1507         /*
1508          * Guest access to VMware backdoor ports could legitimately
1509          * trigger #GP because of TSS I/O permission bitmap.
1510          * We intercept those #GP and allow access to them anyway
1511          * as VMware does.
1512          */
1513         if (enable_vmware_backdoor)
1514                 set_exception_intercept(svm, GP_VECTOR);
1515
1516         set_intercept(svm, INTERCEPT_INTR);
1517         set_intercept(svm, INTERCEPT_NMI);
1518         set_intercept(svm, INTERCEPT_SMI);
1519         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1520         set_intercept(svm, INTERCEPT_RDPMC);
1521         set_intercept(svm, INTERCEPT_CPUID);
1522         set_intercept(svm, INTERCEPT_INVD);
1523         set_intercept(svm, INTERCEPT_INVLPG);
1524         set_intercept(svm, INTERCEPT_INVLPGA);
1525         set_intercept(svm, INTERCEPT_IOIO_PROT);
1526         set_intercept(svm, INTERCEPT_MSR_PROT);
1527         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1528         set_intercept(svm, INTERCEPT_SHUTDOWN);
1529         set_intercept(svm, INTERCEPT_VMRUN);
1530         set_intercept(svm, INTERCEPT_VMMCALL);
1531         set_intercept(svm, INTERCEPT_VMLOAD);
1532         set_intercept(svm, INTERCEPT_VMSAVE);
1533         set_intercept(svm, INTERCEPT_STGI);
1534         set_intercept(svm, INTERCEPT_CLGI);
1535         set_intercept(svm, INTERCEPT_SKINIT);
1536         set_intercept(svm, INTERCEPT_WBINVD);
1537         set_intercept(svm, INTERCEPT_XSETBV);
1538         set_intercept(svm, INTERCEPT_RSM);
1539
1540         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1541                 set_intercept(svm, INTERCEPT_MONITOR);
1542                 set_intercept(svm, INTERCEPT_MWAIT);
1543         }
1544
1545         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1546                 set_intercept(svm, INTERCEPT_HLT);
1547
1548         control->iopm_base_pa = __sme_set(iopm_base);
1549         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1550         control->int_ctl = V_INTR_MASKING_MASK;
1551
1552         init_seg(&save->es);
1553         init_seg(&save->ss);
1554         init_seg(&save->ds);
1555         init_seg(&save->fs);
1556         init_seg(&save->gs);
1557
1558         save->cs.selector = 0xf000;
1559         save->cs.base = 0xffff0000;
1560         /* Executable/Readable Code Segment */
1561         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1562                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1563         save->cs.limit = 0xffff;
1564
1565         save->gdtr.limit = 0xffff;
1566         save->idtr.limit = 0xffff;
1567
1568         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1569         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1570
1571         svm_set_efer(&svm->vcpu, 0);
1572         save->dr6 = 0xffff0ff0;
1573         kvm_set_rflags(&svm->vcpu, 2);
1574         save->rip = 0x0000fff0;
1575         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1576
1577         /*
1578          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1579          * It also updates the guest-visible cr0 value.
1580          */
1581         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1582         kvm_mmu_reset_context(&svm->vcpu);
1583
1584         save->cr4 = X86_CR4_PAE;
1585         /* rdx = ?? */
1586
1587         if (npt_enabled) {
1588                 /* Setup VMCB for Nested Paging */
1589                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1590                 clr_intercept(svm, INTERCEPT_INVLPG);
1591                 clr_exception_intercept(svm, PF_VECTOR);
1592                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1593                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1594                 save->g_pat = svm->vcpu.arch.pat;
1595                 save->cr3 = 0;
1596                 save->cr4 = 0;
1597         }
1598         svm->asid_generation = 0;
1599
1600         svm->nested.vmcb = 0;
1601         svm->vcpu.arch.hflags = 0;
1602
1603         if (pause_filter_count) {
1604                 control->pause_filter_count = pause_filter_count;
1605                 if (pause_filter_thresh)
1606                         control->pause_filter_thresh = pause_filter_thresh;
1607                 set_intercept(svm, INTERCEPT_PAUSE);
1608         } else {
1609                 clr_intercept(svm, INTERCEPT_PAUSE);
1610         }
1611
1612         if (kvm_vcpu_apicv_active(&svm->vcpu))
1613                 avic_init_vmcb(svm);
1614
1615         /*
1616          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1617          * in VMCB and clear intercepts to avoid #VMEXIT.
1618          */
1619         if (vls) {
1620                 clr_intercept(svm, INTERCEPT_VMLOAD);
1621                 clr_intercept(svm, INTERCEPT_VMSAVE);
1622                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1623         }
1624
1625         if (vgif) {
1626                 clr_intercept(svm, INTERCEPT_STGI);
1627                 clr_intercept(svm, INTERCEPT_CLGI);
1628                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1629         }
1630
1631         if (sev_guest(svm->vcpu.kvm)) {
1632                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1633                 clr_exception_intercept(svm, UD_VECTOR);
1634         }
1635
1636         mark_all_dirty(svm->vmcb);
1637
1638         enable_gif(svm);
1639
1640 }
1641
1642 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1643                                        unsigned int index)
1644 {
1645         u64 *avic_physical_id_table;
1646         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1647
1648         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1649                 return NULL;
1650
1651         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1652
1653         return &avic_physical_id_table[index];
1654 }
1655
1656 /**
1657  * Note:
1658  * AVIC hardware walks the nested page table to check permissions,
1659  * but does not use the SPA address specified in the leaf page
1660  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1661  * field of the VMCB. Therefore, we set up the
1662  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1663  */
1664 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1665 {
1666         struct kvm *kvm = vcpu->kvm;
1667         int ret;
1668
1669         if (kvm->arch.apic_access_page_done)
1670                 return 0;
1671
1672         ret = x86_set_memory_region(kvm,
1673                                     APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1674                                     APIC_DEFAULT_PHYS_BASE,
1675                                     PAGE_SIZE);
1676         if (ret)
1677                 return ret;
1678
1679         kvm->arch.apic_access_page_done = true;
1680         return 0;
1681 }
1682
1683 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1684 {
1685         int ret;
1686         u64 *entry, new_entry;
1687         int id = vcpu->vcpu_id;
1688         struct vcpu_svm *svm = to_svm(vcpu);
1689
1690         ret = avic_init_access_page(vcpu);
1691         if (ret)
1692                 return ret;
1693
1694         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1695                 return -EINVAL;
1696
1697         if (!svm->vcpu.arch.apic->regs)
1698                 return -EINVAL;
1699
1700         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1701
1702         /* Setting AVIC backing page address in the phy APIC ID table */
1703         entry = avic_get_physical_id_entry(vcpu, id);
1704         if (!entry)
1705                 return -EINVAL;
1706
1707         new_entry = READ_ONCE(*entry);
1708         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1709                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1710                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1711         WRITE_ONCE(*entry, new_entry);
1712
1713         svm->avic_physical_id_cache = entry;
1714
1715         return 0;
1716 }
1717
1718 static void __sev_asid_free(int asid)
1719 {
1720         struct svm_cpu_data *sd;
1721         int cpu, pos;
1722
1723         pos = asid - 1;
1724         clear_bit(pos, sev_asid_bitmap);
1725
1726         for_each_possible_cpu(cpu) {
1727                 sd = per_cpu(svm_data, cpu);
1728                 sd->sev_vmcbs[pos] = NULL;
1729         }
1730 }
1731
1732 static void sev_asid_free(struct kvm *kvm)
1733 {
1734         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1735
1736         __sev_asid_free(sev->asid);
1737 }
1738
1739 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1740 {
1741         struct sev_data_decommission *decommission;
1742         struct sev_data_deactivate *data;
1743
1744         if (!handle)
1745                 return;
1746
1747         data = kzalloc(sizeof(*data), GFP_KERNEL);
1748         if (!data)
1749                 return;
1750
1751         /* deactivate handle */
1752         data->handle = handle;
1753         sev_guest_deactivate(data, NULL);
1754
1755         wbinvd_on_all_cpus();
1756         sev_guest_df_flush(NULL);
1757         kfree(data);
1758
1759         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1760         if (!decommission)
1761                 return;
1762
1763         /* decommission handle */
1764         decommission->handle = handle;
1765         sev_guest_decommission(decommission, NULL);
1766
1767         kfree(decommission);
1768 }
1769
1770 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1771                                     unsigned long ulen, unsigned long *n,
1772                                     int write)
1773 {
1774         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1775         unsigned long npages, npinned, size;
1776         unsigned long locked, lock_limit;
1777         struct page **pages;
1778         unsigned long first, last;
1779
1780         if (ulen == 0 || uaddr + ulen < uaddr)
1781                 return NULL;
1782
1783         /* Calculate number of pages. */
1784         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1785         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1786         npages = (last - first + 1);
1787
1788         locked = sev->pages_locked + npages;
1789         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1790         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1791                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1792                 return NULL;
1793         }
1794
1795         /* Avoid using vmalloc for smaller buffers. */
1796         size = npages * sizeof(struct page *);
1797         if (size > PAGE_SIZE)
1798                 pages = vmalloc(size);
1799         else
1800                 pages = kmalloc(size, GFP_KERNEL);
1801
1802         if (!pages)
1803                 return NULL;
1804
1805         /* Pin the user virtual address. */
1806         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1807         if (npinned != npages) {
1808                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1809                 goto err;
1810         }
1811
1812         *n = npages;
1813         sev->pages_locked = locked;
1814
1815         return pages;
1816
1817 err:
1818         if (npinned > 0)
1819                 release_pages(pages, npinned);
1820
1821         kvfree(pages);
1822         return NULL;
1823 }
1824
1825 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1826                              unsigned long npages)
1827 {
1828         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1829
1830         release_pages(pages, npages);
1831         kvfree(pages);
1832         sev->pages_locked -= npages;
1833 }
1834
1835 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1836 {
1837         uint8_t *page_virtual;
1838         unsigned long i;
1839
1840         if (npages == 0 || pages == NULL)
1841                 return;
1842
1843         for (i = 0; i < npages; i++) {
1844                 page_virtual = kmap_atomic(pages[i]);
1845                 clflush_cache_range(page_virtual, PAGE_SIZE);
1846                 kunmap_atomic(page_virtual);
1847         }
1848 }
1849
1850 static void __unregister_enc_region_locked(struct kvm *kvm,
1851                                            struct enc_region *region)
1852 {
1853         /*
1854          * The guest may change the memory encryption attribute from C=0 -> C=1
1855          * or vice versa for this memory range. Lets make sure caches are
1856          * flushed to ensure that guest data gets written into memory with
1857          * correct C-bit.
1858          */
1859         sev_clflush_pages(region->pages, region->npages);
1860
1861         sev_unpin_memory(kvm, region->pages, region->npages);
1862         list_del(&region->list);
1863         kfree(region);
1864 }
1865
1866 static struct kvm *svm_vm_alloc(void)
1867 {
1868         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1869         return &kvm_svm->kvm;
1870 }
1871
1872 static void svm_vm_free(struct kvm *kvm)
1873 {
1874         vfree(to_kvm_svm(kvm));
1875 }
1876
1877 static void sev_vm_destroy(struct kvm *kvm)
1878 {
1879         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1880         struct list_head *head = &sev->regions_list;
1881         struct list_head *pos, *q;
1882
1883         if (!sev_guest(kvm))
1884                 return;
1885
1886         mutex_lock(&kvm->lock);
1887
1888         /*
1889          * if userspace was terminated before unregistering the memory regions
1890          * then lets unpin all the registered memory.
1891          */
1892         if (!list_empty(head)) {
1893                 list_for_each_safe(pos, q, head) {
1894                         __unregister_enc_region_locked(kvm,
1895                                 list_entry(pos, struct enc_region, list));
1896                 }
1897         }
1898
1899         mutex_unlock(&kvm->lock);
1900
1901         sev_unbind_asid(kvm, sev->handle);
1902         sev_asid_free(kvm);
1903 }
1904
1905 static void avic_vm_destroy(struct kvm *kvm)
1906 {
1907         unsigned long flags;
1908         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1909
1910         if (!avic)
1911                 return;
1912
1913         if (kvm_svm->avic_logical_id_table_page)
1914                 __free_page(kvm_svm->avic_logical_id_table_page);
1915         if (kvm_svm->avic_physical_id_table_page)
1916                 __free_page(kvm_svm->avic_physical_id_table_page);
1917
1918         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1919         hash_del(&kvm_svm->hnode);
1920         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1921 }
1922
1923 static void svm_vm_destroy(struct kvm *kvm)
1924 {
1925         avic_vm_destroy(kvm);
1926         sev_vm_destroy(kvm);
1927 }
1928
1929 static int avic_vm_init(struct kvm *kvm)
1930 {
1931         unsigned long flags;
1932         int err = -ENOMEM;
1933         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1934         struct kvm_svm *k2;
1935         struct page *p_page;
1936         struct page *l_page;
1937         u32 vm_id;
1938
1939         if (!avic)
1940                 return 0;
1941
1942         /* Allocating physical APIC ID table (4KB) */
1943         p_page = alloc_page(GFP_KERNEL);
1944         if (!p_page)
1945                 goto free_avic;
1946
1947         kvm_svm->avic_physical_id_table_page = p_page;
1948         clear_page(page_address(p_page));
1949
1950         /* Allocating logical APIC ID table (4KB) */
1951         l_page = alloc_page(GFP_KERNEL);
1952         if (!l_page)
1953                 goto free_avic;
1954
1955         kvm_svm->avic_logical_id_table_page = l_page;
1956         clear_page(page_address(l_page));
1957
1958         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1959  again:
1960         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1961         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1962                 next_vm_id_wrapped = 1;
1963                 goto again;
1964         }
1965         /* Is it still in use? Only possible if wrapped at least once */
1966         if (next_vm_id_wrapped) {
1967                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1968                         if (k2->avic_vm_id == vm_id)
1969                                 goto again;
1970                 }
1971         }
1972         kvm_svm->avic_vm_id = vm_id;
1973         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1974         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1975
1976         return 0;
1977
1978 free_avic:
1979         avic_vm_destroy(kvm);
1980         return err;
1981 }
1982
1983 static inline int
1984 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1985 {
1986         int ret = 0;
1987         unsigned long flags;
1988         struct amd_svm_iommu_ir *ir;
1989         struct vcpu_svm *svm = to_svm(vcpu);
1990
1991         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1992                 return 0;
1993
1994         /*
1995          * Here, we go through the per-vcpu ir_list to update all existing
1996          * interrupt remapping table entry targeting this vcpu.
1997          */
1998         spin_lock_irqsave(&svm->ir_list_lock, flags);
1999
2000         if (list_empty(&svm->ir_list))
2001                 goto out;
2002
2003         list_for_each_entry(ir, &svm->ir_list, node) {
2004                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2005                 if (ret)
2006                         break;
2007         }
2008 out:
2009         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2010         return ret;
2011 }
2012
2013 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2014 {
2015         u64 entry;
2016         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2017         int h_physical_id = kvm_cpu_get_apicid(cpu);
2018         struct vcpu_svm *svm = to_svm(vcpu);
2019
2020         if (!kvm_vcpu_apicv_active(vcpu))
2021                 return;
2022
2023         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2024                 return;
2025
2026         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2027         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2028
2029         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2030         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2031
2032         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2033         if (svm->avic_is_running)
2034                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2035
2036         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2037         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2038                                         svm->avic_is_running);
2039 }
2040
2041 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2042 {
2043         u64 entry;
2044         struct vcpu_svm *svm = to_svm(vcpu);
2045
2046         if (!kvm_vcpu_apicv_active(vcpu))
2047                 return;
2048
2049         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2050         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2051                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2052
2053         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2054         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2055 }
2056
2057 /**
2058  * This function is called during VCPU halt/unhalt.
2059  */
2060 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2061 {
2062         struct vcpu_svm *svm = to_svm(vcpu);
2063
2064         svm->avic_is_running = is_run;
2065         if (is_run)
2066                 avic_vcpu_load(vcpu, vcpu->cpu);
2067         else
2068                 avic_vcpu_put(vcpu);
2069 }
2070
2071 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2072 {
2073         struct vcpu_svm *svm = to_svm(vcpu);
2074         u32 dummy;
2075         u32 eax = 1;
2076
2077         vcpu->arch.microcode_version = 0x01000065;
2078         svm->spec_ctrl = 0;
2079         svm->virt_spec_ctrl = 0;
2080
2081         if (!init_event) {
2082                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2083                                            MSR_IA32_APICBASE_ENABLE;
2084                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2085                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2086         }
2087         init_vmcb(svm);
2088
2089         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2090         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2091
2092         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2093                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2094 }
2095
2096 static int avic_init_vcpu(struct vcpu_svm *svm)
2097 {
2098         int ret;
2099
2100         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2101                 return 0;
2102
2103         ret = avic_init_backing_page(&svm->vcpu);
2104         if (ret)
2105                 return ret;
2106
2107         INIT_LIST_HEAD(&svm->ir_list);
2108         spin_lock_init(&svm->ir_list_lock);
2109
2110         return ret;
2111 }
2112
2113 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2114 {
2115         struct vcpu_svm *svm;
2116         struct page *page;
2117         struct page *msrpm_pages;
2118         struct page *hsave_page;
2119         struct page *nested_msrpm_pages;
2120         int err;
2121
2122         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2123         if (!svm) {
2124                 err = -ENOMEM;
2125                 goto out;
2126         }
2127
2128         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2129         if (err)
2130                 goto free_svm;
2131
2132         err = -ENOMEM;
2133         page = alloc_page(GFP_KERNEL);
2134         if (!page)
2135                 goto uninit;
2136
2137         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2138         if (!msrpm_pages)
2139                 goto free_page1;
2140
2141         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2142         if (!nested_msrpm_pages)
2143                 goto free_page2;
2144
2145         hsave_page = alloc_page(GFP_KERNEL);
2146         if (!hsave_page)
2147                 goto free_page3;
2148
2149         err = avic_init_vcpu(svm);
2150         if (err)
2151                 goto free_page4;
2152
2153         /* We initialize this flag to true to make sure that the is_running
2154          * bit would be set the first time the vcpu is loaded.
2155          */
2156         svm->avic_is_running = true;
2157
2158         svm->nested.hsave = page_address(hsave_page);
2159
2160         svm->msrpm = page_address(msrpm_pages);
2161         svm_vcpu_init_msrpm(svm->msrpm);
2162
2163         svm->nested.msrpm = page_address(nested_msrpm_pages);
2164         svm_vcpu_init_msrpm(svm->nested.msrpm);
2165
2166         svm->vmcb = page_address(page);
2167         clear_page(svm->vmcb);
2168         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2169         svm->asid_generation = 0;
2170         init_vmcb(svm);
2171
2172         svm_init_osvw(&svm->vcpu);
2173
2174         return &svm->vcpu;
2175
2176 free_page4:
2177         __free_page(hsave_page);
2178 free_page3:
2179         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2180 free_page2:
2181         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2182 free_page1:
2183         __free_page(page);
2184 uninit:
2185         kvm_vcpu_uninit(&svm->vcpu);
2186 free_svm:
2187         kmem_cache_free(kvm_vcpu_cache, svm);
2188 out:
2189         return ERR_PTR(err);
2190 }
2191
2192 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2193 {
2194         struct vcpu_svm *svm = to_svm(vcpu);
2195
2196         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2197         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2198         __free_page(virt_to_page(svm->nested.hsave));
2199         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2200         kvm_vcpu_uninit(vcpu);
2201         kmem_cache_free(kvm_vcpu_cache, svm);
2202         /*
2203          * The vmcb page can be recycled, causing a false negative in
2204          * svm_vcpu_load(). So do a full IBPB now.
2205          */
2206         indirect_branch_prediction_barrier();
2207 }
2208
2209 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2210 {
2211         struct vcpu_svm *svm = to_svm(vcpu);
2212         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2213         int i;
2214
2215         if (unlikely(cpu != vcpu->cpu)) {
2216                 svm->asid_generation = 0;
2217                 mark_all_dirty(svm->vmcb);
2218         }
2219
2220 #ifdef CONFIG_X86_64
2221         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2222 #endif
2223         savesegment(fs, svm->host.fs);
2224         savesegment(gs, svm->host.gs);
2225         svm->host.ldt = kvm_read_ldt();
2226
2227         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2228                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2229
2230         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2231                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2232                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2233                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2234                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2235                 }
2236         }
2237         /* This assumes that the kernel never uses MSR_TSC_AUX */
2238         if (static_cpu_has(X86_FEATURE_RDTSCP))
2239                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2240
2241         if (sd->current_vmcb != svm->vmcb) {
2242                 sd->current_vmcb = svm->vmcb;
2243                 indirect_branch_prediction_barrier();
2244         }
2245         avic_vcpu_load(vcpu, cpu);
2246 }
2247
2248 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2249 {
2250         struct vcpu_svm *svm = to_svm(vcpu);
2251         int i;
2252
2253         avic_vcpu_put(vcpu);
2254
2255         ++vcpu->stat.host_state_reload;
2256         kvm_load_ldt(svm->host.ldt);
2257 #ifdef CONFIG_X86_64
2258         loadsegment(fs, svm->host.fs);
2259         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2260         load_gs_index(svm->host.gs);
2261 #else
2262 #ifdef CONFIG_X86_32_LAZY_GS
2263         loadsegment(gs, svm->host.gs);
2264 #endif
2265 #endif
2266         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2267                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2268 }
2269
2270 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2271 {
2272         avic_set_running(vcpu, false);
2273 }
2274
2275 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2276 {
2277         avic_set_running(vcpu, true);
2278 }
2279
2280 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2281 {
2282         struct vcpu_svm *svm = to_svm(vcpu);
2283         unsigned long rflags = svm->vmcb->save.rflags;
2284
2285         if (svm->nmi_singlestep) {
2286                 /* Hide our flags if they were not set by the guest */
2287                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2288                         rflags &= ~X86_EFLAGS_TF;
2289                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2290                         rflags &= ~X86_EFLAGS_RF;
2291         }
2292         return rflags;
2293 }
2294
2295 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2296 {
2297         if (to_svm(vcpu)->nmi_singlestep)
2298                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2299
2300        /*
2301         * Any change of EFLAGS.VM is accompanied by a reload of SS
2302         * (caused by either a task switch or an inter-privilege IRET),
2303         * so we do not need to update the CPL here.
2304         */
2305         to_svm(vcpu)->vmcb->save.rflags = rflags;
2306 }
2307
2308 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2309 {
2310         switch (reg) {
2311         case VCPU_EXREG_PDPTR:
2312                 BUG_ON(!npt_enabled);
2313                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2314                 break;
2315         default:
2316                 BUG();
2317         }
2318 }
2319
2320 static void svm_set_vintr(struct vcpu_svm *svm)
2321 {
2322         set_intercept(svm, INTERCEPT_VINTR);
2323 }
2324
2325 static void svm_clear_vintr(struct vcpu_svm *svm)
2326 {
2327         clr_intercept(svm, INTERCEPT_VINTR);
2328 }
2329
2330 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2331 {
2332         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2333
2334         switch (seg) {
2335         case VCPU_SREG_CS: return &save->cs;
2336         case VCPU_SREG_DS: return &save->ds;
2337         case VCPU_SREG_ES: return &save->es;
2338         case VCPU_SREG_FS: return &save->fs;
2339         case VCPU_SREG_GS: return &save->gs;
2340         case VCPU_SREG_SS: return &save->ss;
2341         case VCPU_SREG_TR: return &save->tr;
2342         case VCPU_SREG_LDTR: return &save->ldtr;
2343         }
2344         BUG();
2345         return NULL;
2346 }
2347
2348 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2349 {
2350         struct vmcb_seg *s = svm_seg(vcpu, seg);
2351
2352         return s->base;
2353 }
2354
2355 static void svm_get_segment(struct kvm_vcpu *vcpu,
2356                             struct kvm_segment *var, int seg)
2357 {
2358         struct vmcb_seg *s = svm_seg(vcpu, seg);
2359
2360         var->base = s->base;
2361         var->limit = s->limit;
2362         var->selector = s->selector;
2363         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2364         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2365         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2366         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2367         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2368         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2369         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2370
2371         /*
2372          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2373          * However, the SVM spec states that the G bit is not observed by the
2374          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2375          * So let's synthesize a legal G bit for all segments, this helps
2376          * running KVM nested. It also helps cross-vendor migration, because
2377          * Intel's vmentry has a check on the 'G' bit.
2378          */
2379         var->g = s->limit > 0xfffff;
2380
2381         /*
2382          * AMD's VMCB does not have an explicit unusable field, so emulate it
2383          * for cross vendor migration purposes by "not present"
2384          */
2385         var->unusable = !var->present;
2386
2387         switch (seg) {
2388         case VCPU_SREG_TR:
2389                 /*
2390                  * Work around a bug where the busy flag in the tr selector
2391                  * isn't exposed
2392                  */
2393                 var->type |= 0x2;
2394                 break;
2395         case VCPU_SREG_DS:
2396         case VCPU_SREG_ES:
2397         case VCPU_SREG_FS:
2398         case VCPU_SREG_GS:
2399                 /*
2400                  * The accessed bit must always be set in the segment
2401                  * descriptor cache, although it can be cleared in the
2402                  * descriptor, the cached bit always remains at 1. Since
2403                  * Intel has a check on this, set it here to support
2404                  * cross-vendor migration.
2405                  */
2406                 if (!var->unusable)
2407                         var->type |= 0x1;
2408                 break;
2409         case VCPU_SREG_SS:
2410                 /*
2411                  * On AMD CPUs sometimes the DB bit in the segment
2412                  * descriptor is left as 1, although the whole segment has
2413                  * been made unusable. Clear it here to pass an Intel VMX
2414                  * entry check when cross vendor migrating.
2415                  */
2416                 if (var->unusable)
2417                         var->db = 0;
2418                 /* This is symmetric with svm_set_segment() */
2419                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2420                 break;
2421         }
2422 }
2423
2424 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2425 {
2426         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2427
2428         return save->cpl;
2429 }
2430
2431 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2432 {
2433         struct vcpu_svm *svm = to_svm(vcpu);
2434
2435         dt->size = svm->vmcb->save.idtr.limit;
2436         dt->address = svm->vmcb->save.idtr.base;
2437 }
2438
2439 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2440 {
2441         struct vcpu_svm *svm = to_svm(vcpu);
2442
2443         svm->vmcb->save.idtr.limit = dt->size;
2444         svm->vmcb->save.idtr.base = dt->address ;
2445         mark_dirty(svm->vmcb, VMCB_DT);
2446 }
2447
2448 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2449 {
2450         struct vcpu_svm *svm = to_svm(vcpu);
2451
2452         dt->size = svm->vmcb->save.gdtr.limit;
2453         dt->address = svm->vmcb->save.gdtr.base;
2454 }
2455
2456 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2457 {
2458         struct vcpu_svm *svm = to_svm(vcpu);
2459
2460         svm->vmcb->save.gdtr.limit = dt->size;
2461         svm->vmcb->save.gdtr.base = dt->address ;
2462         mark_dirty(svm->vmcb, VMCB_DT);
2463 }
2464
2465 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2466 {
2467 }
2468
2469 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2470 {
2471 }
2472
2473 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2474 {
2475 }
2476
2477 static void update_cr0_intercept(struct vcpu_svm *svm)
2478 {
2479         ulong gcr0 = svm->vcpu.arch.cr0;
2480         u64 *hcr0 = &svm->vmcb->save.cr0;
2481
2482         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2483                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2484
2485         mark_dirty(svm->vmcb, VMCB_CR);
2486
2487         if (gcr0 == *hcr0) {
2488                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2489                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2490         } else {
2491                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2492                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2493         }
2494 }
2495
2496 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2497 {
2498         struct vcpu_svm *svm = to_svm(vcpu);
2499
2500 #ifdef CONFIG_X86_64
2501         if (vcpu->arch.efer & EFER_LME) {
2502                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2503                         vcpu->arch.efer |= EFER_LMA;
2504                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2505                 }
2506
2507                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2508                         vcpu->arch.efer &= ~EFER_LMA;
2509                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2510                 }
2511         }
2512 #endif
2513         vcpu->arch.cr0 = cr0;
2514
2515         if (!npt_enabled)
2516                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2517
2518         /*
2519          * re-enable caching here because the QEMU bios
2520          * does not do it - this results in some delay at
2521          * reboot
2522          */
2523         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2524                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2525         svm->vmcb->save.cr0 = cr0;
2526         mark_dirty(svm->vmcb, VMCB_CR);
2527         update_cr0_intercept(svm);
2528 }
2529
2530 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2531 {
2532         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2533         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2534
2535         if (cr4 & X86_CR4_VMXE)
2536                 return 1;
2537
2538         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2539                 svm_flush_tlb(vcpu, true);
2540
2541         vcpu->arch.cr4 = cr4;
2542         if (!npt_enabled)
2543                 cr4 |= X86_CR4_PAE;
2544         cr4 |= host_cr4_mce;
2545         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2546         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2547         return 0;
2548 }
2549
2550 static void svm_set_segment(struct kvm_vcpu *vcpu,
2551                             struct kvm_segment *var, int seg)
2552 {
2553         struct vcpu_svm *svm = to_svm(vcpu);
2554         struct vmcb_seg *s = svm_seg(vcpu, seg);
2555
2556         s->base = var->base;
2557         s->limit = var->limit;
2558         s->selector = var->selector;
2559         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2560         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2561         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2562         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2563         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2564         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2565         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2566         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2567
2568         /*
2569          * This is always accurate, except if SYSRET returned to a segment
2570          * with SS.DPL != 3.  Intel does not have this quirk, and always
2571          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2572          * would entail passing the CPL to userspace and back.
2573          */
2574         if (seg == VCPU_SREG_SS)
2575                 /* This is symmetric with svm_get_segment() */
2576                 svm->vmcb->save.cpl = (var->dpl & 3);
2577
2578         mark_dirty(svm->vmcb, VMCB_SEG);
2579 }
2580
2581 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2582 {
2583         struct vcpu_svm *svm = to_svm(vcpu);
2584
2585         clr_exception_intercept(svm, BP_VECTOR);
2586
2587         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2588                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2589                         set_exception_intercept(svm, BP_VECTOR);
2590         } else
2591                 vcpu->guest_debug = 0;
2592 }
2593
2594 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2595 {
2596         if (sd->next_asid > sd->max_asid) {
2597                 ++sd->asid_generation;
2598                 sd->next_asid = sd->min_asid;
2599                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2600         }
2601
2602         svm->asid_generation = sd->asid_generation;
2603         svm->vmcb->control.asid = sd->next_asid++;
2604
2605         mark_dirty(svm->vmcb, VMCB_ASID);
2606 }
2607
2608 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2609 {
2610         return to_svm(vcpu)->vmcb->save.dr6;
2611 }
2612
2613 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2614 {
2615         struct vcpu_svm *svm = to_svm(vcpu);
2616
2617         svm->vmcb->save.dr6 = value;
2618         mark_dirty(svm->vmcb, VMCB_DR);
2619 }
2620
2621 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2622 {
2623         struct vcpu_svm *svm = to_svm(vcpu);
2624
2625         get_debugreg(vcpu->arch.db[0], 0);
2626         get_debugreg(vcpu->arch.db[1], 1);
2627         get_debugreg(vcpu->arch.db[2], 2);
2628         get_debugreg(vcpu->arch.db[3], 3);
2629         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2630         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2631
2632         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2633         set_dr_intercepts(svm);
2634 }
2635
2636 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2637 {
2638         struct vcpu_svm *svm = to_svm(vcpu);
2639
2640         svm->vmcb->save.dr7 = value;
2641         mark_dirty(svm->vmcb, VMCB_DR);
2642 }
2643
2644 static int pf_interception(struct vcpu_svm *svm)
2645 {
2646         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2647         u64 error_code = svm->vmcb->control.exit_info_1;
2648
2649         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2650                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2651                         svm->vmcb->control.insn_bytes : NULL,
2652                         svm->vmcb->control.insn_len);
2653 }
2654
2655 static int npf_interception(struct vcpu_svm *svm)
2656 {
2657         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2658         u64 error_code = svm->vmcb->control.exit_info_1;
2659
2660         trace_kvm_page_fault(fault_address, error_code);
2661         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2662                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2663                         svm->vmcb->control.insn_bytes : NULL,
2664                         svm->vmcb->control.insn_len);
2665 }
2666
2667 static int db_interception(struct vcpu_svm *svm)
2668 {
2669         struct kvm_run *kvm_run = svm->vcpu.run;
2670
2671         if (!(svm->vcpu.guest_debug &
2672               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2673                 !svm->nmi_singlestep) {
2674                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2675                 return 1;
2676         }
2677
2678         if (svm->nmi_singlestep) {
2679                 disable_nmi_singlestep(svm);
2680         }
2681
2682         if (svm->vcpu.guest_debug &
2683             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2684                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2685                 kvm_run->debug.arch.pc =
2686                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2687                 kvm_run->debug.arch.exception = DB_VECTOR;
2688                 return 0;
2689         }
2690
2691         return 1;
2692 }
2693
2694 static int bp_interception(struct vcpu_svm *svm)
2695 {
2696         struct kvm_run *kvm_run = svm->vcpu.run;
2697
2698         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2699         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2700         kvm_run->debug.arch.exception = BP_VECTOR;
2701         return 0;
2702 }
2703
2704 static int ud_interception(struct vcpu_svm *svm)
2705 {
2706         return handle_ud(&svm->vcpu);
2707 }
2708
2709 static int ac_interception(struct vcpu_svm *svm)
2710 {
2711         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2712         return 1;
2713 }
2714
2715 static int gp_interception(struct vcpu_svm *svm)
2716 {
2717         struct kvm_vcpu *vcpu = &svm->vcpu;
2718         u32 error_code = svm->vmcb->control.exit_info_1;
2719         int er;
2720
2721         WARN_ON_ONCE(!enable_vmware_backdoor);
2722
2723         er = kvm_emulate_instruction(vcpu,
2724                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2725         if (er == EMULATE_USER_EXIT)
2726                 return 0;
2727         else if (er != EMULATE_DONE)
2728                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2729         return 1;
2730 }
2731
2732 static bool is_erratum_383(void)
2733 {
2734         int err, i;
2735         u64 value;
2736
2737         if (!erratum_383_found)
2738                 return false;
2739
2740         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2741         if (err)
2742                 return false;
2743
2744         /* Bit 62 may or may not be set for this mce */
2745         value &= ~(1ULL << 62);
2746
2747         if (value != 0xb600000000010015ULL)
2748                 return false;
2749
2750         /* Clear MCi_STATUS registers */
2751         for (i = 0; i < 6; ++i)
2752                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2753
2754         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2755         if (!err) {
2756                 u32 low, high;
2757
2758                 value &= ~(1ULL << 2);
2759                 low    = lower_32_bits(value);
2760                 high   = upper_32_bits(value);
2761
2762                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2763         }
2764
2765         /* Flush tlb to evict multi-match entries */
2766         __flush_tlb_all();
2767
2768         return true;
2769 }
2770
2771 static void svm_handle_mce(struct vcpu_svm *svm)
2772 {
2773         if (is_erratum_383()) {
2774                 /*
2775                  * Erratum 383 triggered. Guest state is corrupt so kill the
2776                  * guest.
2777                  */
2778                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2779
2780                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2781
2782                 return;
2783         }
2784
2785         /*
2786          * On an #MC intercept the MCE handler is not called automatically in
2787          * the host. So do it by hand here.
2788          */
2789         asm volatile (
2790                 "int $0x12\n");
2791         /* not sure if we ever come back to this point */
2792
2793         return;
2794 }
2795
2796 static int mc_interception(struct vcpu_svm *svm)
2797 {
2798         return 1;
2799 }
2800
2801 static int shutdown_interception(struct vcpu_svm *svm)
2802 {
2803         struct kvm_run *kvm_run = svm->vcpu.run;
2804
2805         /*
2806          * VMCB is undefined after a SHUTDOWN intercept
2807          * so reinitialize it.
2808          */
2809         clear_page(svm->vmcb);
2810         init_vmcb(svm);
2811
2812         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2813         return 0;
2814 }
2815
2816 static int io_interception(struct vcpu_svm *svm)
2817 {
2818         struct kvm_vcpu *vcpu = &svm->vcpu;
2819         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2820         int size, in, string;
2821         unsigned port;
2822
2823         ++svm->vcpu.stat.io_exits;
2824         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2825         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2826         if (string)
2827                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2828
2829         port = io_info >> 16;
2830         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2831         svm->next_rip = svm->vmcb->control.exit_info_2;
2832
2833         return kvm_fast_pio(&svm->vcpu, size, port, in);
2834 }
2835
2836 static int nmi_interception(struct vcpu_svm *svm)
2837 {
2838         return 1;
2839 }
2840
2841 static int intr_interception(struct vcpu_svm *svm)
2842 {
2843         ++svm->vcpu.stat.irq_exits;
2844         return 1;
2845 }
2846
2847 static int nop_on_interception(struct vcpu_svm *svm)
2848 {
2849         return 1;
2850 }
2851
2852 static int halt_interception(struct vcpu_svm *svm)
2853 {
2854         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2855         return kvm_emulate_halt(&svm->vcpu);
2856 }
2857
2858 static int vmmcall_interception(struct vcpu_svm *svm)
2859 {
2860         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2861         return kvm_emulate_hypercall(&svm->vcpu);
2862 }
2863
2864 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2865 {
2866         struct vcpu_svm *svm = to_svm(vcpu);
2867
2868         return svm->nested.nested_cr3;
2869 }
2870
2871 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2872 {
2873         struct vcpu_svm *svm = to_svm(vcpu);
2874         u64 cr3 = svm->nested.nested_cr3;
2875         u64 pdpte;
2876         int ret;
2877
2878         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2879                                        offset_in_page(cr3) + index * 8, 8);
2880         if (ret)
2881                 return 0;
2882         return pdpte;
2883 }
2884
2885 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2886                                    unsigned long root)
2887 {
2888         struct vcpu_svm *svm = to_svm(vcpu);
2889
2890         svm->vmcb->control.nested_cr3 = __sme_set(root);
2891         mark_dirty(svm->vmcb, VMCB_NPT);
2892 }
2893
2894 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2895                                        struct x86_exception *fault)
2896 {
2897         struct vcpu_svm *svm = to_svm(vcpu);
2898
2899         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2900                 /*
2901                  * TODO: track the cause of the nested page fault, and
2902                  * correctly fill in the high bits of exit_info_1.
2903                  */
2904                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2905                 svm->vmcb->control.exit_code_hi = 0;
2906                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2907                 svm->vmcb->control.exit_info_2 = fault->address;
2908         }
2909
2910         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2911         svm->vmcb->control.exit_info_1 |= fault->error_code;
2912
2913         /*
2914          * The present bit is always zero for page structure faults on real
2915          * hardware.
2916          */
2917         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2918                 svm->vmcb->control.exit_info_1 &= ~1;
2919
2920         nested_svm_vmexit(svm);
2921 }
2922
2923 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2924 {
2925         WARN_ON(mmu_is_nested(vcpu));
2926         kvm_init_shadow_mmu(vcpu);
2927         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2928         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2929         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2930         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2931         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2932         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2933         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2934 }
2935
2936 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2937 {
2938         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2939 }
2940
2941 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2942 {
2943         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2944             !is_paging(&svm->vcpu)) {
2945                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2946                 return 1;
2947         }
2948
2949         if (svm->vmcb->save.cpl) {
2950                 kvm_inject_gp(&svm->vcpu, 0);
2951                 return 1;
2952         }
2953
2954         return 0;
2955 }
2956
2957 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2958                                       bool has_error_code, u32 error_code)
2959 {
2960         int vmexit;
2961
2962         if (!is_guest_mode(&svm->vcpu))
2963                 return 0;
2964
2965         vmexit = nested_svm_intercept(svm);
2966         if (vmexit != NESTED_EXIT_DONE)
2967                 return 0;
2968
2969         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2970         svm->vmcb->control.exit_code_hi = 0;
2971         svm->vmcb->control.exit_info_1 = error_code;
2972
2973         /*
2974          * EXITINFO2 is undefined for all exception intercepts other
2975          * than #PF.
2976          */
2977         if (svm->vcpu.arch.exception.nested_apf)
2978                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2979         else if (svm->vcpu.arch.exception.has_payload)
2980                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
2981         else
2982                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2983
2984         svm->nested.exit_required = true;
2985         return vmexit;
2986 }
2987
2988 /* This function returns true if it is save to enable the irq window */
2989 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2990 {
2991         if (!is_guest_mode(&svm->vcpu))
2992                 return true;
2993
2994         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2995                 return true;
2996
2997         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2998                 return false;
2999
3000         /*
3001          * if vmexit was already requested (by intercepted exception
3002          * for instance) do not overwrite it with "external interrupt"
3003          * vmexit.
3004          */
3005         if (svm->nested.exit_required)
3006                 return false;
3007
3008         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3009         svm->vmcb->control.exit_info_1 = 0;
3010         svm->vmcb->control.exit_info_2 = 0;
3011
3012         if (svm->nested.intercept & 1ULL) {
3013                 /*
3014                  * The #vmexit can't be emulated here directly because this
3015                  * code path runs with irqs and preemption disabled. A
3016                  * #vmexit emulation might sleep. Only signal request for
3017                  * the #vmexit here.
3018                  */
3019                 svm->nested.exit_required = true;
3020                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3021                 return false;
3022         }
3023
3024         return true;
3025 }
3026
3027 /* This function returns true if it is save to enable the nmi window */
3028 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3029 {
3030         if (!is_guest_mode(&svm->vcpu))
3031                 return true;
3032
3033         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3034                 return true;
3035
3036         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3037         svm->nested.exit_required = true;
3038
3039         return false;
3040 }
3041
3042 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3043 {
3044         struct page *page;
3045
3046         might_sleep();
3047
3048         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3049         if (is_error_page(page))
3050                 goto error;
3051
3052         *_page = page;
3053
3054         return kmap(page);
3055
3056 error:
3057         kvm_inject_gp(&svm->vcpu, 0);
3058
3059         return NULL;
3060 }
3061
3062 static void nested_svm_unmap(struct page *page)
3063 {
3064         kunmap(page);
3065         kvm_release_page_dirty(page);
3066 }
3067
3068 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3069 {
3070         unsigned port, size, iopm_len;
3071         u16 val, mask;
3072         u8 start_bit;
3073         u64 gpa;
3074
3075         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3076                 return NESTED_EXIT_HOST;
3077
3078         port = svm->vmcb->control.exit_info_1 >> 16;
3079         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3080                 SVM_IOIO_SIZE_SHIFT;
3081         gpa  = svm->nested.vmcb_iopm + (port / 8);
3082         start_bit = port % 8;
3083         iopm_len = (start_bit + size > 8) ? 2 : 1;
3084         mask = (0xf >> (4 - size)) << start_bit;
3085         val = 0;
3086
3087         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3088                 return NESTED_EXIT_DONE;
3089
3090         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3091 }
3092
3093 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3094 {
3095         u32 offset, msr, value;
3096         int write, mask;
3097
3098         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3099                 return NESTED_EXIT_HOST;
3100
3101         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3102         offset = svm_msrpm_offset(msr);
3103         write  = svm->vmcb->control.exit_info_1 & 1;
3104         mask   = 1 << ((2 * (msr & 0xf)) + write);
3105
3106         if (offset == MSR_INVALID)
3107                 return NESTED_EXIT_DONE;
3108
3109         /* Offset is in 32 bit units but need in 8 bit units */
3110         offset *= 4;
3111
3112         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3113                 return NESTED_EXIT_DONE;
3114
3115         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3116 }
3117
3118 /* DB exceptions for our internal use must not cause vmexit */
3119 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3120 {
3121         unsigned long dr6;
3122
3123         /* if we're not singlestepping, it's not ours */
3124         if (!svm->nmi_singlestep)
3125                 return NESTED_EXIT_DONE;
3126
3127         /* if it's not a singlestep exception, it's not ours */
3128         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3129                 return NESTED_EXIT_DONE;
3130         if (!(dr6 & DR6_BS))
3131                 return NESTED_EXIT_DONE;
3132
3133         /* if the guest is singlestepping, it should get the vmexit */
3134         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3135                 disable_nmi_singlestep(svm);
3136                 return NESTED_EXIT_DONE;
3137         }
3138
3139         /* it's ours, the nested hypervisor must not see this one */
3140         return NESTED_EXIT_HOST;
3141 }
3142
3143 static int nested_svm_exit_special(struct vcpu_svm *svm)
3144 {
3145         u32 exit_code = svm->vmcb->control.exit_code;
3146
3147         switch (exit_code) {
3148         case SVM_EXIT_INTR:
3149         case SVM_EXIT_NMI:
3150         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3151                 return NESTED_EXIT_HOST;
3152         case SVM_EXIT_NPF:
3153                 /* For now we are always handling NPFs when using them */
3154                 if (npt_enabled)
3155                         return NESTED_EXIT_HOST;
3156                 break;
3157         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3158                 /* When we're shadowing, trap PFs, but not async PF */
3159                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3160                         return NESTED_EXIT_HOST;
3161                 break;
3162         default:
3163                 break;
3164         }
3165
3166         return NESTED_EXIT_CONTINUE;
3167 }
3168
3169 /*
3170  * If this function returns true, this #vmexit was already handled
3171  */
3172 static int nested_svm_intercept(struct vcpu_svm *svm)
3173 {
3174         u32 exit_code = svm->vmcb->control.exit_code;
3175         int vmexit = NESTED_EXIT_HOST;
3176
3177         switch (exit_code) {
3178         case SVM_EXIT_MSR:
3179                 vmexit = nested_svm_exit_handled_msr(svm);
3180                 break;
3181         case SVM_EXIT_IOIO:
3182                 vmexit = nested_svm_intercept_ioio(svm);
3183                 break;
3184         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3185                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3186                 if (svm->nested.intercept_cr & bit)
3187                         vmexit = NESTED_EXIT_DONE;
3188                 break;
3189         }
3190         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3191                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3192                 if (svm->nested.intercept_dr & bit)
3193                         vmexit = NESTED_EXIT_DONE;
3194                 break;
3195         }
3196         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3197                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3198                 if (svm->nested.intercept_exceptions & excp_bits) {
3199                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3200                                 vmexit = nested_svm_intercept_db(svm);
3201                         else
3202                                 vmexit = NESTED_EXIT_DONE;
3203                 }
3204                 /* async page fault always cause vmexit */
3205                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3206                          svm->vcpu.arch.exception.nested_apf != 0)
3207                         vmexit = NESTED_EXIT_DONE;
3208                 break;
3209         }
3210         case SVM_EXIT_ERR: {
3211                 vmexit = NESTED_EXIT_DONE;
3212                 break;
3213         }
3214         default: {
3215                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3216                 if (svm->nested.intercept & exit_bits)
3217                         vmexit = NESTED_EXIT_DONE;
3218         }
3219         }
3220
3221         return vmexit;
3222 }
3223
3224 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3225 {
3226         int vmexit;
3227
3228         vmexit = nested_svm_intercept(svm);
3229
3230         if (vmexit == NESTED_EXIT_DONE)
3231                 nested_svm_vmexit(svm);
3232
3233         return vmexit;
3234 }
3235
3236 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3237 {
3238         struct vmcb_control_area *dst  = &dst_vmcb->control;
3239         struct vmcb_control_area *from = &from_vmcb->control;
3240
3241         dst->intercept_cr         = from->intercept_cr;
3242         dst->intercept_dr         = from->intercept_dr;
3243         dst->intercept_exceptions = from->intercept_exceptions;
3244         dst->intercept            = from->intercept;
3245         dst->iopm_base_pa         = from->iopm_base_pa;
3246         dst->msrpm_base_pa        = from->msrpm_base_pa;
3247         dst->tsc_offset           = from->tsc_offset;
3248         dst->asid                 = from->asid;
3249         dst->tlb_ctl              = from->tlb_ctl;
3250         dst->int_ctl              = from->int_ctl;
3251         dst->int_vector           = from->int_vector;
3252         dst->int_state            = from->int_state;
3253         dst->exit_code            = from->exit_code;
3254         dst->exit_code_hi         = from->exit_code_hi;
3255         dst->exit_info_1          = from->exit_info_1;
3256         dst->exit_info_2          = from->exit_info_2;
3257         dst->exit_int_info        = from->exit_int_info;
3258         dst->exit_int_info_err    = from->exit_int_info_err;
3259         dst->nested_ctl           = from->nested_ctl;
3260         dst->event_inj            = from->event_inj;
3261         dst->event_inj_err        = from->event_inj_err;
3262         dst->nested_cr3           = from->nested_cr3;
3263         dst->virt_ext              = from->virt_ext;
3264 }
3265
3266 static int nested_svm_vmexit(struct vcpu_svm *svm)
3267 {
3268         struct vmcb *nested_vmcb;
3269         struct vmcb *hsave = svm->nested.hsave;
3270         struct vmcb *vmcb = svm->vmcb;
3271         struct page *page;
3272
3273         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3274                                        vmcb->control.exit_info_1,
3275                                        vmcb->control.exit_info_2,
3276                                        vmcb->control.exit_int_info,
3277                                        vmcb->control.exit_int_info_err,
3278                                        KVM_ISA_SVM);
3279
3280         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3281         if (!nested_vmcb)
3282                 return 1;
3283
3284         /* Exit Guest-Mode */
3285         leave_guest_mode(&svm->vcpu);
3286         svm->nested.vmcb = 0;
3287
3288         /* Give the current vmcb to the guest */
3289         disable_gif(svm);
3290
3291         nested_vmcb->save.es     = vmcb->save.es;
3292         nested_vmcb->save.cs     = vmcb->save.cs;
3293         nested_vmcb->save.ss     = vmcb->save.ss;
3294         nested_vmcb->save.ds     = vmcb->save.ds;
3295         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3296         nested_vmcb->save.idtr   = vmcb->save.idtr;
3297         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3298         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3299         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3300         nested_vmcb->save.cr2    = vmcb->save.cr2;
3301         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3302         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3303         nested_vmcb->save.rip    = vmcb->save.rip;
3304         nested_vmcb->save.rsp    = vmcb->save.rsp;
3305         nested_vmcb->save.rax    = vmcb->save.rax;
3306         nested_vmcb->save.dr7    = vmcb->save.dr7;
3307         nested_vmcb->save.dr6    = vmcb->save.dr6;
3308         nested_vmcb->save.cpl    = vmcb->save.cpl;
3309
3310         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3311         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3312         nested_vmcb->control.int_state         = vmcb->control.int_state;
3313         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3314         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3315         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3316         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3317         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3318         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3319
3320         if (svm->nrips_enabled)
3321                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3322
3323         /*
3324          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3325          * to make sure that we do not lose injected events. So check event_inj
3326          * here and copy it to exit_int_info if it is valid.
3327          * Exit_int_info and event_inj can't be both valid because the case
3328          * below only happens on a VMRUN instruction intercept which has
3329          * no valid exit_int_info set.
3330          */
3331         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3332                 struct vmcb_control_area *nc = &nested_vmcb->control;
3333
3334                 nc->exit_int_info     = vmcb->control.event_inj;
3335                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3336         }
3337
3338         nested_vmcb->control.tlb_ctl           = 0;
3339         nested_vmcb->control.event_inj         = 0;
3340         nested_vmcb->control.event_inj_err     = 0;
3341
3342         /* We always set V_INTR_MASKING and remember the old value in hflags */
3343         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3344                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3345
3346         /* Restore the original control entries */
3347         copy_vmcb_control_area(vmcb, hsave);
3348
3349         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3350         kvm_clear_exception_queue(&svm->vcpu);
3351         kvm_clear_interrupt_queue(&svm->vcpu);
3352
3353         svm->nested.nested_cr3 = 0;
3354
3355         /* Restore selected save entries */
3356         svm->vmcb->save.es = hsave->save.es;
3357         svm->vmcb->save.cs = hsave->save.cs;
3358         svm->vmcb->save.ss = hsave->save.ss;
3359         svm->vmcb->save.ds = hsave->save.ds;
3360         svm->vmcb->save.gdtr = hsave->save.gdtr;
3361         svm->vmcb->save.idtr = hsave->save.idtr;
3362         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3363         svm_set_efer(&svm->vcpu, hsave->save.efer);
3364         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3365         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3366         if (npt_enabled) {
3367                 svm->vmcb->save.cr3 = hsave->save.cr3;
3368                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3369         } else {
3370                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3371         }
3372         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3373         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3374         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3375         svm->vmcb->save.dr7 = 0;
3376         svm->vmcb->save.cpl = 0;
3377         svm->vmcb->control.exit_int_info = 0;
3378
3379         mark_all_dirty(svm->vmcb);
3380
3381         nested_svm_unmap(page);
3382
3383         nested_svm_uninit_mmu_context(&svm->vcpu);
3384         kvm_mmu_reset_context(&svm->vcpu);
3385         kvm_mmu_load(&svm->vcpu);
3386
3387         return 0;
3388 }
3389
3390 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3391 {
3392         /*
3393          * This function merges the msr permission bitmaps of kvm and the
3394          * nested vmcb. It is optimized in that it only merges the parts where
3395          * the kvm msr permission bitmap may contain zero bits
3396          */
3397         int i;
3398
3399         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3400                 return true;
3401
3402         for (i = 0; i < MSRPM_OFFSETS; i++) {
3403                 u32 value, p;
3404                 u64 offset;
3405
3406                 if (msrpm_offsets[i] == 0xffffffff)
3407                         break;
3408
3409                 p      = msrpm_offsets[i];
3410                 offset = svm->nested.vmcb_msrpm + (p * 4);
3411
3412                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3413                         return false;
3414
3415                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3416         }
3417
3418         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3419
3420         return true;
3421 }
3422
3423 static bool nested_vmcb_checks(struct vmcb *vmcb)
3424 {
3425         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3426                 return false;
3427
3428         if (vmcb->control.asid == 0)
3429                 return false;
3430
3431         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3432             !npt_enabled)
3433                 return false;
3434
3435         return true;
3436 }
3437
3438 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3439                                  struct vmcb *nested_vmcb, struct page *page)
3440 {
3441         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3442                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3443         else
3444                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3445
3446         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3447                 kvm_mmu_unload(&svm->vcpu);
3448                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3449                 nested_svm_init_mmu_context(&svm->vcpu);
3450         }
3451
3452         /* Load the nested guest state */
3453         svm->vmcb->save.es = nested_vmcb->save.es;
3454         svm->vmcb->save.cs = nested_vmcb->save.cs;
3455         svm->vmcb->save.ss = nested_vmcb->save.ss;
3456         svm->vmcb->save.ds = nested_vmcb->save.ds;
3457         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3458         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3459         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3460         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3461         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3462         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3463         if (npt_enabled) {
3464                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3465                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3466         } else
3467                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3468
3469         /* Guest paging mode is active - reset mmu */
3470         kvm_mmu_reset_context(&svm->vcpu);
3471
3472         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3473         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3474         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3475         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3476
3477         /* In case we don't even reach vcpu_run, the fields are not updated */
3478         svm->vmcb->save.rax = nested_vmcb->save.rax;
3479         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3480         svm->vmcb->save.rip = nested_vmcb->save.rip;
3481         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3482         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3483         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3484
3485         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3486         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3487
3488         /* cache intercepts */
3489         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3490         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3491         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3492         svm->nested.intercept            = nested_vmcb->control.intercept;
3493
3494         svm_flush_tlb(&svm->vcpu, true);
3495         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3496         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3497                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3498         else
3499                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3500
3501         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3502                 /* We only want the cr8 intercept bits of the guest */
3503                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3504                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3505         }
3506
3507         /* We don't want to see VMMCALLs from a nested guest */
3508         clr_intercept(svm, INTERCEPT_VMMCALL);
3509
3510         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3511         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3512
3513         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3514         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3515         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3516         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3517         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3518
3519         nested_svm_unmap(page);
3520
3521         /* Enter Guest-Mode */
3522         enter_guest_mode(&svm->vcpu);
3523
3524         /*
3525          * Merge guest and host intercepts - must be called  with vcpu in
3526          * guest-mode to take affect here
3527          */
3528         recalc_intercepts(svm);
3529
3530         svm->nested.vmcb = vmcb_gpa;
3531
3532         enable_gif(svm);
3533
3534         mark_all_dirty(svm->vmcb);
3535 }
3536
3537 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3538 {
3539         struct vmcb *nested_vmcb;
3540         struct vmcb *hsave = svm->nested.hsave;
3541         struct vmcb *vmcb = svm->vmcb;
3542         struct page *page;
3543         u64 vmcb_gpa;
3544
3545         vmcb_gpa = svm->vmcb->save.rax;
3546
3547         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3548         if (!nested_vmcb)
3549                 return false;
3550
3551         if (!nested_vmcb_checks(nested_vmcb)) {
3552                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3553                 nested_vmcb->control.exit_code_hi = 0;
3554                 nested_vmcb->control.exit_info_1  = 0;
3555                 nested_vmcb->control.exit_info_2  = 0;
3556
3557                 nested_svm_unmap(page);
3558
3559                 return false;
3560         }
3561
3562         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3563                                nested_vmcb->save.rip,
3564                                nested_vmcb->control.int_ctl,
3565                                nested_vmcb->control.event_inj,
3566                                nested_vmcb->control.nested_ctl);
3567
3568         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3569                                     nested_vmcb->control.intercept_cr >> 16,
3570                                     nested_vmcb->control.intercept_exceptions,
3571                                     nested_vmcb->control.intercept);
3572
3573         /* Clear internal status */
3574         kvm_clear_exception_queue(&svm->vcpu);
3575         kvm_clear_interrupt_queue(&svm->vcpu);
3576
3577         /*
3578          * Save the old vmcb, so we don't need to pick what we save, but can
3579          * restore everything when a VMEXIT occurs
3580          */
3581         hsave->save.es     = vmcb->save.es;
3582         hsave->save.cs     = vmcb->save.cs;
3583         hsave->save.ss     = vmcb->save.ss;
3584         hsave->save.ds     = vmcb->save.ds;
3585         hsave->save.gdtr   = vmcb->save.gdtr;
3586         hsave->save.idtr   = vmcb->save.idtr;
3587         hsave->save.efer   = svm->vcpu.arch.efer;
3588         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3589         hsave->save.cr4    = svm->vcpu.arch.cr4;
3590         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3591         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3592         hsave->save.rsp    = vmcb->save.rsp;
3593         hsave->save.rax    = vmcb->save.rax;
3594         if (npt_enabled)
3595                 hsave->save.cr3    = vmcb->save.cr3;
3596         else
3597                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3598
3599         copy_vmcb_control_area(hsave, vmcb);
3600
3601         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3602
3603         return true;
3604 }
3605
3606 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3607 {
3608         to_vmcb->save.fs = from_vmcb->save.fs;
3609         to_vmcb->save.gs = from_vmcb->save.gs;
3610         to_vmcb->save.tr = from_vmcb->save.tr;
3611         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3612         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3613         to_vmcb->save.star = from_vmcb->save.star;
3614         to_vmcb->save.lstar = from_vmcb->save.lstar;
3615         to_vmcb->save.cstar = from_vmcb->save.cstar;
3616         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3617         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3618         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3619         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3620 }
3621
3622 static int vmload_interception(struct vcpu_svm *svm)
3623 {
3624         struct vmcb *nested_vmcb;
3625         struct page *page;
3626         int ret;
3627
3628         if (nested_svm_check_permissions(svm))
3629                 return 1;
3630
3631         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3632         if (!nested_vmcb)
3633                 return 1;
3634
3635         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3636         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3637
3638         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3639         nested_svm_unmap(page);
3640
3641         return ret;
3642 }
3643
3644 static int vmsave_interception(struct vcpu_svm *svm)
3645 {
3646         struct vmcb *nested_vmcb;
3647         struct page *page;
3648         int ret;
3649
3650         if (nested_svm_check_permissions(svm))
3651                 return 1;
3652
3653         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3654         if (!nested_vmcb)
3655                 return 1;
3656
3657         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3658         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3659
3660         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3661         nested_svm_unmap(page);
3662
3663         return ret;
3664 }
3665
3666 static int vmrun_interception(struct vcpu_svm *svm)
3667 {
3668         if (nested_svm_check_permissions(svm))
3669                 return 1;
3670
3671         /* Save rip after vmrun instruction */
3672         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3673
3674         if (!nested_svm_vmrun(svm))
3675                 return 1;
3676
3677         if (!nested_svm_vmrun_msrpm(svm))
3678                 goto failed;
3679
3680         return 1;
3681
3682 failed:
3683
3684         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3685         svm->vmcb->control.exit_code_hi = 0;
3686         svm->vmcb->control.exit_info_1  = 0;
3687         svm->vmcb->control.exit_info_2  = 0;
3688
3689         nested_svm_vmexit(svm);
3690
3691         return 1;
3692 }
3693
3694 static int stgi_interception(struct vcpu_svm *svm)
3695 {
3696         int ret;
3697
3698         if (nested_svm_check_permissions(svm))
3699                 return 1;
3700
3701         /*
3702          * If VGIF is enabled, the STGI intercept is only added to
3703          * detect the opening of the SMI/NMI window; remove it now.
3704          */
3705         if (vgif_enabled(svm))
3706                 clr_intercept(svm, INTERCEPT_STGI);
3707
3708         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3709         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3710         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3711
3712         enable_gif(svm);
3713
3714         return ret;
3715 }
3716
3717 static int clgi_interception(struct vcpu_svm *svm)
3718 {
3719         int ret;
3720
3721         if (nested_svm_check_permissions(svm))
3722                 return 1;
3723
3724         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3725         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3726
3727         disable_gif(svm);
3728
3729         /* After a CLGI no interrupts should come */
3730         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3731                 svm_clear_vintr(svm);
3732                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3733                 mark_dirty(svm->vmcb, VMCB_INTR);
3734         }
3735
3736         return ret;
3737 }
3738
3739 static int invlpga_interception(struct vcpu_svm *svm)
3740 {
3741         struct kvm_vcpu *vcpu = &svm->vcpu;
3742
3743         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3744                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3745
3746         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3747         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3748
3749         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3750         return kvm_skip_emulated_instruction(&svm->vcpu);
3751 }
3752
3753 static int skinit_interception(struct vcpu_svm *svm)
3754 {
3755         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3756
3757         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3758         return 1;
3759 }
3760
3761 static int wbinvd_interception(struct vcpu_svm *svm)
3762 {
3763         return kvm_emulate_wbinvd(&svm->vcpu);
3764 }
3765
3766 static int xsetbv_interception(struct vcpu_svm *svm)
3767 {
3768         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3769         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3770
3771         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3772                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3773                 return kvm_skip_emulated_instruction(&svm->vcpu);
3774         }
3775
3776         return 1;
3777 }
3778
3779 static int task_switch_interception(struct vcpu_svm *svm)
3780 {
3781         u16 tss_selector;
3782         int reason;
3783         int int_type = svm->vmcb->control.exit_int_info &
3784                 SVM_EXITINTINFO_TYPE_MASK;
3785         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3786         uint32_t type =
3787                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3788         uint32_t idt_v =
3789                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3790         bool has_error_code = false;
3791         u32 error_code = 0;
3792
3793         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3794
3795         if (svm->vmcb->control.exit_info_2 &
3796             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3797                 reason = TASK_SWITCH_IRET;
3798         else if (svm->vmcb->control.exit_info_2 &
3799                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3800                 reason = TASK_SWITCH_JMP;
3801         else if (idt_v)
3802                 reason = TASK_SWITCH_GATE;
3803         else
3804                 reason = TASK_SWITCH_CALL;
3805
3806         if (reason == TASK_SWITCH_GATE) {
3807                 switch (type) {
3808                 case SVM_EXITINTINFO_TYPE_NMI:
3809                         svm->vcpu.arch.nmi_injected = false;
3810                         break;
3811                 case SVM_EXITINTINFO_TYPE_EXEPT:
3812                         if (svm->vmcb->control.exit_info_2 &
3813                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3814                                 has_error_code = true;
3815                                 error_code =
3816                                         (u32)svm->vmcb->control.exit_info_2;
3817                         }
3818                         kvm_clear_exception_queue(&svm->vcpu);
3819                         break;
3820                 case SVM_EXITINTINFO_TYPE_INTR:
3821                         kvm_clear_interrupt_queue(&svm->vcpu);
3822                         break;
3823                 default:
3824                         break;
3825                 }
3826         }
3827
3828         if (reason != TASK_SWITCH_GATE ||
3829             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3830             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3831              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3832                 skip_emulated_instruction(&svm->vcpu);
3833
3834         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3835                 int_vec = -1;
3836
3837         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3838                                 has_error_code, error_code) == EMULATE_FAIL) {
3839                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3840                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3841                 svm->vcpu.run->internal.ndata = 0;
3842                 return 0;
3843         }
3844         return 1;
3845 }
3846
3847 static int cpuid_interception(struct vcpu_svm *svm)
3848 {
3849         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3850         return kvm_emulate_cpuid(&svm->vcpu);
3851 }
3852
3853 static int iret_interception(struct vcpu_svm *svm)
3854 {
3855         ++svm->vcpu.stat.nmi_window_exits;
3856         clr_intercept(svm, INTERCEPT_IRET);
3857         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3858         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3859         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3860         return 1;
3861 }
3862
3863 static int invlpg_interception(struct vcpu_svm *svm)
3864 {
3865         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3866                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3867
3868         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3869         return kvm_skip_emulated_instruction(&svm->vcpu);
3870 }
3871
3872 static int emulate_on_interception(struct vcpu_svm *svm)
3873 {
3874         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3875 }
3876
3877 static int rsm_interception(struct vcpu_svm *svm)
3878 {
3879         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3880                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3881 }
3882
3883 static int rdpmc_interception(struct vcpu_svm *svm)
3884 {
3885         int err;
3886
3887         if (!static_cpu_has(X86_FEATURE_NRIPS))
3888                 return emulate_on_interception(svm);
3889
3890         err = kvm_rdpmc(&svm->vcpu);
3891         return kvm_complete_insn_gp(&svm->vcpu, err);
3892 }
3893
3894 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3895                                             unsigned long val)
3896 {
3897         unsigned long cr0 = svm->vcpu.arch.cr0;
3898         bool ret = false;
3899         u64 intercept;
3900
3901         intercept = svm->nested.intercept;
3902
3903         if (!is_guest_mode(&svm->vcpu) ||
3904             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3905                 return false;
3906
3907         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3908         val &= ~SVM_CR0_SELECTIVE_MASK;
3909
3910         if (cr0 ^ val) {
3911                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3912                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3913         }
3914
3915         return ret;
3916 }
3917
3918 #define CR_VALID (1ULL << 63)
3919
3920 static int cr_interception(struct vcpu_svm *svm)
3921 {
3922         int reg, cr;
3923         unsigned long val;
3924         int err;
3925
3926         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3927                 return emulate_on_interception(svm);
3928
3929         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3930                 return emulate_on_interception(svm);
3931
3932         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3933         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3934                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3935         else
3936                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3937
3938         err = 0;
3939         if (cr >= 16) { /* mov to cr */
3940                 cr -= 16;
3941                 val = kvm_register_read(&svm->vcpu, reg);
3942                 switch (cr) {
3943                 case 0:
3944                         if (!check_selective_cr0_intercepted(svm, val))
3945                                 err = kvm_set_cr0(&svm->vcpu, val);
3946                         else
3947                                 return 1;
3948
3949                         break;
3950                 case 3:
3951                         err = kvm_set_cr3(&svm->vcpu, val);
3952                         break;
3953                 case 4:
3954                         err = kvm_set_cr4(&svm->vcpu, val);
3955                         break;
3956                 case 8:
3957                         err = kvm_set_cr8(&svm->vcpu, val);
3958                         break;
3959                 default:
3960                         WARN(1, "unhandled write to CR%d", cr);
3961                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3962                         return 1;
3963                 }
3964         } else { /* mov from cr */
3965                 switch (cr) {
3966                 case 0:
3967                         val = kvm_read_cr0(&svm->vcpu);
3968                         break;
3969                 case 2:
3970                         val = svm->vcpu.arch.cr2;
3971                         break;
3972                 case 3:
3973                         val = kvm_read_cr3(&svm->vcpu);
3974                         break;
3975                 case 4:
3976                         val = kvm_read_cr4(&svm->vcpu);
3977                         break;
3978                 case 8:
3979                         val = kvm_get_cr8(&svm->vcpu);
3980                         break;
3981                 default:
3982                         WARN(1, "unhandled read from CR%d", cr);
3983                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3984                         return 1;
3985                 }
3986                 kvm_register_write(&svm->vcpu, reg, val);
3987         }
3988         return kvm_complete_insn_gp(&svm->vcpu, err);
3989 }
3990
3991 static int dr_interception(struct vcpu_svm *svm)
3992 {
3993         int reg, dr;
3994         unsigned long val;
3995
3996         if (svm->vcpu.guest_debug == 0) {
3997                 /*
3998                  * No more DR vmexits; force a reload of the debug registers
3999                  * and reenter on this instruction.  The next vmexit will
4000                  * retrieve the full state of the debug registers.
4001                  */
4002                 clr_dr_intercepts(svm);
4003                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4004                 return 1;
4005         }
4006
4007         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4008                 return emulate_on_interception(svm);
4009
4010         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4011         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4012
4013         if (dr >= 16) { /* mov to DRn */
4014                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4015                         return 1;
4016                 val = kvm_register_read(&svm->vcpu, reg);
4017                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4018         } else {
4019                 if (!kvm_require_dr(&svm->vcpu, dr))
4020                         return 1;
4021                 kvm_get_dr(&svm->vcpu, dr, &val);
4022                 kvm_register_write(&svm->vcpu, reg, val);
4023         }
4024
4025         return kvm_skip_emulated_instruction(&svm->vcpu);
4026 }
4027
4028 static int cr8_write_interception(struct vcpu_svm *svm)
4029 {
4030         struct kvm_run *kvm_run = svm->vcpu.run;
4031         int r;
4032
4033         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4034         /* instruction emulation calls kvm_set_cr8() */
4035         r = cr_interception(svm);
4036         if (lapic_in_kernel(&svm->vcpu))
4037                 return r;
4038         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4039                 return r;
4040         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4041         return 0;
4042 }
4043
4044 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4045 {
4046         msr->data = 0;
4047
4048         switch (msr->index) {
4049         case MSR_F10H_DECFG:
4050                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4051                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4052                 break;
4053         default:
4054                 return 1;
4055         }
4056
4057         return 0;
4058 }
4059
4060 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4061 {
4062         struct vcpu_svm *svm = to_svm(vcpu);
4063
4064         switch (msr_info->index) {
4065         case MSR_STAR:
4066                 msr_info->data = svm->vmcb->save.star;
4067                 break;
4068 #ifdef CONFIG_X86_64
4069         case MSR_LSTAR:
4070                 msr_info->data = svm->vmcb->save.lstar;
4071                 break;
4072         case MSR_CSTAR:
4073                 msr_info->data = svm->vmcb->save.cstar;
4074                 break;
4075         case MSR_KERNEL_GS_BASE:
4076                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4077                 break;
4078         case MSR_SYSCALL_MASK:
4079                 msr_info->data = svm->vmcb->save.sfmask;
4080                 break;
4081 #endif
4082         case MSR_IA32_SYSENTER_CS:
4083                 msr_info->data = svm->vmcb->save.sysenter_cs;
4084                 break;
4085         case MSR_IA32_SYSENTER_EIP:
4086                 msr_info->data = svm->sysenter_eip;
4087                 break;
4088         case MSR_IA32_SYSENTER_ESP:
4089                 msr_info->data = svm->sysenter_esp;
4090                 break;
4091         case MSR_TSC_AUX:
4092                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4093                         return 1;
4094                 msr_info->data = svm->tsc_aux;
4095                 break;
4096         /*
4097          * Nobody will change the following 5 values in the VMCB so we can
4098          * safely return them on rdmsr. They will always be 0 until LBRV is
4099          * implemented.
4100          */
4101         case MSR_IA32_DEBUGCTLMSR:
4102                 msr_info->data = svm->vmcb->save.dbgctl;
4103                 break;
4104         case MSR_IA32_LASTBRANCHFROMIP:
4105                 msr_info->data = svm->vmcb->save.br_from;
4106                 break;
4107         case MSR_IA32_LASTBRANCHTOIP:
4108                 msr_info->data = svm->vmcb->save.br_to;
4109                 break;
4110         case MSR_IA32_LASTINTFROMIP:
4111                 msr_info->data = svm->vmcb->save.last_excp_from;
4112                 break;
4113         case MSR_IA32_LASTINTTOIP:
4114                 msr_info->data = svm->vmcb->save.last_excp_to;
4115                 break;
4116         case MSR_VM_HSAVE_PA:
4117                 msr_info->data = svm->nested.hsave_msr;
4118                 break;
4119         case MSR_VM_CR:
4120                 msr_info->data = svm->nested.vm_cr_msr;
4121                 break;
4122         case MSR_IA32_SPEC_CTRL:
4123                 if (!msr_info->host_initiated &&
4124                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4125                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4126                         return 1;
4127
4128                 msr_info->data = svm->spec_ctrl;
4129                 break;
4130         case MSR_AMD64_VIRT_SPEC_CTRL:
4131                 if (!msr_info->host_initiated &&
4132                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4133                         return 1;
4134
4135                 msr_info->data = svm->virt_spec_ctrl;
4136                 break;
4137         case MSR_F15H_IC_CFG: {
4138
4139                 int family, model;
4140
4141                 family = guest_cpuid_family(vcpu);
4142                 model  = guest_cpuid_model(vcpu);
4143
4144                 if (family < 0 || model < 0)
4145                         return kvm_get_msr_common(vcpu, msr_info);
4146
4147                 msr_info->data = 0;
4148
4149                 if (family == 0x15 &&
4150                     (model >= 0x2 && model < 0x20))
4151                         msr_info->data = 0x1E;
4152                 }
4153                 break;
4154         case MSR_F10H_DECFG:
4155                 msr_info->data = svm->msr_decfg;
4156                 break;
4157         default:
4158                 return kvm_get_msr_common(vcpu, msr_info);
4159         }
4160         return 0;
4161 }
4162
4163 static int rdmsr_interception(struct vcpu_svm *svm)
4164 {
4165         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4166         struct msr_data msr_info;
4167
4168         msr_info.index = ecx;
4169         msr_info.host_initiated = false;
4170         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4171                 trace_kvm_msr_read_ex(ecx);
4172                 kvm_inject_gp(&svm->vcpu, 0);
4173                 return 1;
4174         } else {
4175                 trace_kvm_msr_read(ecx, msr_info.data);
4176
4177                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4178                                    msr_info.data & 0xffffffff);
4179                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4180                                    msr_info.data >> 32);
4181                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4182                 return kvm_skip_emulated_instruction(&svm->vcpu);
4183         }
4184 }
4185
4186 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4187 {
4188         struct vcpu_svm *svm = to_svm(vcpu);
4189         int svm_dis, chg_mask;
4190
4191         if (data & ~SVM_VM_CR_VALID_MASK)
4192                 return 1;
4193
4194         chg_mask = SVM_VM_CR_VALID_MASK;
4195
4196         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4197                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4198
4199         svm->nested.vm_cr_msr &= ~chg_mask;
4200         svm->nested.vm_cr_msr |= (data & chg_mask);
4201
4202         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4203
4204         /* check for svm_disable while efer.svme is set */
4205         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4206                 return 1;
4207
4208         return 0;
4209 }
4210
4211 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4212 {
4213         struct vcpu_svm *svm = to_svm(vcpu);
4214
4215         u32 ecx = msr->index;
4216         u64 data = msr->data;
4217         switch (ecx) {
4218         case MSR_IA32_CR_PAT:
4219                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4220                         return 1;
4221                 vcpu->arch.pat = data;
4222                 svm->vmcb->save.g_pat = data;
4223                 mark_dirty(svm->vmcb, VMCB_NPT);
4224                 break;
4225         case MSR_IA32_SPEC_CTRL:
4226                 if (!msr->host_initiated &&
4227                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4228                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4229                         return 1;
4230
4231                 /* The STIBP bit doesn't fault even if it's not advertised */
4232                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4233                         return 1;
4234
4235                 svm->spec_ctrl = data;
4236
4237                 if (!data)
4238                         break;
4239
4240                 /*
4241                  * For non-nested:
4242                  * When it's written (to non-zero) for the first time, pass
4243                  * it through.
4244                  *
4245                  * For nested:
4246                  * The handling of the MSR bitmap for L2 guests is done in
4247                  * nested_svm_vmrun_msrpm.
4248                  * We update the L1 MSR bit as well since it will end up
4249                  * touching the MSR anyway now.
4250                  */
4251                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4252                 break;
4253         case MSR_IA32_PRED_CMD:
4254                 if (!msr->host_initiated &&
4255                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4256                         return 1;
4257
4258                 if (data & ~PRED_CMD_IBPB)
4259                         return 1;
4260
4261                 if (!data)
4262                         break;
4263
4264                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4265                 if (is_guest_mode(vcpu))
4266                         break;
4267                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4268                 break;
4269         case MSR_AMD64_VIRT_SPEC_CTRL:
4270                 if (!msr->host_initiated &&
4271                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4272                         return 1;
4273
4274                 if (data & ~SPEC_CTRL_SSBD)
4275                         return 1;
4276
4277                 svm->virt_spec_ctrl = data;
4278                 break;
4279         case MSR_STAR:
4280                 svm->vmcb->save.star = data;
4281                 break;
4282 #ifdef CONFIG_X86_64
4283         case MSR_LSTAR:
4284                 svm->vmcb->save.lstar = data;
4285                 break;
4286         case MSR_CSTAR:
4287                 svm->vmcb->save.cstar = data;
4288                 break;
4289         case MSR_KERNEL_GS_BASE:
4290                 svm->vmcb->save.kernel_gs_base = data;
4291                 break;
4292         case MSR_SYSCALL_MASK:
4293                 svm->vmcb->save.sfmask = data;
4294                 break;
4295 #endif
4296         case MSR_IA32_SYSENTER_CS:
4297                 svm->vmcb->save.sysenter_cs = data;
4298                 break;
4299         case MSR_IA32_SYSENTER_EIP:
4300                 svm->sysenter_eip = data;
4301                 svm->vmcb->save.sysenter_eip = data;
4302                 break;
4303         case MSR_IA32_SYSENTER_ESP:
4304                 svm->sysenter_esp = data;
4305                 svm->vmcb->save.sysenter_esp = data;
4306                 break;
4307         case MSR_TSC_AUX:
4308                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4309                         return 1;
4310
4311                 /*
4312                  * This is rare, so we update the MSR here instead of using
4313                  * direct_access_msrs.  Doing that would require a rdmsr in
4314                  * svm_vcpu_put.
4315                  */
4316                 svm->tsc_aux = data;
4317                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4318                 break;
4319         case MSR_IA32_DEBUGCTLMSR:
4320                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4321                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4322                                     __func__, data);
4323                         break;
4324                 }
4325                 if (data & DEBUGCTL_RESERVED_BITS)
4326                         return 1;
4327
4328                 svm->vmcb->save.dbgctl = data;
4329                 mark_dirty(svm->vmcb, VMCB_LBR);
4330                 if (data & (1ULL<<0))
4331                         svm_enable_lbrv(svm);
4332                 else
4333                         svm_disable_lbrv(svm);
4334                 break;
4335         case MSR_VM_HSAVE_PA:
4336                 svm->nested.hsave_msr = data;
4337                 break;
4338         case MSR_VM_CR:
4339                 return svm_set_vm_cr(vcpu, data);
4340         case MSR_VM_IGNNE:
4341                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4342                 break;
4343         case MSR_F10H_DECFG: {
4344                 struct kvm_msr_entry msr_entry;
4345
4346                 msr_entry.index = msr->index;
4347                 if (svm_get_msr_feature(&msr_entry))
4348                         return 1;
4349
4350                 /* Check the supported bits */
4351                 if (data & ~msr_entry.data)
4352                         return 1;
4353
4354                 /* Don't allow the guest to change a bit, #GP */
4355                 if (!msr->host_initiated && (data ^ msr_entry.data))
4356                         return 1;
4357
4358                 svm->msr_decfg = data;
4359                 break;
4360         }
4361         case MSR_IA32_APICBASE:
4362                 if (kvm_vcpu_apicv_active(vcpu))
4363                         avic_update_vapic_bar(to_svm(vcpu), data);
4364                 /* Follow through */
4365         default:
4366                 return kvm_set_msr_common(vcpu, msr);
4367         }
4368         return 0;
4369 }
4370
4371 static int wrmsr_interception(struct vcpu_svm *svm)
4372 {
4373         struct msr_data msr;
4374         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4375         u64 data = kvm_read_edx_eax(&svm->vcpu);
4376
4377         msr.data = data;
4378         msr.index = ecx;
4379         msr.host_initiated = false;
4380
4381         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4382         if (kvm_set_msr(&svm->vcpu, &msr)) {
4383                 trace_kvm_msr_write_ex(ecx, data);
4384                 kvm_inject_gp(&svm->vcpu, 0);
4385                 return 1;
4386         } else {
4387                 trace_kvm_msr_write(ecx, data);
4388                 return kvm_skip_emulated_instruction(&svm->vcpu);
4389         }
4390 }
4391
4392 static int msr_interception(struct vcpu_svm *svm)
4393 {
4394         if (svm->vmcb->control.exit_info_1)
4395                 return wrmsr_interception(svm);
4396         else
4397                 return rdmsr_interception(svm);
4398 }
4399
4400 static int interrupt_window_interception(struct vcpu_svm *svm)
4401 {
4402         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4403         svm_clear_vintr(svm);
4404         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4405         mark_dirty(svm->vmcb, VMCB_INTR);
4406         ++svm->vcpu.stat.irq_window_exits;
4407         return 1;
4408 }
4409
4410 static int pause_interception(struct vcpu_svm *svm)
4411 {
4412         struct kvm_vcpu *vcpu = &svm->vcpu;
4413         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4414
4415         if (pause_filter_thresh)
4416                 grow_ple_window(vcpu);
4417
4418         kvm_vcpu_on_spin(vcpu, in_kernel);
4419         return 1;
4420 }
4421
4422 static int nop_interception(struct vcpu_svm *svm)
4423 {
4424         return kvm_skip_emulated_instruction(&(svm->vcpu));
4425 }
4426
4427 static int monitor_interception(struct vcpu_svm *svm)
4428 {
4429         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4430         return nop_interception(svm);
4431 }
4432
4433 static int mwait_interception(struct vcpu_svm *svm)
4434 {
4435         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4436         return nop_interception(svm);
4437 }
4438
4439 enum avic_ipi_failure_cause {
4440         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4441         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4442         AVIC_IPI_FAILURE_INVALID_TARGET,
4443         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4444 };
4445
4446 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4447 {
4448         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4449         u32 icrl = svm->vmcb->control.exit_info_1;
4450         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4451         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4452         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4453
4454         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4455
4456         switch (id) {
4457         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4458                 /*
4459                  * AVIC hardware handles the generation of
4460                  * IPIs when the specified Message Type is Fixed
4461                  * (also known as fixed delivery mode) and
4462                  * the Trigger Mode is edge-triggered. The hardware
4463                  * also supports self and broadcast delivery modes
4464                  * specified via the Destination Shorthand(DSH)
4465                  * field of the ICRL. Logical and physical APIC ID
4466                  * formats are supported. All other IPI types cause
4467                  * a #VMEXIT, which needs to emulated.
4468                  */
4469                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4470                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4471                 break;
4472         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4473                 int i;
4474                 struct kvm_vcpu *vcpu;
4475                 struct kvm *kvm = svm->vcpu.kvm;
4476                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4477
4478                 /*
4479                  * At this point, we expect that the AVIC HW has already
4480                  * set the appropriate IRR bits on the valid target
4481                  * vcpus. So, we just need to kick the appropriate vcpu.
4482                  */
4483                 kvm_for_each_vcpu(i, vcpu, kvm) {
4484                         bool m = kvm_apic_match_dest(vcpu, apic,
4485                                                      icrl & KVM_APIC_SHORT_MASK,
4486                                                      GET_APIC_DEST_FIELD(icrh),
4487                                                      icrl & KVM_APIC_DEST_MASK);
4488
4489                         if (m && !avic_vcpu_is_running(vcpu))
4490                                 kvm_vcpu_wake_up(vcpu);
4491                 }
4492                 break;
4493         }
4494         case AVIC_IPI_FAILURE_INVALID_TARGET:
4495                 break;
4496         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4497                 WARN_ONCE(1, "Invalid backing page\n");
4498                 break;
4499         default:
4500                 pr_err("Unknown IPI interception\n");
4501         }
4502
4503         return 1;
4504 }
4505
4506 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4507 {
4508         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4509         int index;
4510         u32 *logical_apic_id_table;
4511         int dlid = GET_APIC_LOGICAL_ID(ldr);
4512
4513         if (!dlid)
4514                 return NULL;
4515
4516         if (flat) { /* flat */
4517                 index = ffs(dlid) - 1;
4518                 if (index > 7)
4519                         return NULL;
4520         } else { /* cluster */
4521                 int cluster = (dlid & 0xf0) >> 4;
4522                 int apic = ffs(dlid & 0x0f) - 1;
4523
4524                 if ((apic < 0) || (apic > 7) ||
4525                     (cluster >= 0xf))
4526                         return NULL;
4527                 index = (cluster << 2) + apic;
4528         }
4529
4530         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4531
4532         return &logical_apic_id_table[index];
4533 }
4534
4535 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4536                           bool valid)
4537 {
4538         bool flat;
4539         u32 *entry, new_entry;
4540
4541         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4542         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4543         if (!entry)
4544                 return -EINVAL;
4545
4546         new_entry = READ_ONCE(*entry);
4547         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4548         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4549         if (valid)
4550                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4551         else
4552                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4553         WRITE_ONCE(*entry, new_entry);
4554
4555         return 0;
4556 }
4557
4558 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4559 {
4560         int ret;
4561         struct vcpu_svm *svm = to_svm(vcpu);
4562         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4563
4564         if (!ldr)
4565                 return 1;
4566
4567         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4568         if (ret && svm->ldr_reg) {
4569                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4570                 svm->ldr_reg = 0;
4571         } else {
4572                 svm->ldr_reg = ldr;
4573         }
4574         return ret;
4575 }
4576
4577 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4578 {
4579         u64 *old, *new;
4580         struct vcpu_svm *svm = to_svm(vcpu);
4581         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4582         u32 id = (apic_id_reg >> 24) & 0xff;
4583
4584         if (vcpu->vcpu_id == id)
4585                 return 0;
4586
4587         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4588         new = avic_get_physical_id_entry(vcpu, id);
4589         if (!new || !old)
4590                 return 1;
4591
4592         /* We need to move physical_id_entry to new offset */
4593         *new = *old;
4594         *old = 0ULL;
4595         to_svm(vcpu)->avic_physical_id_cache = new;
4596
4597         /*
4598          * Also update the guest physical APIC ID in the logical
4599          * APIC ID table entry if already setup the LDR.
4600          */
4601         if (svm->ldr_reg)
4602                 avic_handle_ldr_update(vcpu);
4603
4604         return 0;
4605 }
4606
4607 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4608 {
4609         struct vcpu_svm *svm = to_svm(vcpu);
4610         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4611         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4612         u32 mod = (dfr >> 28) & 0xf;
4613
4614         /*
4615          * We assume that all local APICs are using the same type.
4616          * If this changes, we need to flush the AVIC logical
4617          * APID id table.
4618          */
4619         if (kvm_svm->ldr_mode == mod)
4620                 return 0;
4621
4622         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4623         kvm_svm->ldr_mode = mod;
4624
4625         if (svm->ldr_reg)
4626                 avic_handle_ldr_update(vcpu);
4627         return 0;
4628 }
4629
4630 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4631 {
4632         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4633         u32 offset = svm->vmcb->control.exit_info_1 &
4634                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4635
4636         switch (offset) {
4637         case APIC_ID:
4638                 if (avic_handle_apic_id_update(&svm->vcpu))
4639                         return 0;
4640                 break;
4641         case APIC_LDR:
4642                 if (avic_handle_ldr_update(&svm->vcpu))
4643                         return 0;
4644                 break;
4645         case APIC_DFR:
4646                 avic_handle_dfr_update(&svm->vcpu);
4647                 break;
4648         default:
4649                 break;
4650         }
4651
4652         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4653
4654         return 1;
4655 }
4656
4657 static bool is_avic_unaccelerated_access_trap(u32 offset)
4658 {
4659         bool ret = false;
4660
4661         switch (offset) {
4662         case APIC_ID:
4663         case APIC_EOI:
4664         case APIC_RRR:
4665         case APIC_LDR:
4666         case APIC_DFR:
4667         case APIC_SPIV:
4668         case APIC_ESR:
4669         case APIC_ICR:
4670         case APIC_LVTT:
4671         case APIC_LVTTHMR:
4672         case APIC_LVTPC:
4673         case APIC_LVT0:
4674         case APIC_LVT1:
4675         case APIC_LVTERR:
4676         case APIC_TMICT:
4677         case APIC_TDCR:
4678                 ret = true;
4679                 break;
4680         default:
4681                 break;
4682         }
4683         return ret;
4684 }
4685
4686 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4687 {
4688         int ret = 0;
4689         u32 offset = svm->vmcb->control.exit_info_1 &
4690                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4691         u32 vector = svm->vmcb->control.exit_info_2 &
4692                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4693         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4694                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4695         bool trap = is_avic_unaccelerated_access_trap(offset);
4696
4697         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4698                                             trap, write, vector);
4699         if (trap) {
4700                 /* Handling Trap */
4701                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4702                 ret = avic_unaccel_trap_write(svm);
4703         } else {
4704                 /* Handling Fault */
4705                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4706         }
4707
4708         return ret;
4709 }
4710
4711 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4712         [SVM_EXIT_READ_CR0]                     = cr_interception,
4713         [SVM_EXIT_READ_CR3]                     = cr_interception,
4714         [SVM_EXIT_READ_CR4]                     = cr_interception,
4715         [SVM_EXIT_READ_CR8]                     = cr_interception,
4716         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4717         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4718         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4719         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4720         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4721         [SVM_EXIT_READ_DR0]                     = dr_interception,
4722         [SVM_EXIT_READ_DR1]                     = dr_interception,
4723         [SVM_EXIT_READ_DR2]                     = dr_interception,
4724         [SVM_EXIT_READ_DR3]                     = dr_interception,
4725         [SVM_EXIT_READ_DR4]                     = dr_interception,
4726         [SVM_EXIT_READ_DR5]                     = dr_interception,
4727         [SVM_EXIT_READ_DR6]                     = dr_interception,
4728         [SVM_EXIT_READ_DR7]                     = dr_interception,
4729         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4730         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4731         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4732         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4733         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4734         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4735         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4736         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4737         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4738         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4739         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4740         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4741         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4742         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4743         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4744         [SVM_EXIT_INTR]                         = intr_interception,
4745         [SVM_EXIT_NMI]                          = nmi_interception,
4746         [SVM_EXIT_SMI]                          = nop_on_interception,
4747         [SVM_EXIT_INIT]                         = nop_on_interception,
4748         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4749         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4750         [SVM_EXIT_CPUID]                        = cpuid_interception,
4751         [SVM_EXIT_IRET]                         = iret_interception,
4752         [SVM_EXIT_INVD]                         = emulate_on_interception,
4753         [SVM_EXIT_PAUSE]                        = pause_interception,
4754         [SVM_EXIT_HLT]                          = halt_interception,
4755         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4756         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4757         [SVM_EXIT_IOIO]                         = io_interception,
4758         [SVM_EXIT_MSR]                          = msr_interception,
4759         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4760         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4761         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4762         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4763         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4764         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4765         [SVM_EXIT_STGI]                         = stgi_interception,
4766         [SVM_EXIT_CLGI]                         = clgi_interception,
4767         [SVM_EXIT_SKINIT]                       = skinit_interception,
4768         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4769         [SVM_EXIT_MONITOR]                      = monitor_interception,
4770         [SVM_EXIT_MWAIT]                        = mwait_interception,
4771         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4772         [SVM_EXIT_NPF]                          = npf_interception,
4773         [SVM_EXIT_RSM]                          = rsm_interception,
4774         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4775         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4776 };
4777
4778 static void dump_vmcb(struct kvm_vcpu *vcpu)
4779 {
4780         struct vcpu_svm *svm = to_svm(vcpu);
4781         struct vmcb_control_area *control = &svm->vmcb->control;
4782         struct vmcb_save_area *save = &svm->vmcb->save;
4783
4784         pr_err("VMCB Control Area:\n");
4785         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4786         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4787         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4788         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4789         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4790         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4791         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4792         pr_err("%-20s%d\n", "pause filter threshold:",
4793                control->pause_filter_thresh);
4794         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4795         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4796         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4797         pr_err("%-20s%d\n", "asid:", control->asid);
4798         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4799         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4800         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4801         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4802         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4803         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4804         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4805         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4806         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4807         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4808         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4809         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4810         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4811         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4812         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4813         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4814         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4815         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4816         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4817         pr_err("VMCB State Save Area:\n");
4818         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4819                "es:",
4820                save->es.selector, save->es.attrib,
4821                save->es.limit, save->es.base);
4822         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4823                "cs:",
4824                save->cs.selector, save->cs.attrib,
4825                save->cs.limit, save->cs.base);
4826         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4827                "ss:",
4828                save->ss.selector, save->ss.attrib,
4829                save->ss.limit, save->ss.base);
4830         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4831                "ds:",
4832                save->ds.selector, save->ds.attrib,
4833                save->ds.limit, save->ds.base);
4834         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4835                "fs:",
4836                save->fs.selector, save->fs.attrib,
4837                save->fs.limit, save->fs.base);
4838         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4839                "gs:",
4840                save->gs.selector, save->gs.attrib,
4841                save->gs.limit, save->gs.base);
4842         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4843                "gdtr:",
4844                save->gdtr.selector, save->gdtr.attrib,
4845                save->gdtr.limit, save->gdtr.base);
4846         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4847                "ldtr:",
4848                save->ldtr.selector, save->ldtr.attrib,
4849                save->ldtr.limit, save->ldtr.base);
4850         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4851                "idtr:",
4852                save->idtr.selector, save->idtr.attrib,
4853                save->idtr.limit, save->idtr.base);
4854         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4855                "tr:",
4856                save->tr.selector, save->tr.attrib,
4857                save->tr.limit, save->tr.base);
4858         pr_err("cpl:            %d                efer:         %016llx\n",
4859                 save->cpl, save->efer);
4860         pr_err("%-15s %016llx %-13s %016llx\n",
4861                "cr0:", save->cr0, "cr2:", save->cr2);
4862         pr_err("%-15s %016llx %-13s %016llx\n",
4863                "cr3:", save->cr3, "cr4:", save->cr4);
4864         pr_err("%-15s %016llx %-13s %016llx\n",
4865                "dr6:", save->dr6, "dr7:", save->dr7);
4866         pr_err("%-15s %016llx %-13s %016llx\n",
4867                "rip:", save->rip, "rflags:", save->rflags);
4868         pr_err("%-15s %016llx %-13s %016llx\n",
4869                "rsp:", save->rsp, "rax:", save->rax);
4870         pr_err("%-15s %016llx %-13s %016llx\n",
4871                "star:", save->star, "lstar:", save->lstar);
4872         pr_err("%-15s %016llx %-13s %016llx\n",
4873                "cstar:", save->cstar, "sfmask:", save->sfmask);
4874         pr_err("%-15s %016llx %-13s %016llx\n",
4875                "kernel_gs_base:", save->kernel_gs_base,
4876                "sysenter_cs:", save->sysenter_cs);
4877         pr_err("%-15s %016llx %-13s %016llx\n",
4878                "sysenter_esp:", save->sysenter_esp,
4879                "sysenter_eip:", save->sysenter_eip);
4880         pr_err("%-15s %016llx %-13s %016llx\n",
4881                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4882         pr_err("%-15s %016llx %-13s %016llx\n",
4883                "br_from:", save->br_from, "br_to:", save->br_to);
4884         pr_err("%-15s %016llx %-13s %016llx\n",
4885                "excp_from:", save->last_excp_from,
4886                "excp_to:", save->last_excp_to);
4887 }
4888
4889 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4890 {
4891         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4892
4893         *info1 = control->exit_info_1;
4894         *info2 = control->exit_info_2;
4895 }
4896
4897 static int handle_exit(struct kvm_vcpu *vcpu)
4898 {
4899         struct vcpu_svm *svm = to_svm(vcpu);
4900         struct kvm_run *kvm_run = vcpu->run;
4901         u32 exit_code = svm->vmcb->control.exit_code;
4902
4903         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4904
4905         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4906                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4907         if (npt_enabled)
4908                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4909
4910         if (unlikely(svm->nested.exit_required)) {
4911                 nested_svm_vmexit(svm);
4912                 svm->nested.exit_required = false;
4913
4914                 return 1;
4915         }
4916
4917         if (is_guest_mode(vcpu)) {
4918                 int vmexit;
4919
4920                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4921                                         svm->vmcb->control.exit_info_1,
4922                                         svm->vmcb->control.exit_info_2,
4923                                         svm->vmcb->control.exit_int_info,
4924                                         svm->vmcb->control.exit_int_info_err,
4925                                         KVM_ISA_SVM);
4926
4927                 vmexit = nested_svm_exit_special(svm);
4928
4929                 if (vmexit == NESTED_EXIT_CONTINUE)
4930                         vmexit = nested_svm_exit_handled(svm);
4931
4932                 if (vmexit == NESTED_EXIT_DONE)
4933                         return 1;
4934         }
4935
4936         svm_complete_interrupts(svm);
4937
4938         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4939                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4940                 kvm_run->fail_entry.hardware_entry_failure_reason
4941                         = svm->vmcb->control.exit_code;
4942                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4943                 dump_vmcb(vcpu);
4944                 return 0;
4945         }
4946
4947         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4948             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4949             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4950             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4951                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4952                        "exit_code 0x%x\n",
4953                        __func__, svm->vmcb->control.exit_int_info,
4954                        exit_code);
4955
4956         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4957             || !svm_exit_handlers[exit_code]) {
4958                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4959                 kvm_queue_exception(vcpu, UD_VECTOR);
4960                 return 1;
4961         }
4962
4963         return svm_exit_handlers[exit_code](svm);
4964 }
4965
4966 static void reload_tss(struct kvm_vcpu *vcpu)
4967 {
4968         int cpu = raw_smp_processor_id();
4969
4970         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4971         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4972         load_TR_desc();
4973 }
4974
4975 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4976 {
4977         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4978         int asid = sev_get_asid(svm->vcpu.kvm);
4979
4980         /* Assign the asid allocated with this SEV guest */
4981         svm->vmcb->control.asid = asid;
4982
4983         /*
4984          * Flush guest TLB:
4985          *
4986          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4987          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4988          */
4989         if (sd->sev_vmcbs[asid] == svm->vmcb &&
4990             svm->last_cpu == cpu)
4991                 return;
4992
4993         svm->last_cpu = cpu;
4994         sd->sev_vmcbs[asid] = svm->vmcb;
4995         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4996         mark_dirty(svm->vmcb, VMCB_ASID);
4997 }
4998
4999 static void pre_svm_run(struct vcpu_svm *svm)
5000 {
5001         int cpu = raw_smp_processor_id();
5002
5003         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5004
5005         if (sev_guest(svm->vcpu.kvm))
5006                 return pre_sev_run(svm, cpu);
5007
5008         /* FIXME: handle wraparound of asid_generation */
5009         if (svm->asid_generation != sd->asid_generation)
5010                 new_asid(svm, sd);
5011 }
5012
5013 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5014 {
5015         struct vcpu_svm *svm = to_svm(vcpu);
5016
5017         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5018         vcpu->arch.hflags |= HF_NMI_MASK;
5019         set_intercept(svm, INTERCEPT_IRET);
5020         ++vcpu->stat.nmi_injections;
5021 }
5022
5023 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5024 {
5025         struct vmcb_control_area *control;
5026
5027         /* The following fields are ignored when AVIC is enabled */
5028         control = &svm->vmcb->control;
5029         control->int_vector = irq;
5030         control->int_ctl &= ~V_INTR_PRIO_MASK;
5031         control->int_ctl |= V_IRQ_MASK |
5032                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5033         mark_dirty(svm->vmcb, VMCB_INTR);
5034 }
5035
5036 static void svm_set_irq(struct kvm_vcpu *vcpu)
5037 {
5038         struct vcpu_svm *svm = to_svm(vcpu);
5039
5040         BUG_ON(!(gif_set(svm)));
5041
5042         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5043         ++vcpu->stat.irq_injections;
5044
5045         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5046                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5047 }
5048
5049 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5050 {
5051         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5052 }
5053
5054 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5055 {
5056         struct vcpu_svm *svm = to_svm(vcpu);
5057
5058         if (svm_nested_virtualize_tpr(vcpu) ||
5059             kvm_vcpu_apicv_active(vcpu))
5060                 return;
5061
5062         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5063
5064         if (irr == -1)
5065                 return;
5066
5067         if (tpr >= irr)
5068                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5069 }
5070
5071 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5072 {
5073         return;
5074 }
5075
5076 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5077 {
5078         return avic && irqchip_split(vcpu->kvm);
5079 }
5080
5081 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5082 {
5083 }
5084
5085 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5086 {
5087 }
5088
5089 /* Note: Currently only used by Hyper-V. */
5090 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5091 {
5092         struct vcpu_svm *svm = to_svm(vcpu);
5093         struct vmcb *vmcb = svm->vmcb;
5094
5095         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5096                 return;
5097
5098         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5099         mark_dirty(vmcb, VMCB_INTR);
5100 }
5101
5102 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5103 {
5104         return;
5105 }
5106
5107 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5108 {
5109         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5110         smp_mb__after_atomic();
5111
5112         if (avic_vcpu_is_running(vcpu))
5113                 wrmsrl(SVM_AVIC_DOORBELL,
5114                        kvm_cpu_get_apicid(vcpu->cpu));
5115         else
5116                 kvm_vcpu_wake_up(vcpu);
5117 }
5118
5119 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5120 {
5121         unsigned long flags;
5122         struct amd_svm_iommu_ir *cur;
5123
5124         spin_lock_irqsave(&svm->ir_list_lock, flags);
5125         list_for_each_entry(cur, &svm->ir_list, node) {
5126                 if (cur->data != pi->ir_data)
5127                         continue;
5128                 list_del(&cur->node);
5129                 kfree(cur);
5130                 break;
5131         }
5132         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5133 }
5134
5135 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5136 {
5137         int ret = 0;
5138         unsigned long flags;
5139         struct amd_svm_iommu_ir *ir;
5140
5141         /**
5142          * In some cases, the existing irte is updaed and re-set,
5143          * so we need to check here if it's already been * added
5144          * to the ir_list.
5145          */
5146         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5147                 struct kvm *kvm = svm->vcpu.kvm;
5148                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5149                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5150                 struct vcpu_svm *prev_svm;
5151
5152                 if (!prev_vcpu) {
5153                         ret = -EINVAL;
5154                         goto out;
5155                 }
5156
5157                 prev_svm = to_svm(prev_vcpu);
5158                 svm_ir_list_del(prev_svm, pi);
5159         }
5160
5161         /**
5162          * Allocating new amd_iommu_pi_data, which will get
5163          * add to the per-vcpu ir_list.
5164          */
5165         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5166         if (!ir) {
5167                 ret = -ENOMEM;
5168                 goto out;
5169         }
5170         ir->data = pi->ir_data;
5171
5172         spin_lock_irqsave(&svm->ir_list_lock, flags);
5173         list_add(&ir->node, &svm->ir_list);
5174         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5175 out:
5176         return ret;
5177 }
5178
5179 /**
5180  * Note:
5181  * The HW cannot support posting multicast/broadcast
5182  * interrupts to a vCPU. So, we still use legacy interrupt
5183  * remapping for these kind of interrupts.
5184  *
5185  * For lowest-priority interrupts, we only support
5186  * those with single CPU as the destination, e.g. user
5187  * configures the interrupts via /proc/irq or uses
5188  * irqbalance to make the interrupts single-CPU.
5189  */
5190 static int
5191 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5192                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5193 {
5194         struct kvm_lapic_irq irq;
5195         struct kvm_vcpu *vcpu = NULL;
5196
5197         kvm_set_msi_irq(kvm, e, &irq);
5198
5199         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5200                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5201                          __func__, irq.vector);
5202                 return -1;
5203         }
5204
5205         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5206                  irq.vector);
5207         *svm = to_svm(vcpu);
5208         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5209         vcpu_info->vector = irq.vector;
5210
5211         return 0;
5212 }
5213
5214 /*
5215  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5216  *
5217  * @kvm: kvm
5218  * @host_irq: host irq of the interrupt
5219  * @guest_irq: gsi of the interrupt
5220  * @set: set or unset PI
5221  * returns 0 on success, < 0 on failure
5222  */
5223 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5224                               uint32_t guest_irq, bool set)
5225 {
5226         struct kvm_kernel_irq_routing_entry *e;
5227         struct kvm_irq_routing_table *irq_rt;
5228         int idx, ret = -EINVAL;
5229
5230         if (!kvm_arch_has_assigned_device(kvm) ||
5231             !irq_remapping_cap(IRQ_POSTING_CAP))
5232                 return 0;
5233
5234         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5235                  __func__, host_irq, guest_irq, set);
5236
5237         idx = srcu_read_lock(&kvm->irq_srcu);
5238         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5239         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5240
5241         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5242                 struct vcpu_data vcpu_info;
5243                 struct vcpu_svm *svm = NULL;
5244
5245                 if (e->type != KVM_IRQ_ROUTING_MSI)
5246                         continue;
5247
5248                 /**
5249                  * Here, we setup with legacy mode in the following cases:
5250                  * 1. When cannot target interrupt to a specific vcpu.
5251                  * 2. Unsetting posted interrupt.
5252                  * 3. APIC virtialization is disabled for the vcpu.
5253                  */
5254                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5255                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5256                         struct amd_iommu_pi_data pi;
5257
5258                         /* Try to enable guest_mode in IRTE */
5259                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5260                                             AVIC_HPA_MASK);
5261                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5262                                                      svm->vcpu.vcpu_id);
5263                         pi.is_guest_mode = true;
5264                         pi.vcpu_data = &vcpu_info;
5265                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5266
5267                         /**
5268                          * Here, we successfully setting up vcpu affinity in
5269                          * IOMMU guest mode. Now, we need to store the posted
5270                          * interrupt information in a per-vcpu ir_list so that
5271                          * we can reference to them directly when we update vcpu
5272                          * scheduling information in IOMMU irte.
5273                          */
5274                         if (!ret && pi.is_guest_mode)
5275                                 svm_ir_list_add(svm, &pi);
5276                 } else {
5277                         /* Use legacy mode in IRTE */
5278                         struct amd_iommu_pi_data pi;
5279
5280                         /**
5281                          * Here, pi is used to:
5282                          * - Tell IOMMU to use legacy mode for this interrupt.
5283                          * - Retrieve ga_tag of prior interrupt remapping data.
5284                          */
5285                         pi.is_guest_mode = false;
5286                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5287
5288                         /**
5289                          * Check if the posted interrupt was previously
5290                          * setup with the guest_mode by checking if the ga_tag
5291                          * was cached. If so, we need to clean up the per-vcpu
5292                          * ir_list.
5293                          */
5294                         if (!ret && pi.prev_ga_tag) {
5295                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5296                                 struct kvm_vcpu *vcpu;
5297
5298                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5299                                 if (vcpu)
5300                                         svm_ir_list_del(to_svm(vcpu), &pi);
5301                         }
5302                 }
5303
5304                 if (!ret && svm) {
5305                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5306                                                  e->gsi, vcpu_info.vector,
5307                                                  vcpu_info.pi_desc_addr, set);
5308                 }
5309
5310                 if (ret < 0) {
5311                         pr_err("%s: failed to update PI IRTE\n", __func__);
5312                         goto out;
5313                 }
5314         }
5315
5316         ret = 0;
5317 out:
5318         srcu_read_unlock(&kvm->irq_srcu, idx);
5319         return ret;
5320 }
5321
5322 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5323 {
5324         struct vcpu_svm *svm = to_svm(vcpu);
5325         struct vmcb *vmcb = svm->vmcb;
5326         int ret;
5327         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5328               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5329         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5330
5331         return ret;
5332 }
5333
5334 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5335 {
5336         struct vcpu_svm *svm = to_svm(vcpu);
5337
5338         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5339 }
5340
5341 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5342 {
5343         struct vcpu_svm *svm = to_svm(vcpu);
5344
5345         if (masked) {
5346                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5347                 set_intercept(svm, INTERCEPT_IRET);
5348         } else {
5349                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5350                 clr_intercept(svm, INTERCEPT_IRET);
5351         }
5352 }
5353
5354 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5355 {
5356         struct vcpu_svm *svm = to_svm(vcpu);
5357         struct vmcb *vmcb = svm->vmcb;
5358         int ret;
5359
5360         if (!gif_set(svm) ||
5361              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5362                 return 0;
5363
5364         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5365
5366         if (is_guest_mode(vcpu))
5367                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5368
5369         return ret;
5370 }
5371
5372 static void enable_irq_window(struct kvm_vcpu *vcpu)
5373 {
5374         struct vcpu_svm *svm = to_svm(vcpu);
5375
5376         if (kvm_vcpu_apicv_active(vcpu))
5377                 return;
5378
5379         /*
5380          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5381          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5382          * get that intercept, this function will be called again though and
5383          * we'll get the vintr intercept. However, if the vGIF feature is
5384          * enabled, the STGI interception will not occur. Enable the irq
5385          * window under the assumption that the hardware will set the GIF.
5386          */
5387         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5388                 svm_set_vintr(svm);
5389                 svm_inject_irq(svm, 0x0);
5390         }
5391 }
5392
5393 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5394 {
5395         struct vcpu_svm *svm = to_svm(vcpu);
5396
5397         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5398             == HF_NMI_MASK)
5399                 return; /* IRET will cause a vm exit */
5400
5401         if (!gif_set(svm)) {
5402                 if (vgif_enabled(svm))
5403                         set_intercept(svm, INTERCEPT_STGI);
5404                 return; /* STGI will cause a vm exit */
5405         }
5406
5407         if (svm->nested.exit_required)
5408                 return; /* we're not going to run the guest yet */
5409
5410         /*
5411          * Something prevents NMI from been injected. Single step over possible
5412          * problem (IRET or exception injection or interrupt shadow)
5413          */
5414         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5415         svm->nmi_singlestep = true;
5416         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5417 }
5418
5419 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5420 {
5421         return 0;
5422 }
5423
5424 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5425 {
5426         return 0;
5427 }
5428
5429 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5430 {
5431         struct vcpu_svm *svm = to_svm(vcpu);
5432
5433         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5434                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5435         else
5436                 svm->asid_generation--;
5437 }
5438
5439 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5440 {
5441         struct vcpu_svm *svm = to_svm(vcpu);
5442
5443         invlpga(gva, svm->vmcb->control.asid);
5444 }
5445
5446 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5447 {
5448 }
5449
5450 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5451 {
5452         struct vcpu_svm *svm = to_svm(vcpu);
5453
5454         if (svm_nested_virtualize_tpr(vcpu))
5455                 return;
5456
5457         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5458                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5459                 kvm_set_cr8(vcpu, cr8);
5460         }
5461 }
5462
5463 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5464 {
5465         struct vcpu_svm *svm = to_svm(vcpu);
5466         u64 cr8;
5467
5468         if (svm_nested_virtualize_tpr(vcpu) ||
5469             kvm_vcpu_apicv_active(vcpu))
5470                 return;
5471
5472         cr8 = kvm_get_cr8(vcpu);
5473         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5474         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5475 }
5476
5477 static void svm_complete_interrupts(struct vcpu_svm *svm)
5478 {
5479         u8 vector;
5480         int type;
5481         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5482         unsigned int3_injected = svm->int3_injected;
5483
5484         svm->int3_injected = 0;
5485
5486         /*
5487          * If we've made progress since setting HF_IRET_MASK, we've
5488          * executed an IRET and can allow NMI injection.
5489          */
5490         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5491             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5492                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5493                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5494         }
5495
5496         svm->vcpu.arch.nmi_injected = false;
5497         kvm_clear_exception_queue(&svm->vcpu);
5498         kvm_clear_interrupt_queue(&svm->vcpu);
5499
5500         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5501                 return;
5502
5503         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5504
5505         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5506         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5507
5508         switch (type) {
5509         case SVM_EXITINTINFO_TYPE_NMI:
5510                 svm->vcpu.arch.nmi_injected = true;
5511                 break;
5512         case SVM_EXITINTINFO_TYPE_EXEPT:
5513                 /*
5514                  * In case of software exceptions, do not reinject the vector,
5515                  * but re-execute the instruction instead. Rewind RIP first
5516                  * if we emulated INT3 before.
5517                  */
5518                 if (kvm_exception_is_soft(vector)) {
5519                         if (vector == BP_VECTOR && int3_injected &&
5520                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5521                                 kvm_rip_write(&svm->vcpu,
5522                                               kvm_rip_read(&svm->vcpu) -
5523                                               int3_injected);
5524                         break;
5525                 }
5526                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5527                         u32 err = svm->vmcb->control.exit_int_info_err;
5528                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5529
5530                 } else
5531                         kvm_requeue_exception(&svm->vcpu, vector);
5532                 break;
5533         case SVM_EXITINTINFO_TYPE_INTR:
5534                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5535                 break;
5536         default:
5537                 break;
5538         }
5539 }
5540
5541 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5542 {
5543         struct vcpu_svm *svm = to_svm(vcpu);
5544         struct vmcb_control_area *control = &svm->vmcb->control;
5545
5546         control->exit_int_info = control->event_inj;
5547         control->exit_int_info_err = control->event_inj_err;
5548         control->event_inj = 0;
5549         svm_complete_interrupts(svm);
5550 }
5551
5552 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5553 {
5554         struct vcpu_svm *svm = to_svm(vcpu);
5555
5556         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5557         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5558         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5559
5560         /*
5561          * A vmexit emulation is required before the vcpu can be executed
5562          * again.
5563          */
5564         if (unlikely(svm->nested.exit_required))
5565                 return;
5566
5567         /*
5568          * Disable singlestep if we're injecting an interrupt/exception.
5569          * We don't want our modified rflags to be pushed on the stack where
5570          * we might not be able to easily reset them if we disabled NMI
5571          * singlestep later.
5572          */
5573         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5574                 /*
5575                  * Event injection happens before external interrupts cause a
5576                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5577                  * is enough to force an immediate vmexit.
5578                  */
5579                 disable_nmi_singlestep(svm);
5580                 smp_send_reschedule(vcpu->cpu);
5581         }
5582
5583         pre_svm_run(svm);
5584
5585         sync_lapic_to_cr8(vcpu);
5586
5587         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5588
5589         clgi();
5590
5591         /*
5592          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5593          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5594          * is no need to worry about the conditional branch over the wrmsr
5595          * being speculatively taken.
5596          */
5597         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5598
5599         local_irq_enable();
5600
5601         asm volatile (
5602                 "push %%" _ASM_BP "; \n\t"
5603                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5604                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5605                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5606                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5607                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5608                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5609 #ifdef CONFIG_X86_64
5610                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5611                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5612                 "mov %c[r10](%[svm]), %%r10 \n\t"
5613                 "mov %c[r11](%[svm]), %%r11 \n\t"
5614                 "mov %c[r12](%[svm]), %%r12 \n\t"
5615                 "mov %c[r13](%[svm]), %%r13 \n\t"
5616                 "mov %c[r14](%[svm]), %%r14 \n\t"
5617                 "mov %c[r15](%[svm]), %%r15 \n\t"
5618 #endif
5619
5620                 /* Enter guest mode */
5621                 "push %%" _ASM_AX " \n\t"
5622                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5623                 __ex(SVM_VMLOAD) "\n\t"
5624                 __ex(SVM_VMRUN) "\n\t"
5625                 __ex(SVM_VMSAVE) "\n\t"
5626                 "pop %%" _ASM_AX " \n\t"
5627
5628                 /* Save guest registers, load host registers */
5629                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5630                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5631                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5632                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5633                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5634                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5635 #ifdef CONFIG_X86_64
5636                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5637                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5638                 "mov %%r10, %c[r10](%[svm]) \n\t"
5639                 "mov %%r11, %c[r11](%[svm]) \n\t"
5640                 "mov %%r12, %c[r12](%[svm]) \n\t"
5641                 "mov %%r13, %c[r13](%[svm]) \n\t"
5642                 "mov %%r14, %c[r14](%[svm]) \n\t"
5643                 "mov %%r15, %c[r15](%[svm]) \n\t"
5644                 /*
5645                 * Clear host registers marked as clobbered to prevent
5646                 * speculative use.
5647                 */
5648                 "xor %%r8d, %%r8d \n\t"
5649                 "xor %%r9d, %%r9d \n\t"
5650                 "xor %%r10d, %%r10d \n\t"
5651                 "xor %%r11d, %%r11d \n\t"
5652                 "xor %%r12d, %%r12d \n\t"
5653                 "xor %%r13d, %%r13d \n\t"
5654                 "xor %%r14d, %%r14d \n\t"
5655                 "xor %%r15d, %%r15d \n\t"
5656 #endif
5657                 "xor %%ebx, %%ebx \n\t"
5658                 "xor %%ecx, %%ecx \n\t"
5659                 "xor %%edx, %%edx \n\t"
5660                 "xor %%esi, %%esi \n\t"
5661                 "xor %%edi, %%edi \n\t"
5662                 "pop %%" _ASM_BP
5663                 :
5664                 : [svm]"a"(svm),
5665                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5666                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5667                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5668                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5669                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5670                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5671                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5672 #ifdef CONFIG_X86_64
5673                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5674                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5675                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5676                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5677                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5678                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5679                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5680                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5681 #endif
5682                 : "cc", "memory"
5683 #ifdef CONFIG_X86_64
5684                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5685                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5686 #else
5687                 , "ebx", "ecx", "edx", "esi", "edi"
5688 #endif
5689                 );
5690
5691         /* Eliminate branch target predictions from guest mode */
5692         vmexit_fill_RSB();
5693
5694 #ifdef CONFIG_X86_64
5695         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5696 #else
5697         loadsegment(fs, svm->host.fs);
5698 #ifndef CONFIG_X86_32_LAZY_GS
5699         loadsegment(gs, svm->host.gs);
5700 #endif
5701 #endif
5702
5703         /*
5704          * We do not use IBRS in the kernel. If this vCPU has used the
5705          * SPEC_CTRL MSR it may have left it on; save the value and
5706          * turn it off. This is much more efficient than blindly adding
5707          * it to the atomic save/restore list. Especially as the former
5708          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5709          *
5710          * For non-nested case:
5711          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5712          * save it.
5713          *
5714          * For nested case:
5715          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5716          * save it.
5717          */
5718         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5719                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5720
5721         reload_tss(vcpu);
5722
5723         local_irq_disable();
5724
5725         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5726
5727         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5728         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5729         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5730         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5731
5732         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5733                 kvm_before_interrupt(&svm->vcpu);
5734
5735         stgi();
5736
5737         /* Any pending NMI will happen here */
5738
5739         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5740                 kvm_after_interrupt(&svm->vcpu);
5741
5742         sync_cr8_to_lapic(vcpu);
5743
5744         svm->next_rip = 0;
5745
5746         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5747
5748         /* if exit due to PF check for async PF */
5749         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5750                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5751
5752         if (npt_enabled) {
5753                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5754                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5755         }
5756
5757         /*
5758          * We need to handle MC intercepts here before the vcpu has a chance to
5759          * change the physical cpu
5760          */
5761         if (unlikely(svm->vmcb->control.exit_code ==
5762                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5763                 svm_handle_mce(svm);
5764
5765         mark_all_clean(svm->vmcb);
5766 }
5767 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5768
5769 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5770 {
5771         struct vcpu_svm *svm = to_svm(vcpu);
5772
5773         svm->vmcb->save.cr3 = __sme_set(root);
5774         mark_dirty(svm->vmcb, VMCB_CR);
5775 }
5776
5777 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5778 {
5779         struct vcpu_svm *svm = to_svm(vcpu);
5780
5781         svm->vmcb->control.nested_cr3 = __sme_set(root);
5782         mark_dirty(svm->vmcb, VMCB_NPT);
5783
5784         /* Also sync guest cr3 here in case we live migrate */
5785         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5786         mark_dirty(svm->vmcb, VMCB_CR);
5787 }
5788
5789 static int is_disabled(void)
5790 {
5791         u64 vm_cr;
5792
5793         rdmsrl(MSR_VM_CR, vm_cr);
5794         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5795                 return 1;
5796
5797         return 0;
5798 }
5799
5800 static void
5801 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5802 {
5803         /*
5804          * Patch in the VMMCALL instruction:
5805          */
5806         hypercall[0] = 0x0f;
5807         hypercall[1] = 0x01;
5808         hypercall[2] = 0xd9;
5809 }
5810
5811 static void svm_check_processor_compat(void *rtn)
5812 {
5813         *(int *)rtn = 0;
5814 }
5815
5816 static bool svm_cpu_has_accelerated_tpr(void)
5817 {
5818         return false;
5819 }
5820
5821 static bool svm_has_emulated_msr(int index)
5822 {
5823         return true;
5824 }
5825
5826 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5827 {
5828         return 0;
5829 }
5830
5831 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5832 {
5833         struct vcpu_svm *svm = to_svm(vcpu);
5834
5835         /* Update nrips enabled cache */
5836         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5837
5838         if (!kvm_vcpu_apicv_active(vcpu))
5839                 return;
5840
5841         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5842 }
5843
5844 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5845 {
5846         switch (func) {
5847         case 0x1:
5848                 if (avic)
5849                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5850                 break;
5851         case 0x80000001:
5852                 if (nested)
5853                         entry->ecx |= (1 << 2); /* Set SVM bit */
5854                 break;
5855         case 0x8000000A:
5856                 entry->eax = 1; /* SVM revision 1 */
5857                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5858                                    ASID emulation to nested SVM */
5859                 entry->ecx = 0; /* Reserved */
5860                 entry->edx = 0; /* Per default do not support any
5861                                    additional features */
5862
5863                 /* Support next_rip if host supports it */
5864                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5865                         entry->edx |= SVM_FEATURE_NRIP;
5866
5867                 /* Support NPT for the guest if enabled */
5868                 if (npt_enabled)
5869                         entry->edx |= SVM_FEATURE_NPT;
5870
5871                 break;
5872         case 0x8000001F:
5873                 /* Support memory encryption cpuid if host supports it */
5874                 if (boot_cpu_has(X86_FEATURE_SEV))
5875                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5876                                 &entry->ecx, &entry->edx);
5877
5878         }
5879 }
5880
5881 static int svm_get_lpage_level(void)
5882 {
5883         return PT_PDPE_LEVEL;
5884 }
5885
5886 static bool svm_rdtscp_supported(void)
5887 {
5888         return boot_cpu_has(X86_FEATURE_RDTSCP);
5889 }
5890
5891 static bool svm_invpcid_supported(void)
5892 {
5893         return false;
5894 }
5895
5896 static bool svm_mpx_supported(void)
5897 {
5898         return false;
5899 }
5900
5901 static bool svm_xsaves_supported(void)
5902 {
5903         return false;
5904 }
5905
5906 static bool svm_umip_emulated(void)
5907 {
5908         return false;
5909 }
5910
5911 static bool svm_has_wbinvd_exit(void)
5912 {
5913         return true;
5914 }
5915
5916 #define PRE_EX(exit)  { .exit_code = (exit), \
5917                         .stage = X86_ICPT_PRE_EXCEPT, }
5918 #define POST_EX(exit) { .exit_code = (exit), \
5919                         .stage = X86_ICPT_POST_EXCEPT, }
5920 #define POST_MEM(exit) { .exit_code = (exit), \
5921                         .stage = X86_ICPT_POST_MEMACCESS, }
5922
5923 static const struct __x86_intercept {
5924         u32 exit_code;
5925         enum x86_intercept_stage stage;
5926 } x86_intercept_map[] = {
5927         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5928         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5929         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5930         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5931         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5932         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5933         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5934         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5935         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5936         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5937         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5938         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5939         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5940         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5941         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5942         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5943         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5944         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5945         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5946         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5947         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5948         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5949         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5950         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5951         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5952         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5953         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5954         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5955         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5956         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5957         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5958         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5959         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5960         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5961         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5962         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5963         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5964         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5965         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5966         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5967         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5968         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5969         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5970         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5971         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5972         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5973 };
5974
5975 #undef PRE_EX
5976 #undef POST_EX
5977 #undef POST_MEM
5978
5979 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5980                                struct x86_instruction_info *info,
5981                                enum x86_intercept_stage stage)
5982 {
5983         struct vcpu_svm *svm = to_svm(vcpu);
5984         int vmexit, ret = X86EMUL_CONTINUE;
5985         struct __x86_intercept icpt_info;
5986         struct vmcb *vmcb = svm->vmcb;
5987
5988         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5989                 goto out;
5990
5991         icpt_info = x86_intercept_map[info->intercept];
5992
5993         if (stage != icpt_info.stage)
5994                 goto out;
5995
5996         switch (icpt_info.exit_code) {
5997         case SVM_EXIT_READ_CR0:
5998                 if (info->intercept == x86_intercept_cr_read)
5999                         icpt_info.exit_code += info->modrm_reg;
6000                 break;
6001         case SVM_EXIT_WRITE_CR0: {
6002                 unsigned long cr0, val;
6003                 u64 intercept;
6004
6005                 if (info->intercept == x86_intercept_cr_write)
6006                         icpt_info.exit_code += info->modrm_reg;
6007
6008                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6009                     info->intercept == x86_intercept_clts)
6010                         break;
6011
6012                 intercept = svm->nested.intercept;
6013
6014                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6015                         break;
6016
6017                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6018                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6019
6020                 if (info->intercept == x86_intercept_lmsw) {
6021                         cr0 &= 0xfUL;
6022                         val &= 0xfUL;
6023                         /* lmsw can't clear PE - catch this here */
6024                         if (cr0 & X86_CR0_PE)
6025                                 val |= X86_CR0_PE;
6026                 }
6027
6028                 if (cr0 ^ val)
6029                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6030
6031                 break;
6032         }
6033         case SVM_EXIT_READ_DR0:
6034         case SVM_EXIT_WRITE_DR0:
6035                 icpt_info.exit_code += info->modrm_reg;
6036                 break;
6037         case SVM_EXIT_MSR:
6038                 if (info->intercept == x86_intercept_wrmsr)
6039                         vmcb->control.exit_info_1 = 1;
6040                 else
6041                         vmcb->control.exit_info_1 = 0;
6042                 break;
6043         case SVM_EXIT_PAUSE:
6044                 /*
6045                  * We get this for NOP only, but pause
6046                  * is rep not, check this here
6047                  */
6048                 if (info->rep_prefix != REPE_PREFIX)
6049                         goto out;
6050                 break;
6051         case SVM_EXIT_IOIO: {
6052                 u64 exit_info;
6053                 u32 bytes;
6054
6055                 if (info->intercept == x86_intercept_in ||
6056                     info->intercept == x86_intercept_ins) {
6057                         exit_info = ((info->src_val & 0xffff) << 16) |
6058                                 SVM_IOIO_TYPE_MASK;
6059                         bytes = info->dst_bytes;
6060                 } else {
6061                         exit_info = (info->dst_val & 0xffff) << 16;
6062                         bytes = info->src_bytes;
6063                 }
6064
6065                 if (info->intercept == x86_intercept_outs ||
6066                     info->intercept == x86_intercept_ins)
6067                         exit_info |= SVM_IOIO_STR_MASK;
6068
6069                 if (info->rep_prefix)
6070                         exit_info |= SVM_IOIO_REP_MASK;
6071
6072                 bytes = min(bytes, 4u);
6073
6074                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6075
6076                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6077
6078                 vmcb->control.exit_info_1 = exit_info;
6079                 vmcb->control.exit_info_2 = info->next_rip;
6080
6081                 break;
6082         }
6083         default:
6084                 break;
6085         }
6086
6087         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6088         if (static_cpu_has(X86_FEATURE_NRIPS))
6089                 vmcb->control.next_rip  = info->next_rip;
6090         vmcb->control.exit_code = icpt_info.exit_code;
6091         vmexit = nested_svm_exit_handled(svm);
6092
6093         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6094                                            : X86EMUL_CONTINUE;
6095
6096 out:
6097         return ret;
6098 }
6099
6100 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6101 {
6102         local_irq_enable();
6103         /*
6104          * We must have an instruction with interrupts enabled, so
6105          * the timer interrupt isn't delayed by the interrupt shadow.
6106          */
6107         asm("nop");
6108         local_irq_disable();
6109 }
6110
6111 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6112 {
6113         if (pause_filter_thresh)
6114                 shrink_ple_window(vcpu);
6115 }
6116
6117 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6118 {
6119         if (avic_handle_apic_id_update(vcpu) != 0)
6120                 return;
6121         if (avic_handle_dfr_update(vcpu) != 0)
6122                 return;
6123         avic_handle_ldr_update(vcpu);
6124 }
6125
6126 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6127 {
6128         /* [63:9] are reserved. */
6129         vcpu->arch.mcg_cap &= 0x1ff;
6130 }
6131
6132 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6133 {
6134         struct vcpu_svm *svm = to_svm(vcpu);
6135
6136         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6137         if (!gif_set(svm))
6138                 return 0;
6139
6140         if (is_guest_mode(&svm->vcpu) &&
6141             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6142                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6143                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6144                 svm->nested.exit_required = true;
6145                 return 0;
6146         }
6147
6148         return 1;
6149 }
6150
6151 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6152 {
6153         struct vcpu_svm *svm = to_svm(vcpu);
6154         int ret;
6155
6156         if (is_guest_mode(vcpu)) {
6157                 /* FED8h - SVM Guest */
6158                 put_smstate(u64, smstate, 0x7ed8, 1);
6159                 /* FEE0h - SVM Guest VMCB Physical Address */
6160                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6161
6162                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6163                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6164                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6165
6166                 ret = nested_svm_vmexit(svm);
6167                 if (ret)
6168                         return ret;
6169         }
6170         return 0;
6171 }
6172
6173 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6174 {
6175         struct vcpu_svm *svm = to_svm(vcpu);
6176         struct vmcb *nested_vmcb;
6177         struct page *page;
6178         struct {
6179                 u64 guest;
6180                 u64 vmcb;
6181         } svm_state_save;
6182         int ret;
6183
6184         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6185                                   sizeof(svm_state_save));
6186         if (ret)
6187                 return ret;
6188
6189         if (svm_state_save.guest) {
6190                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6191                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6192                 if (nested_vmcb)
6193                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6194                 else
6195                         ret = 1;
6196                 vcpu->arch.hflags |= HF_SMM_MASK;
6197         }
6198         return ret;
6199 }
6200
6201 static int enable_smi_window(struct kvm_vcpu *vcpu)
6202 {
6203         struct vcpu_svm *svm = to_svm(vcpu);
6204
6205         if (!gif_set(svm)) {
6206                 if (vgif_enabled(svm))
6207                         set_intercept(svm, INTERCEPT_STGI);
6208                 /* STGI will cause a vm exit */
6209                 return 1;
6210         }
6211         return 0;
6212 }
6213
6214 static int sev_asid_new(void)
6215 {
6216         int pos;
6217
6218         /*
6219          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6220          */
6221         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6222         if (pos >= max_sev_asid)
6223                 return -EBUSY;
6224
6225         set_bit(pos, sev_asid_bitmap);
6226         return pos + 1;
6227 }
6228
6229 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6230 {
6231         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6232         int asid, ret;
6233
6234         ret = -EBUSY;
6235         asid = sev_asid_new();
6236         if (asid < 0)
6237                 return ret;
6238
6239         ret = sev_platform_init(&argp->error);
6240         if (ret)
6241                 goto e_free;
6242
6243         sev->active = true;
6244         sev->asid = asid;
6245         INIT_LIST_HEAD(&sev->regions_list);
6246
6247         return 0;
6248
6249 e_free:
6250         __sev_asid_free(asid);
6251         return ret;
6252 }
6253
6254 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6255 {
6256         struct sev_data_activate *data;
6257         int asid = sev_get_asid(kvm);
6258         int ret;
6259
6260         wbinvd_on_all_cpus();
6261
6262         ret = sev_guest_df_flush(error);
6263         if (ret)
6264                 return ret;
6265
6266         data = kzalloc(sizeof(*data), GFP_KERNEL);
6267         if (!data)
6268                 return -ENOMEM;
6269
6270         /* activate ASID on the given handle */
6271         data->handle = handle;
6272         data->asid   = asid;
6273         ret = sev_guest_activate(data, error);
6274         kfree(data);
6275
6276         return ret;
6277 }
6278
6279 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6280 {
6281         struct fd f;
6282         int ret;
6283
6284         f = fdget(fd);
6285         if (!f.file)
6286                 return -EBADF;
6287
6288         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6289
6290         fdput(f);
6291         return ret;
6292 }
6293
6294 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6295 {
6296         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6297
6298         return __sev_issue_cmd(sev->fd, id, data, error);
6299 }
6300
6301 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6302 {
6303         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6304         struct sev_data_launch_start *start;
6305         struct kvm_sev_launch_start params;
6306         void *dh_blob, *session_blob;
6307         int *error = &argp->error;
6308         int ret;
6309
6310         if (!sev_guest(kvm))
6311                 return -ENOTTY;
6312
6313         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6314                 return -EFAULT;
6315
6316         start = kzalloc(sizeof(*start), GFP_KERNEL);
6317         if (!start)
6318                 return -ENOMEM;
6319
6320         dh_blob = NULL;
6321         if (params.dh_uaddr) {
6322                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6323                 if (IS_ERR(dh_blob)) {
6324                         ret = PTR_ERR(dh_blob);
6325                         goto e_free;
6326                 }
6327
6328                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6329                 start->dh_cert_len = params.dh_len;
6330         }
6331
6332         session_blob = NULL;
6333         if (params.session_uaddr) {
6334                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6335                 if (IS_ERR(session_blob)) {
6336                         ret = PTR_ERR(session_blob);
6337                         goto e_free_dh;
6338                 }
6339
6340                 start->session_address = __sme_set(__pa(session_blob));
6341                 start->session_len = params.session_len;
6342         }
6343
6344         start->handle = params.handle;
6345         start->policy = params.policy;
6346
6347         /* create memory encryption context */
6348         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6349         if (ret)
6350                 goto e_free_session;
6351
6352         /* Bind ASID to this guest */
6353         ret = sev_bind_asid(kvm, start->handle, error);
6354         if (ret)
6355                 goto e_free_session;
6356
6357         /* return handle to userspace */
6358         params.handle = start->handle;
6359         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6360                 sev_unbind_asid(kvm, start->handle);
6361                 ret = -EFAULT;
6362                 goto e_free_session;
6363         }
6364
6365         sev->handle = start->handle;
6366         sev->fd = argp->sev_fd;
6367
6368 e_free_session:
6369         kfree(session_blob);
6370 e_free_dh:
6371         kfree(dh_blob);
6372 e_free:
6373         kfree(start);
6374         return ret;
6375 }
6376
6377 static int get_num_contig_pages(int idx, struct page **inpages,
6378                                 unsigned long npages)
6379 {
6380         unsigned long paddr, next_paddr;
6381         int i = idx + 1, pages = 1;
6382
6383         /* find the number of contiguous pages starting from idx */
6384         paddr = __sme_page_pa(inpages[idx]);
6385         while (i < npages) {
6386                 next_paddr = __sme_page_pa(inpages[i++]);
6387                 if ((paddr + PAGE_SIZE) == next_paddr) {
6388                         pages++;
6389                         paddr = next_paddr;
6390                         continue;
6391                 }
6392                 break;
6393         }
6394
6395         return pages;
6396 }
6397
6398 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6399 {
6400         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6401         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6402         struct kvm_sev_launch_update_data params;
6403         struct sev_data_launch_update_data *data;
6404         struct page **inpages;
6405         int i, ret, pages;
6406
6407         if (!sev_guest(kvm))
6408                 return -ENOTTY;
6409
6410         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6411                 return -EFAULT;
6412
6413         data = kzalloc(sizeof(*data), GFP_KERNEL);
6414         if (!data)
6415                 return -ENOMEM;
6416
6417         vaddr = params.uaddr;
6418         size = params.len;
6419         vaddr_end = vaddr + size;
6420
6421         /* Lock the user memory. */
6422         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6423         if (!inpages) {
6424                 ret = -ENOMEM;
6425                 goto e_free;
6426         }
6427
6428         /*
6429          * The LAUNCH_UPDATE command will perform in-place encryption of the
6430          * memory content (i.e it will write the same memory region with C=1).
6431          * It's possible that the cache may contain the data with C=0, i.e.,
6432          * unencrypted so invalidate it first.
6433          */
6434         sev_clflush_pages(inpages, npages);
6435
6436         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6437                 int offset, len;
6438
6439                 /*
6440                  * If the user buffer is not page-aligned, calculate the offset
6441                  * within the page.
6442                  */
6443                 offset = vaddr & (PAGE_SIZE - 1);
6444
6445                 /* Calculate the number of pages that can be encrypted in one go. */
6446                 pages = get_num_contig_pages(i, inpages, npages);
6447
6448                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6449
6450                 data->handle = sev->handle;
6451                 data->len = len;
6452                 data->address = __sme_page_pa(inpages[i]) + offset;
6453                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6454                 if (ret)
6455                         goto e_unpin;
6456
6457                 size -= len;
6458                 next_vaddr = vaddr + len;
6459         }
6460
6461 e_unpin:
6462         /* content of memory is updated, mark pages dirty */
6463         for (i = 0; i < npages; i++) {
6464                 set_page_dirty_lock(inpages[i]);
6465                 mark_page_accessed(inpages[i]);
6466         }
6467         /* unlock the user pages */
6468         sev_unpin_memory(kvm, inpages, npages);
6469 e_free:
6470         kfree(data);
6471         return ret;
6472 }
6473
6474 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6475 {
6476         void __user *measure = (void __user *)(uintptr_t)argp->data;
6477         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6478         struct sev_data_launch_measure *data;
6479         struct kvm_sev_launch_measure params;
6480         void __user *p = NULL;
6481         void *blob = NULL;
6482         int ret;
6483
6484         if (!sev_guest(kvm))
6485                 return -ENOTTY;
6486
6487         if (copy_from_user(&params, measure, sizeof(params)))
6488                 return -EFAULT;
6489
6490         data = kzalloc(sizeof(*data), GFP_KERNEL);
6491         if (!data)
6492                 return -ENOMEM;
6493
6494         /* User wants to query the blob length */
6495         if (!params.len)
6496                 goto cmd;
6497
6498         p = (void __user *)(uintptr_t)params.uaddr;
6499         if (p) {
6500                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6501                         ret = -EINVAL;
6502                         goto e_free;
6503                 }
6504
6505                 ret = -ENOMEM;
6506                 blob = kmalloc(params.len, GFP_KERNEL);
6507                 if (!blob)
6508                         goto e_free;
6509
6510                 data->address = __psp_pa(blob);
6511                 data->len = params.len;
6512         }
6513
6514 cmd:
6515         data->handle = sev->handle;
6516         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6517
6518         /*
6519          * If we query the session length, FW responded with expected data.
6520          */
6521         if (!params.len)
6522                 goto done;
6523
6524         if (ret)
6525                 goto e_free_blob;
6526
6527         if (blob) {
6528                 if (copy_to_user(p, blob, params.len))
6529                         ret = -EFAULT;
6530         }
6531
6532 done:
6533         params.len = data->len;
6534         if (copy_to_user(measure, &params, sizeof(params)))
6535                 ret = -EFAULT;
6536 e_free_blob:
6537         kfree(blob);
6538 e_free:
6539         kfree(data);
6540         return ret;
6541 }
6542
6543 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6544 {
6545         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6546         struct sev_data_launch_finish *data;
6547         int ret;
6548
6549         if (!sev_guest(kvm))
6550                 return -ENOTTY;
6551
6552         data = kzalloc(sizeof(*data), GFP_KERNEL);
6553         if (!data)
6554                 return -ENOMEM;
6555
6556         data->handle = sev->handle;
6557         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6558
6559         kfree(data);
6560         return ret;
6561 }
6562
6563 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6564 {
6565         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6566         struct kvm_sev_guest_status params;
6567         struct sev_data_guest_status *data;
6568         int ret;
6569
6570         if (!sev_guest(kvm))
6571                 return -ENOTTY;
6572
6573         data = kzalloc(sizeof(*data), GFP_KERNEL);
6574         if (!data)
6575                 return -ENOMEM;
6576
6577         data->handle = sev->handle;
6578         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6579         if (ret)
6580                 goto e_free;
6581
6582         params.policy = data->policy;
6583         params.state = data->state;
6584         params.handle = data->handle;
6585
6586         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6587                 ret = -EFAULT;
6588 e_free:
6589         kfree(data);
6590         return ret;
6591 }
6592
6593 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6594                                unsigned long dst, int size,
6595                                int *error, bool enc)
6596 {
6597         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6598         struct sev_data_dbg *data;
6599         int ret;
6600
6601         data = kzalloc(sizeof(*data), GFP_KERNEL);
6602         if (!data)
6603                 return -ENOMEM;
6604
6605         data->handle = sev->handle;
6606         data->dst_addr = dst;
6607         data->src_addr = src;
6608         data->len = size;
6609
6610         ret = sev_issue_cmd(kvm,
6611                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6612                             data, error);
6613         kfree(data);
6614         return ret;
6615 }
6616
6617 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6618                              unsigned long dst_paddr, int sz, int *err)
6619 {
6620         int offset;
6621
6622         /*
6623          * Its safe to read more than we are asked, caller should ensure that
6624          * destination has enough space.
6625          */
6626         src_paddr = round_down(src_paddr, 16);
6627         offset = src_paddr & 15;
6628         sz = round_up(sz + offset, 16);
6629
6630         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6631 }
6632
6633 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6634                                   unsigned long __user dst_uaddr,
6635                                   unsigned long dst_paddr,
6636                                   int size, int *err)
6637 {
6638         struct page *tpage = NULL;
6639         int ret, offset;
6640
6641         /* if inputs are not 16-byte then use intermediate buffer */
6642         if (!IS_ALIGNED(dst_paddr, 16) ||
6643             !IS_ALIGNED(paddr,     16) ||
6644             !IS_ALIGNED(size,      16)) {
6645                 tpage = (void *)alloc_page(GFP_KERNEL);
6646                 if (!tpage)
6647                         return -ENOMEM;
6648
6649                 dst_paddr = __sme_page_pa(tpage);
6650         }
6651
6652         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6653         if (ret)
6654                 goto e_free;
6655
6656         if (tpage) {
6657                 offset = paddr & 15;
6658                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6659                                  page_address(tpage) + offset, size))
6660                         ret = -EFAULT;
6661         }
6662
6663 e_free:
6664         if (tpage)
6665                 __free_page(tpage);
6666
6667         return ret;
6668 }
6669
6670 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6671                                   unsigned long __user vaddr,
6672                                   unsigned long dst_paddr,
6673                                   unsigned long __user dst_vaddr,
6674                                   int size, int *error)
6675 {
6676         struct page *src_tpage = NULL;
6677         struct page *dst_tpage = NULL;
6678         int ret, len = size;
6679
6680         /* If source buffer is not aligned then use an intermediate buffer */
6681         if (!IS_ALIGNED(vaddr, 16)) {
6682                 src_tpage = alloc_page(GFP_KERNEL);
6683                 if (!src_tpage)
6684                         return -ENOMEM;
6685
6686                 if (copy_from_user(page_address(src_tpage),
6687                                 (void __user *)(uintptr_t)vaddr, size)) {
6688                         __free_page(src_tpage);
6689                         return -EFAULT;
6690                 }
6691
6692                 paddr = __sme_page_pa(src_tpage);
6693         }
6694
6695         /*
6696          *  If destination buffer or length is not aligned then do read-modify-write:
6697          *   - decrypt destination in an intermediate buffer
6698          *   - copy the source buffer in an intermediate buffer
6699          *   - use the intermediate buffer as source buffer
6700          */
6701         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6702                 int dst_offset;
6703
6704                 dst_tpage = alloc_page(GFP_KERNEL);
6705                 if (!dst_tpage) {
6706                         ret = -ENOMEM;
6707                         goto e_free;
6708                 }
6709
6710                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6711                                         __sme_page_pa(dst_tpage), size, error);
6712                 if (ret)
6713                         goto e_free;
6714
6715                 /*
6716                  *  If source is kernel buffer then use memcpy() otherwise
6717                  *  copy_from_user().
6718                  */
6719                 dst_offset = dst_paddr & 15;
6720
6721                 if (src_tpage)
6722                         memcpy(page_address(dst_tpage) + dst_offset,
6723                                page_address(src_tpage), size);
6724                 else {
6725                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6726                                            (void __user *)(uintptr_t)vaddr, size)) {
6727                                 ret = -EFAULT;
6728                                 goto e_free;
6729                         }
6730                 }
6731
6732                 paddr = __sme_page_pa(dst_tpage);
6733                 dst_paddr = round_down(dst_paddr, 16);
6734                 len = round_up(size, 16);
6735         }
6736
6737         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6738
6739 e_free:
6740         if (src_tpage)
6741                 __free_page(src_tpage);
6742         if (dst_tpage)
6743                 __free_page(dst_tpage);
6744         return ret;
6745 }
6746
6747 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6748 {
6749         unsigned long vaddr, vaddr_end, next_vaddr;
6750         unsigned long dst_vaddr;
6751         struct page **src_p, **dst_p;
6752         struct kvm_sev_dbg debug;
6753         unsigned long n;
6754         int ret, size;
6755
6756         if (!sev_guest(kvm))
6757                 return -ENOTTY;
6758
6759         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6760                 return -EFAULT;
6761
6762         vaddr = debug.src_uaddr;
6763         size = debug.len;
6764         vaddr_end = vaddr + size;
6765         dst_vaddr = debug.dst_uaddr;
6766
6767         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6768                 int len, s_off, d_off;
6769
6770                 /* lock userspace source and destination page */
6771                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6772                 if (!src_p)
6773                         return -EFAULT;
6774
6775                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6776                 if (!dst_p) {
6777                         sev_unpin_memory(kvm, src_p, n);
6778                         return -EFAULT;
6779                 }
6780
6781                 /*
6782                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6783                  * memory content (i.e it will write the same memory region with C=1).
6784                  * It's possible that the cache may contain the data with C=0, i.e.,
6785                  * unencrypted so invalidate it first.
6786                  */
6787                 sev_clflush_pages(src_p, 1);
6788                 sev_clflush_pages(dst_p, 1);
6789
6790                 /*
6791                  * Since user buffer may not be page aligned, calculate the
6792                  * offset within the page.
6793                  */
6794                 s_off = vaddr & ~PAGE_MASK;
6795                 d_off = dst_vaddr & ~PAGE_MASK;
6796                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6797
6798                 if (dec)
6799                         ret = __sev_dbg_decrypt_user(kvm,
6800                                                      __sme_page_pa(src_p[0]) + s_off,
6801                                                      dst_vaddr,
6802                                                      __sme_page_pa(dst_p[0]) + d_off,
6803                                                      len, &argp->error);
6804                 else
6805                         ret = __sev_dbg_encrypt_user(kvm,
6806                                                      __sme_page_pa(src_p[0]) + s_off,
6807                                                      vaddr,
6808                                                      __sme_page_pa(dst_p[0]) + d_off,
6809                                                      dst_vaddr,
6810                                                      len, &argp->error);
6811
6812                 sev_unpin_memory(kvm, src_p, 1);
6813                 sev_unpin_memory(kvm, dst_p, 1);
6814
6815                 if (ret)
6816                         goto err;
6817
6818                 next_vaddr = vaddr + len;
6819                 dst_vaddr = dst_vaddr + len;
6820                 size -= len;
6821         }
6822 err:
6823         return ret;
6824 }
6825
6826 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6827 {
6828         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6829         struct sev_data_launch_secret *data;
6830         struct kvm_sev_launch_secret params;
6831         struct page **pages;
6832         void *blob, *hdr;
6833         unsigned long n;
6834         int ret, offset;
6835
6836         if (!sev_guest(kvm))
6837                 return -ENOTTY;
6838
6839         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6840                 return -EFAULT;
6841
6842         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6843         if (!pages)
6844                 return -ENOMEM;
6845
6846         /*
6847          * The secret must be copied into contiguous memory region, lets verify
6848          * that userspace memory pages are contiguous before we issue command.
6849          */
6850         if (get_num_contig_pages(0, pages, n) != n) {
6851                 ret = -EINVAL;
6852                 goto e_unpin_memory;
6853         }
6854
6855         ret = -ENOMEM;
6856         data = kzalloc(sizeof(*data), GFP_KERNEL);
6857         if (!data)
6858                 goto e_unpin_memory;
6859
6860         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6861         data->guest_address = __sme_page_pa(pages[0]) + offset;
6862         data->guest_len = params.guest_len;
6863
6864         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6865         if (IS_ERR(blob)) {
6866                 ret = PTR_ERR(blob);
6867                 goto e_free;
6868         }
6869
6870         data->trans_address = __psp_pa(blob);
6871         data->trans_len = params.trans_len;
6872
6873         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6874         if (IS_ERR(hdr)) {
6875                 ret = PTR_ERR(hdr);
6876                 goto e_free_blob;
6877         }
6878         data->hdr_address = __psp_pa(hdr);
6879         data->hdr_len = params.hdr_len;
6880
6881         data->handle = sev->handle;
6882         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6883
6884         kfree(hdr);
6885
6886 e_free_blob:
6887         kfree(blob);
6888 e_free:
6889         kfree(data);
6890 e_unpin_memory:
6891         sev_unpin_memory(kvm, pages, n);
6892         return ret;
6893 }
6894
6895 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6896 {
6897         struct kvm_sev_cmd sev_cmd;
6898         int r;
6899
6900         if (!svm_sev_enabled())
6901                 return -ENOTTY;
6902
6903         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6904                 return -EFAULT;
6905
6906         mutex_lock(&kvm->lock);
6907
6908         switch (sev_cmd.id) {
6909         case KVM_SEV_INIT:
6910                 r = sev_guest_init(kvm, &sev_cmd);
6911                 break;
6912         case KVM_SEV_LAUNCH_START:
6913                 r = sev_launch_start(kvm, &sev_cmd);
6914                 break;
6915         case KVM_SEV_LAUNCH_UPDATE_DATA:
6916                 r = sev_launch_update_data(kvm, &sev_cmd);
6917                 break;
6918         case KVM_SEV_LAUNCH_MEASURE:
6919                 r = sev_launch_measure(kvm, &sev_cmd);
6920                 break;
6921         case KVM_SEV_LAUNCH_FINISH:
6922                 r = sev_launch_finish(kvm, &sev_cmd);
6923                 break;
6924         case KVM_SEV_GUEST_STATUS:
6925                 r = sev_guest_status(kvm, &sev_cmd);
6926                 break;
6927         case KVM_SEV_DBG_DECRYPT:
6928                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6929                 break;
6930         case KVM_SEV_DBG_ENCRYPT:
6931                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6932                 break;
6933         case KVM_SEV_LAUNCH_SECRET:
6934                 r = sev_launch_secret(kvm, &sev_cmd);
6935                 break;
6936         default:
6937                 r = -EINVAL;
6938                 goto out;
6939         }
6940
6941         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6942                 r = -EFAULT;
6943
6944 out:
6945         mutex_unlock(&kvm->lock);
6946         return r;
6947 }
6948
6949 static int svm_register_enc_region(struct kvm *kvm,
6950                                    struct kvm_enc_region *range)
6951 {
6952         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6953         struct enc_region *region;
6954         int ret = 0;
6955
6956         if (!sev_guest(kvm))
6957                 return -ENOTTY;
6958
6959         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6960                 return -EINVAL;
6961
6962         region = kzalloc(sizeof(*region), GFP_KERNEL);
6963         if (!region)
6964                 return -ENOMEM;
6965
6966         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6967         if (!region->pages) {
6968                 ret = -ENOMEM;
6969                 goto e_free;
6970         }
6971
6972         /*
6973          * The guest may change the memory encryption attribute from C=0 -> C=1
6974          * or vice versa for this memory range. Lets make sure caches are
6975          * flushed to ensure that guest data gets written into memory with
6976          * correct C-bit.
6977          */
6978         sev_clflush_pages(region->pages, region->npages);
6979
6980         region->uaddr = range->addr;
6981         region->size = range->size;
6982
6983         mutex_lock(&kvm->lock);
6984         list_add_tail(&region->list, &sev->regions_list);
6985         mutex_unlock(&kvm->lock);
6986
6987         return ret;
6988
6989 e_free:
6990         kfree(region);
6991         return ret;
6992 }
6993
6994 static struct enc_region *
6995 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
6996 {
6997         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6998         struct list_head *head = &sev->regions_list;
6999         struct enc_region *i;
7000
7001         list_for_each_entry(i, head, list) {
7002                 if (i->uaddr == range->addr &&
7003                     i->size == range->size)
7004                         return i;
7005         }
7006
7007         return NULL;
7008 }
7009
7010
7011 static int svm_unregister_enc_region(struct kvm *kvm,
7012                                      struct kvm_enc_region *range)
7013 {
7014         struct enc_region *region;
7015         int ret;
7016
7017         mutex_lock(&kvm->lock);
7018
7019         if (!sev_guest(kvm)) {
7020                 ret = -ENOTTY;
7021                 goto failed;
7022         }
7023
7024         region = find_enc_region(kvm, range);
7025         if (!region) {
7026                 ret = -EINVAL;
7027                 goto failed;
7028         }
7029
7030         __unregister_enc_region_locked(kvm, region);
7031
7032         mutex_unlock(&kvm->lock);
7033         return 0;
7034
7035 failed:
7036         mutex_unlock(&kvm->lock);
7037         return ret;
7038 }
7039
7040 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7041                                    uint16_t *vmcs_version)
7042 {
7043         /* Intel-only feature */
7044         return -ENODEV;
7045 }
7046
7047 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7048         .cpu_has_kvm_support = has_svm,
7049         .disabled_by_bios = is_disabled,
7050         .hardware_setup = svm_hardware_setup,
7051         .hardware_unsetup = svm_hardware_unsetup,
7052         .check_processor_compatibility = svm_check_processor_compat,
7053         .hardware_enable = svm_hardware_enable,
7054         .hardware_disable = svm_hardware_disable,
7055         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7056         .has_emulated_msr = svm_has_emulated_msr,
7057
7058         .vcpu_create = svm_create_vcpu,
7059         .vcpu_free = svm_free_vcpu,
7060         .vcpu_reset = svm_vcpu_reset,
7061
7062         .vm_alloc = svm_vm_alloc,
7063         .vm_free = svm_vm_free,
7064         .vm_init = avic_vm_init,
7065         .vm_destroy = svm_vm_destroy,
7066
7067         .prepare_guest_switch = svm_prepare_guest_switch,
7068         .vcpu_load = svm_vcpu_load,
7069         .vcpu_put = svm_vcpu_put,
7070         .vcpu_blocking = svm_vcpu_blocking,
7071         .vcpu_unblocking = svm_vcpu_unblocking,
7072
7073         .update_bp_intercept = update_bp_intercept,
7074         .get_msr_feature = svm_get_msr_feature,
7075         .get_msr = svm_get_msr,
7076         .set_msr = svm_set_msr,
7077         .get_segment_base = svm_get_segment_base,
7078         .get_segment = svm_get_segment,
7079         .set_segment = svm_set_segment,
7080         .get_cpl = svm_get_cpl,
7081         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7082         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7083         .decache_cr3 = svm_decache_cr3,
7084         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7085         .set_cr0 = svm_set_cr0,
7086         .set_cr3 = svm_set_cr3,
7087         .set_cr4 = svm_set_cr4,
7088         .set_efer = svm_set_efer,
7089         .get_idt = svm_get_idt,
7090         .set_idt = svm_set_idt,
7091         .get_gdt = svm_get_gdt,
7092         .set_gdt = svm_set_gdt,
7093         .get_dr6 = svm_get_dr6,
7094         .set_dr6 = svm_set_dr6,
7095         .set_dr7 = svm_set_dr7,
7096         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7097         .cache_reg = svm_cache_reg,
7098         .get_rflags = svm_get_rflags,
7099         .set_rflags = svm_set_rflags,
7100
7101         .tlb_flush = svm_flush_tlb,
7102         .tlb_flush_gva = svm_flush_tlb_gva,
7103
7104         .run = svm_vcpu_run,
7105         .handle_exit = handle_exit,
7106         .skip_emulated_instruction = skip_emulated_instruction,
7107         .set_interrupt_shadow = svm_set_interrupt_shadow,
7108         .get_interrupt_shadow = svm_get_interrupt_shadow,
7109         .patch_hypercall = svm_patch_hypercall,
7110         .set_irq = svm_set_irq,
7111         .set_nmi = svm_inject_nmi,
7112         .queue_exception = svm_queue_exception,
7113         .cancel_injection = svm_cancel_injection,
7114         .interrupt_allowed = svm_interrupt_allowed,
7115         .nmi_allowed = svm_nmi_allowed,
7116         .get_nmi_mask = svm_get_nmi_mask,
7117         .set_nmi_mask = svm_set_nmi_mask,
7118         .enable_nmi_window = enable_nmi_window,
7119         .enable_irq_window = enable_irq_window,
7120         .update_cr8_intercept = update_cr8_intercept,
7121         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7122         .get_enable_apicv = svm_get_enable_apicv,
7123         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7124         .load_eoi_exitmap = svm_load_eoi_exitmap,
7125         .hwapic_irr_update = svm_hwapic_irr_update,
7126         .hwapic_isr_update = svm_hwapic_isr_update,
7127         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7128         .apicv_post_state_restore = avic_post_state_restore,
7129
7130         .set_tss_addr = svm_set_tss_addr,
7131         .set_identity_map_addr = svm_set_identity_map_addr,
7132         .get_tdp_level = get_npt_level,
7133         .get_mt_mask = svm_get_mt_mask,
7134
7135         .get_exit_info = svm_get_exit_info,
7136
7137         .get_lpage_level = svm_get_lpage_level,
7138
7139         .cpuid_update = svm_cpuid_update,
7140
7141         .rdtscp_supported = svm_rdtscp_supported,
7142         .invpcid_supported = svm_invpcid_supported,
7143         .mpx_supported = svm_mpx_supported,
7144         .xsaves_supported = svm_xsaves_supported,
7145         .umip_emulated = svm_umip_emulated,
7146
7147         .set_supported_cpuid = svm_set_supported_cpuid,
7148
7149         .has_wbinvd_exit = svm_has_wbinvd_exit,
7150
7151         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7152         .write_tsc_offset = svm_write_tsc_offset,
7153
7154         .set_tdp_cr3 = set_tdp_cr3,
7155
7156         .check_intercept = svm_check_intercept,
7157         .handle_external_intr = svm_handle_external_intr,
7158
7159         .request_immediate_exit = __kvm_request_immediate_exit,
7160
7161         .sched_in = svm_sched_in,
7162
7163         .pmu_ops = &amd_pmu_ops,
7164         .deliver_posted_interrupt = svm_deliver_avic_intr,
7165         .update_pi_irte = svm_update_pi_irte,
7166         .setup_mce = svm_setup_mce,
7167
7168         .smi_allowed = svm_smi_allowed,
7169         .pre_enter_smm = svm_pre_enter_smm,
7170         .pre_leave_smm = svm_pre_leave_smm,
7171         .enable_smi_window = enable_smi_window,
7172
7173         .mem_enc_op = svm_mem_enc_op,
7174         .mem_enc_reg_region = svm_register_enc_region,
7175         .mem_enc_unreg_region = svm_unregister_enc_region,
7176
7177         .nested_enable_evmcs = nested_enable_evmcs,
7178 };
7179
7180 static int __init svm_init(void)
7181 {
7182         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7183                         __alignof__(struct vcpu_svm), THIS_MODULE);
7184 }
7185
7186 static void __exit svm_exit(void)
7187 {
7188         kvm_exit();
7189 }
7190
7191 module_init(svm_init)
7192 module_exit(svm_exit)