drivers/mmc/host/sdhci-pci-gli.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Genesys Logic, Inc.
   4  *
   5  * Authors: Ben Chuang <[email protected]>
   6  *
   7  * Version: v0.9.0 (2019-08-08)
   8  */
   9
  10 #include <linux/bitfield.h>
  11 #include <linux/bits.h>
  12 #include <linux/pci.h>
  13 #include <linux/mmc/mmc.h>
  14 #include <linux/delay.h>
  15 #include <linux/of.h>
  16 #include <linux/iopoll.h>
  17 #include "sdhci.h"
  18 #include "sdhci-cqhci.h"
  19 #include "sdhci-pci.h"
  20 #include "cqhci.h"
  21 #include "sdhci-uhs2.h"
  22
  23 /*  Genesys Logic extra registers */
  24 #define SDHCI_GLI_9750_WT         0x800
  25 #define   SDHCI_GLI_9750_WT_EN      BIT(0)
  26 #define   GLI_9750_WT_EN_ON         0x1
  27 #define   GLI_9750_WT_EN_OFF        0x0
  28
  29 #define SDHCI_GLI_9750_CFG2          0x848
  30 #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
  31 #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
  32
  33 #define SDHCI_GLI_9750_DRIVING      0x860
  34 #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
  35 #define   SDHCI_GLI_9750_DRIVING_2    GENMASK(27, 26)
  36 #define   GLI_9750_DRIVING_1_VALUE    0xFFF
  37 #define   GLI_9750_DRIVING_2_VALUE    0x3
  38 #define   SDHCI_GLI_9750_SEL_1        BIT(29)
  39 #define   SDHCI_GLI_9750_SEL_2        BIT(31)
  40 #define   SDHCI_GLI_9750_ALL_RST      (BIT(24)|BIT(25)|BIT(28)|BIT(30))
  41
  42 #define SDHCI_GLI_9750_PLL            0x864
  43 #define   SDHCI_GLI_9750_PLL_LDIV       GENMASK(9, 0)
  44 #define   SDHCI_GLI_9750_PLL_PDIV       GENMASK(14, 12)
  45 #define   SDHCI_GLI_9750_PLL_DIR        BIT(15)
  46 #define   SDHCI_GLI_9750_PLL_TX2_INV    BIT(23)
  47 #define   SDHCI_GLI_9750_PLL_TX2_DLY    GENMASK(22, 20)
  48 #define   GLI_9750_PLL_TX2_INV_VALUE    0x1
  49 #define   GLI_9750_PLL_TX2_DLY_VALUE    0x0
  50 #define   SDHCI_GLI_9750_PLLSSC_STEP    GENMASK(28, 24)
  51 #define   SDHCI_GLI_9750_PLLSSC_EN      BIT(31)
  52
  53 #define SDHCI_GLI_9750_PLLSSC        0x86C
  54 #define   SDHCI_GLI_9750_PLLSSC_PPM    GENMASK(31, 16)
  55
  56 #define SDHCI_GLI_9750_SW_CTRL      0x874
  57 #define   SDHCI_GLI_9750_SW_CTRL_4    GENMASK(7, 6)
  58 #define   GLI_9750_SW_CTRL_4_VALUE    0x3
  59
  60 #define SDHCI_GLI_9750_MISC            0x878
  61 #define   SDHCI_GLI_9750_MISC_TX1_INV    BIT(2)
  62 #define   SDHCI_GLI_9750_MISC_RX_INV     BIT(3)
  63 #define   SDHCI_GLI_9750_MISC_TX1_DLY    GENMASK(6, 4)
  64 #define   GLI_9750_MISC_TX1_INV_VALUE    0x0
  65 #define   GLI_9750_MISC_RX_INV_ON        0x1
  66 #define   GLI_9750_MISC_RX_INV_OFF       0x0
  67 #define   GLI_9750_MISC_RX_INV_VALUE     GLI_9750_MISC_RX_INV_OFF
  68 #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
  69 #define   SDHCI_GLI_9750_MISC_SSC_OFF    BIT(26)
  70
  71 #define SDHCI_GLI_9750_TUNING_CONTROL             0x540
  72 #define   SDHCI_GLI_9750_TUNING_CONTROL_EN          BIT(4)
  73 #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
  74 #define   GLI_9750_TUNING_CONTROL_EN_OFF            0x0
  75 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1    BIT(16)
  76 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2    GENMASK(20, 19)
  77 #define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE    0x1
  78 #define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE    0x2
  79
  80 #define SDHCI_GLI_9750_TUNING_PARAMETERS           0x544
  81 #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
  82 #define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE    0x1
  83
  84 #define SDHCI_GLI_9763E_CTRL_HS400  0x7
  85
  86 #define SDHCI_GLI_9763E_HS400_ES_REG      0x52C
  87 #define   SDHCI_GLI_9763E_HS400_ES_BIT      BIT(8)
  88
  89 #define PCIE_GLI_9763E_VHS       0x884
  90 #define   GLI_9763E_VHS_REV        GENMASK(19, 16)
  91 #define   GLI_9763E_VHS_REV_R      0x0
  92 #define   GLI_9763E_VHS_REV_M      0x1
  93 #define   GLI_9763E_VHS_REV_W      0x2
  94 #define PCIE_GLI_9763E_MB        0x888
  95 #define   GLI_9763E_MB_CMDQ_OFF    BIT(19)
  96 #define   GLI_9763E_MB_ERP_ON      BIT(7)
  97 #define PCIE_GLI_9763E_SCR       0x8E0
  98 #define   GLI_9763E_SCR_AXI_REQ    BIT(9)
  99
 100 #define PCIE_GLI_9763E_CFG       0x8A0
 101 #define   GLI_9763E_CFG_LPSN_DIS   BIT(12)
 102
 103 #define PCIE_GLI_9763E_CFG2      0x8A4
 104 #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
 105 #define   GLI_9763E_CFG2_L1DLY_MID 0x54
 106
 107 #define PCIE_GLI_9763E_MMC_CTRL  0x960
 108 #define   GLI_9763E_HS400_SLOW     BIT(3)
 109
 110 #define PCIE_GLI_9763E_CLKRXDLY  0x934
 111 #define   GLI_9763E_HS400_RXDLY    GENMASK(31, 28)
 112 #define   GLI_9763E_HS400_RXDLY_5  0x5
 113
 114 #define SDHCI_GLI_9763E_CQE_BASE_ADDR    0x200
 115 #define GLI_9763E_CQE_TRNS_MODE    (SDHCI_TRNS_MULTI | \
 116                                     SDHCI_TRNS_BLK_CNT_EN | \
 117                                     SDHCI_TRNS_DMA)
 118
 119 #define PCI_GLI_9755_WT       0x800
 120 #define   PCI_GLI_9755_WT_EN    BIT(0)
 121 #define   GLI_9755_WT_EN_ON     0x1
 122 #define   GLI_9755_WT_EN_OFF    0x0
 123
 124 #define PCI_GLI_9755_PECONF   0x44
 125 #define   PCI_GLI_9755_LFCLK    GENMASK(14, 12)
 126 #define   PCI_GLI_9755_DMACLK   BIT(29)
 127 #define   PCI_GLI_9755_INVERT_CD  BIT(30)
 128 #define   PCI_GLI_9755_INVERT_WP  BIT(31)
 129
 130 #define PCI_GLI_9755_CFG2          0x48
 131 #define   PCI_GLI_9755_CFG2_L1DLY    GENMASK(28, 24)
 132 #define   GLI_9755_CFG2_L1DLY_VALUE  0x1F
 133
 134 #define PCI_GLI_9755_PLL            0x64
 135 #define   PCI_GLI_9755_PLL_LDIV       GENMASK(9, 0)
 136 #define   PCI_GLI_9755_PLL_PDIV       GENMASK(14, 12)
 137 #define   PCI_GLI_9755_PLL_DIR        BIT(15)
 138 #define   PCI_GLI_9755_PLLSSC_STEP    GENMASK(28, 24)
 139 #define   PCI_GLI_9755_PLLSSC_EN      BIT(31)
 140
 141 #define PCI_GLI_9755_PLLSSC        0x68
 142 #define   PCI_GLI_9755_PLLSSC_PPM    GENMASK(15, 0)
 143 #define   PCI_GLI_9755_PLLSSC_RTL             BIT(24)
 144 #define   GLI_9755_PLLSSC_RTL_VALUE           0x1
 145 #define   PCI_GLI_9755_PLLSSC_TRANS_PASS      BIT(27)
 146 #define   GLI_9755_PLLSSC_TRANS_PASS_VALUE    0x1
 147 #define   PCI_GLI_9755_PLLSSC_RECV            GENMASK(29, 28)
 148 #define   GLI_9755_PLLSSC_RECV_VALUE          0x0
 149 #define   PCI_GLI_9755_PLLSSC_TRAN            GENMASK(31, 30)
 150 #define   GLI_9755_PLLSSC_TRAN_VALUE          0x3
 151
 152 #define PCI_GLI_9755_UHS2_PLL            0x6C
 153 #define   PCI_GLI_9755_UHS2_PLL_SSC        GENMASK(9, 8)
 154 #define   GLI_9755_UHS2_PLL_SSC_VALUE      0x0
 155 #define   PCI_GLI_9755_UHS2_PLL_DELAY      BIT(18)
 156 #define   GLI_9755_UHS2_PLL_DELAY_VALUE    0x1
 157 #define   PCI_GLI_9755_UHS2_PLL_PDRST      BIT(27)
 158 #define   GLI_9755_UHS2_PLL_PDRST_VALUE    0x1
 159
 160 #define PCI_GLI_9755_SerDes  0x70
 161 #define   PCI_GLI_9755_UHS2_SERDES_INTR       GENMASK(2, 0)
 162 #define   GLI_9755_UHS2_SERDES_INTR_VALUE     0x3
 163 #define   PCI_GLI_9755_UHS2_SERDES_ZC1        BIT(3)
 164 #define   GLI_9755_UHS2_SERDES_ZC1_VALUE      0x0
 165 #define   PCI_GLI_9755_UHS2_SERDES_ZC2        GENMASK(7, 4)
 166 #define   GLI_9755_UHS2_SERDES_ZC2_DEFAULT    0xB
 167 #define   GLI_9755_UHS2_SERDES_ZC2_SANDISK    0x0
 168 #define PCI_GLI_9755_SCP_DIS   BIT(19)
 169 #define   PCI_GLI_9755_UHS2_SERDES_TRAN       GENMASK(27, 24)
 170 #define   GLI_9755_UHS2_SERDES_TRAN_VALUE     0xC
 171 #define   PCI_GLI_9755_UHS2_SERDES_RECV       GENMASK(31, 28)
 172 #define   GLI_9755_UHS2_SERDES_RECV_VALUE     0xF
 173
 174 #define PCI_GLI_9755_MISC           0x78
 175 #define   PCI_GLI_9755_MISC_SSC_OFF    BIT(26)
 176
 177 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL                            0x508
 178 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK         BIT(0)
 179 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE                   GENMASK(21, 16)
 180 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE     0x05
 181 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE    0x3F
 182 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE             GENMASK(23, 22)
 183 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS         0x2
 184 #define   SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS        0x3
 185
 186 #define SDHCI_GLI_9767_GM_BURST_SIZE                    0x510
 187 #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET     BIT(8)
 188
 189 #define PCIE_GLI_9767_VHS       0x884
 190 #define   GLI_9767_VHS_REV        GENMASK(19, 16)
 191 #define   GLI_9767_VHS_REV_R      0x0
 192 #define   GLI_9767_VHS_REV_M      0x1
 193 #define   GLI_9767_VHS_REV_W      0x2
 194
 195 #define PCIE_GLI_9767_COM_MAILBOX               0x888
 196 #define   PCIE_GLI_9767_COM_MAILBOX_SSC_EN        BIT(1)
 197
 198 #define PCIE_GLI_9767_CFG               0x8A0
 199 #define   PCIE_GLI_9767_CFG_LOW_PWR_OFF   BIT(12)
 200
 201 #define PCIE_GLI_9767_COMBO_MUX_CTL                     0x8C8
 202 #define   PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN              BIT(6)
 203 #define   PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN       BIT(10)
 204
 205 #define PCIE_GLI_9767_PWR_MACRO_CTL                                     0x8D0
 206 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE                         GENMASK(3, 0)
 207 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE              GENMASK(15, 12)
 208 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE        0x7
 209 #define   PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL                  GENMASK(29, 28)
 210 #define   PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE            0x3
 211
 212 #define PCIE_GLI_9767_SCR                               0x8E0
 213 #define   PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST              BIT(6)
 214 #define   PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST              BIT(7)
 215 #define   PCIE_GLI_9767_SCR_AXI_REQ                       BIT(9)
 216 #define   PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN        BIT(10)
 217 #define   PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0       BIT(16)
 218 #define   PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1       BIT(17)
 219 #define   PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF               BIT(21)
 220 #define   PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN        BIT(30)
 221
 222 #define PCIE_GLI_9767_RESET_REG                         0x8E4
 223 #define   PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET        BIT(0)
 224
 225 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1                         0x90C
 226 #define   PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR             GENMASK(31, 29)
 227 #define   PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE       0x3
 228
 229 #define PCIE_GLI_9767_SDHC_CAP                  0x91C
 230 #define   PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT      BIT(5)
 231
 232 #define PCIE_GLI_9767_SD_PLL_CTL                        0x938
 233 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV               GENMASK(9, 0)
 234 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV               GENMASK(15, 12)
 235 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN             BIT(16)
 236 #define   PCIE_GLI_9767_SD_PLL_CTL_SSC_EN                 BIT(19)
 237 #define   PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING       GENMASK(28, 24)
 238
 239 #define PCIE_GLI_9767_SD_PLL_CTL2               0x93C
 240 #define   PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM    GENMASK(31, 16)
 241
 242 #define PCIE_GLI_9767_SD_EXPRESS_CTL                    0x940
 243 #define   PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE           BIT(0)
 244 #define   PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE    BIT(1)
 245
 246 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL                         0x944
 247 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2             BIT(5)
 248 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL         BIT(8)
 249 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME         GENMASK(23, 16)
 250 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE   0x64
 251
 252 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2                                 0x948
 253 #define   PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING                 GENMASK(22, 21)
 254 #define   PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE           0x0
 255
 256 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2                        0x950
 257 #define   PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE          BIT(0)
 258
 259 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2                             0x954
 260 #define   PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN     BIT(0)
 261
 262 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2                             0x958
 263 #define   PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN     BIT(0)
 264
 265 #define PCIE_GLI_9767_UHS2_CTL1                         0x95C
 266 #define   PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS              BIT(5)
 267 #define   PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE        0x1
 268 #define   PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL            BIT(6)
 269 #define   PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE      0x1
 270 #define   PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN             GENMASK(10, 7)
 271 #define   PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE       0x3
 272 #define   PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV             GENMASK(14, 11)
 273 #define   PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE       0xf
 274 #define   PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS               GENMASK(16, 15)
 275 #define   PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE         0x0
 276 #define   PCIE_GLI_9767_UHS2_CTL1_DIR_RECV                GENMASK(18, 17)
 277 #define   PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE          0x0
 278 #define   PCIE_GLI_9767_UHS2_CTL1_PDRST                   BIT(25)
 279 #define   PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE             0x1
 280
 281 #define PCIE_GLI_9767_UHS2_CTL2                 0x964
 282 #define   PCIE_GLI_9767_UHS2_CTL2_ZC              GENMASK(3, 0)
 283 #define   PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE        0xb
 284 #define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL          BIT(6)
 285 #define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE    0x1
 286
 287 #define GLI_MAX_TUNING_LOOP 40
 288
 289 /* Genesys Logic chipset */
 290 static inline void gl9750_wt_on(struct sdhci_host *host)
 291 {
 292         u32 wt_value;
 293         u32 wt_enable;
 294
 295         wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
 296         wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
 297
 298         if (wt_enable == GLI_9750_WT_EN_ON)
 299                 return;
 300
 301         wt_value &= ~SDHCI_GLI_9750_WT_EN;
 302         wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
 303
 304         sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
 305 }
 306
 307 static inline void gl9750_wt_off(struct sdhci_host *host)
 308 {
 309         u32 wt_value;
 310         u32 wt_enable;
 311
 312         wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
 313         wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
 314
 315         if (wt_enable == GLI_9750_WT_EN_OFF)
 316                 return;
 317
 318         wt_value &= ~SDHCI_GLI_9750_WT_EN;
 319         wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
 320
 321         sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
 322 }
 323
 324 static void gli_set_9750(struct sdhci_host *host)
 325 {
 326         u32 driving_value;
 327         u32 pll_value;
 328         u32 sw_ctrl_value;
 329         u32 misc_value;
 330         u32 parameter_value;
 331         u32 control_value;
 332         u16 ctrl2;
 333
 334         gl9750_wt_on(host);
 335
 336         driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
 337         pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 338         sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
 339         misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 340         parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
 341         control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
 342
 343         driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
 344         driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
 345         driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
 346                                     GLI_9750_DRIVING_1_VALUE);
 347         driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
 348                                     GLI_9750_DRIVING_2_VALUE);
 349         driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
 350         driving_value |= SDHCI_GLI_9750_SEL_2;
 351         sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
 352
 353         sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
 354         sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
 355                                     GLI_9750_SW_CTRL_4_VALUE);
 356         sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
 357
 358         /* reset the tuning flow after reinit and before starting tuning */
 359         pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
 360         pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
 361         pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
 362                                 GLI_9750_PLL_TX2_INV_VALUE);
 363         pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
 364                                 GLI_9750_PLL_TX2_DLY_VALUE);
 365
 366         misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
 367         misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
 368         misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
 369         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
 370                                  GLI_9750_MISC_TX1_INV_VALUE);
 371         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 372                                  GLI_9750_MISC_RX_INV_VALUE);
 373         misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
 374                                  GLI_9750_MISC_TX1_DLY_VALUE);
 375
 376         parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
 377         parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
 378                                       GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
 379
 380         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
 381         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
 382         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
 383                                     GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
 384         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
 385                                     GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
 386
 387         sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
 388         sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
 389
 390         /* disable tuned clk */
 391         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 392         ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 393         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 394
 395         /* enable tuning parameters control */
 396         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
 397         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
 398                                     GLI_9750_TUNING_CONTROL_EN_ON);
 399         sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
 400
 401         /* write tuning parameters */
 402         sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
 403
 404         /* disable tuning parameters control */
 405         control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
 406         control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
 407                                     GLI_9750_TUNING_CONTROL_EN_OFF);
 408         sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
 409
 410         /* clear tuned clk */
 411         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 412         ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 413         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 414
 415         gl9750_wt_off(host);
 416 }
 417
 418 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
 419 {
 420         u32 misc_value;
 421
 422         gl9750_wt_on(host);
 423
 424         misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 425         misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
 426         if (b) {
 427                 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 428                                          GLI_9750_MISC_RX_INV_ON);
 429         } else {
 430                 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
 431                                          GLI_9750_MISC_RX_INV_OFF);
 432         }
 433         sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
 434
 435         gl9750_wt_off(host);
 436 }
 437
 438 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
 439 {
 440         int i;
 441         int rx_inv;
 442
 443         for (rx_inv = 0; rx_inv < 2; rx_inv++) {
 444                 gli_set_9750_rx_inv(host, !!rx_inv);
 445                 sdhci_start_tuning(host);
 446
 447                 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
 448                         u16 ctrl;
 449
 450                         sdhci_send_tuning(host, opcode);
 451
 452                         if (!host->tuning_done) {
 453                                 sdhci_abort_tuning(host, opcode);
 454                                 break;
 455                         }
 456
 457                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 458                         if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
 459                                 if (ctrl & SDHCI_CTRL_TUNED_CLK)
 460                                         return 0; /* Success! */
 461                                 break;
 462                         }
 463                 }
 464         }
 465         if (!host->tuning_done) {
 466                 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
 467                         mmc_hostname(host->mmc));
 468                 return -ETIMEDOUT;
 469         }
 470
 471         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
 472                 mmc_hostname(host->mmc));
 473         sdhci_reset_tuning(host);
 474
 475         return -EAGAIN;
 476 }
 477
 478 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
 479 {
 480         host->mmc->retune_period = 0;
 481         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
 482                 host->mmc->retune_period = host->tuning_count;
 483
 484         gli_set_9750(host);
 485         host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
 486         sdhci_end_tuning(host);
 487
 488         return 0;
 489 }
 490
 491 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
 492 {
 493         u32 pll;
 494
 495         gl9750_wt_on(host);
 496         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 497         pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
 498         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 499         gl9750_wt_off(host);
 500 }
 501
 502 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
 503 {
 504         u32 pll;
 505
 506         gl9750_wt_on(host);
 507         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 508         pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
 509                  SDHCI_GLI_9750_PLL_PDIV |
 510                  SDHCI_GLI_9750_PLL_DIR);
 511         pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
 512                FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
 513                FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
 514         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 515         gl9750_wt_off(host);
 516
 517         /* wait for pll stable */
 518         mdelay(1);
 519 }
 520
 521 static bool gl9750_ssc_enable(struct sdhci_host *host)
 522 {
 523         u32 misc;
 524         u8 off;
 525
 526         gl9750_wt_on(host);
 527         misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
 528         off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
 529         gl9750_wt_off(host);
 530
 531         return !off;
 532 }
 533
 534 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
 535 {
 536         u32 pll;
 537         u32 ssc;
 538
 539         gl9750_wt_on(host);
 540         pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
 541         ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
 542         pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
 543                  SDHCI_GLI_9750_PLLSSC_EN);
 544         ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
 545         pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
 546                FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
 547         ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
 548         sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
 549         sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
 550         gl9750_wt_off(host);
 551 }
 552
 553 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
 554 {
 555         bool enable = gl9750_ssc_enable(host);
 556
 557         /* set pll to 205MHz and ssc */
 558         gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
 559         gl9750_set_pll(host, 0x1, 0x246, 0x0);
 560 }
 561
 562 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
 563 {
 564         bool enable = gl9750_ssc_enable(host);
 565
 566         /* set pll to 100MHz and ssc */
 567         gl9750_set_ssc(host, enable, 0xE, 0x51EC);
 568         gl9750_set_pll(host, 0x1, 0x244, 0x1);
 569 }
 570
 571 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
 572 {
 573         bool enable = gl9750_ssc_enable(host);
 574
 575         /* set pll to 50MHz and ssc */
 576         gl9750_set_ssc(host, enable, 0xE, 0x51EC);
 577         gl9750_set_pll(host, 0x1, 0x244, 0x3);
 578 }
 579
 580 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
 581 {
 582         struct mmc_ios *ios = &host->mmc->ios;
 583         u16 clk;
 584
 585         host->mmc->actual_clock = 0;
 586
 587         gl9750_disable_ssc_pll(host);
 588         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 589
 590         if (clock == 0)
 591                 return;
 592
 593         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 594         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
 595                 host->mmc->actual_clock = 205000000;
 596                 gl9750_set_ssc_pll_205mhz(host);
 597         } else if (clock == 100000000) {
 598                 gl9750_set_ssc_pll_100mhz(host);
 599         } else if (clock == 50000000) {
 600                 gl9750_set_ssc_pll_50mhz(host);
 601         }
 602
 603         sdhci_enable_clk(host, clk);
 604 }
 605
 606 static void gl9750_hw_setting(struct sdhci_host *host)
 607 {
 608         struct sdhci_pci_slot *slot = sdhci_priv(host);
 609         struct pci_dev *pdev;
 610         int aer;
 611         u32 value;
 612
 613         pdev = slot->chip->pdev;
 614
 615         gl9750_wt_on(host);
 616
 617         value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
 618         value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
 619         /* set ASPM L1 entry delay to 7.9us */
 620         value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
 621                             GLI_9750_CFG2_L1DLY_VALUE);
 622         sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
 623
 624         /* toggle PM state to allow GL9750 to enter ASPM L1.2 */
 625         pci_set_power_state(pdev, PCI_D3hot);
 626         pci_set_power_state(pdev, PCI_D0);
 627
 628         /* mask the replay timer timeout of AER */
 629         aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 630         if (aer) {
 631                 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
 632                 value |= PCI_ERR_COR_REP_TIMER;
 633                 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
 634         }
 635
 636         gl9750_wt_off(host);
 637 }
 638
 639 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
 640 {
 641         int ret;
 642
 643         ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
 644                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 645         if (ret < 0) {
 646                 pr_warn("%s: enable PCI MSI failed, error=%d\n",
 647                        mmc_hostname(slot->host->mmc), ret);
 648                 return;
 649         }
 650
 651         slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
 652 }
 653
 654 static inline void gl9755_wt_on(struct pci_dev *pdev)
 655 {
 656         u32 wt_value;
 657         u32 wt_enable;
 658
 659         pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
 660         wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
 661
 662         if (wt_enable == GLI_9755_WT_EN_ON)
 663                 return;
 664
 665         wt_value &= ~PCI_GLI_9755_WT_EN;
 666         wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
 667
 668         pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
 669 }
 670
 671 static inline void gl9755_wt_off(struct pci_dev *pdev)
 672 {
 673         u32 wt_value;
 674         u32 wt_enable;
 675
 676         pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
 677         wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
 678
 679         if (wt_enable == GLI_9755_WT_EN_OFF)
 680                 return;
 681
 682         wt_value &= ~PCI_GLI_9755_WT_EN;
 683         wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
 684
 685         pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
 686 }
 687
 688 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
 689 {
 690         u32 pll;
 691
 692         gl9755_wt_on(pdev);
 693         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 694         pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
 695         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 696         gl9755_wt_off(pdev);
 697 }
 698
 699 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
 700 {
 701         u32 pll;
 702
 703         gl9755_wt_on(pdev);
 704         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 705         pll &= ~(PCI_GLI_9755_PLL_LDIV |
 706                  PCI_GLI_9755_PLL_PDIV |
 707                  PCI_GLI_9755_PLL_DIR);
 708         pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
 709                FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
 710                FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
 711         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 712         gl9755_wt_off(pdev);
 713
 714         /* wait for pll stable */
 715         mdelay(1);
 716 }
 717
 718 static bool gl9755_ssc_enable(struct pci_dev *pdev)
 719 {
 720         u32 misc;
 721         u8 off;
 722
 723         gl9755_wt_on(pdev);
 724         pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
 725         off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
 726         gl9755_wt_off(pdev);
 727
 728         return !off;
 729 }
 730
 731 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
 732 {
 733         u32 pll;
 734         u32 ssc;
 735
 736         gl9755_wt_on(pdev);
 737         pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
 738         pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
 739         pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
 740                  PCI_GLI_9755_PLLSSC_EN);
 741         ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
 742         pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
 743                FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
 744         ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
 745         pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
 746         pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
 747         gl9755_wt_off(pdev);
 748 }
 749
 750 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
 751 {
 752         bool enable = gl9755_ssc_enable(pdev);
 753
 754         /* set pll to 205MHz and ssc */
 755         gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
 756         gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
 757 }
 758
 759 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
 760 {
 761         bool enable = gl9755_ssc_enable(pdev);
 762
 763         /* set pll to 100MHz and ssc */
 764         gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
 765         gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
 766 }
 767
 768 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
 769 {
 770         bool enable = gl9755_ssc_enable(pdev);
 771
 772         /* set pll to 50MHz and ssc */
 773         gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
 774         gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
 775 }
 776
 777 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
 778 {
 779         struct sdhci_pci_slot *slot = sdhci_priv(host);
 780         struct mmc_ios *ios = &host->mmc->ios;
 781         struct pci_dev *pdev;
 782         u16 clk;
 783
 784         pdev = slot->chip->pdev;
 785         host->mmc->actual_clock = 0;
 786
 787         gl9755_disable_ssc_pll(pdev);
 788         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 789
 790         if (clock == 0)
 791                 return;
 792
 793         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
 794         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
 795                 host->mmc->actual_clock = 205000000;
 796                 gl9755_set_ssc_pll_205mhz(pdev);
 797         } else if (clock == 100000000) {
 798                 gl9755_set_ssc_pll_100mhz(pdev);
 799         } else if (clock == 50000000) {
 800                 gl9755_set_ssc_pll_50mhz(pdev);
 801         }
 802
 803         sdhci_enable_clk(host, clk);
 804 }
 805
 806 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
 807 {
 808         struct pci_dev *pdev = slot->chip->pdev;
 809         int aer;
 810         u32 value;
 811
 812         gl9755_wt_on(pdev);
 813
 814         pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
 815         /*
 816          * Apple ARM64 platforms using these chips may have
 817          * inverted CD/WP detection.
 818          */
 819         if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
 820                 value |= PCI_GLI_9755_INVERT_CD;
 821         if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
 822                 value |= PCI_GLI_9755_INVERT_WP;
 823         value &= ~PCI_GLI_9755_LFCLK;
 824         value &= ~PCI_GLI_9755_DMACLK;
 825         pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
 826
 827         /* enable short circuit protection */
 828         pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
 829         value &= ~PCI_GLI_9755_SCP_DIS;
 830         pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
 831
 832         pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
 833         value &= ~PCI_GLI_9755_CFG2_L1DLY;
 834         /* set ASPM L1 entry delay to 7.9us */
 835         value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
 836                             GLI_9755_CFG2_L1DLY_VALUE);
 837         pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
 838
 839         /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
 840         pci_set_power_state(pdev, PCI_D3hot);
 841         pci_set_power_state(pdev, PCI_D0);
 842
 843         /* mask the replay timer timeout of AER */
 844         aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 845         if (aer) {
 846                 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
 847                 value |= PCI_ERR_COR_REP_TIMER;
 848                 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
 849         }
 850
 851         gl9755_wt_off(pdev);
 852 }
 853
 854 static void gl9755_vendor_init(struct sdhci_host *host)
 855 {
 856         struct sdhci_pci_slot *slot = sdhci_priv(host);
 857         struct pci_dev *pdev = slot->chip->pdev;
 858         u32 serdes;
 859         u32 pllssc;
 860         u32 uhs2_pll;
 861
 862         gl9755_wt_on(pdev);
 863
 864         pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes);
 865         serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN;
 866         serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN,
 867                              GLI_9755_UHS2_SERDES_TRAN_VALUE);
 868         serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV;
 869         serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV,
 870                              GLI_9755_UHS2_SERDES_RECV_VALUE);
 871         serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR;
 872         serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR,
 873                              GLI_9755_UHS2_SERDES_INTR_VALUE);
 874         serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1;
 875         serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1,
 876                              GLI_9755_UHS2_SERDES_ZC1_VALUE);
 877         serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2;
 878         serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2,
 879                              GLI_9755_UHS2_SERDES_ZC2_DEFAULT);
 880         pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes);
 881
 882         pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll);
 883         uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC;
 884         uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC,
 885                           GLI_9755_UHS2_PLL_SSC_VALUE);
 886         uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY;
 887         uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY,
 888                           GLI_9755_UHS2_PLL_DELAY_VALUE);
 889         uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST;
 890         uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST,
 891                           GLI_9755_UHS2_PLL_PDRST_VALUE);
 892         pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll);
 893
 894         pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc);
 895         pllssc &= ~PCI_GLI_9755_PLLSSC_RTL;
 896         pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL,
 897                           GLI_9755_PLLSSC_RTL_VALUE);
 898         pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS;
 899         pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS,
 900                           GLI_9755_PLLSSC_TRANS_PASS_VALUE);
 901         pllssc &= ~PCI_GLI_9755_PLLSSC_RECV;
 902         pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV,
 903                           GLI_9755_PLLSSC_RECV_VALUE);
 904         pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN;
 905         pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN,
 906                           GLI_9755_PLLSSC_TRAN_VALUE);
 907         pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc);
 908
 909         gl9755_wt_off(pdev);
 910 }
 911
 912 static void sdhci_gli_pre_detect_init(struct sdhci_host *host)
 913 {
 914         /* Need more time on UHS2 detect flow */
 915         sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL);
 916 }
 917
 918 static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable)
 919 {
 920         u32 mask;
 921
 922         mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 923         if (enable)
 924                 mask |= SDHCI_INT_BUS_POWER;
 925         else
 926                 mask &= ~SDHCI_INT_BUS_POWER;
 927
 928         sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE);
 929
 930         mask = sdhci_readl(host, SDHCI_INT_ENABLE);
 931         if (enable)
 932                 mask |= SDHCI_INT_BUS_POWER;
 933         else
 934                 mask &= ~SDHCI_INT_BUS_POWER;
 935
 936         sdhci_writel(host, mask, SDHCI_INT_ENABLE);
 937 }
 938
 939 static void gl9755_set_power(struct sdhci_host *host, unsigned char mode,
 940                              unsigned short vdd)
 941 {
 942         u8 pwr = 0;
 943
 944         if (mode != MMC_POWER_OFF) {
 945                 pwr = sdhci_get_vdd_value(vdd);
 946                 if (!pwr)
 947                         WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd);
 948                 pwr |= SDHCI_VDD2_POWER_180;
 949         }
 950
 951         if (host->pwr == pwr)
 952                 return;
 953
 954         host->pwr = pwr;
 955
 956         if (pwr == 0) {
 957                 sdhci_gli_overcurrent_event_enable(host, false);
 958                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 959         } else {
 960                 sdhci_gli_overcurrent_event_enable(host, false);
 961                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 962
 963                 pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON);
 964
 965                 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);
 966                 /* wait stable */
 967                 mdelay(5);
 968                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 969                 /* wait stable */
 970                 mdelay(5);
 971                 sdhci_gli_overcurrent_event_enable(host, true);
 972         }
 973 }
 974
 975 static bool sdhci_wait_clock_stable(struct sdhci_host *host)
 976 {
 977         u16 clk = 0;
 978
 979         if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
 980                                      10, 20000, false, host, SDHCI_CLOCK_CONTROL)) {
 981                 pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));
 982                 sdhci_dumpregs(host);
 983                 return false;
 984         }
 985         return true;
 986 }
 987
 988 static void sdhci_gli_enable_internal_clock(struct sdhci_host *host)
 989 {
 990         u16 ctrl2;
 991
 992         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 993
 994         sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL);
 995
 996         if (!((ctrl2 & SDHCI_CTRL_V4_MODE) &&
 997               (ctrl2 & SDHCI_CTRL_UHS2_ENABLE))) {
 998                 sdhci_wait_clock_stable(host);
 999                 sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2);
1000         }
1001 }
1002
1003 static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 mask)
1004 {
1005         u8 rst;
1006
1007         /* hw clears the bit when it's done */
1008         if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask),
1009                                      10, 100000, false, host, SDHCI_SOFTWARE_RESET)) {
1010                 pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask);
1011                 sdhci_dumpregs(host);
1012                 /* manual clear */
1013                 sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET);
1014                 return -ETIMEDOUT;
1015         }
1016
1017         return 0;
1018 }
1019
1020 static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host)
1021 {
1022         /* do this on UHS2 mode */
1023         if (host->mmc->uhs2_sd_tran) {
1024                 sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD);
1025                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1026                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1027                 sdhci_uhs2_clear_set_irqs(host,
1028                                           SDHCI_INT_ALL_MASK,
1029                                           SDHCI_UHS2_INT_ERROR_MASK);
1030         }
1031 }
1032
1033 static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask)
1034 {
1035         /* need internal clock */
1036         if (mask & SDHCI_RESET_ALL)
1037                 sdhci_gli_enable_internal_clock(host);
1038
1039         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
1040
1041         /* reset sd-tran on UHS2 mode if need to reset cmd/data */
1042         if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA))
1043                 sdhci_gli_uhs2_reset_sd_tran(host);
1044
1045         if (mask & SDHCI_RESET_ALL)
1046                 host->clock = 0;
1047
1048         sdhci_gli_wait_software_reset_done(host, mask);
1049 }
1050
1051 static inline void gl9767_vhs_read(struct pci_dev *pdev)
1052 {
1053         u32 vhs_enable;
1054         u32 vhs_value;
1055
1056         pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
1057         vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
1058
1059         if (vhs_enable == GLI_9767_VHS_REV_R)
1060                 return;
1061
1062         vhs_value &= ~GLI_9767_VHS_REV;
1063         vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);
1064
1065         pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
1066 }
1067
1068 static inline void gl9767_vhs_write(struct pci_dev *pdev)
1069 {
1070         u32 vhs_enable;
1071         u32 vhs_value;
1072
1073         pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
1074         vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
1075
1076         if (vhs_enable == GLI_9767_VHS_REV_W)
1077                 return;
1078
1079         vhs_value &= ~GLI_9767_VHS_REV;
1080         vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);
1081
1082         pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
1083 }
1084
1085 static bool gl9767_ssc_enable(struct pci_dev *pdev)
1086 {
1087         u32 value;
1088         u8 enable;
1089
1090         gl9767_vhs_write(pdev);
1091
1092         pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
1093         enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
1094
1095         gl9767_vhs_read(pdev);
1096
1097         return enable;
1098 }
1099
1100 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
1101 {
1102         u32 pll;
1103         u32 ssc;
1104
1105         gl9767_vhs_write(pdev);
1106
1107         pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
1108         pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
1109         pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
1110                  PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
1111         ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
1112         pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
1113                FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
1114         ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
1115         pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
1116         pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
1117
1118         gl9767_vhs_read(pdev);
1119 }
1120
1121 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
1122 {
1123         u32 pll;
1124
1125         gl9767_vhs_write(pdev);
1126
1127         pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
1128         pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
1129                  PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
1130                  PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
1131         pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
1132                FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
1133                FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
1134         pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
1135
1136         gl9767_vhs_read(pdev);
1137
1138         /* wait for pll stable */
1139         usleep_range(1000, 1100);
1140 }
1141
1142 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
1143 {
1144         bool enable = gl9767_ssc_enable(pdev);
1145
1146         /* set pll to 205MHz and ssc */
1147         gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
1148         gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
1149 }
1150
1151 static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
1152 {
1153         u32 pll;
1154
1155         gl9767_vhs_write(pdev);
1156
1157         pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
1158         pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
1159         pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
1160
1161         gl9767_vhs_read(pdev);
1162 }
1163
1164 static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable)
1165 {
1166         u32 value;
1167
1168         gl9767_vhs_write(pdev);
1169
1170         pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1171         if (enable)
1172                 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1173         else
1174                 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1175         pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1176
1177         gl9767_vhs_read(pdev);
1178 }
1179
1180 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
1181 {
1182         struct sdhci_pci_slot *slot = sdhci_priv(host);
1183         struct mmc_ios *ios = &host->mmc->ios;
1184         struct pci_dev *pdev;
1185         u16 clk;
1186
1187         pdev = slot->chip->pdev;
1188         host->mmc->actual_clock = 0;
1189
1190         gl9767_set_low_power_negotiation(pdev, false);
1191         gl9767_disable_ssc_pll(pdev);
1192         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1193
1194         if (clock == 0) {
1195                 gl9767_set_low_power_negotiation(pdev, true);
1196                 return;
1197         }
1198
1199         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1200         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
1201                 host->mmc->actual_clock = 205000000;
1202                 gl9767_set_ssc_pll_205mhz(pdev);
1203         }
1204
1205         sdhci_enable_clk(host, clk);
1206         gl9767_set_low_power_negotiation(pdev, true);
1207 }
1208
1209 static void sdhci_gl9767_set_card_detect_debounce_time(struct sdhci_host *host)
1210 {
1211         u32 value;
1212
1213         value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);
1214         value &= ~(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE |
1215                    SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE);
1216         if (sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1217                 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE,
1218                                     SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE) |
1219                          FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE,
1220                                     SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS);
1221         else
1222                 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE,
1223                                     SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE) |
1224                          FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE,
1225                                     SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS);
1226         sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);
1227 }
1228
1229 static void sdhci_gl9767_card_event(struct sdhci_host *host)
1230 {
1231         sdhci_gl9767_set_card_detect_debounce_time(host);
1232 }
1233
1234 static void gli_set_9767(struct sdhci_host *host)
1235 {
1236         u32 value;
1237
1238         value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
1239         value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;
1240         sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
1241
1242         value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);
1243         value &= ~SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK;
1244         sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL);
1245
1246         sdhci_gl9767_set_card_detect_debounce_time(host);
1247 }
1248
1249 static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
1250 {
1251         struct pci_dev *pdev = slot->chip->pdev;
1252         u32 value;
1253
1254         gl9767_vhs_write(pdev);
1255
1256         pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
1257         value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
1258                    PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |
1259                    PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);
1260
1261         value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
1262                  FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,
1263                             PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |
1264                  FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,
1265                             PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);
1266         pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
1267
1268         pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
1269         value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |
1270                    PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |
1271                    PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);
1272
1273         value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |
1274                  PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |
1275                  PCIE_GLI_9767_SCR_AXI_REQ |
1276                  PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |
1277                  PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
1278         pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
1279
1280         gl9767_vhs_read(pdev);
1281 }
1282
1283 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
1284 {
1285         struct sdhci_pci_slot *slot = sdhci_priv(host);
1286         struct pci_dev *pdev = slot->chip->pdev;
1287         u32 value;
1288
1289         /* need internal clock */
1290         if (mask & SDHCI_RESET_ALL) {
1291                 sdhci_gli_enable_internal_clock(host);
1292
1293                 gl9767_vhs_write(pdev);
1294
1295                 pci_read_config_dword(pdev, PCIE_GLI_9767_RESET_REG, &value);
1296                 value &= ~PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET;
1297                 pci_write_config_dword(pdev, PCIE_GLI_9767_RESET_REG, value);
1298
1299                 if (read_poll_timeout_atomic(pci_read_config_dword, value,
1300                                              !(value & PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET),
1301                                              1, 5, true, pdev, PCIE_GLI_9767_RESET_REG, &value)) {
1302                         pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n",
1303                                 __func__, mmc_hostname(host->mmc));
1304                         gl9767_vhs_read(pdev);
1305                         return;
1306                 }
1307                 gl9767_vhs_read(pdev);
1308         }
1309
1310         if (mmc_card_uhs2(host->mmc)) {
1311                 if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) {
1312                         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
1313                         sdhci_gli_uhs2_reset_sd_tran(host);
1314                         sdhci_gli_wait_software_reset_done(host, mask);
1315                 } else {
1316                         sdhci_uhs2_reset(host, mask);
1317                 }
1318         } else {
1319                 sdhci_reset(host, mask);
1320         }
1321
1322         gli_set_9767(host);
1323 }
1324
1325 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
1326 {
1327         struct sdhci_host *host = mmc_priv(mmc);
1328         struct sdhci_pci_slot *slot = sdhci_priv(host);
1329         struct pci_dev *pdev;
1330         u32 value;
1331         int i;
1332
1333         pdev = slot->chip->pdev;
1334
1335         if (mmc->ops->get_ro(mmc)) {
1336                 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
1337                 return 0;
1338         }
1339
1340         gl9767_vhs_write(pdev);
1341
1342         pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
1343         value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
1344         pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
1345
1346         pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
1347         value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
1348         value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
1349                             PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
1350         pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
1351
1352         pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1353         value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
1354         pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
1355
1356         pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
1357         value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
1358         pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
1359
1360         pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
1361         value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
1362         pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
1363
1364         pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1365         value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1366         pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1367
1368         value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1369         value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
1370         sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1371
1372         value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1373         value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
1374         sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1375
1376         pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1377         value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
1378         pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1379
1380         for (i = 0; i < 2; i++) {
1381                 usleep_range(10000, 10100);
1382                 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1383                 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
1384                         pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
1385                                                value);
1386                         break;
1387                 }
1388         }
1389
1390         pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
1391         if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
1392                 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1393                 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
1394                 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1395         } else {
1396                 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
1397
1398                 value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1399                 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
1400                 sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1401
1402                 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1403                 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
1404                 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1405         }
1406
1407         pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1408         value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1409         pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1410         gl9767_vhs_read(pdev);
1411
1412         return 0;
1413 }
1414
1415 static void gl9767_vendor_init(struct sdhci_host *host)
1416 {
1417         struct sdhci_pci_slot *slot = sdhci_priv(host);
1418         struct pci_dev *pdev = slot->chip->pdev;
1419         u32 value;
1420
1421         gl9767_vhs_write(pdev);
1422
1423         pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value);
1424         value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR,
1425                             PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE);
1426         pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value);
1427
1428         pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value);
1429         value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING,
1430                             PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE);
1431         pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value);
1432
1433         pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value);
1434         value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS,
1435                             PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) |
1436                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL,
1437                             PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) |
1438                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN,
1439                             PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) |
1440                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV,
1441                             PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) |
1442                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS,
1443                             PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) |
1444                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV,
1445                             PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) |
1446                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST,
1447                             PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE);
1448         pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value);
1449
1450         pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
1451         value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC,
1452                             PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) |
1453                  FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL,
1454                             PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE);
1455         pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
1456
1457         gl9767_vhs_read(pdev);
1458 }
1459
1460 static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)
1461 {
1462         struct sdhci_pci_slot *slot = sdhci_priv(host);
1463         struct pci_dev *pdev = slot->chip->pdev;
1464         u32 value;
1465
1466         if (mmc_card_uhs2(host->mmc)) {
1467                 gl9767_vhs_write(pdev);
1468
1469                 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
1470                 value |= PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 |
1471                          PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL;
1472                 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
1473
1474                 gl9767_vhs_read(pdev);
1475
1476                 sdhci_gli_overcurrent_event_enable(host, false);
1477                 sdhci_uhs2_set_power(host, mode, vdd);
1478                 sdhci_gli_overcurrent_event_enable(host, true);
1479         } else {
1480                 gl9767_vhs_write(pdev);
1481
1482                 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
1483                 value &= ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 |
1484                            PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL);
1485                 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
1486
1487                 gl9767_vhs_read(pdev);
1488
1489                 sdhci_gli_overcurrent_event_enable(host, false);
1490                 sdhci_set_power(host, mode, vdd);
1491                 sdhci_gli_overcurrent_event_enable(host, true);
1492         }
1493 }
1494
1495 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
1496 {
1497         struct sdhci_host *host = slot->host;
1498
1499         gl9750_hw_setting(host);
1500         gli_pcie_enable_msi(slot);
1501         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1502         sdhci_enable_v4_mode(host);
1503
1504         return 0;
1505 }
1506
1507 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
1508 {
1509         struct sdhci_host *host = slot->host;
1510
1511         gl9755_hw_setting(slot);
1512         gli_pcie_enable_msi(slot);
1513         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1514         sdhci_enable_v4_mode(host);
1515         gl9755_vendor_init(host);
1516
1517         return 0;
1518 }
1519
1520 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
1521 {
1522         struct sdhci_host *host = slot->host;
1523
1524         gli_set_9767(host);
1525         gl9767_hw_setting(slot);
1526         gli_pcie_enable_msi(slot);
1527         slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1528         host->mmc->caps2 |= MMC_CAP2_SD_EXP;
1529         host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
1530         sdhci_enable_v4_mode(host);
1531         gl9767_vendor_init(host);
1532
1533         return 0;
1534 }
1535
1536 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
1537 {
1538         /*
1539          * According to Section 3.6.1 signal voltage switch procedure in
1540          * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1541          * follows:
1542          * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1543          * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1544          *     period.
1545          * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1546          *     step (12).
1547          *
1548          * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1549          * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
1550          *
1551          * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
1552          * slightly longer than 5ms before the control register reports that
1553          * 1.8V is ready, and far longer still before the card will actually
1554          * work reliably.
1555          */
1556         usleep_range(100000, 110000);
1557 }
1558
1559 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
1560 {
1561         /*
1562          * According to Section 3.6.1 signal voltage switch procedure in
1563          * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1564          * follows:
1565          * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1566          * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1567          *     period.
1568          * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1569          *     step (12).
1570          *
1571          * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1572          * to ensure 1.8V signal enable bit is set by GL9767.
1573          *
1574          */
1575         usleep_range(5000, 5500);
1576 }
1577
1578 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
1579 {
1580         sdhci_reset(host, mask);
1581         gli_set_9750(host);
1582 }
1583
1584 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
1585 {
1586         u32 value;
1587
1588         value = readl(host->ioaddr + reg);
1589         if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
1590                 value |= 0xc8;
1591
1592         return value;
1593 }
1594
1595 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
1596                                           struct mmc_ios *ios)
1597 {
1598         struct sdhci_host *host = mmc_priv(mmc);
1599         u32 val;
1600
1601         val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
1602         if (ios->enhanced_strobe)
1603                 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
1604         else
1605                 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
1606
1607         sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
1608 }
1609
1610 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot,
1611                                               bool enable)
1612 {
1613         struct pci_dev *pdev = slot->chip->pdev;
1614         u32 value;
1615
1616         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1617         value &= ~GLI_9763E_VHS_REV;
1618         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1619         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1620
1621         pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);
1622
1623         if (enable)
1624                 value &= ~GLI_9763E_CFG_LPSN_DIS;
1625         else
1626                 value |= GLI_9763E_CFG_LPSN_DIS;
1627
1628         pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);
1629
1630         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1631         value &= ~GLI_9763E_VHS_REV;
1632         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1633         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1634 }
1635
1636 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
1637                                         unsigned int timing)
1638 {
1639         u16 ctrl_2;
1640
1641         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1642         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1643         if (timing == MMC_TIMING_MMC_HS200)
1644                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1645         else if (timing == MMC_TIMING_MMC_HS)
1646                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1647         else if (timing == MMC_TIMING_MMC_DDR52)
1648                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1649         else if (timing == MMC_TIMING_MMC_HS400)
1650                 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
1651
1652         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1653 }
1654
1655 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
1656 {
1657         sdhci_dumpregs(mmc_priv(mmc));
1658 }
1659
1660 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
1661 {
1662         struct cqhci_host *cq_host = mmc->cqe_private;
1663         u32 value;
1664
1665         value = cqhci_readl(cq_host, CQHCI_CFG);
1666         value |= CQHCI_ENABLE;
1667         cqhci_writel(cq_host, value, CQHCI_CFG);
1668 }
1669
1670 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
1671 {
1672         struct sdhci_host *host = mmc_priv(mmc);
1673
1674         sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1675         sdhci_cqe_enable(mmc);
1676 }
1677
1678 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
1679 {
1680         int cmd_error = 0;
1681         int data_error = 0;
1682
1683         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1684                 return intmask;
1685
1686         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1687
1688         return 0;
1689 }
1690
1691 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
1692 {
1693         struct sdhci_host *host = mmc_priv(mmc);
1694         struct cqhci_host *cq_host = mmc->cqe_private;
1695         u32 value;
1696
1697         value = cqhci_readl(cq_host, CQHCI_CFG);
1698         value &= ~CQHCI_ENABLE;
1699         cqhci_writel(cq_host, value, CQHCI_CFG);
1700         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1701 }
1702
1703 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
1704         .enable         = sdhci_gl9763e_cqe_enable,
1705         .disable        = sdhci_cqe_disable,
1706         .dumpregs       = sdhci_gl9763e_dumpregs,
1707         .pre_enable     = sdhci_gl9763e_cqe_pre_enable,
1708         .post_disable   = sdhci_gl9763e_cqe_post_disable,
1709 };
1710
1711 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
1712 {
1713         struct device *dev = &slot->chip->pdev->dev;
1714         struct sdhci_host *host = slot->host;
1715         struct cqhci_host *cq_host;
1716         bool dma64;
1717         int ret;
1718
1719         ret = sdhci_setup_host(host);
1720         if (ret)
1721                 return ret;
1722
1723         cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
1724         if (!cq_host) {
1725                 ret = -ENOMEM;
1726                 goto cleanup;
1727         }
1728
1729         cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
1730         cq_host->ops = &sdhci_gl9763e_cqhci_ops;
1731
1732         dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1733         if (dma64)
1734                 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1735
1736         ret = cqhci_init(cq_host, host->mmc, dma64);
1737         if (ret)
1738                 goto cleanup;
1739
1740         ret = __sdhci_add_host(host);
1741         if (ret)
1742                 goto cleanup;
1743
1744         /* Disable LPM negotiation to avoid entering L1 state. */
1745         gl9763e_set_low_power_negotiation(slot, false);
1746
1747         return 0;
1748
1749 cleanup:
1750         sdhci_cleanup_host(host);
1751         return ret;
1752 }
1753
1754 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
1755 {
1756         struct pci_dev *pdev = slot->chip->pdev;
1757         u32 value;
1758
1759         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1760         value &= ~GLI_9763E_VHS_REV;
1761         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1762         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1763
1764         pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
1765         value |= GLI_9763E_SCR_AXI_REQ;
1766         pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
1767
1768         pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
1769         value &= ~GLI_9763E_HS400_SLOW;
1770         pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
1771
1772         pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
1773         value &= ~GLI_9763E_CFG2_L1DLY;
1774         /* set ASPM L1 entry delay to 21us */
1775         value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
1776         pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
1777
1778         pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
1779         value &= ~GLI_9763E_HS400_RXDLY;
1780         value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
1781         pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
1782
1783         pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1784         value &= ~GLI_9763E_VHS_REV;
1785         value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1786         pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1787 }
1788
1789 #ifdef CONFIG_PM
1790 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)
1791 {
1792         struct sdhci_pci_slot *slot = chip->slots[0];
1793         struct sdhci_host *host = slot->host;
1794         u16 clock;
1795
1796         /* Enable LPM negotiation to allow entering L1 state */
1797         gl9763e_set_low_power_negotiation(slot, true);
1798
1799         clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1800         clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);
1801         sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1802
1803         return 0;
1804 }
1805
1806 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)
1807 {
1808         struct sdhci_pci_slot *slot = chip->slots[0];
1809         struct sdhci_host *host = slot->host;
1810         u16 clock;
1811
1812         if (host->mmc->ios.power_mode != MMC_POWER_ON)
1813                 return 0;
1814
1815         clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1816
1817         clock |= SDHCI_CLOCK_PLL_EN;
1818         clock &= ~SDHCI_CLOCK_INT_STABLE;
1819         sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1820
1821         /* Wait max 150 ms */
1822         if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
1823                               1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
1824                 pr_err("%s: PLL clock never stabilised.\n",
1825                        mmc_hostname(host->mmc));
1826                 sdhci_dumpregs(host);
1827         }
1828
1829         clock |= SDHCI_CLOCK_CARD_EN;
1830         sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1831
1832         /* Disable LPM negotiation to avoid entering L1 state. */
1833         gl9763e_set_low_power_negotiation(slot, false);
1834
1835         return 0;
1836 }
1837 #endif
1838
1839 #ifdef CONFIG_PM_SLEEP
1840 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
1841 {
1842         struct sdhci_pci_slot *slot = chip->slots[0];
1843
1844         pci_free_irq_vectors(slot->chip->pdev);
1845         gli_pcie_enable_msi(slot);
1846
1847         return sdhci_pci_resume_host(chip);
1848 }
1849
1850 static int gl9763e_resume(struct sdhci_pci_chip *chip)
1851 {
1852         struct sdhci_pci_slot *slot = chip->slots[0];
1853         int ret;
1854
1855         ret = sdhci_pci_gli_resume(chip);
1856         if (ret)
1857                 return ret;
1858
1859         ret = cqhci_resume(slot->host->mmc);
1860         if (ret)
1861                 return ret;
1862
1863         /*
1864          * Disable LPM negotiation to bring device back in sync
1865          * with its runtime_pm state.
1866          */
1867         gl9763e_set_low_power_negotiation(slot, false);
1868
1869         return 0;
1870 }
1871
1872 static int gl9763e_suspend(struct sdhci_pci_chip *chip)
1873 {
1874         struct sdhci_pci_slot *slot = chip->slots[0];
1875         int ret;
1876
1877         /*
1878          * Certain SoCs can suspend only with the bus in low-
1879          * power state, notably x86 SoCs when using S0ix.
1880          * Re-enable LPM negotiation to allow entering L1 state
1881          * and entering system suspend.
1882          */
1883         gl9763e_set_low_power_negotiation(slot, true);
1884
1885         ret = cqhci_suspend(slot->host->mmc);
1886         if (ret)
1887                 goto err_suspend;
1888
1889         ret = sdhci_suspend_host(slot->host);
1890         if (ret)
1891                 goto err_suspend_host;
1892
1893         return 0;
1894
1895 err_suspend_host:
1896         cqhci_resume(slot->host->mmc);
1897 err_suspend:
1898         gl9763e_set_low_power_negotiation(slot, false);
1899         return ret;
1900 }
1901 #endif
1902
1903 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
1904 {
1905         struct pci_dev *pdev = slot->chip->pdev;
1906         struct sdhci_host *host = slot->host;
1907         u32 value;
1908
1909         host->mmc->caps |= MMC_CAP_8_BIT_DATA |
1910                            MMC_CAP_1_8V_DDR |
1911                            MMC_CAP_NONREMOVABLE;
1912         host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
1913                             MMC_CAP2_HS400_1_8V |
1914                             MMC_CAP2_HS400_ES |
1915                             MMC_CAP2_NO_SDIO |
1916                             MMC_CAP2_NO_SD;
1917
1918         pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
1919         if (!(value & GLI_9763E_MB_CMDQ_OFF))
1920                 if (value & GLI_9763E_MB_ERP_ON)
1921                         host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1922
1923         gli_pcie_enable_msi(slot);
1924         host->mmc_host_ops.hs400_enhanced_strobe =
1925                                         gl9763e_hs400_enhanced_strobe;
1926         gli_set_gl9763e(slot);
1927         sdhci_enable_v4_mode(host);
1928
1929         return 0;
1930 }
1931
1932 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
1933
1934 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1935 {
1936         u32 val = readl(host->ioaddr + (reg & ~3));
1937         u16 word;
1938
1939         word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
1940         return word;
1941 }
1942
1943 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1944 {
1945         u32 val = readl(host->ioaddr + (reg & ~3));
1946         u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
1947
1948         return byte;
1949 }
1950
1951 static const struct sdhci_ops sdhci_gl9755_ops = {
1952         .read_w                 = sdhci_gli_readw,
1953         .read_b                 = sdhci_gli_readb,
1954         .set_clock              = sdhci_gl9755_set_clock,
1955         .set_power              = gl9755_set_power,
1956         .enable_dma             = sdhci_pci_enable_dma,
1957         .set_bus_width          = sdhci_set_bus_width,
1958         .reset                  = sdhci_gl9755_reset,
1959         .set_uhs_signaling      = sdhci_set_uhs_signaling,
1960         .voltage_switch         = sdhci_gli_voltage_switch,
1961         .dump_uhs2_regs         = sdhci_uhs2_dump_regs,
1962         .set_timeout            = sdhci_uhs2_set_timeout,
1963         .irq                    = sdhci_uhs2_irq,
1964         .uhs2_pre_detect_init   = sdhci_gli_pre_detect_init,
1965 };
1966
1967 const struct sdhci_pci_fixes sdhci_gl9755 = {
1968         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1969         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
1970         .probe_slot     = gli_probe_slot_gl9755,
1971         .add_host       = sdhci_pci_uhs2_add_host,
1972         .remove_host    = sdhci_pci_uhs2_remove_host,
1973         .ops            = &sdhci_gl9755_ops,
1974 #ifdef CONFIG_PM_SLEEP
1975         .resume         = sdhci_pci_gli_resume,
1976 #endif
1977 };
1978
1979 static const struct sdhci_ops sdhci_gl9750_ops = {
1980         .read_w                 = sdhci_gli_readw,
1981         .read_b                 = sdhci_gli_readb,
1982         .read_l                 = sdhci_gl9750_readl,
1983         .set_clock              = sdhci_gl9750_set_clock,
1984         .enable_dma             = sdhci_pci_enable_dma,
1985         .set_bus_width          = sdhci_set_bus_width,
1986         .reset                  = sdhci_gl9750_reset,
1987         .set_uhs_signaling      = sdhci_set_uhs_signaling,
1988         .voltage_switch         = sdhci_gli_voltage_switch,
1989         .platform_execute_tuning = gl9750_execute_tuning,
1990 };
1991
1992 const struct sdhci_pci_fixes sdhci_gl9750 = {
1993         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1994         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
1995         .probe_slot     = gli_probe_slot_gl9750,
1996         .ops            = &sdhci_gl9750_ops,
1997 #ifdef CONFIG_PM_SLEEP
1998         .resume         = sdhci_pci_gli_resume,
1999 #endif
2000 };
2001
2002 static const struct sdhci_ops sdhci_gl9763e_ops = {
2003         .set_clock              = sdhci_set_clock,
2004         .enable_dma             = sdhci_pci_enable_dma,
2005         .set_bus_width          = sdhci_set_bus_width,
2006         .reset                  = sdhci_and_cqhci_reset,
2007         .set_uhs_signaling      = sdhci_set_gl9763e_signaling,
2008         .voltage_switch         = sdhci_gli_voltage_switch,
2009         .irq                    = sdhci_gl9763e_cqhci_irq,
2010 };
2011
2012 const struct sdhci_pci_fixes sdhci_gl9763e = {
2013         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
2014         .probe_slot     = gli_probe_slot_gl9763e,
2015         .ops            = &sdhci_gl9763e_ops,
2016 #ifdef CONFIG_PM_SLEEP
2017         .resume         = gl9763e_resume,
2018         .suspend        = gl9763e_suspend,
2019 #endif
2020 #ifdef CONFIG_PM
2021         .runtime_suspend = gl9763e_runtime_suspend,
2022         .runtime_resume  = gl9763e_runtime_resume,
2023         .allow_runtime_pm = true,
2024 #endif
2025         .add_host       = gl9763e_add_host,
2026 };
2027
2028 static const struct sdhci_ops sdhci_gl9767_ops = {
2029         .set_clock               = sdhci_gl9767_set_clock,
2030         .enable_dma              = sdhci_pci_enable_dma,
2031         .set_bus_width           = sdhci_set_bus_width,
2032         .reset                   = sdhci_gl9767_reset,
2033         .set_uhs_signaling       = sdhci_set_uhs_signaling,
2034         .voltage_switch          = sdhci_gl9767_voltage_switch,
2035         .dump_uhs2_regs          = sdhci_uhs2_dump_regs,
2036         .set_timeout             = sdhci_uhs2_set_timeout,
2037         .irq                     = sdhci_uhs2_irq,
2038         .set_power               = sdhci_gl9767_set_power,
2039         .uhs2_pre_detect_init    = sdhci_gli_pre_detect_init,
2040         .card_event              = sdhci_gl9767_card_event,
2041 };
2042
2043 const struct sdhci_pci_fixes sdhci_gl9767 = {
2044         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
2045         .quirks2        = SDHCI_QUIRK2_BROKEN_DDR50,
2046         .probe_slot     = gli_probe_slot_gl9767,
2047         .add_host       = sdhci_pci_uhs2_add_host,
2048         .remove_host    = sdhci_pci_uhs2_remove_host,
2049         .ops            = &sdhci_gl9767_ops,
2050 #ifdef CONFIG_PM_SLEEP
2051         .resume         = sdhci_pci_gli_resume,
2052 #endif
2053 };