drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  73                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  74 {
  75         u32 bar_reg = (bar_id == BAR_ID_0 ?
  76                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  77         u32 val;
  78
  79         if (IS_VF(p_hwfn->cdev))
  80                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
  81
  82         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  83         if (val)
  84                 return 1 << (val + 15);
  85
  86         /* Old MFW initialized above registered only conditionally */
  87         if (p_hwfn->cdev->num_hwfns > 1) {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  90                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  91         } else {
  92                 DP_INFO(p_hwfn,
  93                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  94                         return 512 * 1024;
  95         }
  96 }
  97
  98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  99 {
 100         u32 i;
 101
 102         cdev->dp_level = dp_level;
 103         cdev->dp_module = dp_module;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109         }
 110 }
 111
 112 void qed_init_struct(struct qed_dev *cdev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 118
 119                 p_hwfn->cdev = cdev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 mutex_init(&p_hwfn->dmae_info.mutex);
 124         }
 125
 126         /* hwfn 0 is always active */
 127         cdev->hwfns[0].b_active = true;
 128
 129         /* set the default cache alignment to 128 */
 130         cdev->cache_shift = 7;
 131 }
 132
 133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 134 {
 135         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 136
 137         kfree(qm_info->qm_pq_params);
 138         qm_info->qm_pq_params = NULL;
 139         kfree(qm_info->qm_vport_params);
 140         qm_info->qm_vport_params = NULL;
 141         kfree(qm_info->qm_port_params);
 142         qm_info->qm_port_params = NULL;
 143         kfree(qm_info->wfq_data);
 144         qm_info->wfq_data = NULL;
 145 }
 146
 147 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
 148 {
 149         kfree(p_hwfn->dbg_user_info);
 150         p_hwfn->dbg_user_info = NULL;
 151 }
 152
 153 void qed_resc_free(struct qed_dev *cdev)
 154 {
 155         int i;
 156
 157         if (IS_VF(cdev)) {
 158                 for_each_hwfn(cdev, i)
 159                         qed_l2_free(&cdev->hwfns[i]);
 160                 return;
 161         }
 162
 163         kfree(cdev->fw_data);
 164         cdev->fw_data = NULL;
 165
 166         kfree(cdev->reset_stats);
 167         cdev->reset_stats = NULL;
 168
 169         for_each_hwfn(cdev, i) {
 170                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 171
 172                 qed_cxt_mngr_free(p_hwfn);
 173                 qed_qm_info_free(p_hwfn);
 174                 qed_spq_free(p_hwfn);
 175                 qed_eq_free(p_hwfn);
 176                 qed_consq_free(p_hwfn);
 177                 qed_int_free(p_hwfn);
 178 #ifdef CONFIG_QED_LL2
 179                 qed_ll2_free(p_hwfn);
 180 #endif
 181                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 182                         qed_fcoe_free(p_hwfn);
 183
 184                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 185                         qed_iscsi_free(p_hwfn);
 186                         qed_ooo_free(p_hwfn);
 187                 }
 188                 qed_iov_free(p_hwfn);
 189                 qed_l2_free(p_hwfn);
 190                 qed_dmae_info_free(p_hwfn);
 191                 qed_dcbx_info_free(p_hwfn);
 192                 qed_dbg_user_data_free(p_hwfn);
 193         }
 194 }
 195
 196 /******************** QM initialization *******************/
 197 #define ACTIVE_TCS_BMAP 0x9f
 198 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 199
 200 /* determines the physical queue flags for a given PF. */
 201 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 202 {
 203         u32 flags;
 204
 205         /* common flags */
 206         flags = PQ_FLAGS_LB;
 207
 208         /* feature flags */
 209         if (IS_QED_SRIOV(p_hwfn->cdev))
 210                 flags |= PQ_FLAGS_VFS;
 211
 212         /* protocol flags */
 213         switch (p_hwfn->hw_info.personality) {
 214         case QED_PCI_ETH:
 215                 flags |= PQ_FLAGS_MCOS;
 216                 break;
 217         case QED_PCI_FCOE:
 218                 flags |= PQ_FLAGS_OFLD;
 219                 break;
 220         case QED_PCI_ISCSI:
 221                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 222                 break;
 223         case QED_PCI_ETH_ROCE:
 224                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 225                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
 226                         flags |= PQ_FLAGS_MTC;
 227                 break;
 228         case QED_PCI_ETH_IWARP:
 229                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 230                     PQ_FLAGS_OFLD;
 231                 break;
 232         default:
 233                 DP_ERR(p_hwfn,
 234                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 235                 return 0;
 236         }
 237
 238         return flags;
 239 }
 240
 241 /* Getters for resource amounts necessary for qm initialization */
 242 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 243 {
 244         return p_hwfn->hw_info.num_hw_tc;
 245 }
 246
 247 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 248 {
 249         return IS_QED_SRIOV(p_hwfn->cdev) ?
 250                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 251 }
 252
 253 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
 254 {
 255         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 256
 257         if (!(PQ_FLAGS_MTC & pq_flags))
 258                 return 1;
 259
 260         return qed_init_qm_get_num_tcs(p_hwfn);
 261 }
 262
 263 #define NUM_DEFAULT_RLS 1
 264
 265 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 266 {
 267         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 268
 269         /* num RLs can't exceed resource amount of rls or vports */
 270         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 271                                  RESC_NUM(p_hwfn, QED_VPORT));
 272
 273         /* Make sure after we reserve there's something left */
 274         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 275                 return 0;
 276
 277         /* subtract rls necessary for VFs and one default one for the PF */
 278         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 279
 280         return num_pf_rls;
 281 }
 282
 283 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 284 {
 285         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 286
 287         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 288         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 289                qed_init_qm_get_num_pf_rls(p_hwfn) +
 290                (!!(PQ_FLAGS_VFS & pq_flags)) *
 291                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 292 }
 293
 294 /* calc amount of PQs according to the requested flags */
 295 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 296 {
 297         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 298
 299         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 300                qed_init_qm_get_num_pf_rls(p_hwfn) +
 301                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 302                qed_init_qm_get_num_tcs(p_hwfn) +
 303                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 304                (!!(PQ_FLAGS_ACK & pq_flags)) +
 305                (!!(PQ_FLAGS_OFLD & pq_flags)) *
 306                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 307                (!!(PQ_FLAGS_LLT & pq_flags)) *
 308                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 309                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 310 }
 311
 312 /* initialize the top level QM params */
 313 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 314 {
 315         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 316         bool four_port;
 317
 318         /* pq and vport bases for this PF */
 319         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 320         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 321
 322         /* rate limiting and weighted fair queueing are always enabled */
 323         qm_info->vport_rl_en = true;
 324         qm_info->vport_wfq_en = true;
 325
 326         /* TC config is different for AH 4 port */
 327         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 328
 329         /* in AH 4 port we have fewer TCs per port */
 330         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 331                                                      NUM_OF_PHYS_TCS;
 332
 333         /* unless MFW indicated otherwise, ooo_tc == 3 for
 334          * AH 4-port and 4 otherwise.
 335          */
 336         if (!qm_info->ooo_tc)
 337                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 338                                               DCBX_TCP_OOO_TC;
 339 }
 340
 341 /* initialize qm vport params */
 342 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 343 {
 344         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 345         u8 i;
 346
 347         /* all vports participate in weighted fair queueing */
 348         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 349                 qm_info->qm_vport_params[i].vport_wfq = 1;
 350 }
 351
 352 /* initialize qm port params */
 353 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 354 {
 355         /* Initialize qm port parameters */
 356         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 357
 358         /* indicate how ooo and high pri traffic is dealt with */
 359         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 360                           ACTIVE_TCS_BMAP_4PORT_K2 :
 361                           ACTIVE_TCS_BMAP;
 362
 363         for (i = 0; i < num_ports; i++) {
 364                 struct init_qm_port_params *p_qm_port =
 365                     &p_hwfn->qm_info.qm_port_params[i];
 366
 367                 p_qm_port->active = 1;
 368                 p_qm_port->active_phys_tcs = active_phys_tcs;
 369                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 370                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 371         }
 372 }
 373
 374 /* Reset the params which must be reset for qm init. QM init may be called as
 375  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 376  * params may be affected by the init but would simply recalculate to the same
 377  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 378  * affected as these amounts stay the same.
 379  */
 380 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 381 {
 382         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 383
 384         qm_info->num_pqs = 0;
 385         qm_info->num_vports = 0;
 386         qm_info->num_pf_rls = 0;
 387         qm_info->num_vf_pqs = 0;
 388         qm_info->first_vf_pq = 0;
 389         qm_info->first_mcos_pq = 0;
 390         qm_info->first_rl_pq = 0;
 391 }
 392
 393 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 394 {
 395         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 396
 397         qm_info->num_vports++;
 398
 399         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 400                 DP_ERR(p_hwfn,
 401                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 402                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 403 }
 404
 405 /* initialize a single pq and manage qm_info resources accounting.
 406  * The pq_init_flags param determines whether the PQ is rate limited
 407  * (for VF or PF) and whether a new vport is allocated to the pq or not
 408  * (i.e. vport will be shared).
 409  */
 410
 411 /* flags for pq init */
 412 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 413 #define PQ_INIT_PF_RL           (1 << 1)
 414 #define PQ_INIT_VF_RL           (1 << 2)
 415
 416 /* defines for pq init */
 417 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 418 #define PQ_INIT_DEFAULT_TC              0
 419
 420 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
 421 {
 422         p_info->offload_tc = tc;
 423         p_info->offload_tc_set = true;
 424 }
 425
 426 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
 427 {
 428         return p_hwfn->hw_info.offload_tc_set;
 429 }
 430
 431 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
 432 {
 433         if (qed_is_offload_tc_set(p_hwfn))
 434                 return p_hwfn->hw_info.offload_tc;
 435
 436         return PQ_INIT_DEFAULT_TC;
 437 }
 438
 439 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 440                            struct qed_qm_info *qm_info,
 441                            u8 tc, u32 pq_init_flags)
 442 {
 443         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 444
 445         if (pq_idx > max_pq)
 446                 DP_ERR(p_hwfn,
 447                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 448
 449         /* init pq params */
 450         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 451         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 452             qm_info->num_vports;
 453         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 454         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 455         qm_info->qm_pq_params[pq_idx].rl_valid =
 456             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 457
 458         /* qm params accounting */
 459         qm_info->num_pqs++;
 460         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 461                 qm_info->num_vports++;
 462
 463         if (pq_init_flags & PQ_INIT_PF_RL)
 464                 qm_info->num_pf_rls++;
 465
 466         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 467                 DP_ERR(p_hwfn,
 468                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 469                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 470
 471         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 472                 DP_ERR(p_hwfn,
 473                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 474                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 475 }
 476
 477 /* get pq index according to PQ_FLAGS */
 478 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 479                                            u32 pq_flags)
 480 {
 481         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 482
 483         /* Can't have multiple flags set here */
 484         if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
 485                 goto err;
 486
 487         switch (pq_flags) {
 488         case PQ_FLAGS_RLS:
 489                 return &qm_info->first_rl_pq;
 490         case PQ_FLAGS_MCOS:
 491                 return &qm_info->first_mcos_pq;
 492         case PQ_FLAGS_LB:
 493                 return &qm_info->pure_lb_pq;
 494         case PQ_FLAGS_OOO:
 495                 return &qm_info->ooo_pq;
 496         case PQ_FLAGS_ACK:
 497                 return &qm_info->pure_ack_pq;
 498         case PQ_FLAGS_OFLD:
 499                 return &qm_info->first_ofld_pq;
 500         case PQ_FLAGS_LLT:
 501                 return &qm_info->first_llt_pq;
 502         case PQ_FLAGS_VFS:
 503                 return &qm_info->first_vf_pq;
 504         default:
 505                 goto err;
 506         }
 507
 508 err:
 509         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 510         return NULL;
 511 }
 512
 513 /* save pq index in qm info */
 514 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 515                                 u32 pq_flags, u16 pq_val)
 516 {
 517         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 518
 519         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 520 }
 521
 522 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 523 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 524 {
 525         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 526
 527         return *base_pq_idx + CM_TX_PQ_BASE;
 528 }
 529
 530 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 531 {
 532         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 533
 534         if (tc > max_tc)
 535                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 536
 537         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 538 }
 539
 540 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 541 {
 542         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 543
 544         if (vf > max_vf)
 545                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 546
 547         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 548 }
 549
 550 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 551 {
 552         u16 first_ofld_pq, pq_offset;
 553
 554         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 555         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 556                     tc : PQ_INIT_DEFAULT_TC;
 557
 558         return first_ofld_pq + pq_offset;
 559 }
 560
 561 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 562 {
 563         u16 first_llt_pq, pq_offset;
 564
 565         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
 566         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 567                     tc : PQ_INIT_DEFAULT_TC;
 568
 569         return first_llt_pq + pq_offset;
 570 }
 571
 572 /* Functions for creating specific types of pqs */
 573 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 574 {
 575         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 576
 577         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 578                 return;
 579
 580         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 581         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 582 }
 583
 584 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 585 {
 586         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 587
 588         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 589                 return;
 590
 591         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 592         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 593 }
 594
 595 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 596 {
 597         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 598
 599         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 600                 return;
 601
 602         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 603         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 604                        PQ_INIT_SHARE_VPORT);
 605 }
 606
 607 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
 608 {
 609         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
 610         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 611         u8 tc;
 612
 613         /* override pq's TC if offload TC is set */
 614         for (tc = 0; tc < num_tcs; tc++)
 615                 qed_init_qm_pq(p_hwfn, qm_info,
 616                                qed_is_offload_tc_set(p_hwfn) ?
 617                                p_hwfn->hw_info.offload_tc : tc,
 618                                PQ_INIT_SHARE_VPORT);
 619 }
 620
 621 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 622 {
 623         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 624
 625         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 626                 return;
 627
 628         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 629         qed_init_qm_mtc_pqs(p_hwfn);
 630 }
 631
 632 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 633 {
 634         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 635
 636         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 637                 return;
 638
 639         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 640         qed_init_qm_mtc_pqs(p_hwfn);
 641 }
 642
 643 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 644 {
 645         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 646         u8 tc_idx;
 647
 648         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 649                 return;
 650
 651         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 652         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 653                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 654 }
 655
 656 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 657 {
 658         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 659         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 660
 661         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 662                 return;
 663
 664         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 665         qm_info->num_vf_pqs = num_vfs;
 666         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 667                 qed_init_qm_pq(p_hwfn,
 668                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 669 }
 670
 671 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 672 {
 673         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 674         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 675
 676         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 677                 return;
 678
 679         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 680         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 681                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 682                                PQ_INIT_PF_RL);
 683 }
 684
 685 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 686 {
 687         /* rate limited pqs, must come first (FW assumption) */
 688         qed_init_qm_rl_pqs(p_hwfn);
 689
 690         /* pqs for multi cos */
 691         qed_init_qm_mcos_pqs(p_hwfn);
 692
 693         /* pure loopback pq */
 694         qed_init_qm_lb_pq(p_hwfn);
 695
 696         /* out of order pq */
 697         qed_init_qm_ooo_pq(p_hwfn);
 698
 699         /* pure ack pq */
 700         qed_init_qm_pure_ack_pq(p_hwfn);
 701
 702         /* pq for offloaded protocol */
 703         qed_init_qm_offload_pq(p_hwfn);
 704
 705         /* low latency pq */
 706         qed_init_qm_low_latency_pq(p_hwfn);
 707
 708         /* done sharing vports */
 709         qed_init_qm_advance_vport(p_hwfn);
 710
 711         /* pqs for vfs */
 712         qed_init_qm_vf_pqs(p_hwfn);
 713 }
 714
 715 /* compare values of getters against resources amounts */
 716 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 717 {
 718         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 719                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 720                 return -EINVAL;
 721         }
 722
 723         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
 724                 return 0;
 725
 726         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
 727                 p_hwfn->hw_info.multi_tc_roce_en = 0;
 728                 DP_NOTICE(p_hwfn,
 729                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
 730                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
 731                         return 0;
 732         }
 733
 734         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 735         return -EINVAL;
 736 }
 737
 738 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 739 {
 740         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 741         struct init_qm_vport_params *vport;
 742         struct init_qm_port_params *port;
 743         struct init_qm_pq_params *pq;
 744         int i, tc;
 745
 746         /* top level params */
 747         DP_VERBOSE(p_hwfn,
 748                    NETIF_MSG_HW,
 749                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
 750                    qm_info->start_pq,
 751                    qm_info->start_vport,
 752                    qm_info->pure_lb_pq,
 753                    qm_info->first_ofld_pq,
 754                    qm_info->first_llt_pq,
 755                    qm_info->pure_ack_pq);
 756         DP_VERBOSE(p_hwfn,
 757                    NETIF_MSG_HW,
 758                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 759                    qm_info->ooo_pq,
 760                    qm_info->first_vf_pq,
 761                    qm_info->num_pqs,
 762                    qm_info->num_vf_pqs,
 763                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 764         DP_VERBOSE(p_hwfn,
 765                    NETIF_MSG_HW,
 766                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 767                    qm_info->pf_rl_en,
 768                    qm_info->pf_wfq_en,
 769                    qm_info->vport_rl_en,
 770                    qm_info->vport_wfq_en,
 771                    qm_info->pf_wfq,
 772                    qm_info->pf_rl,
 773                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 774
 775         /* port table */
 776         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 777                 port = &(qm_info->qm_port_params[i]);
 778                 DP_VERBOSE(p_hwfn,
 779                            NETIF_MSG_HW,
 780                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 781                            i,
 782                            port->active,
 783                            port->active_phys_tcs,
 784                            port->num_pbf_cmd_lines,
 785                            port->num_btb_blocks, port->reserved);
 786         }
 787
 788         /* vport table */
 789         for (i = 0; i < qm_info->num_vports; i++) {
 790                 vport = &(qm_info->qm_vport_params[i]);
 791                 DP_VERBOSE(p_hwfn,
 792                            NETIF_MSG_HW,
 793                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 794                            qm_info->start_vport + i,
 795                            vport->vport_rl, vport->vport_wfq);
 796                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 797                         DP_VERBOSE(p_hwfn,
 798                                    NETIF_MSG_HW,
 799                                    "%d ", vport->first_tx_pq_id[tc]);
 800                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 801         }
 802
 803         /* pq table */
 804         for (i = 0; i < qm_info->num_pqs; i++) {
 805                 pq = &(qm_info->qm_pq_params[i]);
 806                 DP_VERBOSE(p_hwfn,
 807                            NETIF_MSG_HW,
 808                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 809                            qm_info->start_pq + i,
 810                            pq->port_id,
 811                            pq->vport_id,
 812                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 813         }
 814 }
 815
 816 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 817 {
 818         /* reset params required for init run */
 819         qed_init_qm_reset_params(p_hwfn);
 820
 821         /* init QM top level params */
 822         qed_init_qm_params(p_hwfn);
 823
 824         /* init QM port params */
 825         qed_init_qm_port_params(p_hwfn);
 826
 827         /* init QM vport params */
 828         qed_init_qm_vport_params(p_hwfn);
 829
 830         /* init QM physical queue params */
 831         qed_init_qm_pq_params(p_hwfn);
 832
 833         /* display all that init */
 834         qed_dp_init_qm_params(p_hwfn);
 835 }
 836
 837 /* This function reconfigures the QM pf on the fly.
 838  * For this purpose we:
 839  * 1. reconfigure the QM database
 840  * 2. set new values to runtime array
 841  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 842  * 4. activate init tool in QM_PF stage
 843  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 844  */
 845 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 846 {
 847         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 848         bool b_rc;
 849         int rc;
 850
 851         /* initialize qed's qm data structure */
 852         qed_init_qm_info(p_hwfn);
 853
 854         /* stop PF's qm queues */
 855         spin_lock_bh(&qm_lock);
 856         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 857                                     qm_info->start_pq, qm_info->num_pqs);
 858         spin_unlock_bh(&qm_lock);
 859         if (!b_rc)
 860                 return -EINVAL;
 861
 862         /* clear the QM_PF runtime phase leftovers from previous init */
 863         qed_init_clear_rt_data(p_hwfn);
 864
 865         /* prepare QM portion of runtime array */
 866         qed_qm_init_pf(p_hwfn, p_ptt, false);
 867
 868         /* activate init tool on runtime array */
 869         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 870                           p_hwfn->hw_info.hw_mode);
 871         if (rc)
 872                 return rc;
 873
 874         /* start PF's qm queues */
 875         spin_lock_bh(&qm_lock);
 876         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 877                                     qm_info->start_pq, qm_info->num_pqs);
 878         spin_unlock_bh(&qm_lock);
 879         if (!b_rc)
 880                 return -EINVAL;
 881
 882         return 0;
 883 }
 884
 885 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 886 {
 887         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 888         int rc;
 889
 890         rc = qed_init_qm_sanity(p_hwfn);
 891         if (rc)
 892                 goto alloc_err;
 893
 894         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
 895                                         sizeof(*qm_info->qm_pq_params),
 896                                         GFP_KERNEL);
 897         if (!qm_info->qm_pq_params)
 898                 goto alloc_err;
 899
 900         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
 901                                            sizeof(*qm_info->qm_vport_params),
 902                                            GFP_KERNEL);
 903         if (!qm_info->qm_vport_params)
 904                 goto alloc_err;
 905
 906         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
 907                                           sizeof(*qm_info->qm_port_params),
 908                                           GFP_KERNEL);
 909         if (!qm_info->qm_port_params)
 910                 goto alloc_err;
 911
 912         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
 913                                     sizeof(*qm_info->wfq_data),
 914                                     GFP_KERNEL);
 915         if (!qm_info->wfq_data)
 916                 goto alloc_err;
 917
 918         return 0;
 919
 920 alloc_err:
 921         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 922         qed_qm_info_free(p_hwfn);
 923         return -ENOMEM;
 924 }
 925
 926 int qed_resc_alloc(struct qed_dev *cdev)
 927 {
 928         u32 rdma_tasks, excess_tasks;
 929         u32 line_count;
 930         int i, rc = 0;
 931
 932         if (IS_VF(cdev)) {
 933                 for_each_hwfn(cdev, i) {
 934                         rc = qed_l2_alloc(&cdev->hwfns[i]);
 935                         if (rc)
 936                                 return rc;
 937                 }
 938                 return rc;
 939         }
 940
 941         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 942         if (!cdev->fw_data)
 943                 return -ENOMEM;
 944
 945         for_each_hwfn(cdev, i) {
 946                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 947                 u32 n_eqes, num_cons;
 948
 949                 /* First allocate the context manager structure */
 950                 rc = qed_cxt_mngr_alloc(p_hwfn);
 951                 if (rc)
 952                         goto alloc_err;
 953
 954                 /* Set the HW cid/tid numbers (in the contest manager)
 955                  * Must be done prior to any further computations.
 956                  */
 957                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 958                 if (rc)
 959                         goto alloc_err;
 960
 961                 rc = qed_alloc_qm_data(p_hwfn);
 962                 if (rc)
 963                         goto alloc_err;
 964
 965                 /* init qm info */
 966                 qed_init_qm_info(p_hwfn);
 967
 968                 /* Compute the ILT client partition */
 969                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 970                 if (rc) {
 971                         DP_NOTICE(p_hwfn,
 972                                   "too many ILT lines; re-computing with less lines\n");
 973                         /* In case there are not enough ILT lines we reduce the
 974                          * number of RDMA tasks and re-compute.
 975                          */
 976                         excess_tasks =
 977                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 978                         if (!excess_tasks)
 979                                 goto alloc_err;
 980
 981                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 982                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 983                         if (rc)
 984                                 goto alloc_err;
 985
 986                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 987                         if (rc) {
 988                                 DP_ERR(p_hwfn,
 989                                        "failed ILT compute. Requested too many lines: %u\n",
 990                                        line_count);
 991
 992                                 goto alloc_err;
 993                         }
 994                 }
 995
 996                 /* CID map / ILT shadow table / T2
 997                  * The talbes sizes are determined by the computations above
 998                  */
 999                 rc = qed_cxt_tables_alloc(p_hwfn);
1000                 if (rc)
1001                         goto alloc_err;
1002
1003                 /* SPQ, must follow ILT because initializes SPQ context */
1004                 rc = qed_spq_alloc(p_hwfn);
1005                 if (rc)
1006                         goto alloc_err;
1007
1008                 /* SP status block allocation */
1009                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1010                                                          RESERVED_PTT_DPC);
1011
1012                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1013                 if (rc)
1014                         goto alloc_err;
1015
1016                 rc = qed_iov_alloc(p_hwfn);
1017                 if (rc)
1018                         goto alloc_err;
1019
1020                 /* EQ */
1021                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1022                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1023                         enum protocol_type rdma_proto;
1024
1025                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1026                                 rdma_proto = PROTOCOLID_ROCE;
1027                         else
1028                                 rdma_proto = PROTOCOLID_IWARP;
1029
1030                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1031                                                                rdma_proto,
1032                                                                NULL) * 2;
1033                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1034                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1035                         num_cons =
1036                             qed_cxt_get_proto_cid_count(p_hwfn,
1037                                                         PROTOCOLID_ISCSI,
1038                                                         NULL);
1039                         n_eqes += 2 * num_cons;
1040                 }
1041
1042                 if (n_eqes > 0xFFFF) {
1043                         DP_ERR(p_hwfn,
1044                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1045                                n_eqes, 0xFFFF);
1046                         goto alloc_no_mem;
1047                 }
1048
1049                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1050                 if (rc)
1051                         goto alloc_err;
1052
1053                 rc = qed_consq_alloc(p_hwfn);
1054                 if (rc)
1055                         goto alloc_err;
1056
1057                 rc = qed_l2_alloc(p_hwfn);
1058                 if (rc)
1059                         goto alloc_err;
1060
1061 #ifdef CONFIG_QED_LL2
1062                 if (p_hwfn->using_ll2) {
1063                         rc = qed_ll2_alloc(p_hwfn);
1064                         if (rc)
1065                                 goto alloc_err;
1066                 }
1067 #endif
1068
1069                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1070                         rc = qed_fcoe_alloc(p_hwfn);
1071                         if (rc)
1072                                 goto alloc_err;
1073                 }
1074
1075                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1076                         rc = qed_iscsi_alloc(p_hwfn);
1077                         if (rc)
1078                                 goto alloc_err;
1079                         rc = qed_ooo_alloc(p_hwfn);
1080                         if (rc)
1081                                 goto alloc_err;
1082                 }
1083
1084                 /* DMA info initialization */
1085                 rc = qed_dmae_info_alloc(p_hwfn);
1086                 if (rc)
1087                         goto alloc_err;
1088
1089                 /* DCBX initialization */
1090                 rc = qed_dcbx_info_alloc(p_hwfn);
1091                 if (rc)
1092                         goto alloc_err;
1093
1094                 rc = qed_dbg_alloc_user_data(p_hwfn);
1095                 if (rc)
1096                         goto alloc_err;
1097         }
1098
1099         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1100         if (!cdev->reset_stats)
1101                 goto alloc_no_mem;
1102
1103         return 0;
1104
1105 alloc_no_mem:
1106         rc = -ENOMEM;
1107 alloc_err:
1108         qed_resc_free(cdev);
1109         return rc;
1110 }
1111
1112 void qed_resc_setup(struct qed_dev *cdev)
1113 {
1114         int i;
1115
1116         if (IS_VF(cdev)) {
1117                 for_each_hwfn(cdev, i)
1118                         qed_l2_setup(&cdev->hwfns[i]);
1119                 return;
1120         }
1121
1122         for_each_hwfn(cdev, i) {
1123                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1124
1125                 qed_cxt_mngr_setup(p_hwfn);
1126                 qed_spq_setup(p_hwfn);
1127                 qed_eq_setup(p_hwfn);
1128                 qed_consq_setup(p_hwfn);
1129
1130                 /* Read shadow of current MFW mailbox */
1131                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1132                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1133                        p_hwfn->mcp_info->mfw_mb_cur,
1134                        p_hwfn->mcp_info->mfw_mb_length);
1135
1136                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1137
1138                 qed_l2_setup(p_hwfn);
1139                 qed_iov_setup(p_hwfn);
1140 #ifdef CONFIG_QED_LL2
1141                 if (p_hwfn->using_ll2)
1142                         qed_ll2_setup(p_hwfn);
1143 #endif
1144                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1145                         qed_fcoe_setup(p_hwfn);
1146
1147                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1148                         qed_iscsi_setup(p_hwfn);
1149                         qed_ooo_setup(p_hwfn);
1150                 }
1151         }
1152 }
1153
1154 #define FINAL_CLEANUP_POLL_CNT          (100)
1155 #define FINAL_CLEANUP_POLL_TIME         (10)
1156 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1157                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1158 {
1159         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1160         int rc = -EBUSY;
1161
1162         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1163                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1164
1165         if (is_vf)
1166                 id += 0x10;
1167
1168         command |= X_FINAL_CLEANUP_AGG_INT <<
1169                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1170         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1171         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1172         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1173
1174         /* Make sure notification is not set before initiating final cleanup */
1175         if (REG_RD(p_hwfn, addr)) {
1176                 DP_NOTICE(p_hwfn,
1177                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1178                 REG_WR(p_hwfn, addr, 0);
1179         }
1180
1181         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1182                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1183                    id, command);
1184
1185         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1186
1187         /* Poll until completion */
1188         while (!REG_RD(p_hwfn, addr) && count--)
1189                 msleep(FINAL_CLEANUP_POLL_TIME);
1190
1191         if (REG_RD(p_hwfn, addr))
1192                 rc = 0;
1193         else
1194                 DP_NOTICE(p_hwfn,
1195                           "Failed to receive FW final cleanup notification\n");
1196
1197         /* Cleanup afterwards */
1198         REG_WR(p_hwfn, addr, 0);
1199
1200         return rc;
1201 }
1202
1203 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1204 {
1205         int hw_mode = 0;
1206
1207         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1208                 hw_mode |= 1 << MODE_BB;
1209         } else if (QED_IS_AH(p_hwfn->cdev)) {
1210                 hw_mode |= 1 << MODE_K2;
1211         } else {
1212                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1213                           p_hwfn->cdev->type);
1214                 return -EINVAL;
1215         }
1216
1217         switch (p_hwfn->cdev->num_ports_in_engine) {
1218         case 1:
1219                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1220                 break;
1221         case 2:
1222                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1223                 break;
1224         case 4:
1225                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1226                 break;
1227         default:
1228                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1229                           p_hwfn->cdev->num_ports_in_engine);
1230                 return -EINVAL;
1231         }
1232
1233         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1234                 hw_mode |= 1 << MODE_MF_SD;
1235         else
1236                 hw_mode |= 1 << MODE_MF_SI;
1237
1238         hw_mode |= 1 << MODE_ASIC;
1239
1240         if (p_hwfn->cdev->num_hwfns > 1)
1241                 hw_mode |= 1 << MODE_100G;
1242
1243         p_hwfn->hw_info.hw_mode = hw_mode;
1244
1245         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1246                    "Configuring function for hw_mode: 0x%08x\n",
1247                    p_hwfn->hw_info.hw_mode);
1248
1249         return 0;
1250 }
1251
1252 /* Init run time data for all PFs on an engine. */
1253 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1254 {
1255         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1256         int i, igu_sb_id;
1257
1258         for_each_hwfn(cdev, i) {
1259                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1260                 struct qed_igu_info *p_igu_info;
1261                 struct qed_igu_block *p_block;
1262                 struct cau_sb_entry sb_entry;
1263
1264                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1265
1266                 for (igu_sb_id = 0;
1267                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1268                         p_block = &p_igu_info->entry[igu_sb_id];
1269
1270                         if (!p_block->is_pf)
1271                                 continue;
1272
1273                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1274                                               p_block->function_id, 0, 0);
1275                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1276                                          sb_entry);
1277                 }
1278         }
1279 }
1280
1281 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1282                                      struct qed_ptt *p_ptt)
1283 {
1284         u32 val, wr_mbs, cache_line_size;
1285
1286         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1287         switch (val) {
1288         case 0:
1289                 wr_mbs = 128;
1290                 break;
1291         case 1:
1292                 wr_mbs = 256;
1293                 break;
1294         case 2:
1295                 wr_mbs = 512;
1296                 break;
1297         default:
1298                 DP_INFO(p_hwfn,
1299                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1300                         val);
1301                 return;
1302         }
1303
1304         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1305         switch (cache_line_size) {
1306         case 32:
1307                 val = 0;
1308                 break;
1309         case 64:
1310                 val = 1;
1311                 break;
1312         case 128:
1313                 val = 2;
1314                 break;
1315         case 256:
1316                 val = 3;
1317                 break;
1318         default:
1319                 DP_INFO(p_hwfn,
1320                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1321                         cache_line_size);
1322         }
1323
1324         if (L1_CACHE_BYTES > wr_mbs)
1325                 DP_INFO(p_hwfn,
1326                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1327                         L1_CACHE_BYTES, wr_mbs);
1328
1329         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1330         if (val > 0) {
1331                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1332                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1333         }
1334 }
1335
1336 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1337                               struct qed_ptt *p_ptt, int hw_mode)
1338 {
1339         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1340         struct qed_qm_common_rt_init_params params;
1341         struct qed_dev *cdev = p_hwfn->cdev;
1342         u8 vf_id, max_num_vfs;
1343         u16 num_pfs, pf_id;
1344         u32 concrete_fid;
1345         int rc = 0;
1346
1347         qed_init_cau_rt_data(cdev);
1348
1349         /* Program GTT windows */
1350         qed_gtt_init(p_hwfn);
1351
1352         if (p_hwfn->mcp_info) {
1353                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1354                         qm_info->pf_rl_en = true;
1355                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1356                         qm_info->pf_wfq_en = true;
1357         }
1358
1359         memset(&params, 0, sizeof(params));
1360         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1361         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1362         params.pf_rl_en = qm_info->pf_rl_en;
1363         params.pf_wfq_en = qm_info->pf_wfq_en;
1364         params.vport_rl_en = qm_info->vport_rl_en;
1365         params.vport_wfq_en = qm_info->vport_wfq_en;
1366         params.port_params = qm_info->qm_port_params;
1367
1368         qed_qm_common_rt_init(p_hwfn, &params);
1369
1370         qed_cxt_hw_init_common(p_hwfn);
1371
1372         qed_init_cache_line_size(p_hwfn, p_ptt);
1373
1374         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1375         if (rc)
1376                 return rc;
1377
1378         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1379         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1380
1381         if (QED_IS_BB(p_hwfn->cdev)) {
1382                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1383                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1384                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1385                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1386                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1387                 }
1388                 /* pretend to original PF */
1389                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1390         }
1391
1392         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1393         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1394                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1395                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1396                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1397                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1398                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1399                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1400         }
1401         /* pretend to original PF */
1402         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1403
1404         return rc;
1405 }
1406
1407 static int
1408 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1409                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1410 {
1411         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1412         u32 min_dpis;
1413         u32 n_wids;
1414
1415         /* Calculate DPI size */
1416         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1417         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1418         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1419         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1420         dpi_count = pwm_region_size / dpi_page_size;
1421
1422         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1423         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1424
1425         p_hwfn->dpi_size = dpi_page_size;
1426         p_hwfn->dpi_count = dpi_count;
1427
1428         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1429
1430         if (dpi_count < min_dpis)
1431                 return -EINVAL;
1432
1433         return 0;
1434 }
1435
1436 enum QED_ROCE_EDPM_MODE {
1437         QED_ROCE_EDPM_MODE_ENABLE = 0,
1438         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1439         QED_ROCE_EDPM_MODE_DISABLE = 2,
1440 };
1441
1442 static int
1443 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1444 {
1445         u32 pwm_regsize, norm_regsize;
1446         u32 non_pwm_conn, min_addr_reg1;
1447         u32 db_bar_size, n_cpus = 1;
1448         u32 roce_edpm_mode;
1449         u32 pf_dems_shift;
1450         int rc = 0;
1451         u8 cond;
1452
1453         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1454         if (p_hwfn->cdev->num_hwfns > 1)
1455                 db_bar_size /= 2;
1456
1457         /* Calculate doorbell regions */
1458         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1459                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1460                                                    NULL) +
1461                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1462                                                    NULL);
1463         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1464         min_addr_reg1 = norm_regsize / 4096;
1465         pwm_regsize = db_bar_size - norm_regsize;
1466
1467         /* Check that the normal and PWM sizes are valid */
1468         if (db_bar_size < norm_regsize) {
1469                 DP_ERR(p_hwfn->cdev,
1470                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1471                        db_bar_size, norm_regsize);
1472                 return -EINVAL;
1473         }
1474
1475         if (pwm_regsize < QED_MIN_PWM_REGION) {
1476                 DP_ERR(p_hwfn->cdev,
1477                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1478                        pwm_regsize,
1479                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1480                 return -EINVAL;
1481         }
1482
1483         /* Calculate number of DPIs */
1484         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1485         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1486             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1487                 /* Either EDPM is mandatory, or we are attempting to allocate a
1488                  * WID per CPU.
1489                  */
1490                 n_cpus = num_present_cpus();
1491                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1492         }
1493
1494         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1495                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1496         if (cond || p_hwfn->dcbx_no_edpm) {
1497                 /* Either EDPM is disabled from user configuration, or it is
1498                  * disabled via DCBx, or it is not mandatory and we failed to
1499                  * allocated a WID per CPU.
1500                  */
1501                 n_cpus = 1;
1502                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1503
1504                 if (cond)
1505                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1506         }
1507
1508         p_hwfn->wid_count = (u16) n_cpus;
1509
1510         DP_INFO(p_hwfn,
1511                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1512                 norm_regsize,
1513                 pwm_regsize,
1514                 p_hwfn->dpi_size,
1515                 p_hwfn->dpi_count,
1516                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1517                 "disabled" : "enabled");
1518
1519         if (rc) {
1520                 DP_ERR(p_hwfn,
1521                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1522                        p_hwfn->dpi_count,
1523                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1524                 return -EINVAL;
1525         }
1526
1527         p_hwfn->dpi_start_offset = norm_regsize;
1528
1529         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1530         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1531         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1532         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1533
1534         return 0;
1535 }
1536
1537 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1538                             struct qed_ptt *p_ptt, int hw_mode)
1539 {
1540         int rc = 0;
1541
1542         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1543         if (rc)
1544                 return rc;
1545
1546         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1547
1548         return 0;
1549 }
1550
1551 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1552                           struct qed_ptt *p_ptt,
1553                           struct qed_tunnel_info *p_tunn,
1554                           int hw_mode,
1555                           bool b_hw_start,
1556                           enum qed_int_mode int_mode,
1557                           bool allow_npar_tx_switch)
1558 {
1559         u8 rel_pf_id = p_hwfn->rel_pf_id;
1560         int rc = 0;
1561
1562         if (p_hwfn->mcp_info) {
1563                 struct qed_mcp_function_info *p_info;
1564
1565                 p_info = &p_hwfn->mcp_info->func_info;
1566                 if (p_info->bandwidth_min)
1567                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1568
1569                 /* Update rate limit once we'll actually have a link */
1570                 p_hwfn->qm_info.pf_rl = 100000;
1571         }
1572
1573         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1574
1575         qed_int_igu_init_rt(p_hwfn);
1576
1577         /* Set VLAN in NIG if needed */
1578         if (hw_mode & BIT(MODE_MF_SD)) {
1579                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1580                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1581                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1582                              p_hwfn->hw_info.ovlan);
1583
1584                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1585                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1586                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1587                              1);
1588         }
1589
1590         /* Enable classification by MAC if needed */
1591         if (hw_mode & BIT(MODE_MF_SI)) {
1592                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1593                            "Configuring TAGMAC_CLS_TYPE\n");
1594                 STORE_RT_REG(p_hwfn,
1595                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1596         }
1597
1598         /* Protocol Configuration */
1599         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1600                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1601         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1602                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1603         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1604
1605         /* Cleanup chip from previous driver if such remains exist */
1606         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1607         if (rc)
1608                 return rc;
1609
1610         /* Sanity check before the PF init sequence that uses DMAE */
1611         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1612         if (rc)
1613                 return rc;
1614
1615         /* PF Init sequence */
1616         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1617         if (rc)
1618                 return rc;
1619
1620         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1621         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1622         if (rc)
1623                 return rc;
1624
1625         /* Pure runtime initializations - directly to the HW  */
1626         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1627
1628         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1629         if (rc)
1630                 return rc;
1631
1632         if (b_hw_start) {
1633                 /* enable interrupts */
1634                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1635
1636                 /* send function start command */
1637                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1638                                      allow_npar_tx_switch);
1639                 if (rc) {
1640                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1641                         return rc;
1642                 }
1643                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1644                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1645                         qed_wr(p_hwfn, p_ptt,
1646                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1647                                0x100);
1648                 }
1649         }
1650         return rc;
1651 }
1652
1653 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1654                                struct qed_ptt *p_ptt,
1655                                u8 enable)
1656 {
1657         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1658
1659         /* Change PF in PXP */
1660         qed_wr(p_hwfn, p_ptt,
1661                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1662
1663         /* wait until value is set - try for 1 second every 50us */
1664         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1665                 val = qed_rd(p_hwfn, p_ptt,
1666                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1667                 if (val == set_val)
1668                         break;
1669
1670                 usleep_range(50, 60);
1671         }
1672
1673         if (val != set_val) {
1674                 DP_NOTICE(p_hwfn,
1675                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1676                 return -EAGAIN;
1677         }
1678
1679         return 0;
1680 }
1681
1682 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1683                                 struct qed_ptt *p_main_ptt)
1684 {
1685         /* Read shadow of current MFW mailbox */
1686         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1687         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1688                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1689 }
1690
1691 static void
1692 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1693                          struct qed_drv_load_params *p_drv_load)
1694 {
1695         memset(p_load_req, 0, sizeof(*p_load_req));
1696
1697         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1698                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1699         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1700         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1701         p_load_req->override_force_load = p_drv_load->override_force_load;
1702 }
1703
1704 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1705                         struct qed_hw_init_params *p_params)
1706 {
1707         if (p_params->p_tunn) {
1708                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1709                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1710         }
1711
1712         p_hwfn->b_int_enabled = true;
1713
1714         return 0;
1715 }
1716
1717 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1718 {
1719         struct qed_load_req_params load_req_params;
1720         u32 load_code, resp, param, drv_mb_param;
1721         bool b_default_mtu = true;
1722         struct qed_hwfn *p_hwfn;
1723         int rc = 0, mfw_rc, i;
1724         u16 ether_type;
1725
1726         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1727                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1728                 return -EINVAL;
1729         }
1730
1731         if (IS_PF(cdev)) {
1732                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1733                 if (rc)
1734                         return rc;
1735         }
1736
1737         for_each_hwfn(cdev, i) {
1738                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1739
1740                 /* If management didn't provide a default, set one of our own */
1741                 if (!p_hwfn->hw_info.mtu) {
1742                         p_hwfn->hw_info.mtu = 1500;
1743                         b_default_mtu = false;
1744                 }
1745
1746                 if (IS_VF(cdev)) {
1747                         qed_vf_start(p_hwfn, p_params);
1748                         continue;
1749                 }
1750
1751                 /* Enable DMAE in PXP */
1752                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1753
1754                 rc = qed_calc_hw_mode(p_hwfn);
1755                 if (rc)
1756                         return rc;
1757
1758                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
1759                                              &cdev->mf_bits) ||
1760                                     test_bit(QED_MF_8021AD_TAGGING,
1761                                              &cdev->mf_bits))) {
1762                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
1763                                 ether_type = ETH_P_8021Q;
1764                         else
1765                                 ether_type = ETH_P_8021AD;
1766                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1767                                      ether_type);
1768                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1769                                      ether_type);
1770                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1771                                      ether_type);
1772                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
1773                                      ether_type);
1774                 }
1775
1776                 qed_fill_load_req_params(&load_req_params,
1777                                          p_params->p_drv_load_params);
1778                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1779                                       &load_req_params);
1780                 if (rc) {
1781                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1782                         return rc;
1783                 }
1784
1785                 load_code = load_req_params.load_code;
1786                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1787                            "Load request was sent. Load code: 0x%x\n",
1788                            load_code);
1789
1790                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1791
1792                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1793
1794                 p_hwfn->first_on_engine = (load_code ==
1795                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1796
1797                 switch (load_code) {
1798                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1799                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1800                                                 p_hwfn->hw_info.hw_mode);
1801                         if (rc)
1802                                 break;
1803                 /* Fall through */
1804                 case FW_MSG_CODE_DRV_LOAD_PORT:
1805                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1806                                               p_hwfn->hw_info.hw_mode);
1807                         if (rc)
1808                                 break;
1809
1810                 /* Fall through */
1811                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1812                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1813                                             p_params->p_tunn,
1814                                             p_hwfn->hw_info.hw_mode,
1815                                             p_params->b_hw_start,
1816                                             p_params->int_mode,
1817                                             p_params->allow_npar_tx_switch);
1818                         break;
1819                 default:
1820                         DP_NOTICE(p_hwfn,
1821                                   "Unexpected load code [0x%08x]", load_code);
1822                         rc = -EINVAL;
1823                         break;
1824                 }
1825
1826                 if (rc)
1827                         DP_NOTICE(p_hwfn,
1828                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1829                                    load_code, rc);
1830
1831                 /* ACK mfw regardless of success or failure of initialization */
1832                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1833                                      DRV_MSG_CODE_LOAD_DONE,
1834                                      0, &load_code, &param);
1835                 if (rc)
1836                         return rc;
1837                 if (mfw_rc) {
1838                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1839                         return mfw_rc;
1840                 }
1841
1842                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1843                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1844                         DP_NOTICE(p_hwfn,
1845                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1846
1847                 /* send DCBX attention request command */
1848                 DP_VERBOSE(p_hwfn,
1849                            QED_MSG_DCB,
1850                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1851                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1852                                      DRV_MSG_CODE_SET_DCBX,
1853                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1854                                      &load_code, &param);
1855                 if (mfw_rc) {
1856                         DP_NOTICE(p_hwfn,
1857                                   "Failed to send DCBX attention request\n");
1858                         return mfw_rc;
1859                 }
1860
1861                 p_hwfn->hw_init_done = true;
1862         }
1863
1864         if (IS_PF(cdev)) {
1865                 p_hwfn = QED_LEADING_HWFN(cdev);
1866
1867                 /* Get pre-negotiated values for stag, bandwidth etc. */
1868                 DP_VERBOSE(p_hwfn,
1869                            QED_MSG_SPQ,
1870                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
1871                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
1872                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1873                                  DRV_MSG_CODE_GET_OEM_UPDATES,
1874                                  drv_mb_param, &resp, &param);
1875                 if (rc)
1876                         DP_NOTICE(p_hwfn,
1877                                   "Failed to send GET_OEM_UPDATES attention request\n");
1878
1879                 drv_mb_param = STORM_FW_VERSION;
1880                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1881                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1882                                  drv_mb_param, &load_code, &param);
1883                 if (rc)
1884                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1885
1886                 if (!b_default_mtu) {
1887                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1888                                                    p_hwfn->hw_info.mtu);
1889                         if (rc)
1890                                 DP_INFO(p_hwfn,
1891                                         "Failed to update default mtu\n");
1892                 }
1893
1894                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1895                                                     p_hwfn->p_main_ptt,
1896                                                   QED_OV_DRIVER_STATE_DISABLED);
1897                 if (rc)
1898                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1899
1900                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1901                                                QED_OV_ESWITCH_NONE);
1902                 if (rc)
1903                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1904         }
1905
1906         return 0;
1907 }
1908
1909 #define QED_HW_STOP_RETRY_LIMIT (10)
1910 static void qed_hw_timers_stop(struct qed_dev *cdev,
1911                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1912 {
1913         int i;
1914
1915         /* close timers */
1916         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1917         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1918
1919         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1920                 if ((!qed_rd(p_hwfn, p_ptt,
1921                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1922                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1923                         break;
1924
1925                 /* Dependent on number of connection/tasks, possibly
1926                  * 1ms sleep is required between polls
1927                  */
1928                 usleep_range(1000, 2000);
1929         }
1930
1931         if (i < QED_HW_STOP_RETRY_LIMIT)
1932                 return;
1933
1934         DP_NOTICE(p_hwfn,
1935                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1936                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1937                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1938 }
1939
1940 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1941 {
1942         int j;
1943
1944         for_each_hwfn(cdev, j) {
1945                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1946                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1947
1948                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1949         }
1950 }
1951
1952 int qed_hw_stop(struct qed_dev *cdev)
1953 {
1954         struct qed_hwfn *p_hwfn;
1955         struct qed_ptt *p_ptt;
1956         int rc, rc2 = 0;
1957         int j;
1958
1959         for_each_hwfn(cdev, j) {
1960                 p_hwfn = &cdev->hwfns[j];
1961                 p_ptt = p_hwfn->p_main_ptt;
1962
1963                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1964
1965                 if (IS_VF(cdev)) {
1966                         qed_vf_pf_int_cleanup(p_hwfn);
1967                         rc = qed_vf_pf_reset(p_hwfn);
1968                         if (rc) {
1969                                 DP_NOTICE(p_hwfn,
1970                                           "qed_vf_pf_reset failed. rc = %d.\n",
1971                                           rc);
1972                                 rc2 = -EINVAL;
1973                         }
1974                         continue;
1975                 }
1976
1977                 /* mark the hw as uninitialized... */
1978                 p_hwfn->hw_init_done = false;
1979
1980                 /* Send unload command to MCP */
1981                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1982                 if (rc) {
1983                         DP_NOTICE(p_hwfn,
1984                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1985                                   rc);
1986                         rc2 = -EINVAL;
1987                 }
1988
1989                 qed_slowpath_irq_sync(p_hwfn);
1990
1991                 /* After this point no MFW attentions are expected, e.g. prevent
1992                  * race between pf stop and dcbx pf update.
1993                  */
1994                 rc = qed_sp_pf_stop(p_hwfn);
1995                 if (rc) {
1996                         DP_NOTICE(p_hwfn,
1997                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1998                                   rc);
1999                         rc2 = -EINVAL;
2000                 }
2001
2002                 qed_wr(p_hwfn, p_ptt,
2003                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2004
2005                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2006                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2007                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2008                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2009                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2010
2011                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2012
2013                 /* Disable Attention Generation */
2014                 qed_int_igu_disable_int(p_hwfn, p_ptt);
2015
2016                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2017                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2018
2019                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2020
2021                 /* Need to wait 1ms to guarantee SBs are cleared */
2022                 usleep_range(1000, 2000);
2023
2024                 /* Disable PF in HW blocks */
2025                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2026                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2027
2028                 qed_mcp_unload_done(p_hwfn, p_ptt);
2029                 if (rc) {
2030                         DP_NOTICE(p_hwfn,
2031                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2032                                   rc);
2033                         rc2 = -EINVAL;
2034                 }
2035         }
2036
2037         if (IS_PF(cdev)) {
2038                 p_hwfn = QED_LEADING_HWFN(cdev);
2039                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2040
2041                 /* Disable DMAE in PXP - in CMT, this should only be done for
2042                  * first hw-function, and only after all transactions have
2043                  * stopped for all active hw-functions.
2044                  */
2045                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
2046                 if (rc) {
2047                         DP_NOTICE(p_hwfn,
2048                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
2049                         rc2 = -EINVAL;
2050                 }
2051         }
2052
2053         return rc2;
2054 }
2055
2056 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2057 {
2058         int j;
2059
2060         for_each_hwfn(cdev, j) {
2061                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2062                 struct qed_ptt *p_ptt;
2063
2064                 if (IS_VF(cdev)) {
2065                         qed_vf_pf_int_cleanup(p_hwfn);
2066                         continue;
2067                 }
2068                 p_ptt = qed_ptt_acquire(p_hwfn);
2069                 if (!p_ptt)
2070                         return -EAGAIN;
2071
2072                 DP_VERBOSE(p_hwfn,
2073                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2074
2075                 qed_wr(p_hwfn, p_ptt,
2076                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2077
2078                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2079                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2080                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2081                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2082                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2083
2084                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2085
2086                 /* Need to wait 1ms to guarantee SBs are cleared */
2087                 usleep_range(1000, 2000);
2088                 qed_ptt_release(p_hwfn, p_ptt);
2089         }
2090
2091         return 0;
2092 }
2093
2094 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2095 {
2096         struct qed_ptt *p_ptt;
2097
2098         if (IS_VF(p_hwfn->cdev))
2099                 return 0;
2100
2101         p_ptt = qed_ptt_acquire(p_hwfn);
2102         if (!p_ptt)
2103                 return -EAGAIN;
2104
2105         /* If roce info is allocated it means roce is initialized and should
2106          * be enabled in searcher.
2107          */
2108         if (p_hwfn->p_rdma_info &&
2109             p_hwfn->b_rdma_enabled_in_prs)
2110                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2111
2112         /* Re-open incoming traffic */
2113         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2114         qed_ptt_release(p_hwfn, p_ptt);
2115
2116         return 0;
2117 }
2118
2119 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2120 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2121 {
2122         qed_ptt_pool_free(p_hwfn);
2123         kfree(p_hwfn->hw_info.p_igu_info);
2124         p_hwfn->hw_info.p_igu_info = NULL;
2125 }
2126
2127 /* Setup bar access */
2128 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2129 {
2130         /* clear indirect access */
2131         if (QED_IS_AH(p_hwfn->cdev)) {
2132                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2133                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2134                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2135                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2136                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2137                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2138                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2139                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2140         } else {
2141                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2142                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2143                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2144                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2145                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2146                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2147                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2148                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2149         }
2150
2151         /* Clean Previous errors if such exist */
2152         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2153                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2154
2155         /* enable internal target-read */
2156         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2157                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2158 }
2159
2160 static void get_function_id(struct qed_hwfn *p_hwfn)
2161 {
2162         /* ME Register */
2163         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2164                                                   PXP_PF_ME_OPAQUE_ADDR);
2165
2166         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2167
2168         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2169         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2170                                       PXP_CONCRETE_FID_PFID);
2171         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2172                                     PXP_CONCRETE_FID_PORT);
2173
2174         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2175                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2176                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2177 }
2178
2179 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2180 {
2181         u32 *feat_num = p_hwfn->hw_info.feat_num;
2182         struct qed_sb_cnt_info sb_cnt;
2183         u32 non_l2_sbs = 0;
2184
2185         memset(&sb_cnt, 0, sizeof(sb_cnt));
2186         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2187
2188         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2189             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2190                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2191                  * the status blocks equally between L2 / RoCE but with
2192                  * consideration as to how many l2 queues / cnqs we have.
2193                  */
2194                 feat_num[QED_RDMA_CNQ] =
2195                         min_t(u32, sb_cnt.cnt / 2,
2196                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2197
2198                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2199         }
2200         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2201                 /* Start by allocating VF queues, then PF's */
2202                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2203                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2204                                                 sb_cnt.iov_cnt);
2205                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2206                                                 sb_cnt.cnt - non_l2_sbs,
2207                                                 RESC_NUM(p_hwfn,
2208                                                          QED_L2_QUEUE) -
2209                                                 FEAT_NUM(p_hwfn,
2210                                                          QED_VF_L2_QUE));
2211         }
2212
2213         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2214                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2215                                                RESC_NUM(p_hwfn,
2216                                                         QED_CMDQS_CQS));
2217
2218         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2219                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2220                                                RESC_NUM(p_hwfn,
2221                                                         QED_CMDQS_CQS));
2222         DP_VERBOSE(p_hwfn,
2223                    NETIF_MSG_PROBE,
2224                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2225                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2226                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2227                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2228                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2229                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2230                    (int)sb_cnt.cnt);
2231 }
2232
2233 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2234 {
2235         switch (res_id) {
2236         case QED_L2_QUEUE:
2237                 return "L2_QUEUE";
2238         case QED_VPORT:
2239                 return "VPORT";
2240         case QED_RSS_ENG:
2241                 return "RSS_ENG";
2242         case QED_PQ:
2243                 return "PQ";
2244         case QED_RL:
2245                 return "RL";
2246         case QED_MAC:
2247                 return "MAC";
2248         case QED_VLAN:
2249                 return "VLAN";
2250         case QED_RDMA_CNQ_RAM:
2251                 return "RDMA_CNQ_RAM";
2252         case QED_ILT:
2253                 return "ILT";
2254         case QED_LL2_QUEUE:
2255                 return "LL2_QUEUE";
2256         case QED_CMDQS_CQS:
2257                 return "CMDQS_CQS";
2258         case QED_RDMA_STATS_QUEUE:
2259                 return "RDMA_STATS_QUEUE";
2260         case QED_BDQ:
2261                 return "BDQ";
2262         case QED_SB:
2263                 return "SB";
2264         default:
2265                 return "UNKNOWN_RESOURCE";
2266         }
2267 }
2268
2269 static int
2270 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2271                             struct qed_ptt *p_ptt,
2272                             enum qed_resources res_id,
2273                             u32 resc_max_val, u32 *p_mcp_resp)
2274 {
2275         int rc;
2276
2277         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2278                                       resc_max_val, p_mcp_resp);
2279         if (rc) {
2280                 DP_NOTICE(p_hwfn,
2281                           "MFW response failure for a max value setting of resource %d [%s]\n",
2282                           res_id, qed_hw_get_resc_name(res_id));
2283                 return rc;
2284         }
2285
2286         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2287                 DP_INFO(p_hwfn,
2288                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2289                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2290
2291         return 0;
2292 }
2293
2294 static int
2295 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2296 {
2297         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2298         u32 resc_max_val, mcp_resp;
2299         u8 res_id;
2300         int rc;
2301
2302         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2303                 switch (res_id) {
2304                 case QED_LL2_QUEUE:
2305                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2306                         break;
2307                 case QED_RDMA_CNQ_RAM:
2308                         /* No need for a case for QED_CMDQS_CQS since
2309                          * CNQ/CMDQS are the same resource.
2310                          */
2311                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
2312                         break;
2313                 case QED_RDMA_STATS_QUEUE:
2314                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2315                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2316                         break;
2317                 case QED_BDQ:
2318                         resc_max_val = BDQ_NUM_RESOURCES;
2319                         break;
2320                 default:
2321                         continue;
2322                 }
2323
2324                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2325                                                  resc_max_val, &mcp_resp);
2326                 if (rc)
2327                         return rc;
2328
2329                 /* There's no point to continue to the next resource if the
2330                  * command is not supported by the MFW.
2331                  * We do continue if the command is supported but the resource
2332                  * is unknown to the MFW. Such a resource will be later
2333                  * configured with the default allocation values.
2334                  */
2335                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2336                         return -EINVAL;
2337         }
2338
2339         return 0;
2340 }
2341
2342 static
2343 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2344                          enum qed_resources res_id,
2345                          u32 *p_resc_num, u32 *p_resc_start)
2346 {
2347         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2348         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2349
2350         switch (res_id) {
2351         case QED_L2_QUEUE:
2352                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2353                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2354                 break;
2355         case QED_VPORT:
2356                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2357                                MAX_NUM_VPORTS_BB) / num_funcs;
2358                 break;
2359         case QED_RSS_ENG:
2360                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2361                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2362                 break;
2363         case QED_PQ:
2364                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2365                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2366                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2367                 break;
2368         case QED_RL:
2369                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2370                 break;
2371         case QED_MAC:
2372         case QED_VLAN:
2373                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2374                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2375                 break;
2376         case QED_ILT:
2377                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2378                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2379                 break;
2380         case QED_LL2_QUEUE:
2381                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2382                 break;
2383         case QED_RDMA_CNQ_RAM:
2384         case QED_CMDQS_CQS:
2385                 /* CNQ/CMDQS are the same resource */
2386                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2387                 break;
2388         case QED_RDMA_STATS_QUEUE:
2389                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2390                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2391                 break;
2392         case QED_BDQ:
2393                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2394                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2395                         *p_resc_num = 0;
2396                 else
2397                         *p_resc_num = 1;
2398                 break;
2399         case QED_SB:
2400                 /* Since we want its value to reflect whether MFW supports
2401                  * the new scheme, have a default of 0.
2402                  */
2403                 *p_resc_num = 0;
2404                 break;
2405         default:
2406                 return -EINVAL;
2407         }
2408
2409         switch (res_id) {
2410         case QED_BDQ:
2411                 if (!*p_resc_num)
2412                         *p_resc_start = 0;
2413                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2414                         *p_resc_start = p_hwfn->port_id;
2415                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2416                         *p_resc_start = p_hwfn->port_id;
2417                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2418                         *p_resc_start = p_hwfn->port_id + 2;
2419                 break;
2420         default:
2421                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2422                 break;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2429                                   enum qed_resources res_id)
2430 {
2431         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2432         u32 mcp_resp, *p_resc_num, *p_resc_start;
2433         int rc;
2434
2435         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2436         p_resc_start = &RESC_START(p_hwfn, res_id);
2437
2438         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2439                                   &dflt_resc_start);
2440         if (rc) {
2441                 DP_ERR(p_hwfn,
2442                        "Failed to get default amount for resource %d [%s]\n",
2443                        res_id, qed_hw_get_resc_name(res_id));
2444                 return rc;
2445         }
2446
2447         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2448                                    &mcp_resp, p_resc_num, p_resc_start);
2449         if (rc) {
2450                 DP_NOTICE(p_hwfn,
2451                           "MFW response failure for an allocation request for resource %d [%s]\n",
2452                           res_id, qed_hw_get_resc_name(res_id));
2453                 return rc;
2454         }
2455
2456         /* Default driver values are applied in the following cases:
2457          * - The resource allocation MB command is not supported by the MFW
2458          * - There is an internal error in the MFW while processing the request
2459          * - The resource ID is unknown to the MFW
2460          */
2461         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2462                 DP_INFO(p_hwfn,
2463                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2464                         res_id,
2465                         qed_hw_get_resc_name(res_id),
2466                         mcp_resp, dflt_resc_num, dflt_resc_start);
2467                 *p_resc_num = dflt_resc_num;
2468                 *p_resc_start = dflt_resc_start;
2469                 goto out;
2470         }
2471
2472 out:
2473         /* PQs have to divide by 8 [that's the HW granularity].
2474          * Reduce number so it would fit.
2475          */
2476         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2477                 DP_INFO(p_hwfn,
2478                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2479                         *p_resc_num,
2480                         (*p_resc_num) & ~0x7,
2481                         *p_resc_start, (*p_resc_start) & ~0x7);
2482                 *p_resc_num &= ~0x7;
2483                 *p_resc_start &= ~0x7;
2484         }
2485
2486         return 0;
2487 }
2488
2489 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2490 {
2491         int rc;
2492         u8 res_id;
2493
2494         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2495                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2496                 if (rc)
2497                         return rc;
2498         }
2499
2500         return 0;
2501 }
2502
2503 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2504 {
2505         struct qed_resc_unlock_params resc_unlock_params;
2506         struct qed_resc_lock_params resc_lock_params;
2507         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2508         u8 res_id;
2509         int rc;
2510
2511         /* Setting the max values of the soft resources and the following
2512          * resources allocation queries should be atomic. Since several PFs can
2513          * run in parallel - a resource lock is needed.
2514          * If either the resource lock or resource set value commands are not
2515          * supported - skip the the max values setting, release the lock if
2516          * needed, and proceed to the queries. Other failures, including a
2517          * failure to acquire the lock, will cause this function to fail.
2518          */
2519         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2520                                        QED_RESC_LOCK_RESC_ALLOC, false);
2521
2522         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2523         if (rc && rc != -EINVAL) {
2524                 return rc;
2525         } else if (rc == -EINVAL) {
2526                 DP_INFO(p_hwfn,
2527                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2528         } else if (!rc && !resc_lock_params.b_granted) {
2529                 DP_NOTICE(p_hwfn,
2530                           "Failed to acquire the resource lock for the resource allocation commands\n");
2531                 return -EBUSY;
2532         } else {
2533                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2534                 if (rc && rc != -EINVAL) {
2535                         DP_NOTICE(p_hwfn,
2536                                   "Failed to set the max values of the soft resources\n");
2537                         goto unlock_and_exit;
2538                 } else if (rc == -EINVAL) {
2539                         DP_INFO(p_hwfn,
2540                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2541                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2542                                                  &resc_unlock_params);
2543                         if (rc)
2544                                 DP_INFO(p_hwfn,
2545                                         "Failed to release the resource lock for the resource allocation commands\n");
2546                 }
2547         }
2548
2549         rc = qed_hw_set_resc_info(p_hwfn);
2550         if (rc)
2551                 goto unlock_and_exit;
2552
2553         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2554                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2555                 if (rc)
2556                         DP_INFO(p_hwfn,
2557                                 "Failed to release the resource lock for the resource allocation commands\n");
2558         }
2559
2560         /* Sanity for ILT */
2561         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2562             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2563                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2564                           RESC_START(p_hwfn, QED_ILT),
2565                           RESC_END(p_hwfn, QED_ILT) - 1);
2566                 return -EINVAL;
2567         }
2568
2569         /* This will also learn the number of SBs from MFW */
2570         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2571                 return -EINVAL;
2572
2573         qed_hw_set_feat(p_hwfn);
2574
2575         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2576                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2577                            qed_hw_get_resc_name(res_id),
2578                            RESC_NUM(p_hwfn, res_id),
2579                            RESC_START(p_hwfn, res_id));
2580
2581         return 0;
2582
2583 unlock_and_exit:
2584         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2585                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2586         return rc;
2587 }
2588
2589 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2590 {
2591         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2592         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2593         struct qed_mcp_link_capabilities *p_caps;
2594         struct qed_mcp_link_params *link;
2595
2596         /* Read global nvm_cfg address */
2597         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2598
2599         /* Verify MCP has initialized it */
2600         if (!nvm_cfg_addr) {
2601                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2602                 return -EINVAL;
2603         }
2604
2605         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2606         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2607
2608         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2609                offsetof(struct nvm_cfg1, glob) +
2610                offsetof(struct nvm_cfg1_glob, core_cfg);
2611
2612         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2613
2614         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2615                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2616         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2617                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2618                 break;
2619         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2620                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2621                 break;
2622         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2623                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2624                 break;
2625         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2626                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2627                 break;
2628         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2629                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2630                 break;
2631         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2632                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2633                 break;
2634         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2635                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2636                 break;
2637         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2638                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2639                 break;
2640         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2641                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2642                 break;
2643         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2644                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2645                 break;
2646         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2647                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2648                 break;
2649         default:
2650                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2651                 break;
2652         }
2653
2654         /* Read default link configuration */
2655         link = &p_hwfn->mcp_info->link_input;
2656         p_caps = &p_hwfn->mcp_info->link_capabilities;
2657         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2658                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2659         link_temp = qed_rd(p_hwfn, p_ptt,
2660                            port_cfg_addr +
2661                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2662         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2663         link->speed.advertised_speeds = link_temp;
2664
2665         link_temp = link->speed.advertised_speeds;
2666         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2667
2668         link_temp = qed_rd(p_hwfn, p_ptt,
2669                            port_cfg_addr +
2670                            offsetof(struct nvm_cfg1_port, link_settings));
2671         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2672                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2673         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2674                 link->speed.autoneg = true;
2675                 break;
2676         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2677                 link->speed.forced_speed = 1000;
2678                 break;
2679         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2680                 link->speed.forced_speed = 10000;
2681                 break;
2682         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
2683                 link->speed.forced_speed = 20000;
2684                 break;
2685         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2686                 link->speed.forced_speed = 25000;
2687                 break;
2688         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2689                 link->speed.forced_speed = 40000;
2690                 break;
2691         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2692                 link->speed.forced_speed = 50000;
2693                 break;
2694         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2695                 link->speed.forced_speed = 100000;
2696                 break;
2697         default:
2698                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2699         }
2700
2701         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2702                 link->speed.autoneg;
2703
2704         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2705         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2706         link->pause.autoneg = !!(link_temp &
2707                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2708         link->pause.forced_rx = !!(link_temp &
2709                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2710         link->pause.forced_tx = !!(link_temp &
2711                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2712         link->loopback_mode = 0;
2713
2714         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2715                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2716                                    offsetof(struct nvm_cfg1_port, ext_phy));
2717                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2718                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2719                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2720                 link->eee.enable = true;
2721                 switch (link_temp) {
2722                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2723                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
2724                         link->eee.enable = false;
2725                         break;
2726                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2727                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2728                         break;
2729                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2730                         p_caps->eee_lpi_timer =
2731                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2732                         break;
2733                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2734                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2735                         break;
2736                 }
2737
2738                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2739                 link->eee.tx_lpi_enable = link->eee.enable;
2740                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2741         } else {
2742                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2743         }
2744
2745         DP_VERBOSE(p_hwfn,
2746                    NETIF_MSG_LINK,
2747                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2748                    link->speed.forced_speed,
2749                    link->speed.advertised_speeds,
2750                    link->speed.autoneg,
2751                    link->pause.autoneg,
2752                    p_caps->default_eee, p_caps->eee_lpi_timer);
2753
2754         if (IS_LEAD_HWFN(p_hwfn)) {
2755                 struct qed_dev *cdev = p_hwfn->cdev;
2756
2757                 /* Read Multi-function information from shmem */
2758                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2759                        offsetof(struct nvm_cfg1, glob) +
2760                        offsetof(struct nvm_cfg1_glob, generic_cont0);
2761
2762                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2763
2764                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2765                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
2766
2767                 switch (mf_mode) {
2768                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2769                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
2770                         break;
2771                 case NVM_CFG1_GLOB_MF_MODE_UFP:
2772                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2773                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2774                                         BIT(QED_MF_UFP_SPECIFIC) |
2775                                         BIT(QED_MF_8021Q_TAGGING);
2776                         break;
2777                 case NVM_CFG1_GLOB_MF_MODE_BD:
2778                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2779                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2780                                         BIT(QED_MF_8021AD_TAGGING);
2781                         break;
2782                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2783                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2784                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2785                                         BIT(QED_MF_LL2_NON_UNICAST) |
2786                                         BIT(QED_MF_INTER_PF_SWITCH);
2787                         break;
2788                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2789                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2790                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2791                                         BIT(QED_MF_LL2_NON_UNICAST);
2792                         if (QED_IS_BB(p_hwfn->cdev))
2793                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
2794                         break;
2795                 }
2796
2797                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2798                         cdev->mf_bits);
2799         }
2800
2801         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2802                 p_hwfn->cdev->mf_bits);
2803
2804         /* Read device capabilities information from shmem */
2805         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2806                 offsetof(struct nvm_cfg1, glob) +
2807                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2808
2809         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2810         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2811                 __set_bit(QED_DEV_CAP_ETH,
2812                           &p_hwfn->hw_info.device_capabilities);
2813         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2814                 __set_bit(QED_DEV_CAP_FCOE,
2815                           &p_hwfn->hw_info.device_capabilities);
2816         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2817                 __set_bit(QED_DEV_CAP_ISCSI,
2818                           &p_hwfn->hw_info.device_capabilities);
2819         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2820                 __set_bit(QED_DEV_CAP_ROCE,
2821                           &p_hwfn->hw_info.device_capabilities);
2822
2823         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2824 }
2825
2826 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2827 {
2828         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2829         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2830         struct qed_dev *cdev = p_hwfn->cdev;
2831
2832         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2833
2834         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2835          * in the other bits are selected.
2836          * Bits 1-15 are for functions 1-15, respectively, and their value is
2837          * '0' only for enabled functions (function 0 always exists and
2838          * enabled).
2839          * In case of CMT, only the "even" functions are enabled, and thus the
2840          * number of functions for both hwfns is learnt from the same bits.
2841          */
2842         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2843
2844         if (reg_function_hide & 0x1) {
2845                 if (QED_IS_BB(cdev)) {
2846                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2847                                 num_funcs = 0;
2848                                 eng_mask = 0xaaaa;
2849                         } else {
2850                                 num_funcs = 1;
2851                                 eng_mask = 0x5554;
2852                         }
2853                 } else {
2854                         num_funcs = 1;
2855                         eng_mask = 0xfffe;
2856                 }
2857
2858                 /* Get the number of the enabled functions on the engine */
2859                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2860                 while (tmp) {
2861                         if (tmp & 0x1)
2862                                 num_funcs++;
2863                         tmp >>= 0x1;
2864                 }
2865
2866                 /* Get the PF index within the enabled functions */
2867                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2868                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2869                 while (tmp) {
2870                         if (tmp & 0x1)
2871                                 enabled_func_idx--;
2872                         tmp >>= 0x1;
2873                 }
2874         }
2875
2876         p_hwfn->num_funcs_on_engine = num_funcs;
2877         p_hwfn->enabled_func_idx = enabled_func_idx;
2878
2879         DP_VERBOSE(p_hwfn,
2880                    NETIF_MSG_PROBE,
2881                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2882                    p_hwfn->rel_pf_id,
2883                    p_hwfn->abs_pf_id,
2884                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2885 }
2886
2887 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2888                                     struct qed_ptt *p_ptt)
2889 {
2890         u32 port_mode;
2891
2892         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2893
2894         if (port_mode < 3) {
2895                 p_hwfn->cdev->num_ports_in_engine = 1;
2896         } else if (port_mode <= 5) {
2897                 p_hwfn->cdev->num_ports_in_engine = 2;
2898         } else {
2899                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2900                           p_hwfn->cdev->num_ports_in_engine);
2901
2902                 /* Default num_ports_in_engine to something */
2903                 p_hwfn->cdev->num_ports_in_engine = 1;
2904         }
2905 }
2906
2907 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2908                                     struct qed_ptt *p_ptt)
2909 {
2910         u32 port;
2911         int i;
2912
2913         p_hwfn->cdev->num_ports_in_engine = 0;
2914
2915         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2916                 port = qed_rd(p_hwfn, p_ptt,
2917                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2918                 if (port & 1)
2919                         p_hwfn->cdev->num_ports_in_engine++;
2920         }
2921
2922         if (!p_hwfn->cdev->num_ports_in_engine) {
2923                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2924
2925                 /* Default num_ports_in_engine to something */
2926                 p_hwfn->cdev->num_ports_in_engine = 1;
2927         }
2928 }
2929
2930 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2931 {
2932         if (QED_IS_BB(p_hwfn->cdev))
2933                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2934         else
2935                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2936 }
2937
2938 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2939 {
2940         struct qed_mcp_link_capabilities *p_caps;
2941         u32 eee_status;
2942
2943         p_caps = &p_hwfn->mcp_info->link_capabilities;
2944         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2945                 return;
2946
2947         p_caps->eee_speed_caps = 0;
2948         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2949                             offsetof(struct public_port, eee_status));
2950         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2951                         EEE_SUPPORTED_SPEED_OFFSET;
2952
2953         if (eee_status & EEE_1G_SUPPORTED)
2954                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2955         if (eee_status & EEE_10G_ADV)
2956                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2957 }
2958
2959 static int
2960 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2961                 struct qed_ptt *p_ptt,
2962                 enum qed_pci_personality personality)
2963 {
2964         int rc;
2965
2966         /* Since all information is common, only first hwfns should do this */
2967         if (IS_LEAD_HWFN(p_hwfn)) {
2968                 rc = qed_iov_hw_info(p_hwfn);
2969                 if (rc)
2970                         return rc;
2971         }
2972
2973         qed_hw_info_port_num(p_hwfn, p_ptt);
2974
2975         qed_mcp_get_capabilities(p_hwfn, p_ptt);
2976
2977         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2978
2979         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2980         if (rc)
2981                 return rc;
2982
2983         if (qed_mcp_is_init(p_hwfn))
2984                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2985                                 p_hwfn->mcp_info->func_info.mac);
2986         else
2987                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2988
2989         if (qed_mcp_is_init(p_hwfn)) {
2990                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2991                         p_hwfn->hw_info.ovlan =
2992                                 p_hwfn->mcp_info->func_info.ovlan;
2993
2994                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2995
2996                 qed_get_eee_caps(p_hwfn, p_ptt);
2997
2998                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
2999         }
3000
3001         if (qed_mcp_is_init(p_hwfn)) {
3002                 enum qed_pci_personality protocol;
3003
3004                 protocol = p_hwfn->mcp_info->func_info.protocol;
3005                 p_hwfn->hw_info.personality = protocol;
3006         }
3007
3008         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
3009                 p_hwfn->hw_info.multi_tc_roce_en = 1;
3010
3011         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3012         p_hwfn->hw_info.num_active_tc = 1;
3013
3014         qed_get_num_funcs(p_hwfn, p_ptt);
3015
3016         if (qed_mcp_is_init(p_hwfn))
3017                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3018
3019         return qed_hw_get_resc(p_hwfn, p_ptt);
3020 }
3021
3022 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3023 {
3024         struct qed_dev *cdev = p_hwfn->cdev;
3025         u16 device_id_mask;
3026         u32 tmp;
3027
3028         /* Read Vendor Id / Device Id */
3029         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3030         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3031
3032         /* Determine type */
3033         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3034         switch (device_id_mask) {
3035         case QED_DEV_ID_MASK_BB:
3036                 cdev->type = QED_DEV_TYPE_BB;
3037                 break;
3038         case QED_DEV_ID_MASK_AH:
3039                 cdev->type = QED_DEV_TYPE_AH;
3040                 break;
3041         default:
3042                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3043                 return -EBUSY;
3044         }
3045
3046         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3047         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3048
3049         MASK_FIELD(CHIP_REV, cdev->chip_rev);
3050
3051         /* Learn number of HW-functions */
3052         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3053
3054         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3055                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3056                 cdev->num_hwfns = 2;
3057         } else {
3058                 cdev->num_hwfns = 1;
3059         }
3060
3061         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3062                                     MISCS_REG_CHIP_TEST_REG) >> 4;
3063         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3064         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3065         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3066
3067         DP_INFO(cdev->hwfns,
3068                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3069                 QED_IS_BB(cdev) ? "BB" : "AH",
3070                 'A' + cdev->chip_rev,
3071                 (int)cdev->chip_metal,
3072                 cdev->chip_num, cdev->chip_rev,
3073                 cdev->chip_bond_id, cdev->chip_metal);
3074
3075         return 0;
3076 }
3077
3078 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3079 {
3080         kfree(p_hwfn->nvm_info.image_att);
3081         p_hwfn->nvm_info.image_att = NULL;
3082 }
3083
3084 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3085                                  void __iomem *p_regview,
3086                                  void __iomem *p_doorbells,
3087                                  enum qed_pci_personality personality)
3088 {
3089         int rc = 0;
3090
3091         /* Split PCI bars evenly between hwfns */
3092         p_hwfn->regview = p_regview;
3093         p_hwfn->doorbells = p_doorbells;
3094
3095         if (IS_VF(p_hwfn->cdev))
3096                 return qed_vf_hw_prepare(p_hwfn);
3097
3098         /* Validate that chip access is feasible */
3099         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3100                 DP_ERR(p_hwfn,
3101                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3102                 return -EINVAL;
3103         }
3104
3105         get_function_id(p_hwfn);
3106
3107         /* Allocate PTT pool */
3108         rc = qed_ptt_pool_alloc(p_hwfn);
3109         if (rc)
3110                 goto err0;
3111
3112         /* Allocate the main PTT */
3113         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3114
3115         /* First hwfn learns basic information, e.g., number of hwfns */
3116         if (!p_hwfn->my_id) {
3117                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3118                 if (rc)
3119                         goto err1;
3120         }
3121
3122         qed_hw_hwfn_prepare(p_hwfn);
3123
3124         /* Initialize MCP structure */
3125         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3126         if (rc) {
3127                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3128                 goto err1;
3129         }
3130
3131         /* Read the device configuration information from the HW and SHMEM */
3132         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3133         if (rc) {
3134                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3135                 goto err2;
3136         }
3137
3138         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3139          * is called as it sets the ports number in an engine.
3140          */
3141         if (IS_LEAD_HWFN(p_hwfn)) {
3142                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3143                 if (rc)
3144                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3145         }
3146
3147         /* NVRAM info initialization and population */
3148         if (IS_LEAD_HWFN(p_hwfn)) {
3149                 rc = qed_mcp_nvm_info_populate(p_hwfn);
3150                 if (rc) {
3151                         DP_NOTICE(p_hwfn,
3152                                   "Failed to populate nvm info shadow\n");
3153                         goto err2;
3154                 }
3155         }
3156
3157         /* Allocate the init RT array and initialize the init-ops engine */
3158         rc = qed_init_alloc(p_hwfn);
3159         if (rc)
3160                 goto err3;
3161
3162         return rc;
3163 err3:
3164         if (IS_LEAD_HWFN(p_hwfn))
3165                 qed_nvm_info_free(p_hwfn);
3166 err2:
3167         if (IS_LEAD_HWFN(p_hwfn))
3168                 qed_iov_free_hw_info(p_hwfn->cdev);
3169         qed_mcp_free(p_hwfn);
3170 err1:
3171         qed_hw_hwfn_free(p_hwfn);
3172 err0:
3173         return rc;
3174 }
3175
3176 int qed_hw_prepare(struct qed_dev *cdev,
3177                    int personality)
3178 {
3179         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3180         int rc;
3181
3182         /* Store the precompiled init data ptrs */
3183         if (IS_PF(cdev))
3184                 qed_init_iro_array(cdev);
3185
3186         /* Initialize the first hwfn - will learn number of hwfns */
3187         rc = qed_hw_prepare_single(p_hwfn,
3188                                    cdev->regview,
3189                                    cdev->doorbells, personality);
3190         if (rc)
3191                 return rc;
3192
3193         personality = p_hwfn->hw_info.personality;
3194
3195         /* Initialize the rest of the hwfns */
3196         if (cdev->num_hwfns > 1) {
3197                 void __iomem *p_regview, *p_doorbell;
3198                 u8 __iomem *addr;
3199
3200                 /* adjust bar offset for second engine */
3201                 addr = cdev->regview +
3202                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3203                                        BAR_ID_0) / 2;
3204                 p_regview = addr;
3205
3206                 addr = cdev->doorbells +
3207                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3208                                        BAR_ID_1) / 2;
3209                 p_doorbell = addr;
3210
3211                 /* prepare second hw function */
3212                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3213                                            p_doorbell, personality);
3214
3215                 /* in case of error, need to free the previously
3216                  * initiliazed hwfn 0.
3217                  */
3218                 if (rc) {
3219                         if (IS_PF(cdev)) {
3220                                 qed_init_free(p_hwfn);
3221                                 qed_nvm_info_free(p_hwfn);
3222                                 qed_mcp_free(p_hwfn);
3223                                 qed_hw_hwfn_free(p_hwfn);
3224                         }
3225                 }
3226         }
3227
3228         return rc;
3229 }
3230
3231 void qed_hw_remove(struct qed_dev *cdev)
3232 {
3233         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3234         int i;
3235
3236         if (IS_PF(cdev))
3237                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3238                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3239
3240         for_each_hwfn(cdev, i) {
3241                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3242
3243                 if (IS_VF(cdev)) {
3244                         qed_vf_pf_release(p_hwfn);
3245                         continue;
3246                 }
3247
3248                 qed_init_free(p_hwfn);
3249                 qed_hw_hwfn_free(p_hwfn);
3250                 qed_mcp_free(p_hwfn);
3251         }
3252
3253         qed_iov_free_hw_info(cdev);
3254
3255         qed_nvm_info_free(p_hwfn);
3256 }
3257
3258 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3259                                     struct qed_chain *p_chain)
3260 {
3261         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3262         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3263         struct qed_chain_next *p_next;
3264         u32 size, i;
3265
3266         if (!p_virt)
3267                 return;
3268
3269         size = p_chain->elem_size * p_chain->usable_per_page;
3270
3271         for (i = 0; i < p_chain->page_cnt; i++) {
3272                 if (!p_virt)
3273                         break;
3274
3275                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3276                 p_virt_next = p_next->next_virt;
3277                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3278
3279                 dma_free_coherent(&cdev->pdev->dev,
3280                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3281
3282                 p_virt = p_virt_next;
3283                 p_phys = p_phys_next;
3284         }
3285 }
3286
3287 static void qed_chain_free_single(struct qed_dev *cdev,
3288                                   struct qed_chain *p_chain)
3289 {
3290         if (!p_chain->p_virt_addr)
3291                 return;
3292
3293         dma_free_coherent(&cdev->pdev->dev,
3294                           QED_CHAIN_PAGE_SIZE,
3295                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3296 }
3297
3298 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3299 {
3300         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3301         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3302         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3303
3304         if (!pp_virt_addr_tbl)
3305                 return;
3306
3307         if (!p_pbl_virt)
3308                 goto out;
3309
3310         for (i = 0; i < page_cnt; i++) {
3311                 if (!pp_virt_addr_tbl[i])
3312                         break;
3313
3314                 dma_free_coherent(&cdev->pdev->dev,
3315                                   QED_CHAIN_PAGE_SIZE,
3316                                   pp_virt_addr_tbl[i],
3317                                   *(dma_addr_t *)p_pbl_virt);
3318
3319                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3320         }
3321
3322         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3323
3324         if (!p_chain->b_external_pbl)
3325                 dma_free_coherent(&cdev->pdev->dev,
3326                                   pbl_size,
3327                                   p_chain->pbl_sp.p_virt_table,
3328                                   p_chain->pbl_sp.p_phys_table);
3329 out:
3330         vfree(p_chain->pbl.pp_virt_addr_tbl);
3331         p_chain->pbl.pp_virt_addr_tbl = NULL;
3332 }
3333
3334 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3335 {
3336         switch (p_chain->mode) {
3337         case QED_CHAIN_MODE_NEXT_PTR:
3338                 qed_chain_free_next_ptr(cdev, p_chain);
3339                 break;
3340         case QED_CHAIN_MODE_SINGLE:
3341                 qed_chain_free_single(cdev, p_chain);
3342                 break;
3343         case QED_CHAIN_MODE_PBL:
3344                 qed_chain_free_pbl(cdev, p_chain);
3345                 break;
3346         }
3347 }
3348
3349 static int
3350 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3351                              enum qed_chain_cnt_type cnt_type,
3352                              size_t elem_size, u32 page_cnt)
3353 {
3354         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3355
3356         /* The actual chain size can be larger than the maximal possible value
3357          * after rounding up the requested elements number to pages, and after
3358          * taking into acount the unusuable elements (next-ptr elements).
3359          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3360          * size/capacity fields are of a u32 type.
3361          */
3362         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3363              chain_size > ((u32)U16_MAX + 1)) ||
3364             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3365                 DP_NOTICE(cdev,
3366                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3367                           chain_size);
3368                 return -EINVAL;
3369         }
3370
3371         return 0;
3372 }
3373
3374 static int
3375 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3376 {
3377         void *p_virt = NULL, *p_virt_prev = NULL;
3378         dma_addr_t p_phys = 0;
3379         u32 i;
3380
3381         for (i = 0; i < p_chain->page_cnt; i++) {
3382                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3383                                             QED_CHAIN_PAGE_SIZE,
3384                                             &p_phys, GFP_KERNEL);
3385                 if (!p_virt)
3386                         return -ENOMEM;
3387
3388                 if (i == 0) {
3389                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3390                         qed_chain_reset(p_chain);
3391                 } else {
3392                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3393                                                      p_virt, p_phys);
3394                 }
3395
3396                 p_virt_prev = p_virt;
3397         }
3398         /* Last page's next element should point to the beginning of the
3399          * chain.
3400          */
3401         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3402                                      p_chain->p_virt_addr,
3403                                      p_chain->p_phys_addr);
3404
3405         return 0;
3406 }
3407
3408 static int
3409 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3410 {
3411         dma_addr_t p_phys = 0;
3412         void *p_virt = NULL;
3413
3414         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3415                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3416         if (!p_virt)
3417                 return -ENOMEM;
3418
3419         qed_chain_init_mem(p_chain, p_virt, p_phys);
3420         qed_chain_reset(p_chain);
3421
3422         return 0;
3423 }
3424
3425 static int
3426 qed_chain_alloc_pbl(struct qed_dev *cdev,
3427                     struct qed_chain *p_chain,
3428                     struct qed_chain_ext_pbl *ext_pbl)
3429 {
3430         u32 page_cnt = p_chain->page_cnt, size, i;
3431         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3432         void **pp_virt_addr_tbl = NULL;
3433         u8 *p_pbl_virt = NULL;
3434         void *p_virt = NULL;
3435
3436         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3437         pp_virt_addr_tbl = vzalloc(size);
3438         if (!pp_virt_addr_tbl)
3439                 return -ENOMEM;
3440
3441         /* The allocation of the PBL table is done with its full size, since it
3442          * is expected to be successive.
3443          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3444          * failure, since pp_virt_addr_tbl was previously allocated, and it
3445          * should be saved to allow its freeing during the error flow.
3446          */
3447         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3448
3449         if (!ext_pbl) {
3450                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3451                                                 size, &p_pbl_phys, GFP_KERNEL);
3452         } else {
3453                 p_pbl_virt = ext_pbl->p_pbl_virt;
3454                 p_pbl_phys = ext_pbl->p_pbl_phys;
3455                 p_chain->b_external_pbl = true;
3456         }
3457
3458         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3459                                pp_virt_addr_tbl);
3460         if (!p_pbl_virt)
3461                 return -ENOMEM;
3462
3463         for (i = 0; i < page_cnt; i++) {
3464                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3465                                             QED_CHAIN_PAGE_SIZE,
3466                                             &p_phys, GFP_KERNEL);
3467                 if (!p_virt)
3468                         return -ENOMEM;
3469
3470                 if (i == 0) {
3471                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3472                         qed_chain_reset(p_chain);
3473                 }
3474
3475                 /* Fill the PBL table with the physical address of the page */
3476                 *(dma_addr_t *)p_pbl_virt = p_phys;
3477                 /* Keep the virtual address of the page */
3478                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3479
3480                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3481         }
3482
3483         return 0;
3484 }
3485
3486 int qed_chain_alloc(struct qed_dev *cdev,
3487                     enum qed_chain_use_mode intended_use,
3488                     enum qed_chain_mode mode,
3489                     enum qed_chain_cnt_type cnt_type,
3490                     u32 num_elems,
3491                     size_t elem_size,
3492                     struct qed_chain *p_chain,
3493                     struct qed_chain_ext_pbl *ext_pbl)
3494 {
3495         u32 page_cnt;
3496         int rc = 0;
3497
3498         if (mode == QED_CHAIN_MODE_SINGLE)
3499                 page_cnt = 1;
3500         else
3501                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3502
3503         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3504         if (rc) {
3505                 DP_NOTICE(cdev,
3506                           "Cannot allocate a chain with the given arguments:\n");
3507                 DP_NOTICE(cdev,
3508                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3509                           intended_use, mode, cnt_type, num_elems, elem_size);
3510                 return rc;
3511         }
3512
3513         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3514                               mode, cnt_type);
3515
3516         switch (mode) {
3517         case QED_CHAIN_MODE_NEXT_PTR:
3518                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3519                 break;
3520         case QED_CHAIN_MODE_SINGLE:
3521                 rc = qed_chain_alloc_single(cdev, p_chain);
3522                 break;
3523         case QED_CHAIN_MODE_PBL:
3524                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3525                 break;
3526         }
3527         if (rc)
3528                 goto nomem;
3529
3530         return 0;
3531
3532 nomem:
3533         qed_chain_free(cdev, p_chain);
3534         return rc;
3535 }
3536
3537 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3538 {
3539         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3540                 u16 min, max;
3541
3542                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3543                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3544                 DP_NOTICE(p_hwfn,
3545                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3546                           src_id, min, max);
3547
3548                 return -EINVAL;
3549         }
3550
3551         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3552
3553         return 0;
3554 }
3555
3556 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3557 {
3558         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3559                 u8 min, max;
3560
3561                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3562                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3563                 DP_NOTICE(p_hwfn,
3564                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3565                           src_id, min, max);
3566
3567                 return -EINVAL;
3568         }
3569
3570         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3571
3572         return 0;
3573 }
3574
3575 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3576 {
3577         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3578                 u8 min, max;
3579
3580                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3581                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3582                 DP_NOTICE(p_hwfn,
3583                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3584                           src_id, min, max);
3585
3586                 return -EINVAL;
3587         }
3588
3589         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3590
3591         return 0;
3592 }
3593
3594 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3595                                   u8 *p_filter)
3596 {
3597         *p_high = p_filter[1] | (p_filter[0] << 8);
3598         *p_low = p_filter[5] | (p_filter[4] << 8) |
3599                  (p_filter[3] << 16) | (p_filter[2] << 24);
3600 }
3601
3602 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3603                            struct qed_ptt *p_ptt, u8 *p_filter)
3604 {
3605         u32 high = 0, low = 0, en;
3606         int i;
3607
3608         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3609                 return 0;
3610
3611         qed_llh_mac_to_filter(&high, &low, p_filter);
3612
3613         /* Find a free entry and utilize it */
3614         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3615                 en = qed_rd(p_hwfn, p_ptt,
3616                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3617                 if (en)
3618                         continue;
3619                 qed_wr(p_hwfn, p_ptt,
3620                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3621                        2 * i * sizeof(u32), low);
3622                 qed_wr(p_hwfn, p_ptt,
3623                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3624                        (2 * i + 1) * sizeof(u32), high);
3625                 qed_wr(p_hwfn, p_ptt,
3626                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3627                 qed_wr(p_hwfn, p_ptt,
3628                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3629                        i * sizeof(u32), 0);
3630                 qed_wr(p_hwfn, p_ptt,
3631                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3632                 break;
3633         }
3634         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3635                 DP_NOTICE(p_hwfn,
3636                           "Failed to find an empty LLH filter to utilize\n");
3637                 return -EINVAL;
3638         }
3639
3640         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3641                    "mac: %pM is added at %d\n",
3642                    p_filter, i);
3643
3644         return 0;
3645 }
3646
3647 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3648                                struct qed_ptt *p_ptt, u8 *p_filter)
3649 {
3650         u32 high = 0, low = 0;
3651         int i;
3652
3653         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3654                 return;
3655
3656         qed_llh_mac_to_filter(&high, &low, p_filter);
3657
3658         /* Find the entry and clean it */
3659         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3660                 if (qed_rd(p_hwfn, p_ptt,
3661                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3662                            2 * i * sizeof(u32)) != low)
3663                         continue;
3664                 if (qed_rd(p_hwfn, p_ptt,
3665                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3666                            (2 * i + 1) * sizeof(u32)) != high)
3667                         continue;
3668
3669                 qed_wr(p_hwfn, p_ptt,
3670                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3671                 qed_wr(p_hwfn, p_ptt,
3672                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3673                 qed_wr(p_hwfn, p_ptt,
3674                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3675                        (2 * i + 1) * sizeof(u32), 0);
3676
3677                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3678                            "mac: %pM is removed from %d\n",
3679                            p_filter, i);
3680                 break;
3681         }
3682         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3683                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3684 }
3685
3686 int
3687 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3688                             struct qed_ptt *p_ptt,
3689                             u16 source_port_or_eth_type,
3690                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3691 {
3692         u32 high = 0, low = 0, en;
3693         int i;
3694
3695         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3696                 return 0;
3697
3698         switch (type) {
3699         case QED_LLH_FILTER_ETHERTYPE:
3700                 high = source_port_or_eth_type;
3701                 break;
3702         case QED_LLH_FILTER_TCP_SRC_PORT:
3703         case QED_LLH_FILTER_UDP_SRC_PORT:
3704                 low = source_port_or_eth_type << 16;
3705                 break;
3706         case QED_LLH_FILTER_TCP_DEST_PORT:
3707         case QED_LLH_FILTER_UDP_DEST_PORT:
3708                 low = dest_port;
3709                 break;
3710         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3711         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3712                 low = (source_port_or_eth_type << 16) | dest_port;
3713                 break;
3714         default:
3715                 DP_NOTICE(p_hwfn,
3716                           "Non valid LLH protocol filter type %d\n", type);
3717                 return -EINVAL;
3718         }
3719         /* Find a free entry and utilize it */
3720         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3721                 en = qed_rd(p_hwfn, p_ptt,
3722                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3723                 if (en)
3724                         continue;
3725                 qed_wr(p_hwfn, p_ptt,
3726                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3727                        2 * i * sizeof(u32), low);
3728                 qed_wr(p_hwfn, p_ptt,
3729                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3730                        (2 * i + 1) * sizeof(u32), high);
3731                 qed_wr(p_hwfn, p_ptt,
3732                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3733                 qed_wr(p_hwfn, p_ptt,
3734                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3735                        i * sizeof(u32), 1 << type);
3736                 qed_wr(p_hwfn, p_ptt,
3737                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3738                 break;
3739         }
3740         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3741                 DP_NOTICE(p_hwfn,
3742                           "Failed to find an empty LLH filter to utilize\n");
3743                 return -EINVAL;
3744         }
3745         switch (type) {
3746         case QED_LLH_FILTER_ETHERTYPE:
3747                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3748                            "ETH type %x is added at %d\n",
3749                            source_port_or_eth_type, i);
3750                 break;
3751         case QED_LLH_FILTER_TCP_SRC_PORT:
3752                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3753                            "TCP src port %x is added at %d\n",
3754                            source_port_or_eth_type, i);
3755                 break;
3756         case QED_LLH_FILTER_UDP_SRC_PORT:
3757                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3758                            "UDP src port %x is added at %d\n",
3759                            source_port_or_eth_type, i);
3760                 break;
3761         case QED_LLH_FILTER_TCP_DEST_PORT:
3762                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3763                            "TCP dst port %x is added at %d\n", dest_port, i);
3764                 break;
3765         case QED_LLH_FILTER_UDP_DEST_PORT:
3766                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3767                            "UDP dst port %x is added at %d\n", dest_port, i);
3768                 break;
3769         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3770                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3771                            "TCP src/dst ports %x/%x are added at %d\n",
3772                            source_port_or_eth_type, dest_port, i);
3773                 break;
3774         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3775                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3776                            "UDP src/dst ports %x/%x are added at %d\n",
3777                            source_port_or_eth_type, dest_port, i);
3778                 break;
3779         }
3780         return 0;
3781 }
3782
3783 void
3784 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3785                                struct qed_ptt *p_ptt,
3786                                u16 source_port_or_eth_type,
3787                                u16 dest_port,
3788                                enum qed_llh_port_filter_type_t type)
3789 {
3790         u32 high = 0, low = 0;
3791         int i;
3792
3793         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3794                 return;
3795
3796         switch (type) {
3797         case QED_LLH_FILTER_ETHERTYPE:
3798                 high = source_port_or_eth_type;
3799                 break;
3800         case QED_LLH_FILTER_TCP_SRC_PORT:
3801         case QED_LLH_FILTER_UDP_SRC_PORT:
3802                 low = source_port_or_eth_type << 16;
3803                 break;
3804         case QED_LLH_FILTER_TCP_DEST_PORT:
3805         case QED_LLH_FILTER_UDP_DEST_PORT:
3806                 low = dest_port;
3807                 break;
3808         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3809         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3810                 low = (source_port_or_eth_type << 16) | dest_port;
3811                 break;
3812         default:
3813                 DP_NOTICE(p_hwfn,
3814                           "Non valid LLH protocol filter type %d\n", type);
3815                 return;
3816         }
3817
3818         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3819                 if (!qed_rd(p_hwfn, p_ptt,
3820                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3821                         continue;
3822                 if (!qed_rd(p_hwfn, p_ptt,
3823                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3824                         continue;
3825                 if (!(qed_rd(p_hwfn, p_ptt,
3826                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3827                              i * sizeof(u32)) & BIT(type)))
3828                         continue;
3829                 if (qed_rd(p_hwfn, p_ptt,
3830                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3831                            2 * i * sizeof(u32)) != low)
3832                         continue;
3833                 if (qed_rd(p_hwfn, p_ptt,
3834                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3835                            (2 * i + 1) * sizeof(u32)) != high)
3836                         continue;
3837
3838                 qed_wr(p_hwfn, p_ptt,
3839                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3840                 qed_wr(p_hwfn, p_ptt,
3841                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3842                 qed_wr(p_hwfn, p_ptt,
3843                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3844                        i * sizeof(u32), 0);
3845                 qed_wr(p_hwfn, p_ptt,
3846                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3847                 qed_wr(p_hwfn, p_ptt,
3848                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3849                        (2 * i + 1) * sizeof(u32), 0);
3850                 break;
3851         }
3852
3853         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3854                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3855 }
3856
3857 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3858                             u32 hw_addr, void *p_eth_qzone,
3859                             size_t eth_qzone_size, u8 timeset)
3860 {
3861         struct coalescing_timeset *p_coal_timeset;
3862
3863         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3864                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3865                 return -EINVAL;
3866         }
3867
3868         p_coal_timeset = p_eth_qzone;
3869         memset(p_eth_qzone, 0, eth_qzone_size);
3870         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3871         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3872         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3873
3874         return 0;
3875 }
3876
3877 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3878 {
3879         struct qed_queue_cid *p_cid = p_handle;
3880         struct qed_hwfn *p_hwfn;
3881         struct qed_ptt *p_ptt;
3882         int rc = 0;
3883
3884         p_hwfn = p_cid->p_owner;
3885
3886         if (IS_VF(p_hwfn->cdev))
3887                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3888
3889         p_ptt = qed_ptt_acquire(p_hwfn);
3890         if (!p_ptt)
3891                 return -EAGAIN;
3892
3893         if (rx_coal) {
3894                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3895                 if (rc)
3896                         goto out;
3897                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3898         }
3899
3900         if (tx_coal) {
3901                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3902                 if (rc)
3903                         goto out;
3904                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3905         }
3906 out:
3907         qed_ptt_release(p_hwfn, p_ptt);
3908         return rc;
3909 }
3910
3911 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3912                          struct qed_ptt *p_ptt,
3913                          u16 coalesce, struct qed_queue_cid *p_cid)
3914 {
3915         struct ustorm_eth_queue_zone eth_qzone;
3916         u8 timeset, timer_res;
3917         u32 address;
3918         int rc;
3919
3920         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3921         if (coalesce <= 0x7F) {
3922                 timer_res = 0;
3923         } else if (coalesce <= 0xFF) {
3924                 timer_res = 1;
3925         } else if (coalesce <= 0x1FF) {
3926                 timer_res = 2;
3927         } else {
3928                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3929                 return -EINVAL;
3930         }
3931         timeset = (u8)(coalesce >> timer_res);
3932
3933         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3934                                    p_cid->sb_igu_id, false);
3935         if (rc)
3936                 goto out;
3937
3938         address = BAR0_MAP_REG_USDM_RAM +
3939                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3940
3941         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3942                               sizeof(struct ustorm_eth_queue_zone), timeset);
3943         if (rc)
3944                 goto out;
3945
3946 out:
3947         return rc;
3948 }
3949
3950 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3951                          struct qed_ptt *p_ptt,
3952                          u16 coalesce, struct qed_queue_cid *p_cid)
3953 {
3954         struct xstorm_eth_queue_zone eth_qzone;
3955         u8 timeset, timer_res;
3956         u32 address;
3957         int rc;
3958
3959         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3960         if (coalesce <= 0x7F) {
3961                 timer_res = 0;
3962         } else if (coalesce <= 0xFF) {
3963                 timer_res = 1;
3964         } else if (coalesce <= 0x1FF) {
3965                 timer_res = 2;
3966         } else {
3967                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3968                 return -EINVAL;
3969         }
3970         timeset = (u8)(coalesce >> timer_res);
3971
3972         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3973                                    p_cid->sb_igu_id, true);
3974         if (rc)
3975                 goto out;
3976
3977         address = BAR0_MAP_REG_XSDM_RAM +
3978                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3979
3980         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3981                               sizeof(struct xstorm_eth_queue_zone), timeset);
3982 out:
3983         return rc;
3984 }
3985
3986 /* Calculate final WFQ values for all vports and configure them.
3987  * After this configuration each vport will have
3988  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3989  */
3990 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3991                                              struct qed_ptt *p_ptt,
3992                                              u32 min_pf_rate)
3993 {
3994         struct init_qm_vport_params *vport_params;
3995         int i;
3996
3997         vport_params = p_hwfn->qm_info.qm_vport_params;
3998
3999         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4000                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4001
4002                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
4003                                                 min_pf_rate;
4004                 qed_init_vport_wfq(p_hwfn, p_ptt,
4005                                    vport_params[i].first_tx_pq_id,
4006                                    vport_params[i].vport_wfq);
4007         }
4008 }
4009
4010 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4011                                        u32 min_pf_rate)
4012
4013 {
4014         int i;
4015
4016         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4017                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4018 }
4019
4020 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4021                                            struct qed_ptt *p_ptt,
4022                                            u32 min_pf_rate)
4023 {
4024         struct init_qm_vport_params *vport_params;
4025         int i;
4026
4027         vport_params = p_hwfn->qm_info.qm_vport_params;
4028
4029         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4030                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4031                 qed_init_vport_wfq(p_hwfn, p_ptt,
4032                                    vport_params[i].first_tx_pq_id,
4033                                    vport_params[i].vport_wfq);
4034         }
4035 }
4036
4037 /* This function performs several validations for WFQ
4038  * configuration and required min rate for a given vport
4039  * 1. req_rate must be greater than one percent of min_pf_rate.
4040  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4041  *    rates to get less than one percent of min_pf_rate.
4042  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4043  */
4044 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4045                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
4046 {
4047         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4048         int non_requested_count = 0, req_count = 0, i, num_vports;
4049
4050         num_vports = p_hwfn->qm_info.num_vports;
4051
4052         /* Accounting for the vports which are configured for WFQ explicitly */
4053         for (i = 0; i < num_vports; i++) {
4054                 u32 tmp_speed;
4055
4056                 if ((i != vport_id) &&
4057                     p_hwfn->qm_info.wfq_data[i].configured) {
4058                         req_count++;
4059                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4060                         total_req_min_rate += tmp_speed;
4061                 }
4062         }
4063
4064         /* Include current vport data as well */
4065         req_count++;
4066         total_req_min_rate += req_rate;
4067         non_requested_count = num_vports - req_count;
4068
4069         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4070                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4071                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4072                            vport_id, req_rate, min_pf_rate);
4073                 return -EINVAL;
4074         }
4075
4076         if (num_vports > QED_WFQ_UNIT) {
4077                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4078                            "Number of vports is greater than %d\n",
4079                            QED_WFQ_UNIT);
4080                 return -EINVAL;
4081         }
4082
4083         if (total_req_min_rate > min_pf_rate) {
4084                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4085                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4086                            total_req_min_rate, min_pf_rate);
4087                 return -EINVAL;
4088         }
4089
4090         total_left_rate = min_pf_rate - total_req_min_rate;
4091
4092         left_rate_per_vp = total_left_rate / non_requested_count;
4093         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
4094                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4095                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4096                            left_rate_per_vp, min_pf_rate);
4097                 return -EINVAL;
4098         }
4099
4100         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4101         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4102
4103         for (i = 0; i < num_vports; i++) {
4104                 if (p_hwfn->qm_info.wfq_data[i].configured)
4105                         continue;
4106
4107                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4108         }
4109
4110         return 0;
4111 }
4112
4113 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4114                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4115 {
4116         struct qed_mcp_link_state *p_link;
4117         int rc = 0;
4118
4119         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4120
4121         if (!p_link->min_pf_rate) {
4122                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4123                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4124                 return rc;
4125         }
4126
4127         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4128
4129         if (!rc)
4130                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4131                                                  p_link->min_pf_rate);
4132         else
4133                 DP_NOTICE(p_hwfn,
4134                           "Validation failed while configuring min rate\n");
4135
4136         return rc;
4137 }
4138
4139 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4140                                                  struct qed_ptt *p_ptt,
4141                                                  u32 min_pf_rate)
4142 {
4143         bool use_wfq = false;
4144         int rc = 0;
4145         u16 i;
4146
4147         /* Validate all pre configured vports for wfq */
4148         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4149                 u32 rate;
4150
4151                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4152                         continue;
4153
4154                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4155                 use_wfq = true;
4156
4157                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4158                 if (rc) {
4159                         DP_NOTICE(p_hwfn,
4160                                   "WFQ validation failed while configuring min rate\n");
4161                         break;
4162                 }
4163         }
4164
4165         if (!rc && use_wfq)
4166                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4167         else
4168                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4169
4170         return rc;
4171 }
4172
4173 /* Main API for qed clients to configure vport min rate.
4174  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4175  * rate - Speed in Mbps needs to be assigned to a given vport.
4176  */
4177 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4178 {
4179         int i, rc = -EINVAL;
4180
4181         /* Currently not supported; Might change in future */
4182         if (cdev->num_hwfns > 1) {
4183                 DP_NOTICE(cdev,
4184                           "WFQ configuration is not supported for this device\n");
4185                 return rc;
4186         }
4187
4188         for_each_hwfn(cdev, i) {
4189                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4190                 struct qed_ptt *p_ptt;
4191
4192                 p_ptt = qed_ptt_acquire(p_hwfn);
4193                 if (!p_ptt)
4194                         return -EBUSY;
4195
4196                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4197
4198                 if (rc) {
4199                         qed_ptt_release(p_hwfn, p_ptt);
4200                         return rc;
4201                 }
4202
4203                 qed_ptt_release(p_hwfn, p_ptt);
4204         }
4205
4206         return rc;
4207 }
4208
4209 /* API to configure WFQ from mcp link change */
4210 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4211                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4212 {
4213         int i;
4214
4215         if (cdev->num_hwfns > 1) {
4216                 DP_VERBOSE(cdev,
4217                            NETIF_MSG_LINK,
4218                            "WFQ configuration is not supported for this device\n");
4219                 return;
4220         }
4221
4222         for_each_hwfn(cdev, i) {
4223                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4224
4225                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4226                                                       min_pf_rate);
4227         }
4228 }
4229
4230 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4231                                      struct qed_ptt *p_ptt,
4232                                      struct qed_mcp_link_state *p_link,
4233                                      u8 max_bw)
4234 {
4235         int rc = 0;
4236
4237         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4238
4239         if (!p_link->line_speed && (max_bw != 100))
4240                 return rc;
4241
4242         p_link->speed = (p_link->line_speed * max_bw) / 100;
4243         p_hwfn->qm_info.pf_rl = p_link->speed;
4244
4245         /* Since the limiter also affects Tx-switched traffic, we don't want it
4246          * to limit such traffic in case there's no actual limit.
4247          * In that case, set limit to imaginary high boundary.
4248          */
4249         if (max_bw == 100)
4250                 p_hwfn->qm_info.pf_rl = 100000;
4251
4252         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4253                             p_hwfn->qm_info.pf_rl);
4254
4255         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4256                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4257                    p_link->speed);
4258
4259         return rc;
4260 }
4261
4262 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4263 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4264 {
4265         int i, rc = -EINVAL;
4266
4267         if (max_bw < 1 || max_bw > 100) {
4268                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4269                 return rc;
4270         }
4271
4272         for_each_hwfn(cdev, i) {
4273                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4274                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4275                 struct qed_mcp_link_state *p_link;
4276                 struct qed_ptt *p_ptt;
4277
4278                 p_link = &p_lead->mcp_info->link_output;
4279
4280                 p_ptt = qed_ptt_acquire(p_hwfn);
4281                 if (!p_ptt)
4282                         return -EBUSY;
4283
4284                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4285                                                       p_link, max_bw);
4286
4287                 qed_ptt_release(p_hwfn, p_ptt);
4288
4289                 if (rc)
4290                         break;
4291         }
4292
4293         return rc;
4294 }
4295
4296 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4297                                      struct qed_ptt *p_ptt,
4298                                      struct qed_mcp_link_state *p_link,
4299                                      u8 min_bw)
4300 {
4301         int rc = 0;
4302
4303         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4304         p_hwfn->qm_info.pf_wfq = min_bw;
4305
4306         if (!p_link->line_speed)
4307                 return rc;
4308
4309         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4310
4311         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4312
4313         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4314                    "Configured MIN bandwidth to be %d Mb/sec\n",
4315                    p_link->min_pf_rate);
4316
4317         return rc;
4318 }
4319
4320 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4321 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4322 {
4323         int i, rc = -EINVAL;
4324
4325         if (min_bw < 1 || min_bw > 100) {
4326                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4327                 return rc;
4328         }
4329
4330         for_each_hwfn(cdev, i) {
4331                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4332                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4333                 struct qed_mcp_link_state *p_link;
4334                 struct qed_ptt *p_ptt;
4335
4336                 p_link = &p_lead->mcp_info->link_output;
4337
4338                 p_ptt = qed_ptt_acquire(p_hwfn);
4339                 if (!p_ptt)
4340                         return -EBUSY;
4341
4342                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4343                                                       p_link, min_bw);
4344                 if (rc) {
4345                         qed_ptt_release(p_hwfn, p_ptt);
4346                         return rc;
4347                 }
4348
4349                 if (p_link->min_pf_rate) {
4350                         u32 min_rate = p_link->min_pf_rate;
4351
4352                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4353                                                                    p_ptt,
4354                                                                    min_rate);
4355                 }
4356
4357                 qed_ptt_release(p_hwfn, p_ptt);
4358         }
4359
4360         return rc;
4361 }
4362
4363 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4364 {
4365         struct qed_mcp_link_state *p_link;
4366
4367         p_link = &p_hwfn->mcp_info->link_output;
4368
4369         if (p_link->min_pf_rate)
4370                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4371                                                p_link->min_pf_rate);
4372
4373         memset(p_hwfn->qm_info.wfq_data, 0,
4374                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4375 }
4376
4377 int qed_device_num_engines(struct qed_dev *cdev)
4378 {
4379         return QED_IS_BB(cdev) ? 2 : 1;
4380 }
4381
4382 static int qed_device_num_ports(struct qed_dev *cdev)
4383 {
4384         /* in CMT always only one port */
4385         if (cdev->num_hwfns > 1)
4386                 return 1;
4387
4388         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4389 }
4390
4391 int qed_device_get_port_id(struct qed_dev *cdev)
4392 {
4393         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4394 }
4395
4396 void qed_set_fw_mac_addr(__le16 *fw_msb,
4397                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4398 {
4399         ((u8 *)fw_msb)[0] = mac[1];
4400         ((u8 *)fw_msb)[1] = mac[0];
4401         ((u8 *)fw_mid)[0] = mac[3];
4402         ((u8 *)fw_mid)[1] = mac[2];
4403         ((u8 *)fw_lsb)[0] = mac[5];
4404         ((u8 *)fw_lsb)[1] = mac[4];
4405 }