drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <net/ip6_checksum.h>
  38 #include <net/page_pool.h>
  39 #include <net/inet_ecn.h>
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "eswitch.h"
  43 #include "en_rep.h"
  44 #include "ipoib/ipoib.h"
  45 #include "en_accel/ipsec_rxtx.h"
  46 #include "en_accel/tls_rxtx.h"
  47 #include "lib/clock.h"
  48 #include "en/xdp.h"
  49
  50 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  51 {
  52         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  53 }
  54
  55 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  56                                        void *data)
  57 {
  58         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
  59
  60         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  61 }
  62
  63 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  64                                          struct mlx5e_cq *cq, u32 cqcc)
  65 {
  66         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  67         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  68         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  69         rq->stats->cqe_compress_blks++;
  70 }
  71
  72 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  73 {
  74         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  75         cq->mini_arr_idx = 0;
  76 }
  77
  78 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  79 {
  80         struct mlx5_cqwq *wq = &cq->wq;
  81
  82         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  83         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  84         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  85         u32 ci_top = min_t(u32, wq_sz, ci + n);
  86
  87         for (; ci < ci_top; ci++, n--) {
  88                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  89
  90                 cqe->op_own = op_own;
  91         }
  92
  93         if (unlikely(ci == wq_sz)) {
  94                 op_own = !op_own;
  95                 for (ci = 0; ci < n; ci++) {
  96                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  97
  98                         cqe->op_own = op_own;
  99                 }
 100         }
 101 }
 102
 103 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 104                                         struct mlx5e_cq *cq, u32 cqcc)
 105 {
 106         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 107         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 108         cq->title.op_own      &= 0xf0;
 109         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 110         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 111
 112         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 113                 cq->decmprs_wqe_counter +=
 114                         mpwrq_get_cqe_consumed_strides(&cq->title);
 115         else
 116                 cq->decmprs_wqe_counter =
 117                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
 118 }
 119
 120 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 121                                                 struct mlx5e_cq *cq, u32 cqcc)
 122 {
 123         mlx5e_decompress_cqe(rq, cq, cqcc);
 124         cq->title.rss_hash_type   = 0;
 125         cq->title.rss_hash_result = 0;
 126 }
 127
 128 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 129                                              struct mlx5e_cq *cq,
 130                                              int update_owner_only,
 131                                              int budget_rem)
 132 {
 133         u32 cqcc = cq->wq.cc + update_owner_only;
 134         u32 cqe_count;
 135         u32 i;
 136
 137         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 138
 139         for (i = update_owner_only; i < cqe_count;
 140              i++, cq->mini_arr_idx++, cqcc++) {
 141                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 142                         mlx5e_read_mini_arr_slot(cq, cqcc);
 143
 144                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 145                 rq->handle_rx_cqe(rq, &cq->title);
 146         }
 147         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 148         cq->wq.cc = cqcc;
 149         cq->decmprs_left -= cqe_count;
 150         rq->stats->cqe_compress_pkts += cqe_count;
 151
 152         return cqe_count;
 153 }
 154
 155 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 156                                               struct mlx5e_cq *cq,
 157                                               int budget_rem)
 158 {
 159         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 160         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 161         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 162         rq->handle_rx_cqe(rq, &cq->title);
 163         cq->mini_arr_idx++;
 164
 165         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 166 }
 167
 168 static inline bool mlx5e_page_is_reserved(struct page *page)
 169 {
 170         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 171 }
 172
 173 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 174                                       struct mlx5e_dma_info *dma_info)
 175 {
 176         struct mlx5e_page_cache *cache = &rq->page_cache;
 177         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 178         struct mlx5e_rq_stats *stats = rq->stats;
 179
 180         if (tail_next == cache->head) {
 181                 stats->cache_full++;
 182                 return false;
 183         }
 184
 185         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 186                 stats->cache_waive++;
 187                 return false;
 188         }
 189
 190         cache->page_cache[cache->tail] = *dma_info;
 191         cache->tail = tail_next;
 192         return true;
 193 }
 194
 195 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 196                                       struct mlx5e_dma_info *dma_info)
 197 {
 198         struct mlx5e_page_cache *cache = &rq->page_cache;
 199         struct mlx5e_rq_stats *stats = rq->stats;
 200
 201         if (unlikely(cache->head == cache->tail)) {
 202                 stats->cache_empty++;
 203                 return false;
 204         }
 205
 206         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 207                 stats->cache_busy++;
 208                 return false;
 209         }
 210
 211         *dma_info = cache->page_cache[cache->head];
 212         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 213         stats->cache_reuse++;
 214
 215         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 216                                    PAGE_SIZE,
 217                                    DMA_FROM_DEVICE);
 218         return true;
 219 }
 220
 221 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 222                                           struct mlx5e_dma_info *dma_info)
 223 {
 224         if (mlx5e_rx_cache_get(rq, dma_info))
 225                 return 0;
 226
 227         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 228         if (unlikely(!dma_info->page))
 229                 return -ENOMEM;
 230
 231         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 232                                       PAGE_SIZE, rq->buff.map_dir);
 233         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 234                 put_page(dma_info->page);
 235                 dma_info->page = NULL;
 236                 return -ENOMEM;
 237         }
 238
 239         return 0;
 240 }
 241
 242 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 243 {
 244         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 245 }
 246
 247 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 248                         bool recycle)
 249 {
 250         if (likely(recycle)) {
 251                 if (mlx5e_rx_cache_put(rq, dma_info))
 252                         return;
 253
 254                 mlx5e_page_dma_unmap(rq, dma_info);
 255                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 256         } else {
 257                 mlx5e_page_dma_unmap(rq, dma_info);
 258                 put_page(dma_info->page);
 259         }
 260 }
 261
 262 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 263                                     struct mlx5e_wqe_frag_info *frag)
 264 {
 265         int err = 0;
 266
 267         if (!frag->offset)
 268                 /* On first frag (offset == 0), replenish page (dma_info actually).
 269                  * Other frags that point to the same dma_info (with a different
 270                  * offset) should just use the new one without replenishing again
 271                  * by themselves.
 272                  */
 273                 err = mlx5e_page_alloc_mapped(rq, frag->di);
 274
 275         return err;
 276 }
 277
 278 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 279                                      struct mlx5e_wqe_frag_info *frag,
 280                                      bool recycle)
 281 {
 282         if (frag->last_in_page)
 283                 mlx5e_page_release(rq, frag->di, recycle);
 284 }
 285
 286 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 287 {
 288         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 289 }
 290
 291 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 292                               u16 ix)
 293 {
 294         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 295         int err;
 296         int i;
 297
 298         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 299                 err = mlx5e_get_rx_frag(rq, frag);
 300                 if (unlikely(err))
 301                         goto free_frags;
 302
 303                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 304                                                 frag->offset + rq->buff.headroom);
 305         }
 306
 307         return 0;
 308
 309 free_frags:
 310         while (--i >= 0)
 311                 mlx5e_put_rx_frag(rq, --frag, true);
 312
 313         return err;
 314 }
 315
 316 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 317                                      struct mlx5e_wqe_frag_info *wi,
 318                                      bool recycle)
 319 {
 320         int i;
 321
 322         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 323                 mlx5e_put_rx_frag(rq, wi, recycle);
 324 }
 325
 326 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 327 {
 328         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 329
 330         mlx5e_free_rx_wqe(rq, wi, false);
 331 }
 332
 333 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 334 {
 335         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 336         int err;
 337         int i;
 338
 339         for (i = 0; i < wqe_bulk; i++) {
 340                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 341
 342                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 343                 if (unlikely(err))
 344                         goto free_wqes;
 345         }
 346
 347         return 0;
 348
 349 free_wqes:
 350         while (--i >= 0)
 351                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 352
 353         return err;
 354 }
 355
 356 static inline void
 357 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 358                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 359                    unsigned int truesize)
 360 {
 361         dma_sync_single_for_cpu(rq->pdev,
 362                                 di->addr + frag_offset,
 363                                 len, DMA_FROM_DEVICE);
 364         page_ref_inc(di->page);
 365         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 366                         di->page, frag_offset, len, truesize);
 367 }
 368
 369 static inline void
 370 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 371                       struct mlx5e_dma_info *dma_info,
 372                       int offset_from, int offset_to, u32 headlen)
 373 {
 374         const void *from = page_address(dma_info->page) + offset_from;
 375         /* Aligning len to sizeof(long) optimizes memcpy performance */
 376         unsigned int len = ALIGN(headlen, sizeof(long));
 377
 378         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 379                                 DMA_FROM_DEVICE);
 380         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
 381 }
 382
 383 static inline void
 384 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 385                             struct sk_buff *skb,
 386                             struct mlx5e_dma_info *dma_info,
 387                             u32 offset, u32 headlen)
 388 {
 389         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 390
 391         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
 392
 393         if (unlikely(offset + headlen > PAGE_SIZE)) {
 394                 dma_info++;
 395                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
 396                                       headlen - headlen_pg);
 397         }
 398 }
 399
 400 static void
 401 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 402 {
 403         const bool no_xdp_xmit =
 404                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 405         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 406         int i;
 407
 408         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 409                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 410                         mlx5e_page_release(rq, &dma_info[i], recycle);
 411 }
 412
 413 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 414 {
 415         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 416         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 417
 418         rq->mpwqe.umr_in_progress = false;
 419
 420         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 421
 422         /* ensure wqes are visible to device before updating doorbell record */
 423         dma_wmb();
 424
 425         mlx5_wq_ll_update_db_record(wq);
 426 }
 427
 428 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 429 {
 430         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 431 }
 432
 433 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 434                                               struct mlx5_wq_cyc *wq,
 435                                               u16 pi, u16 nnops)
 436 {
 437         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 438
 439         edge_wi = wi + nnops;
 440
 441         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 442         for (; wi < edge_wi; wi++) {
 443                 wi->opcode = MLX5_OPCODE_NOP;
 444                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 445         }
 446 }
 447
 448 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 449 {
 450         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 451         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 452         struct mlx5e_icosq *sq = &rq->channel->icosq;
 453         struct mlx5_wq_cyc *wq = &sq->wq;
 454         struct mlx5e_umr_wqe *umr_wqe;
 455         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 456         u16 pi, contig_wqebbs_room;
 457         int err;
 458         int i;
 459
 460         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 461         contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
 462         if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
 463                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
 464                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 465         }
 466
 467         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 468         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 469                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 470                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 471
 472         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 473                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 474                 if (unlikely(err))
 475                         goto err_unmap;
 476                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 477         }
 478
 479         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 480         wi->consumed_strides = 0;
 481
 482         rq->mpwqe.umr_in_progress = true;
 483
 484         umr_wqe->ctrl.opmod_idx_opcode =
 485                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 486                             MLX5_OPCODE_UMR);
 487         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 488
 489         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 490         sq->pc += MLX5E_UMR_WQEBBS;
 491         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 492
 493         return 0;
 494
 495 err_unmap:
 496         while (--i >= 0) {
 497                 dma_info--;
 498                 mlx5e_page_release(rq, dma_info, true);
 499         }
 500         rq->stats->buff_alloc_err++;
 501
 502         return err;
 503 }
 504
 505 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 506 {
 507         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 508         /* Don't recycle, this function is called on rq/netdev close */
 509         mlx5e_free_rx_mpwqe(rq, wi, false);
 510 }
 511
 512 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 513 {
 514         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 515         u8 wqe_bulk;
 516         int err;
 517
 518         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 519                 return false;
 520
 521         wqe_bulk = rq->wqe.info.wqe_bulk;
 522
 523         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 524                 return false;
 525
 526         do {
 527                 u16 head = mlx5_wq_cyc_get_head(wq);
 528
 529                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 530                 if (unlikely(err)) {
 531                         rq->stats->buff_alloc_err++;
 532                         break;
 533                 }
 534
 535                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 536         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 537
 538         /* ensure wqes are visible to device before updating doorbell record */
 539         dma_wmb();
 540
 541         mlx5_wq_cyc_update_db_record(wq);
 542
 543         return !!err;
 544 }
 545
 546 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 547                                              struct mlx5e_icosq *sq,
 548                                              struct mlx5e_rq *rq,
 549                                              struct mlx5_cqe64 *cqe)
 550 {
 551         struct mlx5_wq_cyc *wq = &sq->wq;
 552         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 553         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 554
 555         mlx5_cqwq_pop(&cq->wq);
 556
 557         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 558                 netdev_WARN_ONCE(cq->channel->netdev,
 559                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 560                 return;
 561         }
 562
 563         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 564                 mlx5e_post_rx_mpwqe(rq);
 565                 return;
 566         }
 567
 568         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 569                 netdev_WARN_ONCE(cq->channel->netdev,
 570                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 571 }
 572
 573 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 574 {
 575         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 576         struct mlx5_cqe64 *cqe;
 577
 578         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 579                 return;
 580
 581         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 582         if (likely(!cqe))
 583                 return;
 584
 585         /* by design, there's only a single cqe */
 586         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 587
 588         mlx5_cqwq_update_db_record(&cq->wq);
 589 }
 590
 591 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 592 {
 593         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 594
 595         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 596                 return false;
 597
 598         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 599
 600         if (mlx5_wq_ll_is_full(wq))
 601                 return false;
 602
 603         if (!rq->mpwqe.umr_in_progress)
 604                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 605         else
 606                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
 607
 608         return false;
 609 }
 610
 611 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 612 {
 613         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 614         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 615                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 616
 617         tcp->check                      = 0;
 618         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 619
 620         if (tcp_ack) {
 621                 tcp->ack                = 1;
 622                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 623                 tcp->window             = cqe->lro_tcp_win;
 624         }
 625 }
 626
 627 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 628                                  u32 cqe_bcnt)
 629 {
 630         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 631         struct tcphdr   *tcp;
 632         int network_depth = 0;
 633         __wsum check;
 634         __be16 proto;
 635         u16 tot_len;
 636         void *ip_p;
 637
 638         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 639
 640         tot_len = cqe_bcnt - network_depth;
 641         ip_p = skb->data + network_depth;
 642
 643         if (proto == htons(ETH_P_IP)) {
 644                 struct iphdr *ipv4 = ip_p;
 645
 646                 tcp = ip_p + sizeof(struct iphdr);
 647                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 648
 649                 ipv4->ttl               = cqe->lro_min_ttl;
 650                 ipv4->tot_len           = cpu_to_be16(tot_len);
 651                 ipv4->check             = 0;
 652                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 653                                                        ipv4->ihl);
 654
 655                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 656                 check = csum_partial(tcp, tcp->doff * 4,
 657                                      csum_unfold((__force __sum16)cqe->check_sum));
 658                 /* Almost done, don't forget the pseudo header */
 659                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 660                                                tot_len - sizeof(struct iphdr),
 661                                                IPPROTO_TCP, check);
 662         } else {
 663                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 664                 struct ipv6hdr *ipv6 = ip_p;
 665
 666                 tcp = ip_p + sizeof(struct ipv6hdr);
 667                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 668
 669                 ipv6->hop_limit         = cqe->lro_min_ttl;
 670                 ipv6->payload_len       = cpu_to_be16(payload_len);
 671
 672                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 673                 check = csum_partial(tcp, tcp->doff * 4,
 674                                      csum_unfold((__force __sum16)cqe->check_sum));
 675                 /* Almost done, don't forget the pseudo header */
 676                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 677                                              IPPROTO_TCP, check);
 678         }
 679 }
 680
 681 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 682                                       struct sk_buff *skb)
 683 {
 684         u8 cht = cqe->rss_hash_type;
 685         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 686                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 687                                             PKT_HASH_TYPE_NONE;
 688         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 689 }
 690
 691 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 692                                         __be16 *proto)
 693 {
 694         *proto = ((struct ethhdr *)skb->data)->h_proto;
 695         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 696         return (*proto == htons(ETH_P_IP) || *proto == htons(ETH_P_IPV6));
 697 }
 698
 699 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 700 {
 701         int network_depth = 0;
 702         __be16 proto;
 703         void *ip;
 704         int rc;
 705
 706         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 707                 return;
 708
 709         ip = skb->data + network_depth;
 710         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 711                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 712
 713         rq->stats->ecn_mark += !!rc;
 714 }
 715
 716 static u32 mlx5e_get_fcs(const struct sk_buff *skb)
 717 {
 718         const void *fcs_bytes;
 719         u32 _fcs_bytes;
 720
 721         fcs_bytes = skb_header_pointer(skb, skb->len - ETH_FCS_LEN,
 722                                        ETH_FCS_LEN, &_fcs_bytes);
 723
 724         return __get_unaligned_cpu32(fcs_bytes);
 725 }
 726
 727 static u8 get_ip_proto(struct sk_buff *skb, __be16 proto)
 728 {
 729         void *ip_p = skb->data + sizeof(struct ethhdr);
 730
 731         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 732                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 733 }
 734
 735 static inline void mlx5e_handle_csum(struct net_device *netdev,
 736                                      struct mlx5_cqe64 *cqe,
 737                                      struct mlx5e_rq *rq,
 738                                      struct sk_buff *skb,
 739                                      bool   lro)
 740 {
 741         struct mlx5e_rq_stats *stats = rq->stats;
 742         int network_depth = 0;
 743         __be16 proto;
 744
 745         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 746                 goto csum_none;
 747
 748         if (lro) {
 749                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 750                 stats->csum_unnecessary++;
 751                 return;
 752         }
 753
 754         if (unlikely(test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state)))
 755                 goto csum_unnecessary;
 756
 757         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 758                 if (unlikely(get_ip_proto(skb, proto) == IPPROTO_SCTP))
 759                         goto csum_unnecessary;
 760
 761                 skb->ip_summed = CHECKSUM_COMPLETE;
 762                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 763                 if (network_depth > ETH_HLEN)
 764                         /* CQE csum is calculated from the IP header and does
 765                          * not cover VLAN headers (if present). This will add
 766                          * the checksum manually.
 767                          */
 768                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 769                                                  network_depth - ETH_HLEN,
 770                                                  skb->csum);
 771                 if (unlikely(netdev->features & NETIF_F_RXFCS))
 772                         skb->csum = csum_block_add(skb->csum,
 773                                                    (__force __wsum)mlx5e_get_fcs(skb),
 774                                                    skb->len - ETH_FCS_LEN);
 775                 stats->csum_complete++;
 776                 return;
 777         }
 778
 779 csum_unnecessary:
 780         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 781                    ((cqe->hds_ip_ext & CQE_L4_OK) ||
 782                     (get_cqe_l4_hdr_type(cqe) == CQE_L4_HDR_TYPE_NONE)))) {
 783                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 784                 if (cqe_is_tunneled(cqe)) {
 785                         skb->csum_level = 1;
 786                         skb->encapsulation = 1;
 787                         stats->csum_unnecessary_inner++;
 788                         return;
 789                 }
 790                 stats->csum_unnecessary++;
 791                 return;
 792         }
 793 csum_none:
 794         skb->ip_summed = CHECKSUM_NONE;
 795         stats->csum_none++;
 796 }
 797
 798 #define MLX5E_CE_BIT_MASK 0x80
 799
 800 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 801                                       u32 cqe_bcnt,
 802                                       struct mlx5e_rq *rq,
 803                                       struct sk_buff *skb)
 804 {
 805         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 806         struct mlx5e_rq_stats *stats = rq->stats;
 807         struct net_device *netdev = rq->netdev;
 808
 809         skb->mac_len = ETH_HLEN;
 810
 811 #ifdef CONFIG_MLX5_EN_TLS
 812         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 813 #endif
 814
 815         if (lro_num_seg > 1) {
 816                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 817                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 818                 /* Subtract one since we already counted this as one
 819                  * "regular" packet in mlx5e_complete_rx_cqe()
 820                  */
 821                 stats->packets += lro_num_seg - 1;
 822                 stats->lro_packets++;
 823                 stats->lro_bytes += cqe_bcnt;
 824         }
 825
 826         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 827                 skb_hwtstamps(skb)->hwtstamp =
 828                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 829
 830         skb_record_rx_queue(skb, rq->ix);
 831
 832         if (likely(netdev->features & NETIF_F_RXHASH))
 833                 mlx5e_skb_set_hash(cqe, skb);
 834
 835         if (cqe_has_vlan(cqe)) {
 836                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 837                                        be16_to_cpu(cqe->vlan_info));
 838                 stats->removed_vlan_packets++;
 839         }
 840
 841         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 842
 843         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 844         /* checking CE bit in cqe - MSB in ml_path field */
 845         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
 846                 mlx5e_enable_ecn(rq, skb);
 847
 848         skb->protocol = eth_type_trans(skb, netdev);
 849 }
 850
 851 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 852                                          struct mlx5_cqe64 *cqe,
 853                                          u32 cqe_bcnt,
 854                                          struct sk_buff *skb)
 855 {
 856         struct mlx5e_rq_stats *stats = rq->stats;
 857
 858         stats->packets++;
 859         stats->bytes += cqe_bcnt;
 860         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 861 }
 862
 863 static inline
 864 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 865                                        u32 frag_size, u16 headroom,
 866                                        u32 cqe_bcnt)
 867 {
 868         struct sk_buff *skb = build_skb(va, frag_size);
 869
 870         if (unlikely(!skb)) {
 871                 rq->stats->buff_alloc_err++;
 872                 return NULL;
 873         }
 874
 875         skb_reserve(skb, headroom);
 876         skb_put(skb, cqe_bcnt);
 877
 878         return skb;
 879 }
 880
 881 struct sk_buff *
 882 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 883                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 884 {
 885         struct mlx5e_dma_info *di = wi->di;
 886         u16 rx_headroom = rq->buff.headroom;
 887         struct sk_buff *skb;
 888         void *va, *data;
 889         bool consumed;
 890         u32 frag_size;
 891
 892         va             = page_address(di->page) + wi->offset;
 893         data           = va + rx_headroom;
 894         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 895
 896         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
 897                                       frag_size, DMA_FROM_DEVICE);
 898         prefetchw(va); /* xdp_frame data area */
 899         prefetch(data);
 900
 901         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 902                 rq->stats->wqe_err++;
 903                 return NULL;
 904         }
 905
 906         rcu_read_lock();
 907         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 908         rcu_read_unlock();
 909         if (consumed)
 910                 return NULL; /* page/packet was consumed by XDP */
 911
 912         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
 913         if (unlikely(!skb))
 914                 return NULL;
 915
 916         /* queue up for recycling/reuse */
 917         page_ref_inc(di->page);
 918
 919         return skb;
 920 }
 921
 922 struct sk_buff *
 923 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 924                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 925 {
 926         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 927         struct mlx5e_wqe_frag_info *head_wi = wi;
 928         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
 929         u16 frag_headlen = headlen;
 930         u16 byte_cnt     = cqe_bcnt - headlen;
 931         struct sk_buff *skb;
 932
 933         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 934                 rq->stats->wqe_err++;
 935                 return NULL;
 936         }
 937
 938         /* XDP is not supported in this configuration, as incoming packets
 939          * might spread among multiple pages.
 940          */
 941         skb = napi_alloc_skb(rq->cq.napi,
 942                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
 943         if (unlikely(!skb)) {
 944                 rq->stats->buff_alloc_err++;
 945                 return NULL;
 946         }
 947
 948         prefetchw(skb->data);
 949
 950         while (byte_cnt) {
 951                 u16 frag_consumed_bytes =
 952                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
 953
 954                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
 955                                    frag_consumed_bytes, frag_info->frag_stride);
 956                 byte_cnt -= frag_consumed_bytes;
 957                 frag_headlen = 0;
 958                 frag_info++;
 959                 wi++;
 960         }
 961
 962         /* copy header */
 963         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
 964                               0, headlen);
 965         /* skb linear part was allocated with headlen and aligned to long */
 966         skb->tail += headlen;
 967         skb->len  += headlen;
 968
 969         return skb;
 970 }
 971
 972 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 973 {
 974         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 975         struct mlx5e_wqe_frag_info *wi;
 976         struct sk_buff *skb;
 977         u32 cqe_bcnt;
 978         u16 ci;
 979
 980         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 981         wi       = get_frag(rq, ci);
 982         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
 983
 984         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 985         if (!skb) {
 986                 /* probably for XDP */
 987                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
 988                         /* do not return page to cache,
 989                          * it will be returned on XDP_TX completion.
 990                          */
 991                         goto wq_cyc_pop;
 992                 }
 993                 goto free_wqe;
 994         }
 995
 996         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 997         napi_gro_receive(rq->cq.napi, skb);
 998
 999 free_wqe:
1000         mlx5e_free_rx_wqe(rq, wi, true);
1001 wq_cyc_pop:
1002         mlx5_wq_cyc_pop(wq);
1003 }
1004
1005 #ifdef CONFIG_MLX5_ESWITCH
1006 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1007 {
1008         struct net_device *netdev = rq->netdev;
1009         struct mlx5e_priv *priv = netdev_priv(netdev);
1010         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1011         struct mlx5_eswitch_rep *rep = rpriv->rep;
1012         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1013         struct mlx5e_wqe_frag_info *wi;
1014         struct sk_buff *skb;
1015         u32 cqe_bcnt;
1016         u16 ci;
1017
1018         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1019         wi       = get_frag(rq, ci);
1020         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1021
1022         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1023         if (!skb) {
1024                 /* probably for XDP */
1025                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1026                         /* do not return page to cache,
1027                          * it will be returned on XDP_TX completion.
1028                          */
1029                         goto wq_cyc_pop;
1030                 }
1031                 goto free_wqe;
1032         }
1033
1034         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1035
1036         if (rep->vlan && skb_vlan_tag_present(skb))
1037                 skb_vlan_pop(skb);
1038
1039         napi_gro_receive(rq->cq.napi, skb);
1040
1041 free_wqe:
1042         mlx5e_free_rx_wqe(rq, wi, true);
1043 wq_cyc_pop:
1044         mlx5_wq_cyc_pop(wq);
1045 }
1046 #endif
1047
1048 struct sk_buff *
1049 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1050                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1051 {
1052         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1053         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1054         u32 frag_offset    = head_offset + headlen;
1055         u32 byte_cnt       = cqe_bcnt - headlen;
1056         struct mlx5e_dma_info *head_di = di;
1057         struct sk_buff *skb;
1058
1059         skb = napi_alloc_skb(rq->cq.napi,
1060                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1061         if (unlikely(!skb)) {
1062                 rq->stats->buff_alloc_err++;
1063                 return NULL;
1064         }
1065
1066         prefetchw(skb->data);
1067
1068         if (unlikely(frag_offset >= PAGE_SIZE)) {
1069                 di++;
1070                 frag_offset -= PAGE_SIZE;
1071         }
1072
1073         while (byte_cnt) {
1074                 u32 pg_consumed_bytes =
1075                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1076                 unsigned int truesize =
1077                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1078
1079                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1080                                    pg_consumed_bytes, truesize);
1081                 byte_cnt -= pg_consumed_bytes;
1082                 frag_offset = 0;
1083                 di++;
1084         }
1085         /* copy header */
1086         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1087                                     head_offset, headlen);
1088         /* skb linear part was allocated with headlen and aligned to long */
1089         skb->tail += headlen;
1090         skb->len  += headlen;
1091
1092         return skb;
1093 }
1094
1095 struct sk_buff *
1096 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1097                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1098 {
1099         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1100         u16 rx_headroom = rq->buff.headroom;
1101         u32 cqe_bcnt32 = cqe_bcnt;
1102         struct sk_buff *skb;
1103         void *va, *data;
1104         u32 frag_size;
1105         bool consumed;
1106
1107         va             = page_address(di->page) + head_offset;
1108         data           = va + rx_headroom;
1109         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1110
1111         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1112                                       frag_size, DMA_FROM_DEVICE);
1113         prefetchw(va); /* xdp_frame data area */
1114         prefetch(data);
1115
1116         rcu_read_lock();
1117         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1118         rcu_read_unlock();
1119         if (consumed) {
1120                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1121                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1122                 return NULL; /* page/packet was consumed by XDP */
1123         }
1124
1125         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1126         if (unlikely(!skb))
1127                 return NULL;
1128
1129         /* queue up for recycling/reuse */
1130         page_ref_inc(di->page);
1131
1132         return skb;
1133 }
1134
1135 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1136 {
1137         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1138         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1139         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1140         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1141         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1142         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1143         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1144         struct mlx5e_rx_wqe_ll *wqe;
1145         struct mlx5_wq_ll *wq;
1146         struct sk_buff *skb;
1147         u16 cqe_bcnt;
1148
1149         wi->consumed_strides += cstrides;
1150
1151         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1152                 rq->stats->wqe_err++;
1153                 goto mpwrq_cqe_out;
1154         }
1155
1156         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1157                 struct mlx5e_rq_stats *stats = rq->stats;
1158
1159                 stats->mpwqe_filler_cqes++;
1160                 stats->mpwqe_filler_strides += cstrides;
1161                 goto mpwrq_cqe_out;
1162         }
1163
1164         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1165
1166         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1167                                            page_idx);
1168         if (!skb)
1169                 goto mpwrq_cqe_out;
1170
1171         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1172         napi_gro_receive(rq->cq.napi, skb);
1173
1174 mpwrq_cqe_out:
1175         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1176                 return;
1177
1178         wq  = &rq->mpwqe.wq;
1179         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1180         mlx5e_free_rx_mpwqe(rq, wi, true);
1181         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1182 }
1183
1184 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1185 {
1186         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1187         struct mlx5e_xdpsq *xdpsq;
1188         struct mlx5_cqe64 *cqe;
1189         int work_done = 0;
1190
1191         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1192                 return 0;
1193
1194         if (cq->decmprs_left)
1195                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1196
1197         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1198         if (!cqe)
1199                 return 0;
1200
1201         xdpsq = &rq->xdpsq;
1202
1203         do {
1204                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1205                         work_done +=
1206                                 mlx5e_decompress_cqes_start(rq, cq,
1207                                                             budget - work_done);
1208                         continue;
1209                 }
1210
1211                 mlx5_cqwq_pop(&cq->wq);
1212
1213                 rq->handle_rx_cqe(rq, cqe);
1214         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1215
1216         if (xdpsq->doorbell) {
1217                 mlx5e_xmit_xdp_doorbell(xdpsq);
1218                 xdpsq->doorbell = false;
1219         }
1220
1221         if (xdpsq->redirect_flush) {
1222                 xdp_do_flush_map();
1223                 xdpsq->redirect_flush = false;
1224         }
1225
1226         mlx5_cqwq_update_db_record(&cq->wq);
1227
1228         /* ensure cq space is freed before enabling more cqes */
1229         wmb();
1230
1231         return work_done;
1232 }
1233
1234 #ifdef CONFIG_MLX5_CORE_IPOIB
1235
1236 #define MLX5_IB_GRH_DGID_OFFSET 24
1237 #define MLX5_GID_SIZE           16
1238
1239 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1240                                          struct mlx5_cqe64 *cqe,
1241                                          u32 cqe_bcnt,
1242                                          struct sk_buff *skb)
1243 {
1244         struct hwtstamp_config *tstamp;
1245         struct mlx5e_rq_stats *stats;
1246         struct net_device *netdev;
1247         struct mlx5e_priv *priv;
1248         char *pseudo_header;
1249         u32 qpn;
1250         u8 *dgid;
1251         u8 g;
1252
1253         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1254         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1255
1256         /* No mapping present, cannot process SKB. This might happen if a child
1257          * interface is going down while having unprocessed CQEs on parent RQ
1258          */
1259         if (unlikely(!netdev)) {
1260                 /* TODO: add drop counters support */
1261                 skb->dev = NULL;
1262                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1263                 return;
1264         }
1265
1266         priv = mlx5i_epriv(netdev);
1267         tstamp = &priv->tstamp;
1268         stats = &priv->channel_stats[rq->ix].rq;
1269
1270         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1271         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1272         if ((!g) || dgid[0] != 0xff)
1273                 skb->pkt_type = PACKET_HOST;
1274         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1275                 skb->pkt_type = PACKET_BROADCAST;
1276         else
1277                 skb->pkt_type = PACKET_MULTICAST;
1278
1279         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1280          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1281          */
1282
1283         skb_pull(skb, MLX5_IB_GRH_BYTES);
1284
1285         skb->protocol = *((__be16 *)(skb->data));
1286
1287         skb->ip_summed = CHECKSUM_COMPLETE;
1288         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1289
1290         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1291                 skb_hwtstamps(skb)->hwtstamp =
1292                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1293
1294         skb_record_rx_queue(skb, rq->ix);
1295
1296         if (likely(netdev->features & NETIF_F_RXHASH))
1297                 mlx5e_skb_set_hash(cqe, skb);
1298
1299         /* 20 bytes of ipoib header and 4 for encap existing */
1300         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1301         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1302         skb_reset_mac_header(skb);
1303         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1304
1305         skb->dev = netdev;
1306
1307         stats->csum_complete++;
1308         stats->packets++;
1309         stats->bytes += cqe_bcnt;
1310 }
1311
1312 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1313 {
1314         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1315         struct mlx5e_wqe_frag_info *wi;
1316         struct sk_buff *skb;
1317         u32 cqe_bcnt;
1318         u16 ci;
1319
1320         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1321         wi       = get_frag(rq, ci);
1322         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1323
1324         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1325         if (!skb)
1326                 goto wq_free_wqe;
1327
1328         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1329         if (unlikely(!skb->dev)) {
1330                 dev_kfree_skb_any(skb);
1331                 goto wq_free_wqe;
1332         }
1333         napi_gro_receive(rq->cq.napi, skb);
1334
1335 wq_free_wqe:
1336         mlx5e_free_rx_wqe(rq, wi, true);
1337         mlx5_wq_cyc_pop(wq);
1338 }
1339
1340 #endif /* CONFIG_MLX5_CORE_IPOIB */
1341
1342 #ifdef CONFIG_MLX5_EN_IPSEC
1343
1344 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1345 {
1346         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1347         struct mlx5e_wqe_frag_info *wi;
1348         struct sk_buff *skb;
1349         u32 cqe_bcnt;
1350         u16 ci;
1351
1352         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1353         wi       = get_frag(rq, ci);
1354         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1355
1356         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1357         if (unlikely(!skb)) {
1358                 /* a DROP, save the page-reuse checks */
1359                 mlx5e_free_rx_wqe(rq, wi, true);
1360                 goto wq_cyc_pop;
1361         }
1362         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1363         if (unlikely(!skb)) {
1364                 mlx5e_free_rx_wqe(rq, wi, true);
1365                 goto wq_cyc_pop;
1366         }
1367
1368         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1369         napi_gro_receive(rq->cq.napi, skb);
1370
1371         mlx5e_free_rx_wqe(rq, wi, true);
1372 wq_cyc_pop:
1373         mlx5_wq_cyc_pop(wq);
1374 }
1375
1376 #endif /* CONFIG_MLX5_EN_IPSEC */