drivers/pwm/pwm-sun4i.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Allwinner sun4i Pulse Width Modulation Controller
   4  *
   5  * Copyright (C) 2014 Alexandre Belloni <[email protected]>
   6  *
   7  * Limitations:
   8  * - When outputing the source clock directly, the PWM logic will be bypassed
   9  *   and the currently running period is not guaranteed to be completed
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pwm.h>
  23 #include <linux/reset.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/time.h>
  27
  28 #define PWM_CTRL_REG            0x0
  29
  30 #define PWM_CH_PRD_BASE         0x4
  31 #define PWM_CH_PRD_OFFSET       0x4
  32 #define PWM_CH_PRD(ch)          (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
  33
  34 #define PWMCH_OFFSET            15
  35 #define PWM_PRESCAL_MASK        GENMASK(3, 0)
  36 #define PWM_PRESCAL_OFF         0
  37 #define PWM_EN                  BIT(4)
  38 #define PWM_ACT_STATE           BIT(5)
  39 #define PWM_CLK_GATING          BIT(6)
  40 #define PWM_MODE                BIT(7)
  41 #define PWM_PULSE               BIT(8)
  42 #define PWM_BYPASS              BIT(9)
  43
  44 #define PWM_RDY_BASE            28
  45 #define PWM_RDY_OFFSET          1
  46 #define PWM_RDY(ch)             BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
  47
  48 #define PWM_PRD(prd)            (((prd) - 1) << 16)
  49 #define PWM_PRD_MASK            GENMASK(15, 0)
  50
  51 #define PWM_DTY_MASK            GENMASK(15, 0)
  52
  53 #define PWM_REG_PRD(reg)        ((((reg) >> 16) & PWM_PRD_MASK) + 1)
  54 #define PWM_REG_DTY(reg)        ((reg) & PWM_DTY_MASK)
  55 #define PWM_REG_PRESCAL(reg, chan)      (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
  56
  57 #define BIT_CH(bit, chan)       ((bit) << ((chan) * PWMCH_OFFSET))
  58
  59 static const u32 prescaler_table[] = {
  60         120,
  61         180,
  62         240,
  63         360,
  64         480,
  65         0,
  66         0,
  67         0,
  68         12000,
  69         24000,
  70         36000,
  71         48000,
  72         72000,
  73         0,
  74         0,
  75         0, /* Actually 1 but tested separately */
  76 };
  77
  78 struct sun4i_pwm_data {
  79         bool has_prescaler_bypass;
  80         bool has_direct_mod_clk_output;
  81         unsigned int npwm;
  82 };
  83
  84 struct sun4i_pwm_chip {
  85         struct pwm_chip chip;
  86         struct clk *bus_clk;
  87         struct clk *clk;
  88         struct reset_control *rst;
  89         void __iomem *base;
  90         spinlock_t ctrl_lock;
  91         const struct sun4i_pwm_data *data;
  92         unsigned long next_period[2];
  93         bool needs_delay[2];
  94 };
  95
  96 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
  97 {
  98         return container_of(chip, struct sun4i_pwm_chip, chip);
  99 }
 100
 101 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
 102                                   unsigned long offset)
 103 {
 104         return readl(chip->base + offset);
 105 }
 106
 107 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
 108                                     u32 val, unsigned long offset)
 109 {
 110         writel(val, chip->base + offset);
 111 }
 112
 113 static void sun4i_pwm_get_state(struct pwm_chip *chip,
 114                                 struct pwm_device *pwm,
 115                                 struct pwm_state *state)
 116 {
 117         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 118         u64 clk_rate, tmp;
 119         u32 val;
 120         unsigned int prescaler;
 121
 122         clk_rate = clk_get_rate(sun4i_pwm->clk);
 123
 124         val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 125
 126         /*
 127          * PWM chapter in H6 manual has a diagram which explains that if bypass
 128          * bit is set, no other setting has any meaning. Even more, experiment
 129          * proved that also enable bit is ignored in this case.
 130          */
 131         if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
 132             sun4i_pwm->data->has_direct_mod_clk_output) {
 133                 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
 134                 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
 135                 state->polarity = PWM_POLARITY_NORMAL;
 136                 state->enabled = true;
 137                 return;
 138         }
 139
 140         if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
 141             sun4i_pwm->data->has_prescaler_bypass)
 142                 prescaler = 1;
 143         else
 144                 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
 145
 146         if (prescaler == 0)
 147                 return;
 148
 149         if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
 150                 state->polarity = PWM_POLARITY_NORMAL;
 151         else
 152                 state->polarity = PWM_POLARITY_INVERSED;
 153
 154         if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
 155             BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
 156                 state->enabled = true;
 157         else
 158                 state->enabled = false;
 159
 160         val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
 161
 162         tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
 163         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 164
 165         tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
 166         state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
 167 }
 168
 169 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
 170                                const struct pwm_state *state,
 171                                u32 *dty, u32 *prd, unsigned int *prsclr,
 172                                bool *bypass)
 173 {
 174         u64 clk_rate, div = 0;
 175         unsigned int prescaler = 0;
 176
 177         clk_rate = clk_get_rate(sun4i_pwm->clk);
 178
 179         *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
 180                   state->enabled &&
 181                   (state->period * clk_rate >= NSEC_PER_SEC) &&
 182                   (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
 183                   (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
 184
 185         /* Skip calculation of other parameters if we bypass them */
 186         if (*bypass)
 187                 return 0;
 188
 189         if (sun4i_pwm->data->has_prescaler_bypass) {
 190                 /* First, test without any prescaler when available */
 191                 prescaler = PWM_PRESCAL_MASK;
 192                 /*
 193                  * When not using any prescaler, the clock period in nanoseconds
 194                  * is not an integer so round it half up instead of
 195                  * truncating to get less surprising values.
 196                  */
 197                 div = clk_rate * state->period + NSEC_PER_SEC / 2;
 198                 do_div(div, NSEC_PER_SEC);
 199                 if (div - 1 > PWM_PRD_MASK)
 200                         prescaler = 0;
 201         }
 202
 203         if (prescaler == 0) {
 204                 /* Go up from the first divider */
 205                 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
 206                         unsigned int pval = prescaler_table[prescaler];
 207
 208                         if (!pval)
 209                                 continue;
 210
 211                         div = clk_rate;
 212                         do_div(div, pval);
 213                         div = div * state->period;
 214                         do_div(div, NSEC_PER_SEC);
 215                         if (div - 1 <= PWM_PRD_MASK)
 216                                 break;
 217                 }
 218
 219                 if (div - 1 > PWM_PRD_MASK)
 220                         return -EINVAL;
 221         }
 222
 223         *prd = div;
 224         div *= state->duty_cycle;
 225         do_div(div, state->period);
 226         *dty = div;
 227         *prsclr = prescaler;
 228
 229         return 0;
 230 }
 231
 232 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 233                            const struct pwm_state *state)
 234 {
 235         struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
 236         struct pwm_state cstate;
 237         u32 ctrl, duty = 0, period = 0, val;
 238         int ret;
 239         unsigned int delay_us, prescaler = 0;
 240         unsigned long now;
 241         bool bypass;
 242
 243         pwm_get_state(pwm, &cstate);
 244
 245         if (!cstate.enabled) {
 246                 ret = clk_prepare_enable(sun4i_pwm->clk);
 247                 if (ret) {
 248                         dev_err(chip->dev, "failed to enable PWM clock\n");
 249                         return ret;
 250                 }
 251         }
 252
 253         ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
 254                                   &bypass);
 255         if (ret) {
 256                 dev_err(chip->dev, "period exceeds the maximum value\n");
 257                 if (!cstate.enabled)
 258                         clk_disable_unprepare(sun4i_pwm->clk);
 259                 return ret;
 260         }
 261
 262         spin_lock(&sun4i_pwm->ctrl_lock);
 263         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 264
 265         if (sun4i_pwm->data->has_direct_mod_clk_output) {
 266                 if (bypass) {
 267                         ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
 268                         /* We can skip other parameter */
 269                         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 270                         spin_unlock(&sun4i_pwm->ctrl_lock);
 271                         return 0;
 272                 }
 273
 274                 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
 275         }
 276
 277         if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
 278                 /* Prescaler changed, the clock has to be gated */
 279                 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 280                 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 281
 282                 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
 283                 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
 284         }
 285
 286         val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
 287         sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
 288         sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
 289                 usecs_to_jiffies(cstate.period / 1000 + 1);
 290         sun4i_pwm->needs_delay[pwm->hwpwm] = true;
 291
 292         if (state->polarity != PWM_POLARITY_NORMAL)
 293                 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 294         else
 295                 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
 296
 297         ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 298
 299         if (state->enabled) {
 300                 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
 301         } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 302                 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 303                 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 304         }
 305
 306         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 307
 308         spin_unlock(&sun4i_pwm->ctrl_lock);
 309
 310         if (state->enabled)
 311                 return 0;
 312
 313         if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
 314                 clk_disable_unprepare(sun4i_pwm->clk);
 315                 return 0;
 316         }
 317
 318         /* We need a full period to elapse before disabling the channel. */
 319         now = jiffies;
 320         if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
 321             time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
 322                 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
 323                                            now);
 324                 if ((delay_us / 500) > MAX_UDELAY_MS)
 325                         msleep(delay_us / 1000 + 1);
 326                 else
 327                         usleep_range(delay_us, delay_us * 2);
 328         }
 329         sun4i_pwm->needs_delay[pwm->hwpwm] = false;
 330
 331         spin_lock(&sun4i_pwm->ctrl_lock);
 332         ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
 333         ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
 334         ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
 335         sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
 336         spin_unlock(&sun4i_pwm->ctrl_lock);
 337
 338         clk_disable_unprepare(sun4i_pwm->clk);
 339
 340         return 0;
 341 }
 342
 343 static const struct pwm_ops sun4i_pwm_ops = {
 344         .apply = sun4i_pwm_apply,
 345         .get_state = sun4i_pwm_get_state,
 346         .owner = THIS_MODULE,
 347 };
 348
 349 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
 350         .has_prescaler_bypass = false,
 351         .npwm = 2,
 352 };
 353
 354 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
 355         .has_prescaler_bypass = true,
 356         .npwm = 2,
 357 };
 358
 359 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
 360         .has_prescaler_bypass = true,
 361         .npwm = 1,
 362 };
 363
 364 static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
 365         .has_prescaler_bypass = true,
 366         .has_direct_mod_clk_output = true,
 367         .npwm = 2,
 368 };
 369
 370 static const struct of_device_id sun4i_pwm_dt_ids[] = {
 371         {
 372                 .compatible = "allwinner,sun4i-a10-pwm",
 373                 .data = &sun4i_pwm_dual_nobypass,
 374         }, {
 375                 .compatible = "allwinner,sun5i-a10s-pwm",
 376                 .data = &sun4i_pwm_dual_bypass,
 377         }, {
 378                 .compatible = "allwinner,sun5i-a13-pwm",
 379                 .data = &sun4i_pwm_single_bypass,
 380         }, {
 381                 .compatible = "allwinner,sun7i-a20-pwm",
 382                 .data = &sun4i_pwm_dual_bypass,
 383         }, {
 384                 .compatible = "allwinner,sun8i-h3-pwm",
 385                 .data = &sun4i_pwm_single_bypass,
 386         }, {
 387                 .compatible = "allwinner,sun50i-h6-pwm",
 388                 .data = &sun50i_h6_pwm_data,
 389         }, {
 390                 /* sentinel */
 391         },
 392 };
 393 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
 394
 395 static int sun4i_pwm_probe(struct platform_device *pdev)
 396 {
 397         struct sun4i_pwm_chip *pwm;
 398         struct resource *res;
 399         int ret;
 400
 401         pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 402         if (!pwm)
 403                 return -ENOMEM;
 404
 405         pwm->data = of_device_get_match_data(&pdev->dev);
 406         if (!pwm->data)
 407                 return -ENODEV;
 408
 409         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 410         pwm->base = devm_ioremap_resource(&pdev->dev, res);
 411         if (IS_ERR(pwm->base))
 412                 return PTR_ERR(pwm->base);
 413
 414         /*
 415          * All hardware variants need a source clock that is divided and
 416          * then feeds the counter that defines the output wave form. In the
 417          * device tree this clock is either unnamed or called "mod".
 418          * Some variants (e.g. H6) need another clock to access the
 419          * hardware registers; this is called "bus".
 420          * So we request "mod" first (and ignore the corner case that a
 421          * parent provides a "mod" clock while the right one would be the
 422          * unnamed one of the PWM device) and if this is not found we fall
 423          * back to the first clock of the PWM.
 424          */
 425         pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
 426         if (IS_ERR(pwm->clk)) {
 427                 if (PTR_ERR(pwm->clk) != -EPROBE_DEFER)
 428                         dev_err(&pdev->dev, "get mod clock failed %pe\n",
 429                                 pwm->clk);
 430                 return PTR_ERR(pwm->clk);
 431         }
 432
 433         if (!pwm->clk) {
 434                 pwm->clk = devm_clk_get(&pdev->dev, NULL);
 435                 if (IS_ERR(pwm->clk)) {
 436                         if (PTR_ERR(pwm->clk) != -EPROBE_DEFER)
 437                                 dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
 438                                         pwm->clk);
 439                         return PTR_ERR(pwm->clk);
 440                 }
 441         }
 442
 443         pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
 444         if (IS_ERR(pwm->bus_clk)) {
 445                 if (PTR_ERR(pwm->bus_clk) != -EPROBE_DEFER)
 446                         dev_err(&pdev->dev, "get bus clock failed %pe\n",
 447                                 pwm->bus_clk);
 448                 return PTR_ERR(pwm->bus_clk);
 449         }
 450
 451         pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 452         if (IS_ERR(pwm->rst)) {
 453                 if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
 454                         dev_err(&pdev->dev, "get reset failed %pe\n",
 455                                 pwm->rst);
 456                 return PTR_ERR(pwm->rst);
 457         }
 458
 459         /* Deassert reset */
 460         ret = reset_control_deassert(pwm->rst);
 461         if (ret) {
 462                 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
 463                         ERR_PTR(ret));
 464                 return ret;
 465         }
 466
 467         /*
 468          * We're keeping the bus clock on for the sake of simplicity.
 469          * Actually it only needs to be on for hardware register accesses.
 470          */
 471         ret = clk_prepare_enable(pwm->bus_clk);
 472         if (ret) {
 473                 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
 474                         ERR_PTR(ret));
 475                 goto err_bus;
 476         }
 477
 478         pwm->chip.dev = &pdev->dev;
 479         pwm->chip.ops = &sun4i_pwm_ops;
 480         pwm->chip.base = -1;
 481         pwm->chip.npwm = pwm->data->npwm;
 482         pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 483         pwm->chip.of_pwm_n_cells = 3;
 484
 485         spin_lock_init(&pwm->ctrl_lock);
 486
 487         ret = pwmchip_add(&pwm->chip);
 488         if (ret < 0) {
 489                 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 490                 goto err_pwm_add;
 491         }
 492
 493         platform_set_drvdata(pdev, pwm);
 494
 495         return 0;
 496
 497 err_pwm_add:
 498         clk_disable_unprepare(pwm->bus_clk);
 499 err_bus:
 500         reset_control_assert(pwm->rst);
 501
 502         return ret;
 503 }
 504
 505 static int sun4i_pwm_remove(struct platform_device *pdev)
 506 {
 507         struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
 508         int ret;
 509
 510         ret = pwmchip_remove(&pwm->chip);
 511         if (ret)
 512                 return ret;
 513
 514         clk_disable_unprepare(pwm->bus_clk);
 515         reset_control_assert(pwm->rst);
 516
 517         return 0;
 518 }
 519
 520 static struct platform_driver sun4i_pwm_driver = {
 521         .driver = {
 522                 .name = "sun4i-pwm",
 523                 .of_match_table = sun4i_pwm_dt_ids,
 524         },
 525         .probe = sun4i_pwm_probe,
 526         .remove = sun4i_pwm_remove,
 527 };
 528 module_platform_driver(sun4i_pwm_driver);
 529
 530 MODULE_ALIAS("platform:sun4i-pwm");
 531 MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
 532 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
 533 MODULE_LICENSE("GPL v2");