arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <[email protected]>
  11  *   Avi Kivity   <[email protected]>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         u32 ldr_mode;
 149         struct page *avic_logical_id_table_page;
 150         struct page *avic_physical_id_table_page;
 151         struct hlist_node hnode;
 152
 153         struct kvm_sev_info sev_info;
 154 };
 155
 156 struct kvm_vcpu;
 157
 158 struct nested_state {
 159         struct vmcb *hsave;
 160         u64 hsave_msr;
 161         u64 vm_cr_msr;
 162         u64 vmcb;
 163
 164         /* These are the merged vectors */
 165         u32 *msrpm;
 166
 167         /* gpa pointers to the real vectors */
 168         u64 vmcb_msrpm;
 169         u64 vmcb_iopm;
 170
 171         /* A VMEXIT is required but not yet emulated */
 172         bool exit_required;
 173
 174         /* cache for intercepts of the guest */
 175         u32 intercept_cr;
 176         u32 intercept_dr;
 177         u32 intercept_exceptions;
 178         u64 intercept;
 179
 180         /* Nested Paging related state */
 181         u64 nested_cr3;
 182 };
 183
 184 #define MSRPM_OFFSETS   16
 185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 186
 187 /*
 188  * Set osvw_len to higher value when updated Revision Guides
 189  * are published and we know what the new status bits are
 190  */
 191 static uint64_t osvw_len = 4, osvw_status;
 192
 193 struct vcpu_svm {
 194         struct kvm_vcpu vcpu;
 195         struct vmcb *vmcb;
 196         unsigned long vmcb_pa;
 197         struct svm_cpu_data *svm_data;
 198         uint64_t asid_generation;
 199         uint64_t sysenter_esp;
 200         uint64_t sysenter_eip;
 201         uint64_t tsc_aux;
 202
 203         u64 msr_decfg;
 204
 205         u64 next_rip;
 206
 207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 208         struct {
 209                 u16 fs;
 210                 u16 gs;
 211                 u16 ldt;
 212                 u64 gs_base;
 213         } host;
 214
 215         u64 spec_ctrl;
 216         /*
 217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 218          * translated into the appropriate L2_CFG bits on the host to
 219          * perform speculative control.
 220          */
 221         u64 virt_spec_ctrl;
 222
 223         u32 *msrpm;
 224
 225         ulong nmi_iret_rip;
 226
 227         struct nested_state nested;
 228
 229         bool nmi_singlestep;
 230         u64 nmi_singlestep_guest_rflags;
 231
 232         unsigned int3_injected;
 233         unsigned long int3_rip;
 234
 235         /* cached guest cpuid flags for faster access */
 236         bool nrips_enabled      : 1;
 237
 238         u32 ldr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444 #ifdef CONFIG_KVM_AMD_SEV
 445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 446
 447         return sev->active;
 448 #else
 449         return false;
 450 #endif
 451 }
 452
 453 static inline int sev_get_asid(struct kvm *kvm)
 454 {
 455         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 456
 457         return sev->asid;
 458 }
 459
 460 static inline void mark_all_dirty(struct vmcb *vmcb)
 461 {
 462         vmcb->control.clean = 0;
 463 }
 464
 465 static inline void mark_all_clean(struct vmcb *vmcb)
 466 {
 467         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 468                                & ~VMCB_ALWAYS_DIRTY_MASK;
 469 }
 470
 471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 472 {
 473         vmcb->control.clean &= ~(1 << bit);
 474 }
 475
 476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 477 {
 478         return container_of(vcpu, struct vcpu_svm, vcpu);
 479 }
 480
 481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 482 {
 483         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 484         mark_dirty(svm->vmcb, VMCB_AVIC);
 485 }
 486
 487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 488 {
 489         struct vcpu_svm *svm = to_svm(vcpu);
 490         u64 *entry = svm->avic_physical_id_cache;
 491
 492         if (!entry)
 493                 return false;
 494
 495         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 496 }
 497
 498 static void recalc_intercepts(struct vcpu_svm *svm)
 499 {
 500         struct vmcb_control_area *c, *h;
 501         struct nested_state *g;
 502
 503         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 504
 505         if (!is_guest_mode(&svm->vcpu))
 506                 return;
 507
 508         c = &svm->vmcb->control;
 509         h = &svm->nested.hsave->control;
 510         g = &svm->nested;
 511
 512         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 513         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 514         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 515         c->intercept = h->intercept | g->intercept;
 516 }
 517
 518 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 519 {
 520         if (is_guest_mode(&svm->vcpu))
 521                 return svm->nested.hsave;
 522         else
 523                 return svm->vmcb;
 524 }
 525
 526 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 527 {
 528         struct vmcb *vmcb = get_host_vmcb(svm);
 529
 530         vmcb->control.intercept_cr |= (1U << bit);
 531
 532         recalc_intercepts(svm);
 533 }
 534
 535 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 536 {
 537         struct vmcb *vmcb = get_host_vmcb(svm);
 538
 539         vmcb->control.intercept_cr &= ~(1U << bit);
 540
 541         recalc_intercepts(svm);
 542 }
 543
 544 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 545 {
 546         struct vmcb *vmcb = get_host_vmcb(svm);
 547
 548         return vmcb->control.intercept_cr & (1U << bit);
 549 }
 550
 551 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 552 {
 553         struct vmcb *vmcb = get_host_vmcb(svm);
 554
 555         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 556                 | (1 << INTERCEPT_DR1_READ)
 557                 | (1 << INTERCEPT_DR2_READ)
 558                 | (1 << INTERCEPT_DR3_READ)
 559                 | (1 << INTERCEPT_DR4_READ)
 560                 | (1 << INTERCEPT_DR5_READ)
 561                 | (1 << INTERCEPT_DR6_READ)
 562                 | (1 << INTERCEPT_DR7_READ)
 563                 | (1 << INTERCEPT_DR0_WRITE)
 564                 | (1 << INTERCEPT_DR1_WRITE)
 565                 | (1 << INTERCEPT_DR2_WRITE)
 566                 | (1 << INTERCEPT_DR3_WRITE)
 567                 | (1 << INTERCEPT_DR4_WRITE)
 568                 | (1 << INTERCEPT_DR5_WRITE)
 569                 | (1 << INTERCEPT_DR6_WRITE)
 570                 | (1 << INTERCEPT_DR7_WRITE);
 571
 572         recalc_intercepts(svm);
 573 }
 574
 575 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 576 {
 577         struct vmcb *vmcb = get_host_vmcb(svm);
 578
 579         vmcb->control.intercept_dr = 0;
 580
 581         recalc_intercepts(svm);
 582 }
 583
 584 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 585 {
 586         struct vmcb *vmcb = get_host_vmcb(svm);
 587
 588         vmcb->control.intercept_exceptions |= (1U << bit);
 589
 590         recalc_intercepts(svm);
 591 }
 592
 593 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 594 {
 595         struct vmcb *vmcb = get_host_vmcb(svm);
 596
 597         vmcb->control.intercept_exceptions &= ~(1U << bit);
 598
 599         recalc_intercepts(svm);
 600 }
 601
 602 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 603 {
 604         struct vmcb *vmcb = get_host_vmcb(svm);
 605
 606         vmcb->control.intercept |= (1ULL << bit);
 607
 608         recalc_intercepts(svm);
 609 }
 610
 611 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 612 {
 613         struct vmcb *vmcb = get_host_vmcb(svm);
 614
 615         vmcb->control.intercept &= ~(1ULL << bit);
 616
 617         recalc_intercepts(svm);
 618 }
 619
 620 static inline bool vgif_enabled(struct vcpu_svm *svm)
 621 {
 622         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 623 }
 624
 625 static inline void enable_gif(struct vcpu_svm *svm)
 626 {
 627         if (vgif_enabled(svm))
 628                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 629         else
 630                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 631 }
 632
 633 static inline void disable_gif(struct vcpu_svm *svm)
 634 {
 635         if (vgif_enabled(svm))
 636                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 637         else
 638                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 639 }
 640
 641 static inline bool gif_set(struct vcpu_svm *svm)
 642 {
 643         if (vgif_enabled(svm))
 644                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 645         else
 646                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 647 }
 648
 649 static unsigned long iopm_base;
 650
 651 struct kvm_ldttss_desc {
 652         u16 limit0;
 653         u16 base0;
 654         unsigned base1:8, type:5, dpl:2, p:1;
 655         unsigned limit1:4, zero0:3, g:1, base2:8;
 656         u32 base3;
 657         u32 zero1;
 658 } __attribute__((packed));
 659
 660 struct svm_cpu_data {
 661         int cpu;
 662
 663         u64 asid_generation;
 664         u32 max_asid;
 665         u32 next_asid;
 666         u32 min_asid;
 667         struct kvm_ldttss_desc *tss_desc;
 668
 669         struct page *save_area;
 670         struct vmcb *current_vmcb;
 671
 672         /* index = sev_asid, value = vmcb pointer */
 673         struct vmcb **sev_vmcbs;
 674 };
 675
 676 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 677
 678 struct svm_init_data {
 679         int cpu;
 680         int r;
 681 };
 682
 683 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 684
 685 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 686 #define MSRS_RANGE_SIZE 2048
 687 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 688
 689 static u32 svm_msrpm_offset(u32 msr)
 690 {
 691         u32 offset;
 692         int i;
 693
 694         for (i = 0; i < NUM_MSR_MAPS; i++) {
 695                 if (msr < msrpm_ranges[i] ||
 696                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 697                         continue;
 698
 699                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 700                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 701
 702                 /* Now we have the u8 offset - but need the u32 offset */
 703                 return offset / 4;
 704         }
 705
 706         /* MSR not in any range */
 707         return MSR_INVALID;
 708 }
 709
 710 #define MAX_INST_SIZE 15
 711
 712 static inline void clgi(void)
 713 {
 714         asm volatile (__ex(SVM_CLGI));
 715 }
 716
 717 static inline void stgi(void)
 718 {
 719         asm volatile (__ex(SVM_STGI));
 720 }
 721
 722 static inline void invlpga(unsigned long addr, u32 asid)
 723 {
 724         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 725 }
 726
 727 static int get_npt_level(struct kvm_vcpu *vcpu)
 728 {
 729 #ifdef CONFIG_X86_64
 730         return PT64_ROOT_4LEVEL;
 731 #else
 732         return PT32E_ROOT_LEVEL;
 733 #endif
 734 }
 735
 736 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 737 {
 738         vcpu->arch.efer = efer;
 739         if (!npt_enabled && !(efer & EFER_LMA))
 740                 efer &= ~EFER_LME;
 741
 742         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 743         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 744 }
 745
 746 static int is_external_interrupt(u32 info)
 747 {
 748         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 749         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 750 }
 751
 752 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 753 {
 754         struct vcpu_svm *svm = to_svm(vcpu);
 755         u32 ret = 0;
 756
 757         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 758                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 759         return ret;
 760 }
 761
 762 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 763 {
 764         struct vcpu_svm *svm = to_svm(vcpu);
 765
 766         if (mask == 0)
 767                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 768         else
 769                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 770
 771 }
 772
 773 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 774 {
 775         struct vcpu_svm *svm = to_svm(vcpu);
 776
 777         if (svm->vmcb->control.next_rip != 0) {
 778                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 779                 svm->next_rip = svm->vmcb->control.next_rip;
 780         }
 781
 782         if (!svm->next_rip) {
 783                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 784                                 EMULATE_DONE)
 785                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 786                 return;
 787         }
 788         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 789                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 790                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 791
 792         kvm_rip_write(vcpu, svm->next_rip);
 793         svm_set_interrupt_shadow(vcpu, 0);
 794 }
 795
 796 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 797 {
 798         struct vcpu_svm *svm = to_svm(vcpu);
 799         unsigned nr = vcpu->arch.exception.nr;
 800         bool has_error_code = vcpu->arch.exception.has_error_code;
 801         bool reinject = vcpu->arch.exception.injected;
 802         u32 error_code = vcpu->arch.exception.error_code;
 803
 804         /*
 805          * If we are within a nested VM we'd better #VMEXIT and let the guest
 806          * handle the exception
 807          */
 808         if (!reinject &&
 809             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 810                 return;
 811
 812         kvm_deliver_exception_payload(&svm->vcpu);
 813
 814         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 815                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 816
 817                 /*
 818                  * For guest debugging where we have to reinject #BP if some
 819                  * INT3 is guest-owned:
 820                  * Emulate nRIP by moving RIP forward. Will fail if injection
 821                  * raises a fault that is not intercepted. Still better than
 822                  * failing in all cases.
 823                  */
 824                 skip_emulated_instruction(&svm->vcpu);
 825                 rip = kvm_rip_read(&svm->vcpu);
 826                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 827                 svm->int3_injected = rip - old_rip;
 828         }
 829
 830         svm->vmcb->control.event_inj = nr
 831                 | SVM_EVTINJ_VALID
 832                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 833                 | SVM_EVTINJ_TYPE_EXEPT;
 834         svm->vmcb->control.event_inj_err = error_code;
 835 }
 836
 837 static void svm_init_erratum_383(void)
 838 {
 839         u32 low, high;
 840         int err;
 841         u64 val;
 842
 843         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 844                 return;
 845
 846         /* Use _safe variants to not break nested virtualization */
 847         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 848         if (err)
 849                 return;
 850
 851         val |= (1ULL << 47);
 852
 853         low  = lower_32_bits(val);
 854         high = upper_32_bits(val);
 855
 856         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 857
 858         erratum_383_found = true;
 859 }
 860
 861 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 862 {
 863         /*
 864          * Guests should see errata 400 and 415 as fixed (assuming that
 865          * HLT and IO instructions are intercepted).
 866          */
 867         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 868         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 869
 870         /*
 871          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 872          * all osvw.status bits inside that length, including bit 0 (which is
 873          * reserved for erratum 298), are valid. However, if host processor's
 874          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 875          * be conservative here and therefore we tell the guest that erratum 298
 876          * is present (because we really don't know).
 877          */
 878         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 879                 vcpu->arch.osvw.status |= 1;
 880 }
 881
 882 static int has_svm(void)
 883 {
 884         const char *msg;
 885
 886         if (!cpu_has_svm(&msg)) {
 887                 printk(KERN_INFO "has_svm: %s\n", msg);
 888                 return 0;
 889         }
 890
 891         return 1;
 892 }
 893
 894 static void svm_hardware_disable(void)
 895 {
 896         /* Make sure we clean up behind us */
 897         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 898                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 899
 900         cpu_svm_disable();
 901
 902         amd_pmu_disable_virt();
 903 }
 904
 905 static int svm_hardware_enable(void)
 906 {
 907
 908         struct svm_cpu_data *sd;
 909         uint64_t efer;
 910         struct desc_struct *gdt;
 911         int me = raw_smp_processor_id();
 912
 913         rdmsrl(MSR_EFER, efer);
 914         if (efer & EFER_SVME)
 915                 return -EBUSY;
 916
 917         if (!has_svm()) {
 918                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 919                 return -EINVAL;
 920         }
 921         sd = per_cpu(svm_data, me);
 922         if (!sd) {
 923                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 924                 return -EINVAL;
 925         }
 926
 927         sd->asid_generation = 1;
 928         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 929         sd->next_asid = sd->max_asid + 1;
 930         sd->min_asid = max_sev_asid + 1;
 931
 932         gdt = get_current_gdt_rw();
 933         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 934
 935         wrmsrl(MSR_EFER, efer | EFER_SVME);
 936
 937         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 938
 939         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 940                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 941                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 942         }
 943
 944
 945         /*
 946          * Get OSVW bits.
 947          *
 948          * Note that it is possible to have a system with mixed processor
 949          * revisions and therefore different OSVW bits. If bits are not the same
 950          * on different processors then choose the worst case (i.e. if erratum
 951          * is present on one processor and not on another then assume that the
 952          * erratum is present everywhere).
 953          */
 954         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 955                 uint64_t len, status = 0;
 956                 int err;
 957
 958                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 959                 if (!err)
 960                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 961                                                       &err);
 962
 963                 if (err)
 964                         osvw_status = osvw_len = 0;
 965                 else {
 966                         if (len < osvw_len)
 967                                 osvw_len = len;
 968                         osvw_status |= status;
 969                         osvw_status &= (1ULL << osvw_len) - 1;
 970                 }
 971         } else
 972                 osvw_status = osvw_len = 0;
 973
 974         svm_init_erratum_383();
 975
 976         amd_pmu_enable_virt();
 977
 978         return 0;
 979 }
 980
 981 static void svm_cpu_uninit(int cpu)
 982 {
 983         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 984
 985         if (!sd)
 986                 return;
 987
 988         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 989         kfree(sd->sev_vmcbs);
 990         __free_page(sd->save_area);
 991         kfree(sd);
 992 }
 993
 994 static int svm_cpu_init(int cpu)
 995 {
 996         struct svm_cpu_data *sd;
 997         int r;
 998
 999         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
1000         if (!sd)
1001                 return -ENOMEM;
1002         sd->cpu = cpu;
1003         r = -ENOMEM;
1004         sd->save_area = alloc_page(GFP_KERNEL);
1005         if (!sd->save_area)
1006                 goto err_1;
1007
1008         if (svm_sev_enabled()) {
1009                 r = -ENOMEM;
1010                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1011                                               sizeof(void *),
1012                                               GFP_KERNEL);
1013                 if (!sd->sev_vmcbs)
1014                         goto err_1;
1015         }
1016
1017         per_cpu(svm_data, cpu) = sd;
1018
1019         return 0;
1020
1021 err_1:
1022         kfree(sd);
1023         return r;
1024
1025 }
1026
1027 static bool valid_msr_intercept(u32 index)
1028 {
1029         int i;
1030
1031         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1032                 if (direct_access_msrs[i].index == index)
1033                         return true;
1034
1035         return false;
1036 }
1037
1038 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1039 {
1040         u8 bit_write;
1041         unsigned long tmp;
1042         u32 offset;
1043         u32 *msrpm;
1044
1045         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1046                                       to_svm(vcpu)->msrpm;
1047
1048         offset    = svm_msrpm_offset(msr);
1049         bit_write = 2 * (msr & 0x0f) + 1;
1050         tmp       = msrpm[offset];
1051
1052         BUG_ON(offset == MSR_INVALID);
1053
1054         return !!test_bit(bit_write,  &tmp);
1055 }
1056
1057 static void set_msr_interception(u32 *msrpm, unsigned msr,
1058                                  int read, int write)
1059 {
1060         u8 bit_read, bit_write;
1061         unsigned long tmp;
1062         u32 offset;
1063
1064         /*
1065          * If this warning triggers extend the direct_access_msrs list at the
1066          * beginning of the file
1067          */
1068         WARN_ON(!valid_msr_intercept(msr));
1069
1070         offset    = svm_msrpm_offset(msr);
1071         bit_read  = 2 * (msr & 0x0f);
1072         bit_write = 2 * (msr & 0x0f) + 1;
1073         tmp       = msrpm[offset];
1074
1075         BUG_ON(offset == MSR_INVALID);
1076
1077         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1078         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1079
1080         msrpm[offset] = tmp;
1081 }
1082
1083 static void svm_vcpu_init_msrpm(u32 *msrpm)
1084 {
1085         int i;
1086
1087         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1088
1089         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1090                 if (!direct_access_msrs[i].always)
1091                         continue;
1092
1093                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1094         }
1095 }
1096
1097 static void add_msr_offset(u32 offset)
1098 {
1099         int i;
1100
1101         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1102
1103                 /* Offset already in list? */
1104                 if (msrpm_offsets[i] == offset)
1105                         return;
1106
1107                 /* Slot used by another offset? */
1108                 if (msrpm_offsets[i] != MSR_INVALID)
1109                         continue;
1110
1111                 /* Add offset to list */
1112                 msrpm_offsets[i] = offset;
1113
1114                 return;
1115         }
1116
1117         /*
1118          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1119          * increase MSRPM_OFFSETS in this case.
1120          */
1121         BUG();
1122 }
1123
1124 static void init_msrpm_offsets(void)
1125 {
1126         int i;
1127
1128         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1129
1130         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1131                 u32 offset;
1132
1133                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1134                 BUG_ON(offset == MSR_INVALID);
1135
1136                 add_msr_offset(offset);
1137         }
1138 }
1139
1140 static void svm_enable_lbrv(struct vcpu_svm *svm)
1141 {
1142         u32 *msrpm = svm->msrpm;
1143
1144         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1145         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1146         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1147         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1148         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1149 }
1150
1151 static void svm_disable_lbrv(struct vcpu_svm *svm)
1152 {
1153         u32 *msrpm = svm->msrpm;
1154
1155         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1156         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1157         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1158         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1159         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1160 }
1161
1162 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1163 {
1164         svm->nmi_singlestep = false;
1165
1166         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1167                 /* Clear our flags if they were not set by the guest */
1168                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1169                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1170                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1171                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1172         }
1173 }
1174
1175 /* Note:
1176  * This hash table is used to map VM_ID to a struct kvm_svm,
1177  * when handling AMD IOMMU GALOG notification to schedule in
1178  * a particular vCPU.
1179  */
1180 #define SVM_VM_DATA_HASH_BITS   8
1181 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1182 static u32 next_vm_id = 0;
1183 static bool next_vm_id_wrapped = 0;
1184 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1185
1186 /* Note:
1187  * This function is called from IOMMU driver to notify
1188  * SVM to schedule in a particular vCPU of a particular VM.
1189  */
1190 static int avic_ga_log_notifier(u32 ga_tag)
1191 {
1192         unsigned long flags;
1193         struct kvm_svm *kvm_svm;
1194         struct kvm_vcpu *vcpu = NULL;
1195         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1196         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1197
1198         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1199
1200         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1201         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1202                 if (kvm_svm->avic_vm_id != vm_id)
1203                         continue;
1204                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1205                 break;
1206         }
1207         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1208
1209         /* Note:
1210          * At this point, the IOMMU should have already set the pending
1211          * bit in the vAPIC backing page. So, we just need to schedule
1212          * in the vcpu.
1213          */
1214         if (vcpu)
1215                 kvm_vcpu_wake_up(vcpu);
1216
1217         return 0;
1218 }
1219
1220 static __init int sev_hardware_setup(void)
1221 {
1222         struct sev_user_data_status *status;
1223         int rc;
1224
1225         /* Maximum number of encrypted guests supported simultaneously */
1226         max_sev_asid = cpuid_ecx(0x8000001F);
1227
1228         if (!max_sev_asid)
1229                 return 1;
1230
1231         /* Minimum ASID value that should be used for SEV guest */
1232         min_sev_asid = cpuid_edx(0x8000001F);
1233
1234         /* Initialize SEV ASID bitmap */
1235         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1236         if (!sev_asid_bitmap)
1237                 return 1;
1238
1239         status = kmalloc(sizeof(*status), GFP_KERNEL);
1240         if (!status)
1241                 return 1;
1242
1243         /*
1244          * Check SEV platform status.
1245          *
1246          * PLATFORM_STATUS can be called in any state, if we failed to query
1247          * the PLATFORM status then either PSP firmware does not support SEV
1248          * feature or SEV firmware is dead.
1249          */
1250         rc = sev_platform_status(status, NULL);
1251         if (rc)
1252                 goto err;
1253
1254         pr_info("SEV supported\n");
1255
1256 err:
1257         kfree(status);
1258         return rc;
1259 }
1260
1261 static void grow_ple_window(struct kvm_vcpu *vcpu)
1262 {
1263         struct vcpu_svm *svm = to_svm(vcpu);
1264         struct vmcb_control_area *control = &svm->vmcb->control;
1265         int old = control->pause_filter_count;
1266
1267         control->pause_filter_count = __grow_ple_window(old,
1268                                                         pause_filter_count,
1269                                                         pause_filter_count_grow,
1270                                                         pause_filter_count_max);
1271
1272         if (control->pause_filter_count != old)
1273                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1274
1275         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1276                                   control->pause_filter_count, old);
1277 }
1278
1279 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1280 {
1281         struct vcpu_svm *svm = to_svm(vcpu);
1282         struct vmcb_control_area *control = &svm->vmcb->control;
1283         int old = control->pause_filter_count;
1284
1285         control->pause_filter_count =
1286                                 __shrink_ple_window(old,
1287                                                     pause_filter_count,
1288                                                     pause_filter_count_shrink,
1289                                                     pause_filter_count);
1290         if (control->pause_filter_count != old)
1291                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1292
1293         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1294                                     control->pause_filter_count, old);
1295 }
1296
1297 static __init int svm_hardware_setup(void)
1298 {
1299         int cpu;
1300         struct page *iopm_pages;
1301         void *iopm_va;
1302         int r;
1303
1304         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1305
1306         if (!iopm_pages)
1307                 return -ENOMEM;
1308
1309         iopm_va = page_address(iopm_pages);
1310         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1311         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1312
1313         init_msrpm_offsets();
1314
1315         if (boot_cpu_has(X86_FEATURE_NX))
1316                 kvm_enable_efer_bits(EFER_NX);
1317
1318         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1319                 kvm_enable_efer_bits(EFER_FFXSR);
1320
1321         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1322                 kvm_has_tsc_control = true;
1323                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1324                 kvm_tsc_scaling_ratio_frac_bits = 32;
1325         }
1326
1327         /* Check for pause filtering support */
1328         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1329                 pause_filter_count = 0;
1330                 pause_filter_thresh = 0;
1331         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1332                 pause_filter_thresh = 0;
1333         }
1334
1335         if (nested) {
1336                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1337                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1338         }
1339
1340         if (sev) {
1341                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1342                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1343                         r = sev_hardware_setup();
1344                         if (r)
1345                                 sev = false;
1346                 } else {
1347                         sev = false;
1348                 }
1349         }
1350
1351         for_each_possible_cpu(cpu) {
1352                 r = svm_cpu_init(cpu);
1353                 if (r)
1354                         goto err;
1355         }
1356
1357         if (!boot_cpu_has(X86_FEATURE_NPT))
1358                 npt_enabled = false;
1359
1360         if (npt_enabled && !npt) {
1361                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1362                 npt_enabled = false;
1363         }
1364
1365         if (npt_enabled) {
1366                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1367                 kvm_enable_tdp();
1368         } else
1369                 kvm_disable_tdp();
1370
1371         if (avic) {
1372                 if (!npt_enabled ||
1373                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1374                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1375                         avic = false;
1376                 } else {
1377                         pr_info("AVIC enabled\n");
1378
1379                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1380                 }
1381         }
1382
1383         if (vls) {
1384                 if (!npt_enabled ||
1385                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1386                     !IS_ENABLED(CONFIG_X86_64)) {
1387                         vls = false;
1388                 } else {
1389                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1390                 }
1391         }
1392
1393         if (vgif) {
1394                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1395                         vgif = false;
1396                 else
1397                         pr_info("Virtual GIF supported\n");
1398         }
1399
1400         return 0;
1401
1402 err:
1403         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1404         iopm_base = 0;
1405         return r;
1406 }
1407
1408 static __exit void svm_hardware_unsetup(void)
1409 {
1410         int cpu;
1411
1412         if (svm_sev_enabled())
1413                 bitmap_free(sev_asid_bitmap);
1414
1415         for_each_possible_cpu(cpu)
1416                 svm_cpu_uninit(cpu);
1417
1418         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1419         iopm_base = 0;
1420 }
1421
1422 static void init_seg(struct vmcb_seg *seg)
1423 {
1424         seg->selector = 0;
1425         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1426                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1427         seg->limit = 0xffff;
1428         seg->base = 0;
1429 }
1430
1431 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1432 {
1433         seg->selector = 0;
1434         seg->attrib = SVM_SELECTOR_P_MASK | type;
1435         seg->limit = 0xffff;
1436         seg->base = 0;
1437 }
1438
1439 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1440 {
1441         struct vcpu_svm *svm = to_svm(vcpu);
1442
1443         if (is_guest_mode(vcpu))
1444                 return svm->nested.hsave->control.tsc_offset;
1445
1446         return vcpu->arch.tsc_offset;
1447 }
1448
1449 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1450 {
1451         struct vcpu_svm *svm = to_svm(vcpu);
1452         u64 g_tsc_offset = 0;
1453
1454         if (is_guest_mode(vcpu)) {
1455                 /* Write L1's TSC offset.  */
1456                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1457                                svm->nested.hsave->control.tsc_offset;
1458                 svm->nested.hsave->control.tsc_offset = offset;
1459         } else
1460                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1461                                            svm->vmcb->control.tsc_offset,
1462                                            offset);
1463
1464         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1465
1466         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1467         return svm->vmcb->control.tsc_offset;
1468 }
1469
1470 static void avic_init_vmcb(struct vcpu_svm *svm)
1471 {
1472         struct vmcb *vmcb = svm->vmcb;
1473         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1474         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1475         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1476         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1477
1478         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1479         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1480         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1481         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1482         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1483 }
1484
1485 static void init_vmcb(struct vcpu_svm *svm)
1486 {
1487         struct vmcb_control_area *control = &svm->vmcb->control;
1488         struct vmcb_save_area *save = &svm->vmcb->save;
1489
1490         svm->vcpu.arch.hflags = 0;
1491
1492         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1493         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1494         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1495         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1496         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1497         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1498         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1499                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1500
1501         set_dr_intercepts(svm);
1502
1503         set_exception_intercept(svm, PF_VECTOR);
1504         set_exception_intercept(svm, UD_VECTOR);
1505         set_exception_intercept(svm, MC_VECTOR);
1506         set_exception_intercept(svm, AC_VECTOR);
1507         set_exception_intercept(svm, DB_VECTOR);
1508         /*
1509          * Guest access to VMware backdoor ports could legitimately
1510          * trigger #GP because of TSS I/O permission bitmap.
1511          * We intercept those #GP and allow access to them anyway
1512          * as VMware does.
1513          */
1514         if (enable_vmware_backdoor)
1515                 set_exception_intercept(svm, GP_VECTOR);
1516
1517         set_intercept(svm, INTERCEPT_INTR);
1518         set_intercept(svm, INTERCEPT_NMI);
1519         set_intercept(svm, INTERCEPT_SMI);
1520         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1521         set_intercept(svm, INTERCEPT_RDPMC);
1522         set_intercept(svm, INTERCEPT_CPUID);
1523         set_intercept(svm, INTERCEPT_INVD);
1524         set_intercept(svm, INTERCEPT_INVLPG);
1525         set_intercept(svm, INTERCEPT_INVLPGA);
1526         set_intercept(svm, INTERCEPT_IOIO_PROT);
1527         set_intercept(svm, INTERCEPT_MSR_PROT);
1528         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1529         set_intercept(svm, INTERCEPT_SHUTDOWN);
1530         set_intercept(svm, INTERCEPT_VMRUN);
1531         set_intercept(svm, INTERCEPT_VMMCALL);
1532         set_intercept(svm, INTERCEPT_VMLOAD);
1533         set_intercept(svm, INTERCEPT_VMSAVE);
1534         set_intercept(svm, INTERCEPT_STGI);
1535         set_intercept(svm, INTERCEPT_CLGI);
1536         set_intercept(svm, INTERCEPT_SKINIT);
1537         set_intercept(svm, INTERCEPT_WBINVD);
1538         set_intercept(svm, INTERCEPT_XSETBV);
1539         set_intercept(svm, INTERCEPT_RSM);
1540
1541         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1542                 set_intercept(svm, INTERCEPT_MONITOR);
1543                 set_intercept(svm, INTERCEPT_MWAIT);
1544         }
1545
1546         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1547                 set_intercept(svm, INTERCEPT_HLT);
1548
1549         control->iopm_base_pa = __sme_set(iopm_base);
1550         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1551         control->int_ctl = V_INTR_MASKING_MASK;
1552
1553         init_seg(&save->es);
1554         init_seg(&save->ss);
1555         init_seg(&save->ds);
1556         init_seg(&save->fs);
1557         init_seg(&save->gs);
1558
1559         save->cs.selector = 0xf000;
1560         save->cs.base = 0xffff0000;
1561         /* Executable/Readable Code Segment */
1562         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1563                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1564         save->cs.limit = 0xffff;
1565
1566         save->gdtr.limit = 0xffff;
1567         save->idtr.limit = 0xffff;
1568
1569         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1570         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1571
1572         svm_set_efer(&svm->vcpu, 0);
1573         save->dr6 = 0xffff0ff0;
1574         kvm_set_rflags(&svm->vcpu, 2);
1575         save->rip = 0x0000fff0;
1576         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1577
1578         /*
1579          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1580          * It also updates the guest-visible cr0 value.
1581          */
1582         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1583         kvm_mmu_reset_context(&svm->vcpu);
1584
1585         save->cr4 = X86_CR4_PAE;
1586         /* rdx = ?? */
1587
1588         if (npt_enabled) {
1589                 /* Setup VMCB for Nested Paging */
1590                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1591                 clr_intercept(svm, INTERCEPT_INVLPG);
1592                 clr_exception_intercept(svm, PF_VECTOR);
1593                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1594                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1595                 save->g_pat = svm->vcpu.arch.pat;
1596                 save->cr3 = 0;
1597                 save->cr4 = 0;
1598         }
1599         svm->asid_generation = 0;
1600
1601         svm->nested.vmcb = 0;
1602         svm->vcpu.arch.hflags = 0;
1603
1604         if (pause_filter_count) {
1605                 control->pause_filter_count = pause_filter_count;
1606                 if (pause_filter_thresh)
1607                         control->pause_filter_thresh = pause_filter_thresh;
1608                 set_intercept(svm, INTERCEPT_PAUSE);
1609         } else {
1610                 clr_intercept(svm, INTERCEPT_PAUSE);
1611         }
1612
1613         if (kvm_vcpu_apicv_active(&svm->vcpu))
1614                 avic_init_vmcb(svm);
1615
1616         /*
1617          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1618          * in VMCB and clear intercepts to avoid #VMEXIT.
1619          */
1620         if (vls) {
1621                 clr_intercept(svm, INTERCEPT_VMLOAD);
1622                 clr_intercept(svm, INTERCEPT_VMSAVE);
1623                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1624         }
1625
1626         if (vgif) {
1627                 clr_intercept(svm, INTERCEPT_STGI);
1628                 clr_intercept(svm, INTERCEPT_CLGI);
1629                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1630         }
1631
1632         if (sev_guest(svm->vcpu.kvm)) {
1633                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1634                 clr_exception_intercept(svm, UD_VECTOR);
1635         }
1636
1637         mark_all_dirty(svm->vmcb);
1638
1639         enable_gif(svm);
1640
1641 }
1642
1643 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1644                                        unsigned int index)
1645 {
1646         u64 *avic_physical_id_table;
1647         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1648
1649         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1650                 return NULL;
1651
1652         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1653
1654         return &avic_physical_id_table[index];
1655 }
1656
1657 /**
1658  * Note:
1659  * AVIC hardware walks the nested page table to check permissions,
1660  * but does not use the SPA address specified in the leaf page
1661  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1662  * field of the VMCB. Therefore, we set up the
1663  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1664  */
1665 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1666 {
1667         struct kvm *kvm = vcpu->kvm;
1668         int ret = 0;
1669
1670         mutex_lock(&kvm->slots_lock);
1671         if (kvm->arch.apic_access_page_done)
1672                 goto out;
1673
1674         ret = __x86_set_memory_region(kvm,
1675                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1676                                       APIC_DEFAULT_PHYS_BASE,
1677                                       PAGE_SIZE);
1678         if (ret)
1679                 goto out;
1680
1681         kvm->arch.apic_access_page_done = true;
1682 out:
1683         mutex_unlock(&kvm->slots_lock);
1684         return ret;
1685 }
1686
1687 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1688 {
1689         int ret;
1690         u64 *entry, new_entry;
1691         int id = vcpu->vcpu_id;
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693
1694         ret = avic_init_access_page(vcpu);
1695         if (ret)
1696                 return ret;
1697
1698         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1699                 return -EINVAL;
1700
1701         if (!svm->vcpu.arch.apic->regs)
1702                 return -EINVAL;
1703
1704         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1705
1706         /* Setting AVIC backing page address in the phy APIC ID table */
1707         entry = avic_get_physical_id_entry(vcpu, id);
1708         if (!entry)
1709                 return -EINVAL;
1710
1711         new_entry = READ_ONCE(*entry);
1712         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1713                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1714                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1715         WRITE_ONCE(*entry, new_entry);
1716
1717         svm->avic_physical_id_cache = entry;
1718
1719         return 0;
1720 }
1721
1722 static void __sev_asid_free(int asid)
1723 {
1724         struct svm_cpu_data *sd;
1725         int cpu, pos;
1726
1727         pos = asid - 1;
1728         clear_bit(pos, sev_asid_bitmap);
1729
1730         for_each_possible_cpu(cpu) {
1731                 sd = per_cpu(svm_data, cpu);
1732                 sd->sev_vmcbs[pos] = NULL;
1733         }
1734 }
1735
1736 static void sev_asid_free(struct kvm *kvm)
1737 {
1738         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1739
1740         __sev_asid_free(sev->asid);
1741 }
1742
1743 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1744 {
1745         struct sev_data_decommission *decommission;
1746         struct sev_data_deactivate *data;
1747
1748         if (!handle)
1749                 return;
1750
1751         data = kzalloc(sizeof(*data), GFP_KERNEL);
1752         if (!data)
1753                 return;
1754
1755         /* deactivate handle */
1756         data->handle = handle;
1757         sev_guest_deactivate(data, NULL);
1758
1759         wbinvd_on_all_cpus();
1760         sev_guest_df_flush(NULL);
1761         kfree(data);
1762
1763         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1764         if (!decommission)
1765                 return;
1766
1767         /* decommission handle */
1768         decommission->handle = handle;
1769         sev_guest_decommission(decommission, NULL);
1770
1771         kfree(decommission);
1772 }
1773
1774 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1775                                     unsigned long ulen, unsigned long *n,
1776                                     int write)
1777 {
1778         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1779         unsigned long npages, npinned, size;
1780         unsigned long locked, lock_limit;
1781         struct page **pages;
1782         unsigned long first, last;
1783
1784         if (ulen == 0 || uaddr + ulen < uaddr)
1785                 return NULL;
1786
1787         /* Calculate number of pages. */
1788         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1789         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1790         npages = (last - first + 1);
1791
1792         locked = sev->pages_locked + npages;
1793         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1794         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1795                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1796                 return NULL;
1797         }
1798
1799         /* Avoid using vmalloc for smaller buffers. */
1800         size = npages * sizeof(struct page *);
1801         if (size > PAGE_SIZE)
1802                 pages = vmalloc(size);
1803         else
1804                 pages = kmalloc(size, GFP_KERNEL);
1805
1806         if (!pages)
1807                 return NULL;
1808
1809         /* Pin the user virtual address. */
1810         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1811         if (npinned != npages) {
1812                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1813                 goto err;
1814         }
1815
1816         *n = npages;
1817         sev->pages_locked = locked;
1818
1819         return pages;
1820
1821 err:
1822         if (npinned > 0)
1823                 release_pages(pages, npinned);
1824
1825         kvfree(pages);
1826         return NULL;
1827 }
1828
1829 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1830                              unsigned long npages)
1831 {
1832         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1833
1834         release_pages(pages, npages);
1835         kvfree(pages);
1836         sev->pages_locked -= npages;
1837 }
1838
1839 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1840 {
1841         uint8_t *page_virtual;
1842         unsigned long i;
1843
1844         if (npages == 0 || pages == NULL)
1845                 return;
1846
1847         for (i = 0; i < npages; i++) {
1848                 page_virtual = kmap_atomic(pages[i]);
1849                 clflush_cache_range(page_virtual, PAGE_SIZE);
1850                 kunmap_atomic(page_virtual);
1851         }
1852 }
1853
1854 static void __unregister_enc_region_locked(struct kvm *kvm,
1855                                            struct enc_region *region)
1856 {
1857         /*
1858          * The guest may change the memory encryption attribute from C=0 -> C=1
1859          * or vice versa for this memory range. Lets make sure caches are
1860          * flushed to ensure that guest data gets written into memory with
1861          * correct C-bit.
1862          */
1863         sev_clflush_pages(region->pages, region->npages);
1864
1865         sev_unpin_memory(kvm, region->pages, region->npages);
1866         list_del(&region->list);
1867         kfree(region);
1868 }
1869
1870 static struct kvm *svm_vm_alloc(void)
1871 {
1872         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1873         return &kvm_svm->kvm;
1874 }
1875
1876 static void svm_vm_free(struct kvm *kvm)
1877 {
1878         vfree(to_kvm_svm(kvm));
1879 }
1880
1881 static void sev_vm_destroy(struct kvm *kvm)
1882 {
1883         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1884         struct list_head *head = &sev->regions_list;
1885         struct list_head *pos, *q;
1886
1887         if (!sev_guest(kvm))
1888                 return;
1889
1890         mutex_lock(&kvm->lock);
1891
1892         /*
1893          * if userspace was terminated before unregistering the memory regions
1894          * then lets unpin all the registered memory.
1895          */
1896         if (!list_empty(head)) {
1897                 list_for_each_safe(pos, q, head) {
1898                         __unregister_enc_region_locked(kvm,
1899                                 list_entry(pos, struct enc_region, list));
1900                 }
1901         }
1902
1903         mutex_unlock(&kvm->lock);
1904
1905         sev_unbind_asid(kvm, sev->handle);
1906         sev_asid_free(kvm);
1907 }
1908
1909 static void avic_vm_destroy(struct kvm *kvm)
1910 {
1911         unsigned long flags;
1912         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1913
1914         if (!avic)
1915                 return;
1916
1917         if (kvm_svm->avic_logical_id_table_page)
1918                 __free_page(kvm_svm->avic_logical_id_table_page);
1919         if (kvm_svm->avic_physical_id_table_page)
1920                 __free_page(kvm_svm->avic_physical_id_table_page);
1921
1922         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1923         hash_del(&kvm_svm->hnode);
1924         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1925 }
1926
1927 static void svm_vm_destroy(struct kvm *kvm)
1928 {
1929         avic_vm_destroy(kvm);
1930         sev_vm_destroy(kvm);
1931 }
1932
1933 static int avic_vm_init(struct kvm *kvm)
1934 {
1935         unsigned long flags;
1936         int err = -ENOMEM;
1937         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1938         struct kvm_svm *k2;
1939         struct page *p_page;
1940         struct page *l_page;
1941         u32 vm_id;
1942
1943         if (!avic)
1944                 return 0;
1945
1946         /* Allocating physical APIC ID table (4KB) */
1947         p_page = alloc_page(GFP_KERNEL);
1948         if (!p_page)
1949                 goto free_avic;
1950
1951         kvm_svm->avic_physical_id_table_page = p_page;
1952         clear_page(page_address(p_page));
1953
1954         /* Allocating logical APIC ID table (4KB) */
1955         l_page = alloc_page(GFP_KERNEL);
1956         if (!l_page)
1957                 goto free_avic;
1958
1959         kvm_svm->avic_logical_id_table_page = l_page;
1960         clear_page(page_address(l_page));
1961
1962         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1963  again:
1964         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1965         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1966                 next_vm_id_wrapped = 1;
1967                 goto again;
1968         }
1969         /* Is it still in use? Only possible if wrapped at least once */
1970         if (next_vm_id_wrapped) {
1971                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1972                         if (k2->avic_vm_id == vm_id)
1973                                 goto again;
1974                 }
1975         }
1976         kvm_svm->avic_vm_id = vm_id;
1977         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1978         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1979
1980         return 0;
1981
1982 free_avic:
1983         avic_vm_destroy(kvm);
1984         return err;
1985 }
1986
1987 static inline int
1988 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1989 {
1990         int ret = 0;
1991         unsigned long flags;
1992         struct amd_svm_iommu_ir *ir;
1993         struct vcpu_svm *svm = to_svm(vcpu);
1994
1995         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1996                 return 0;
1997
1998         /*
1999          * Here, we go through the per-vcpu ir_list to update all existing
2000          * interrupt remapping table entry targeting this vcpu.
2001          */
2002         spin_lock_irqsave(&svm->ir_list_lock, flags);
2003
2004         if (list_empty(&svm->ir_list))
2005                 goto out;
2006
2007         list_for_each_entry(ir, &svm->ir_list, node) {
2008                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2009                 if (ret)
2010                         break;
2011         }
2012 out:
2013         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2014         return ret;
2015 }
2016
2017 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2018 {
2019         u64 entry;
2020         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2021         int h_physical_id = kvm_cpu_get_apicid(cpu);
2022         struct vcpu_svm *svm = to_svm(vcpu);
2023
2024         if (!kvm_vcpu_apicv_active(vcpu))
2025                 return;
2026
2027         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2028                 return;
2029
2030         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2031         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2032
2033         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2034         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2035
2036         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2037         if (svm->avic_is_running)
2038                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2039
2040         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2041         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2042                                         svm->avic_is_running);
2043 }
2044
2045 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2046 {
2047         u64 entry;
2048         struct vcpu_svm *svm = to_svm(vcpu);
2049
2050         if (!kvm_vcpu_apicv_active(vcpu))
2051                 return;
2052
2053         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2054         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2055                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2056
2057         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2058         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2059 }
2060
2061 /**
2062  * This function is called during VCPU halt/unhalt.
2063  */
2064 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2065 {
2066         struct vcpu_svm *svm = to_svm(vcpu);
2067
2068         svm->avic_is_running = is_run;
2069         if (is_run)
2070                 avic_vcpu_load(vcpu, vcpu->cpu);
2071         else
2072                 avic_vcpu_put(vcpu);
2073 }
2074
2075 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2076 {
2077         struct vcpu_svm *svm = to_svm(vcpu);
2078         u32 dummy;
2079         u32 eax = 1;
2080
2081         vcpu->arch.microcode_version = 0x01000065;
2082         svm->spec_ctrl = 0;
2083         svm->virt_spec_ctrl = 0;
2084
2085         if (!init_event) {
2086                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2087                                            MSR_IA32_APICBASE_ENABLE;
2088                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2089                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2090         }
2091         init_vmcb(svm);
2092
2093         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2094         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2095
2096         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2097                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2098 }
2099
2100 static int avic_init_vcpu(struct vcpu_svm *svm)
2101 {
2102         int ret;
2103
2104         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2105                 return 0;
2106
2107         ret = avic_init_backing_page(&svm->vcpu);
2108         if (ret)
2109                 return ret;
2110
2111         INIT_LIST_HEAD(&svm->ir_list);
2112         spin_lock_init(&svm->ir_list_lock);
2113
2114         return ret;
2115 }
2116
2117 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2118 {
2119         struct vcpu_svm *svm;
2120         struct page *page;
2121         struct page *msrpm_pages;
2122         struct page *hsave_page;
2123         struct page *nested_msrpm_pages;
2124         int err;
2125
2126         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2127         if (!svm) {
2128                 err = -ENOMEM;
2129                 goto out;
2130         }
2131
2132         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2133         if (err)
2134                 goto free_svm;
2135
2136         err = -ENOMEM;
2137         page = alloc_page(GFP_KERNEL);
2138         if (!page)
2139                 goto uninit;
2140
2141         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2142         if (!msrpm_pages)
2143                 goto free_page1;
2144
2145         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2146         if (!nested_msrpm_pages)
2147                 goto free_page2;
2148
2149         hsave_page = alloc_page(GFP_KERNEL);
2150         if (!hsave_page)
2151                 goto free_page3;
2152
2153         err = avic_init_vcpu(svm);
2154         if (err)
2155                 goto free_page4;
2156
2157         /* We initialize this flag to true to make sure that the is_running
2158          * bit would be set the first time the vcpu is loaded.
2159          */
2160         svm->avic_is_running = true;
2161
2162         svm->nested.hsave = page_address(hsave_page);
2163
2164         svm->msrpm = page_address(msrpm_pages);
2165         svm_vcpu_init_msrpm(svm->msrpm);
2166
2167         svm->nested.msrpm = page_address(nested_msrpm_pages);
2168         svm_vcpu_init_msrpm(svm->nested.msrpm);
2169
2170         svm->vmcb = page_address(page);
2171         clear_page(svm->vmcb);
2172         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2173         svm->asid_generation = 0;
2174         init_vmcb(svm);
2175
2176         svm_init_osvw(&svm->vcpu);
2177
2178         return &svm->vcpu;
2179
2180 free_page4:
2181         __free_page(hsave_page);
2182 free_page3:
2183         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2184 free_page2:
2185         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2186 free_page1:
2187         __free_page(page);
2188 uninit:
2189         kvm_vcpu_uninit(&svm->vcpu);
2190 free_svm:
2191         kmem_cache_free(kvm_vcpu_cache, svm);
2192 out:
2193         return ERR_PTR(err);
2194 }
2195
2196 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2197 {
2198         int i;
2199
2200         for_each_online_cpu(i)
2201                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2202 }
2203
2204 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2205 {
2206         struct vcpu_svm *svm = to_svm(vcpu);
2207
2208         /*
2209          * The vmcb page can be recycled, causing a false negative in
2210          * svm_vcpu_load(). So, ensure that no logical CPU has this
2211          * vmcb page recorded as its current vmcb.
2212          */
2213         svm_clear_current_vmcb(svm->vmcb);
2214
2215         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2216         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2217         __free_page(virt_to_page(svm->nested.hsave));
2218         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2219         kvm_vcpu_uninit(vcpu);
2220         kmem_cache_free(kvm_vcpu_cache, svm);
2221 }
2222
2223 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2224 {
2225         struct vcpu_svm *svm = to_svm(vcpu);
2226         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2227         int i;
2228
2229         if (unlikely(cpu != vcpu->cpu)) {
2230                 svm->asid_generation = 0;
2231                 mark_all_dirty(svm->vmcb);
2232         }
2233
2234 #ifdef CONFIG_X86_64
2235         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2236 #endif
2237         savesegment(fs, svm->host.fs);
2238         savesegment(gs, svm->host.gs);
2239         svm->host.ldt = kvm_read_ldt();
2240
2241         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2242                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2243
2244         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2245                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2246                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2247                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2248                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2249                 }
2250         }
2251         /* This assumes that the kernel never uses MSR_TSC_AUX */
2252         if (static_cpu_has(X86_FEATURE_RDTSCP))
2253                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2254
2255         if (sd->current_vmcb != svm->vmcb) {
2256                 sd->current_vmcb = svm->vmcb;
2257                 indirect_branch_prediction_barrier();
2258         }
2259         avic_vcpu_load(vcpu, cpu);
2260 }
2261
2262 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2263 {
2264         struct vcpu_svm *svm = to_svm(vcpu);
2265         int i;
2266
2267         avic_vcpu_put(vcpu);
2268
2269         ++vcpu->stat.host_state_reload;
2270         kvm_load_ldt(svm->host.ldt);
2271 #ifdef CONFIG_X86_64
2272         loadsegment(fs, svm->host.fs);
2273         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2274         load_gs_index(svm->host.gs);
2275 #else
2276 #ifdef CONFIG_X86_32_LAZY_GS
2277         loadsegment(gs, svm->host.gs);
2278 #endif
2279 #endif
2280         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2281                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2282 }
2283
2284 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2285 {
2286         avic_set_running(vcpu, false);
2287 }
2288
2289 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2290 {
2291         avic_set_running(vcpu, true);
2292 }
2293
2294 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2295 {
2296         struct vcpu_svm *svm = to_svm(vcpu);
2297         unsigned long rflags = svm->vmcb->save.rflags;
2298
2299         if (svm->nmi_singlestep) {
2300                 /* Hide our flags if they were not set by the guest */
2301                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2302                         rflags &= ~X86_EFLAGS_TF;
2303                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2304                         rflags &= ~X86_EFLAGS_RF;
2305         }
2306         return rflags;
2307 }
2308
2309 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2310 {
2311         if (to_svm(vcpu)->nmi_singlestep)
2312                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2313
2314        /*
2315         * Any change of EFLAGS.VM is accompanied by a reload of SS
2316         * (caused by either a task switch or an inter-privilege IRET),
2317         * so we do not need to update the CPL here.
2318         */
2319         to_svm(vcpu)->vmcb->save.rflags = rflags;
2320 }
2321
2322 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2323 {
2324         switch (reg) {
2325         case VCPU_EXREG_PDPTR:
2326                 BUG_ON(!npt_enabled);
2327                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2328                 break;
2329         default:
2330                 BUG();
2331         }
2332 }
2333
2334 static void svm_set_vintr(struct vcpu_svm *svm)
2335 {
2336         set_intercept(svm, INTERCEPT_VINTR);
2337 }
2338
2339 static void svm_clear_vintr(struct vcpu_svm *svm)
2340 {
2341         clr_intercept(svm, INTERCEPT_VINTR);
2342 }
2343
2344 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2345 {
2346         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2347
2348         switch (seg) {
2349         case VCPU_SREG_CS: return &save->cs;
2350         case VCPU_SREG_DS: return &save->ds;
2351         case VCPU_SREG_ES: return &save->es;
2352         case VCPU_SREG_FS: return &save->fs;
2353         case VCPU_SREG_GS: return &save->gs;
2354         case VCPU_SREG_SS: return &save->ss;
2355         case VCPU_SREG_TR: return &save->tr;
2356         case VCPU_SREG_LDTR: return &save->ldtr;
2357         }
2358         BUG();
2359         return NULL;
2360 }
2361
2362 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2363 {
2364         struct vmcb_seg *s = svm_seg(vcpu, seg);
2365
2366         return s->base;
2367 }
2368
2369 static void svm_get_segment(struct kvm_vcpu *vcpu,
2370                             struct kvm_segment *var, int seg)
2371 {
2372         struct vmcb_seg *s = svm_seg(vcpu, seg);
2373
2374         var->base = s->base;
2375         var->limit = s->limit;
2376         var->selector = s->selector;
2377         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2378         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2379         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2380         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2381         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2382         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2383         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2384
2385         /*
2386          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2387          * However, the SVM spec states that the G bit is not observed by the
2388          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2389          * So let's synthesize a legal G bit for all segments, this helps
2390          * running KVM nested. It also helps cross-vendor migration, because
2391          * Intel's vmentry has a check on the 'G' bit.
2392          */
2393         var->g = s->limit > 0xfffff;
2394
2395         /*
2396          * AMD's VMCB does not have an explicit unusable field, so emulate it
2397          * for cross vendor migration purposes by "not present"
2398          */
2399         var->unusable = !var->present;
2400
2401         switch (seg) {
2402         case VCPU_SREG_TR:
2403                 /*
2404                  * Work around a bug where the busy flag in the tr selector
2405                  * isn't exposed
2406                  */
2407                 var->type |= 0x2;
2408                 break;
2409         case VCPU_SREG_DS:
2410         case VCPU_SREG_ES:
2411         case VCPU_SREG_FS:
2412         case VCPU_SREG_GS:
2413                 /*
2414                  * The accessed bit must always be set in the segment
2415                  * descriptor cache, although it can be cleared in the
2416                  * descriptor, the cached bit always remains at 1. Since
2417                  * Intel has a check on this, set it here to support
2418                  * cross-vendor migration.
2419                  */
2420                 if (!var->unusable)
2421                         var->type |= 0x1;
2422                 break;
2423         case VCPU_SREG_SS:
2424                 /*
2425                  * On AMD CPUs sometimes the DB bit in the segment
2426                  * descriptor is left as 1, although the whole segment has
2427                  * been made unusable. Clear it here to pass an Intel VMX
2428                  * entry check when cross vendor migrating.
2429                  */
2430                 if (var->unusable)
2431                         var->db = 0;
2432                 /* This is symmetric with svm_set_segment() */
2433                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2434                 break;
2435         }
2436 }
2437
2438 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2439 {
2440         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2441
2442         return save->cpl;
2443 }
2444
2445 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2446 {
2447         struct vcpu_svm *svm = to_svm(vcpu);
2448
2449         dt->size = svm->vmcb->save.idtr.limit;
2450         dt->address = svm->vmcb->save.idtr.base;
2451 }
2452
2453 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2454 {
2455         struct vcpu_svm *svm = to_svm(vcpu);
2456
2457         svm->vmcb->save.idtr.limit = dt->size;
2458         svm->vmcb->save.idtr.base = dt->address ;
2459         mark_dirty(svm->vmcb, VMCB_DT);
2460 }
2461
2462 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2463 {
2464         struct vcpu_svm *svm = to_svm(vcpu);
2465
2466         dt->size = svm->vmcb->save.gdtr.limit;
2467         dt->address = svm->vmcb->save.gdtr.base;
2468 }
2469
2470 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2471 {
2472         struct vcpu_svm *svm = to_svm(vcpu);
2473
2474         svm->vmcb->save.gdtr.limit = dt->size;
2475         svm->vmcb->save.gdtr.base = dt->address ;
2476         mark_dirty(svm->vmcb, VMCB_DT);
2477 }
2478
2479 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2480 {
2481 }
2482
2483 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2484 {
2485 }
2486
2487 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2488 {
2489 }
2490
2491 static void update_cr0_intercept(struct vcpu_svm *svm)
2492 {
2493         ulong gcr0 = svm->vcpu.arch.cr0;
2494         u64 *hcr0 = &svm->vmcb->save.cr0;
2495
2496         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2497                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2498
2499         mark_dirty(svm->vmcb, VMCB_CR);
2500
2501         if (gcr0 == *hcr0) {
2502                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2503                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2504         } else {
2505                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2506                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2507         }
2508 }
2509
2510 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2511 {
2512         struct vcpu_svm *svm = to_svm(vcpu);
2513
2514 #ifdef CONFIG_X86_64
2515         if (vcpu->arch.efer & EFER_LME) {
2516                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2517                         vcpu->arch.efer |= EFER_LMA;
2518                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2519                 }
2520
2521                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2522                         vcpu->arch.efer &= ~EFER_LMA;
2523                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2524                 }
2525         }
2526 #endif
2527         vcpu->arch.cr0 = cr0;
2528
2529         if (!npt_enabled)
2530                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2531
2532         /*
2533          * re-enable caching here because the QEMU bios
2534          * does not do it - this results in some delay at
2535          * reboot
2536          */
2537         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2538                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2539         svm->vmcb->save.cr0 = cr0;
2540         mark_dirty(svm->vmcb, VMCB_CR);
2541         update_cr0_intercept(svm);
2542 }
2543
2544 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2545 {
2546         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2547         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2548
2549         if (cr4 & X86_CR4_VMXE)
2550                 return 1;
2551
2552         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2553                 svm_flush_tlb(vcpu, true);
2554
2555         vcpu->arch.cr4 = cr4;
2556         if (!npt_enabled)
2557                 cr4 |= X86_CR4_PAE;
2558         cr4 |= host_cr4_mce;
2559         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2560         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2561         return 0;
2562 }
2563
2564 static void svm_set_segment(struct kvm_vcpu *vcpu,
2565                             struct kvm_segment *var, int seg)
2566 {
2567         struct vcpu_svm *svm = to_svm(vcpu);
2568         struct vmcb_seg *s = svm_seg(vcpu, seg);
2569
2570         s->base = var->base;
2571         s->limit = var->limit;
2572         s->selector = var->selector;
2573         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2574         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2575         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2576         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2577         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2578         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2579         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2580         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2581
2582         /*
2583          * This is always accurate, except if SYSRET returned to a segment
2584          * with SS.DPL != 3.  Intel does not have this quirk, and always
2585          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2586          * would entail passing the CPL to userspace and back.
2587          */
2588         if (seg == VCPU_SREG_SS)
2589                 /* This is symmetric with svm_get_segment() */
2590                 svm->vmcb->save.cpl = (var->dpl & 3);
2591
2592         mark_dirty(svm->vmcb, VMCB_SEG);
2593 }
2594
2595 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2596 {
2597         struct vcpu_svm *svm = to_svm(vcpu);
2598
2599         clr_exception_intercept(svm, BP_VECTOR);
2600
2601         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2602                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2603                         set_exception_intercept(svm, BP_VECTOR);
2604         } else
2605                 vcpu->guest_debug = 0;
2606 }
2607
2608 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2609 {
2610         if (sd->next_asid > sd->max_asid) {
2611                 ++sd->asid_generation;
2612                 sd->next_asid = sd->min_asid;
2613                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2614         }
2615
2616         svm->asid_generation = sd->asid_generation;
2617         svm->vmcb->control.asid = sd->next_asid++;
2618
2619         mark_dirty(svm->vmcb, VMCB_ASID);
2620 }
2621
2622 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2623 {
2624         return to_svm(vcpu)->vmcb->save.dr6;
2625 }
2626
2627 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2628 {
2629         struct vcpu_svm *svm = to_svm(vcpu);
2630
2631         svm->vmcb->save.dr6 = value;
2632         mark_dirty(svm->vmcb, VMCB_DR);
2633 }
2634
2635 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2636 {
2637         struct vcpu_svm *svm = to_svm(vcpu);
2638
2639         get_debugreg(vcpu->arch.db[0], 0);
2640         get_debugreg(vcpu->arch.db[1], 1);
2641         get_debugreg(vcpu->arch.db[2], 2);
2642         get_debugreg(vcpu->arch.db[3], 3);
2643         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2644         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2645
2646         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2647         set_dr_intercepts(svm);
2648 }
2649
2650 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2651 {
2652         struct vcpu_svm *svm = to_svm(vcpu);
2653
2654         svm->vmcb->save.dr7 = value;
2655         mark_dirty(svm->vmcb, VMCB_DR);
2656 }
2657
2658 static int pf_interception(struct vcpu_svm *svm)
2659 {
2660         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2661         u64 error_code = svm->vmcb->control.exit_info_1;
2662
2663         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2664                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2665                         svm->vmcb->control.insn_bytes : NULL,
2666                         svm->vmcb->control.insn_len);
2667 }
2668
2669 static int npf_interception(struct vcpu_svm *svm)
2670 {
2671         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2672         u64 error_code = svm->vmcb->control.exit_info_1;
2673
2674         trace_kvm_page_fault(fault_address, error_code);
2675         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2676                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2677                         svm->vmcb->control.insn_bytes : NULL,
2678                         svm->vmcb->control.insn_len);
2679 }
2680
2681 static int db_interception(struct vcpu_svm *svm)
2682 {
2683         struct kvm_run *kvm_run = svm->vcpu.run;
2684
2685         if (!(svm->vcpu.guest_debug &
2686               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2687                 !svm->nmi_singlestep) {
2688                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2689                 return 1;
2690         }
2691
2692         if (svm->nmi_singlestep) {
2693                 disable_nmi_singlestep(svm);
2694         }
2695
2696         if (svm->vcpu.guest_debug &
2697             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2698                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2699                 kvm_run->debug.arch.pc =
2700                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2701                 kvm_run->debug.arch.exception = DB_VECTOR;
2702                 return 0;
2703         }
2704
2705         return 1;
2706 }
2707
2708 static int bp_interception(struct vcpu_svm *svm)
2709 {
2710         struct kvm_run *kvm_run = svm->vcpu.run;
2711
2712         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2713         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2714         kvm_run->debug.arch.exception = BP_VECTOR;
2715         return 0;
2716 }
2717
2718 static int ud_interception(struct vcpu_svm *svm)
2719 {
2720         return handle_ud(&svm->vcpu);
2721 }
2722
2723 static int ac_interception(struct vcpu_svm *svm)
2724 {
2725         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2726         return 1;
2727 }
2728
2729 static int gp_interception(struct vcpu_svm *svm)
2730 {
2731         struct kvm_vcpu *vcpu = &svm->vcpu;
2732         u32 error_code = svm->vmcb->control.exit_info_1;
2733         int er;
2734
2735         WARN_ON_ONCE(!enable_vmware_backdoor);
2736
2737         er = kvm_emulate_instruction(vcpu,
2738                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2739         if (er == EMULATE_USER_EXIT)
2740                 return 0;
2741         else if (er != EMULATE_DONE)
2742                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2743         return 1;
2744 }
2745
2746 static bool is_erratum_383(void)
2747 {
2748         int err, i;
2749         u64 value;
2750
2751         if (!erratum_383_found)
2752                 return false;
2753
2754         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2755         if (err)
2756                 return false;
2757
2758         /* Bit 62 may or may not be set for this mce */
2759         value &= ~(1ULL << 62);
2760
2761         if (value != 0xb600000000010015ULL)
2762                 return false;
2763
2764         /* Clear MCi_STATUS registers */
2765         for (i = 0; i < 6; ++i)
2766                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2767
2768         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2769         if (!err) {
2770                 u32 low, high;
2771
2772                 value &= ~(1ULL << 2);
2773                 low    = lower_32_bits(value);
2774                 high   = upper_32_bits(value);
2775
2776                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2777         }
2778
2779         /* Flush tlb to evict multi-match entries */
2780         __flush_tlb_all();
2781
2782         return true;
2783 }
2784
2785 static void svm_handle_mce(struct vcpu_svm *svm)
2786 {
2787         if (is_erratum_383()) {
2788                 /*
2789                  * Erratum 383 triggered. Guest state is corrupt so kill the
2790                  * guest.
2791                  */
2792                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2793
2794                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2795
2796                 return;
2797         }
2798
2799         /*
2800          * On an #MC intercept the MCE handler is not called automatically in
2801          * the host. So do it by hand here.
2802          */
2803         asm volatile (
2804                 "int $0x12\n");
2805         /* not sure if we ever come back to this point */
2806
2807         return;
2808 }
2809
2810 static int mc_interception(struct vcpu_svm *svm)
2811 {
2812         return 1;
2813 }
2814
2815 static int shutdown_interception(struct vcpu_svm *svm)
2816 {
2817         struct kvm_run *kvm_run = svm->vcpu.run;
2818
2819         /*
2820          * VMCB is undefined after a SHUTDOWN intercept
2821          * so reinitialize it.
2822          */
2823         clear_page(svm->vmcb);
2824         init_vmcb(svm);
2825
2826         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2827         return 0;
2828 }
2829
2830 static int io_interception(struct vcpu_svm *svm)
2831 {
2832         struct kvm_vcpu *vcpu = &svm->vcpu;
2833         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2834         int size, in, string;
2835         unsigned port;
2836
2837         ++svm->vcpu.stat.io_exits;
2838         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2839         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2840         if (string)
2841                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2842
2843         port = io_info >> 16;
2844         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2845         svm->next_rip = svm->vmcb->control.exit_info_2;
2846
2847         return kvm_fast_pio(&svm->vcpu, size, port, in);
2848 }
2849
2850 static int nmi_interception(struct vcpu_svm *svm)
2851 {
2852         return 1;
2853 }
2854
2855 static int intr_interception(struct vcpu_svm *svm)
2856 {
2857         ++svm->vcpu.stat.irq_exits;
2858         return 1;
2859 }
2860
2861 static int nop_on_interception(struct vcpu_svm *svm)
2862 {
2863         return 1;
2864 }
2865
2866 static int halt_interception(struct vcpu_svm *svm)
2867 {
2868         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2869         return kvm_emulate_halt(&svm->vcpu);
2870 }
2871
2872 static int vmmcall_interception(struct vcpu_svm *svm)
2873 {
2874         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2875         return kvm_emulate_hypercall(&svm->vcpu);
2876 }
2877
2878 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2879 {
2880         struct vcpu_svm *svm = to_svm(vcpu);
2881
2882         return svm->nested.nested_cr3;
2883 }
2884
2885 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2886 {
2887         struct vcpu_svm *svm = to_svm(vcpu);
2888         u64 cr3 = svm->nested.nested_cr3;
2889         u64 pdpte;
2890         int ret;
2891
2892         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2893                                        offset_in_page(cr3) + index * 8, 8);
2894         if (ret)
2895                 return 0;
2896         return pdpte;
2897 }
2898
2899 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2900                                    unsigned long root)
2901 {
2902         struct vcpu_svm *svm = to_svm(vcpu);
2903
2904         svm->vmcb->control.nested_cr3 = __sme_set(root);
2905         mark_dirty(svm->vmcb, VMCB_NPT);
2906 }
2907
2908 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2909                                        struct x86_exception *fault)
2910 {
2911         struct vcpu_svm *svm = to_svm(vcpu);
2912
2913         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2914                 /*
2915                  * TODO: track the cause of the nested page fault, and
2916                  * correctly fill in the high bits of exit_info_1.
2917                  */
2918                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2919                 svm->vmcb->control.exit_code_hi = 0;
2920                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2921                 svm->vmcb->control.exit_info_2 = fault->address;
2922         }
2923
2924         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2925         svm->vmcb->control.exit_info_1 |= fault->error_code;
2926
2927         /*
2928          * The present bit is always zero for page structure faults on real
2929          * hardware.
2930          */
2931         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2932                 svm->vmcb->control.exit_info_1 &= ~1;
2933
2934         nested_svm_vmexit(svm);
2935 }
2936
2937 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2938 {
2939         WARN_ON(mmu_is_nested(vcpu));
2940         kvm_init_shadow_mmu(vcpu);
2941         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2942         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2943         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2944         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2945         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2946         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2947         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2948 }
2949
2950 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2951 {
2952         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2953 }
2954
2955 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2956 {
2957         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2958             !is_paging(&svm->vcpu)) {
2959                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2960                 return 1;
2961         }
2962
2963         if (svm->vmcb->save.cpl) {
2964                 kvm_inject_gp(&svm->vcpu, 0);
2965                 return 1;
2966         }
2967
2968         return 0;
2969 }
2970
2971 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2972                                       bool has_error_code, u32 error_code)
2973 {
2974         int vmexit;
2975
2976         if (!is_guest_mode(&svm->vcpu))
2977                 return 0;
2978
2979         vmexit = nested_svm_intercept(svm);
2980         if (vmexit != NESTED_EXIT_DONE)
2981                 return 0;
2982
2983         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2984         svm->vmcb->control.exit_code_hi = 0;
2985         svm->vmcb->control.exit_info_1 = error_code;
2986
2987         /*
2988          * EXITINFO2 is undefined for all exception intercepts other
2989          * than #PF.
2990          */
2991         if (svm->vcpu.arch.exception.nested_apf)
2992                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2993         else if (svm->vcpu.arch.exception.has_payload)
2994                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
2995         else
2996                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2997
2998         svm->nested.exit_required = true;
2999         return vmexit;
3000 }
3001
3002 /* This function returns true if it is save to enable the irq window */
3003 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3004 {
3005         if (!is_guest_mode(&svm->vcpu))
3006                 return true;
3007
3008         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3009                 return true;
3010
3011         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3012                 return false;
3013
3014         /*
3015          * if vmexit was already requested (by intercepted exception
3016          * for instance) do not overwrite it with "external interrupt"
3017          * vmexit.
3018          */
3019         if (svm->nested.exit_required)
3020                 return false;
3021
3022         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3023         svm->vmcb->control.exit_info_1 = 0;
3024         svm->vmcb->control.exit_info_2 = 0;
3025
3026         if (svm->nested.intercept & 1ULL) {
3027                 /*
3028                  * The #vmexit can't be emulated here directly because this
3029                  * code path runs with irqs and preemption disabled. A
3030                  * #vmexit emulation might sleep. Only signal request for
3031                  * the #vmexit here.
3032                  */
3033                 svm->nested.exit_required = true;
3034                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3035                 return false;
3036         }
3037
3038         return true;
3039 }
3040
3041 /* This function returns true if it is save to enable the nmi window */
3042 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3043 {
3044         if (!is_guest_mode(&svm->vcpu))
3045                 return true;
3046
3047         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3048                 return true;
3049
3050         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3051         svm->nested.exit_required = true;
3052
3053         return false;
3054 }
3055
3056 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3057 {
3058         struct page *page;
3059
3060         might_sleep();
3061
3062         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3063         if (is_error_page(page))
3064                 goto error;
3065
3066         *_page = page;
3067
3068         return kmap(page);
3069
3070 error:
3071         kvm_inject_gp(&svm->vcpu, 0);
3072
3073         return NULL;
3074 }
3075
3076 static void nested_svm_unmap(struct page *page)
3077 {
3078         kunmap(page);
3079         kvm_release_page_dirty(page);
3080 }
3081
3082 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3083 {
3084         unsigned port, size, iopm_len;
3085         u16 val, mask;
3086         u8 start_bit;
3087         u64 gpa;
3088
3089         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3090                 return NESTED_EXIT_HOST;
3091
3092         port = svm->vmcb->control.exit_info_1 >> 16;
3093         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3094                 SVM_IOIO_SIZE_SHIFT;
3095         gpa  = svm->nested.vmcb_iopm + (port / 8);
3096         start_bit = port % 8;
3097         iopm_len = (start_bit + size > 8) ? 2 : 1;
3098         mask = (0xf >> (4 - size)) << start_bit;
3099         val = 0;
3100
3101         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3102                 return NESTED_EXIT_DONE;
3103
3104         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3105 }
3106
3107 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3108 {
3109         u32 offset, msr, value;
3110         int write, mask;
3111
3112         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3113                 return NESTED_EXIT_HOST;
3114
3115         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3116         offset = svm_msrpm_offset(msr);
3117         write  = svm->vmcb->control.exit_info_1 & 1;
3118         mask   = 1 << ((2 * (msr & 0xf)) + write);
3119
3120         if (offset == MSR_INVALID)
3121                 return NESTED_EXIT_DONE;
3122
3123         /* Offset is in 32 bit units but need in 8 bit units */
3124         offset *= 4;
3125
3126         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3127                 return NESTED_EXIT_DONE;
3128
3129         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3130 }
3131
3132 /* DB exceptions for our internal use must not cause vmexit */
3133 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3134 {
3135         unsigned long dr6;
3136
3137         /* if we're not singlestepping, it's not ours */
3138         if (!svm->nmi_singlestep)
3139                 return NESTED_EXIT_DONE;
3140
3141         /* if it's not a singlestep exception, it's not ours */
3142         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3143                 return NESTED_EXIT_DONE;
3144         if (!(dr6 & DR6_BS))
3145                 return NESTED_EXIT_DONE;
3146
3147         /* if the guest is singlestepping, it should get the vmexit */
3148         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3149                 disable_nmi_singlestep(svm);
3150                 return NESTED_EXIT_DONE;
3151         }
3152
3153         /* it's ours, the nested hypervisor must not see this one */
3154         return NESTED_EXIT_HOST;
3155 }
3156
3157 static int nested_svm_exit_special(struct vcpu_svm *svm)
3158 {
3159         u32 exit_code = svm->vmcb->control.exit_code;
3160
3161         switch (exit_code) {
3162         case SVM_EXIT_INTR:
3163         case SVM_EXIT_NMI:
3164         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3165                 return NESTED_EXIT_HOST;
3166         case SVM_EXIT_NPF:
3167                 /* For now we are always handling NPFs when using them */
3168                 if (npt_enabled)
3169                         return NESTED_EXIT_HOST;
3170                 break;
3171         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3172                 /* When we're shadowing, trap PFs, but not async PF */
3173                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3174                         return NESTED_EXIT_HOST;
3175                 break;
3176         default:
3177                 break;
3178         }
3179
3180         return NESTED_EXIT_CONTINUE;
3181 }
3182
3183 /*
3184  * If this function returns true, this #vmexit was already handled
3185  */
3186 static int nested_svm_intercept(struct vcpu_svm *svm)
3187 {
3188         u32 exit_code = svm->vmcb->control.exit_code;
3189         int vmexit = NESTED_EXIT_HOST;
3190
3191         switch (exit_code) {
3192         case SVM_EXIT_MSR:
3193                 vmexit = nested_svm_exit_handled_msr(svm);
3194                 break;
3195         case SVM_EXIT_IOIO:
3196                 vmexit = nested_svm_intercept_ioio(svm);
3197                 break;
3198         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3199                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3200                 if (svm->nested.intercept_cr & bit)
3201                         vmexit = NESTED_EXIT_DONE;
3202                 break;
3203         }
3204         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3205                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3206                 if (svm->nested.intercept_dr & bit)
3207                         vmexit = NESTED_EXIT_DONE;
3208                 break;
3209         }
3210         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3211                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3212                 if (svm->nested.intercept_exceptions & excp_bits) {
3213                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3214                                 vmexit = nested_svm_intercept_db(svm);
3215                         else
3216                                 vmexit = NESTED_EXIT_DONE;
3217                 }
3218                 /* async page fault always cause vmexit */
3219                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3220                          svm->vcpu.arch.exception.nested_apf != 0)
3221                         vmexit = NESTED_EXIT_DONE;
3222                 break;
3223         }
3224         case SVM_EXIT_ERR: {
3225                 vmexit = NESTED_EXIT_DONE;
3226                 break;
3227         }
3228         default: {
3229                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3230                 if (svm->nested.intercept & exit_bits)
3231                         vmexit = NESTED_EXIT_DONE;
3232         }
3233         }
3234
3235         return vmexit;
3236 }
3237
3238 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3239 {
3240         int vmexit;
3241
3242         vmexit = nested_svm_intercept(svm);
3243
3244         if (vmexit == NESTED_EXIT_DONE)
3245                 nested_svm_vmexit(svm);
3246
3247         return vmexit;
3248 }
3249
3250 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3251 {
3252         struct vmcb_control_area *dst  = &dst_vmcb->control;
3253         struct vmcb_control_area *from = &from_vmcb->control;
3254
3255         dst->intercept_cr         = from->intercept_cr;
3256         dst->intercept_dr         = from->intercept_dr;
3257         dst->intercept_exceptions = from->intercept_exceptions;
3258         dst->intercept            = from->intercept;
3259         dst->iopm_base_pa         = from->iopm_base_pa;
3260         dst->msrpm_base_pa        = from->msrpm_base_pa;
3261         dst->tsc_offset           = from->tsc_offset;
3262         dst->asid                 = from->asid;
3263         dst->tlb_ctl              = from->tlb_ctl;
3264         dst->int_ctl              = from->int_ctl;
3265         dst->int_vector           = from->int_vector;
3266         dst->int_state            = from->int_state;
3267         dst->exit_code            = from->exit_code;
3268         dst->exit_code_hi         = from->exit_code_hi;
3269         dst->exit_info_1          = from->exit_info_1;
3270         dst->exit_info_2          = from->exit_info_2;
3271         dst->exit_int_info        = from->exit_int_info;
3272         dst->exit_int_info_err    = from->exit_int_info_err;
3273         dst->nested_ctl           = from->nested_ctl;
3274         dst->event_inj            = from->event_inj;
3275         dst->event_inj_err        = from->event_inj_err;
3276         dst->nested_cr3           = from->nested_cr3;
3277         dst->virt_ext              = from->virt_ext;
3278 }
3279
3280 static int nested_svm_vmexit(struct vcpu_svm *svm)
3281 {
3282         struct vmcb *nested_vmcb;
3283         struct vmcb *hsave = svm->nested.hsave;
3284         struct vmcb *vmcb = svm->vmcb;
3285         struct page *page;
3286
3287         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3288                                        vmcb->control.exit_info_1,
3289                                        vmcb->control.exit_info_2,
3290                                        vmcb->control.exit_int_info,
3291                                        vmcb->control.exit_int_info_err,
3292                                        KVM_ISA_SVM);
3293
3294         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3295         if (!nested_vmcb)
3296                 return 1;
3297
3298         /* Exit Guest-Mode */
3299         leave_guest_mode(&svm->vcpu);
3300         svm->nested.vmcb = 0;
3301
3302         /* Give the current vmcb to the guest */
3303         disable_gif(svm);
3304
3305         nested_vmcb->save.es     = vmcb->save.es;
3306         nested_vmcb->save.cs     = vmcb->save.cs;
3307         nested_vmcb->save.ss     = vmcb->save.ss;
3308         nested_vmcb->save.ds     = vmcb->save.ds;
3309         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3310         nested_vmcb->save.idtr   = vmcb->save.idtr;
3311         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3312         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3313         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3314         nested_vmcb->save.cr2    = vmcb->save.cr2;
3315         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3316         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3317         nested_vmcb->save.rip    = vmcb->save.rip;
3318         nested_vmcb->save.rsp    = vmcb->save.rsp;
3319         nested_vmcb->save.rax    = vmcb->save.rax;
3320         nested_vmcb->save.dr7    = vmcb->save.dr7;
3321         nested_vmcb->save.dr6    = vmcb->save.dr6;
3322         nested_vmcb->save.cpl    = vmcb->save.cpl;
3323
3324         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3325         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3326         nested_vmcb->control.int_state         = vmcb->control.int_state;
3327         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3328         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3329         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3330         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3331         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3332         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3333
3334         if (svm->nrips_enabled)
3335                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3336
3337         /*
3338          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3339          * to make sure that we do not lose injected events. So check event_inj
3340          * here and copy it to exit_int_info if it is valid.
3341          * Exit_int_info and event_inj can't be both valid because the case
3342          * below only happens on a VMRUN instruction intercept which has
3343          * no valid exit_int_info set.
3344          */
3345         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3346                 struct vmcb_control_area *nc = &nested_vmcb->control;
3347
3348                 nc->exit_int_info     = vmcb->control.event_inj;
3349                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3350         }
3351
3352         nested_vmcb->control.tlb_ctl           = 0;
3353         nested_vmcb->control.event_inj         = 0;
3354         nested_vmcb->control.event_inj_err     = 0;
3355
3356         /* We always set V_INTR_MASKING and remember the old value in hflags */
3357         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3358                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3359
3360         /* Restore the original control entries */
3361         copy_vmcb_control_area(vmcb, hsave);
3362
3363         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3364         kvm_clear_exception_queue(&svm->vcpu);
3365         kvm_clear_interrupt_queue(&svm->vcpu);
3366
3367         svm->nested.nested_cr3 = 0;
3368
3369         /* Restore selected save entries */
3370         svm->vmcb->save.es = hsave->save.es;
3371         svm->vmcb->save.cs = hsave->save.cs;
3372         svm->vmcb->save.ss = hsave->save.ss;
3373         svm->vmcb->save.ds = hsave->save.ds;
3374         svm->vmcb->save.gdtr = hsave->save.gdtr;
3375         svm->vmcb->save.idtr = hsave->save.idtr;
3376         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3377         svm_set_efer(&svm->vcpu, hsave->save.efer);
3378         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3379         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3380         if (npt_enabled) {
3381                 svm->vmcb->save.cr3 = hsave->save.cr3;
3382                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3383         } else {
3384                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3385         }
3386         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3387         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3388         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3389         svm->vmcb->save.dr7 = 0;
3390         svm->vmcb->save.cpl = 0;
3391         svm->vmcb->control.exit_int_info = 0;
3392
3393         mark_all_dirty(svm->vmcb);
3394
3395         nested_svm_unmap(page);
3396
3397         nested_svm_uninit_mmu_context(&svm->vcpu);
3398         kvm_mmu_reset_context(&svm->vcpu);
3399         kvm_mmu_load(&svm->vcpu);
3400
3401         return 0;
3402 }
3403
3404 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3405 {
3406         /*
3407          * This function merges the msr permission bitmaps of kvm and the
3408          * nested vmcb. It is optimized in that it only merges the parts where
3409          * the kvm msr permission bitmap may contain zero bits
3410          */
3411         int i;
3412
3413         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3414                 return true;
3415
3416         for (i = 0; i < MSRPM_OFFSETS; i++) {
3417                 u32 value, p;
3418                 u64 offset;
3419
3420                 if (msrpm_offsets[i] == 0xffffffff)
3421                         break;
3422
3423                 p      = msrpm_offsets[i];
3424                 offset = svm->nested.vmcb_msrpm + (p * 4);
3425
3426                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3427                         return false;
3428
3429                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3430         }
3431
3432         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3433
3434         return true;
3435 }
3436
3437 static bool nested_vmcb_checks(struct vmcb *vmcb)
3438 {
3439         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3440                 return false;
3441
3442         if (vmcb->control.asid == 0)
3443                 return false;
3444
3445         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3446             !npt_enabled)
3447                 return false;
3448
3449         return true;
3450 }
3451
3452 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3453                                  struct vmcb *nested_vmcb, struct page *page)
3454 {
3455         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3456                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3457         else
3458                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3459
3460         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3461                 kvm_mmu_unload(&svm->vcpu);
3462                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3463                 nested_svm_init_mmu_context(&svm->vcpu);
3464         }
3465
3466         /* Load the nested guest state */
3467         svm->vmcb->save.es = nested_vmcb->save.es;
3468         svm->vmcb->save.cs = nested_vmcb->save.cs;
3469         svm->vmcb->save.ss = nested_vmcb->save.ss;
3470         svm->vmcb->save.ds = nested_vmcb->save.ds;
3471         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3472         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3473         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3474         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3475         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3476         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3477         if (npt_enabled) {
3478                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3479                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3480         } else
3481                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3482
3483         /* Guest paging mode is active - reset mmu */
3484         kvm_mmu_reset_context(&svm->vcpu);
3485
3486         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3487         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3488         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3489         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3490
3491         /* In case we don't even reach vcpu_run, the fields are not updated */
3492         svm->vmcb->save.rax = nested_vmcb->save.rax;
3493         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3494         svm->vmcb->save.rip = nested_vmcb->save.rip;
3495         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3496         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3497         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3498
3499         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3500         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3501
3502         /* cache intercepts */
3503         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3504         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3505         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3506         svm->nested.intercept            = nested_vmcb->control.intercept;
3507
3508         svm_flush_tlb(&svm->vcpu, true);
3509         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3510         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3511                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3512         else
3513                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3514
3515         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3516                 /* We only want the cr8 intercept bits of the guest */
3517                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3518                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3519         }
3520
3521         /* We don't want to see VMMCALLs from a nested guest */
3522         clr_intercept(svm, INTERCEPT_VMMCALL);
3523
3524         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3525         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3526
3527         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3528         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3529         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3530         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3531         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3532
3533         nested_svm_unmap(page);
3534
3535         /* Enter Guest-Mode */
3536         enter_guest_mode(&svm->vcpu);
3537
3538         /*
3539          * Merge guest and host intercepts - must be called  with vcpu in
3540          * guest-mode to take affect here
3541          */
3542         recalc_intercepts(svm);
3543
3544         svm->nested.vmcb = vmcb_gpa;
3545
3546         enable_gif(svm);
3547
3548         mark_all_dirty(svm->vmcb);
3549 }
3550
3551 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3552 {
3553         struct vmcb *nested_vmcb;
3554         struct vmcb *hsave = svm->nested.hsave;
3555         struct vmcb *vmcb = svm->vmcb;
3556         struct page *page;
3557         u64 vmcb_gpa;
3558
3559         vmcb_gpa = svm->vmcb->save.rax;
3560
3561         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3562         if (!nested_vmcb)
3563                 return false;
3564
3565         if (!nested_vmcb_checks(nested_vmcb)) {
3566                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3567                 nested_vmcb->control.exit_code_hi = 0;
3568                 nested_vmcb->control.exit_info_1  = 0;
3569                 nested_vmcb->control.exit_info_2  = 0;
3570
3571                 nested_svm_unmap(page);
3572
3573                 return false;
3574         }
3575
3576         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3577                                nested_vmcb->save.rip,
3578                                nested_vmcb->control.int_ctl,
3579                                nested_vmcb->control.event_inj,
3580                                nested_vmcb->control.nested_ctl);
3581
3582         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3583                                     nested_vmcb->control.intercept_cr >> 16,
3584                                     nested_vmcb->control.intercept_exceptions,
3585                                     nested_vmcb->control.intercept);
3586
3587         /* Clear internal status */
3588         kvm_clear_exception_queue(&svm->vcpu);
3589         kvm_clear_interrupt_queue(&svm->vcpu);
3590
3591         /*
3592          * Save the old vmcb, so we don't need to pick what we save, but can
3593          * restore everything when a VMEXIT occurs
3594          */
3595         hsave->save.es     = vmcb->save.es;
3596         hsave->save.cs     = vmcb->save.cs;
3597         hsave->save.ss     = vmcb->save.ss;
3598         hsave->save.ds     = vmcb->save.ds;
3599         hsave->save.gdtr   = vmcb->save.gdtr;
3600         hsave->save.idtr   = vmcb->save.idtr;
3601         hsave->save.efer   = svm->vcpu.arch.efer;
3602         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3603         hsave->save.cr4    = svm->vcpu.arch.cr4;
3604         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3605         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3606         hsave->save.rsp    = vmcb->save.rsp;
3607         hsave->save.rax    = vmcb->save.rax;
3608         if (npt_enabled)
3609                 hsave->save.cr3    = vmcb->save.cr3;
3610         else
3611                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3612
3613         copy_vmcb_control_area(hsave, vmcb);
3614
3615         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3616
3617         return true;
3618 }
3619
3620 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3621 {
3622         to_vmcb->save.fs = from_vmcb->save.fs;
3623         to_vmcb->save.gs = from_vmcb->save.gs;
3624         to_vmcb->save.tr = from_vmcb->save.tr;
3625         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3626         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3627         to_vmcb->save.star = from_vmcb->save.star;
3628         to_vmcb->save.lstar = from_vmcb->save.lstar;
3629         to_vmcb->save.cstar = from_vmcb->save.cstar;
3630         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3631         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3632         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3633         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3634 }
3635
3636 static int vmload_interception(struct vcpu_svm *svm)
3637 {
3638         struct vmcb *nested_vmcb;
3639         struct page *page;
3640         int ret;
3641
3642         if (nested_svm_check_permissions(svm))
3643                 return 1;
3644
3645         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3646         if (!nested_vmcb)
3647                 return 1;
3648
3649         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3650         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3651
3652         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3653         nested_svm_unmap(page);
3654
3655         return ret;
3656 }
3657
3658 static int vmsave_interception(struct vcpu_svm *svm)
3659 {
3660         struct vmcb *nested_vmcb;
3661         struct page *page;
3662         int ret;
3663
3664         if (nested_svm_check_permissions(svm))
3665                 return 1;
3666
3667         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3668         if (!nested_vmcb)
3669                 return 1;
3670
3671         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3672         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3673
3674         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3675         nested_svm_unmap(page);
3676
3677         return ret;
3678 }
3679
3680 static int vmrun_interception(struct vcpu_svm *svm)
3681 {
3682         if (nested_svm_check_permissions(svm))
3683                 return 1;
3684
3685         /* Save rip after vmrun instruction */
3686         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3687
3688         if (!nested_svm_vmrun(svm))
3689                 return 1;
3690
3691         if (!nested_svm_vmrun_msrpm(svm))
3692                 goto failed;
3693
3694         return 1;
3695
3696 failed:
3697
3698         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3699         svm->vmcb->control.exit_code_hi = 0;
3700         svm->vmcb->control.exit_info_1  = 0;
3701         svm->vmcb->control.exit_info_2  = 0;
3702
3703         nested_svm_vmexit(svm);
3704
3705         return 1;
3706 }
3707
3708 static int stgi_interception(struct vcpu_svm *svm)
3709 {
3710         int ret;
3711
3712         if (nested_svm_check_permissions(svm))
3713                 return 1;
3714
3715         /*
3716          * If VGIF is enabled, the STGI intercept is only added to
3717          * detect the opening of the SMI/NMI window; remove it now.
3718          */
3719         if (vgif_enabled(svm))
3720                 clr_intercept(svm, INTERCEPT_STGI);
3721
3722         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3723         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3724         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3725
3726         enable_gif(svm);
3727
3728         return ret;
3729 }
3730
3731 static int clgi_interception(struct vcpu_svm *svm)
3732 {
3733         int ret;
3734
3735         if (nested_svm_check_permissions(svm))
3736                 return 1;
3737
3738         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3739         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3740
3741         disable_gif(svm);
3742
3743         /* After a CLGI no interrupts should come */
3744         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3745                 svm_clear_vintr(svm);
3746                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3747                 mark_dirty(svm->vmcb, VMCB_INTR);
3748         }
3749
3750         return ret;
3751 }
3752
3753 static int invlpga_interception(struct vcpu_svm *svm)
3754 {
3755         struct kvm_vcpu *vcpu = &svm->vcpu;
3756
3757         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3758                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3759
3760         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3761         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3762
3763         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3764         return kvm_skip_emulated_instruction(&svm->vcpu);
3765 }
3766
3767 static int skinit_interception(struct vcpu_svm *svm)
3768 {
3769         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3770
3771         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3772         return 1;
3773 }
3774
3775 static int wbinvd_interception(struct vcpu_svm *svm)
3776 {
3777         return kvm_emulate_wbinvd(&svm->vcpu);
3778 }
3779
3780 static int xsetbv_interception(struct vcpu_svm *svm)
3781 {
3782         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3783         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3784
3785         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3786                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3787                 return kvm_skip_emulated_instruction(&svm->vcpu);
3788         }
3789
3790         return 1;
3791 }
3792
3793 static int task_switch_interception(struct vcpu_svm *svm)
3794 {
3795         u16 tss_selector;
3796         int reason;
3797         int int_type = svm->vmcb->control.exit_int_info &
3798                 SVM_EXITINTINFO_TYPE_MASK;
3799         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3800         uint32_t type =
3801                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3802         uint32_t idt_v =
3803                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3804         bool has_error_code = false;
3805         u32 error_code = 0;
3806
3807         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3808
3809         if (svm->vmcb->control.exit_info_2 &
3810             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3811                 reason = TASK_SWITCH_IRET;
3812         else if (svm->vmcb->control.exit_info_2 &
3813                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3814                 reason = TASK_SWITCH_JMP;
3815         else if (idt_v)
3816                 reason = TASK_SWITCH_GATE;
3817         else
3818                 reason = TASK_SWITCH_CALL;
3819
3820         if (reason == TASK_SWITCH_GATE) {
3821                 switch (type) {
3822                 case SVM_EXITINTINFO_TYPE_NMI:
3823                         svm->vcpu.arch.nmi_injected = false;
3824                         break;
3825                 case SVM_EXITINTINFO_TYPE_EXEPT:
3826                         if (svm->vmcb->control.exit_info_2 &
3827                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3828                                 has_error_code = true;
3829                                 error_code =
3830                                         (u32)svm->vmcb->control.exit_info_2;
3831                         }
3832                         kvm_clear_exception_queue(&svm->vcpu);
3833                         break;
3834                 case SVM_EXITINTINFO_TYPE_INTR:
3835                         kvm_clear_interrupt_queue(&svm->vcpu);
3836                         break;
3837                 default:
3838                         break;
3839                 }
3840         }
3841
3842         if (reason != TASK_SWITCH_GATE ||
3843             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3844             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3845              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3846                 skip_emulated_instruction(&svm->vcpu);
3847
3848         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3849                 int_vec = -1;
3850
3851         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3852                                 has_error_code, error_code) == EMULATE_FAIL) {
3853                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3854                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3855                 svm->vcpu.run->internal.ndata = 0;
3856                 return 0;
3857         }
3858         return 1;
3859 }
3860
3861 static int cpuid_interception(struct vcpu_svm *svm)
3862 {
3863         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3864         return kvm_emulate_cpuid(&svm->vcpu);
3865 }
3866
3867 static int iret_interception(struct vcpu_svm *svm)
3868 {
3869         ++svm->vcpu.stat.nmi_window_exits;
3870         clr_intercept(svm, INTERCEPT_IRET);
3871         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3872         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3873         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3874         return 1;
3875 }
3876
3877 static int invlpg_interception(struct vcpu_svm *svm)
3878 {
3879         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3880                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3881
3882         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3883         return kvm_skip_emulated_instruction(&svm->vcpu);
3884 }
3885
3886 static int emulate_on_interception(struct vcpu_svm *svm)
3887 {
3888         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3889 }
3890
3891 static int rsm_interception(struct vcpu_svm *svm)
3892 {
3893         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3894                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3895 }
3896
3897 static int rdpmc_interception(struct vcpu_svm *svm)
3898 {
3899         int err;
3900
3901         if (!static_cpu_has(X86_FEATURE_NRIPS))
3902                 return emulate_on_interception(svm);
3903
3904         err = kvm_rdpmc(&svm->vcpu);
3905         return kvm_complete_insn_gp(&svm->vcpu, err);
3906 }
3907
3908 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3909                                             unsigned long val)
3910 {
3911         unsigned long cr0 = svm->vcpu.arch.cr0;
3912         bool ret = false;
3913         u64 intercept;
3914
3915         intercept = svm->nested.intercept;
3916
3917         if (!is_guest_mode(&svm->vcpu) ||
3918             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3919                 return false;
3920
3921         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3922         val &= ~SVM_CR0_SELECTIVE_MASK;
3923
3924         if (cr0 ^ val) {
3925                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3926                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3927         }
3928
3929         return ret;
3930 }
3931
3932 #define CR_VALID (1ULL << 63)
3933
3934 static int cr_interception(struct vcpu_svm *svm)
3935 {
3936         int reg, cr;
3937         unsigned long val;
3938         int err;
3939
3940         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3941                 return emulate_on_interception(svm);
3942
3943         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3944                 return emulate_on_interception(svm);
3945
3946         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3947         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3948                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3949         else
3950                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3951
3952         err = 0;
3953         if (cr >= 16) { /* mov to cr */
3954                 cr -= 16;
3955                 val = kvm_register_read(&svm->vcpu, reg);
3956                 switch (cr) {
3957                 case 0:
3958                         if (!check_selective_cr0_intercepted(svm, val))
3959                                 err = kvm_set_cr0(&svm->vcpu, val);
3960                         else
3961                                 return 1;
3962
3963                         break;
3964                 case 3:
3965                         err = kvm_set_cr3(&svm->vcpu, val);
3966                         break;
3967                 case 4:
3968                         err = kvm_set_cr4(&svm->vcpu, val);
3969                         break;
3970                 case 8:
3971                         err = kvm_set_cr8(&svm->vcpu, val);
3972                         break;
3973                 default:
3974                         WARN(1, "unhandled write to CR%d", cr);
3975                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3976                         return 1;
3977                 }
3978         } else { /* mov from cr */
3979                 switch (cr) {
3980                 case 0:
3981                         val = kvm_read_cr0(&svm->vcpu);
3982                         break;
3983                 case 2:
3984                         val = svm->vcpu.arch.cr2;
3985                         break;
3986                 case 3:
3987                         val = kvm_read_cr3(&svm->vcpu);
3988                         break;
3989                 case 4:
3990                         val = kvm_read_cr4(&svm->vcpu);
3991                         break;
3992                 case 8:
3993                         val = kvm_get_cr8(&svm->vcpu);
3994                         break;
3995                 default:
3996                         WARN(1, "unhandled read from CR%d", cr);
3997                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3998                         return 1;
3999                 }
4000                 kvm_register_write(&svm->vcpu, reg, val);
4001         }
4002         return kvm_complete_insn_gp(&svm->vcpu, err);
4003 }
4004
4005 static int dr_interception(struct vcpu_svm *svm)
4006 {
4007         int reg, dr;
4008         unsigned long val;
4009
4010         if (svm->vcpu.guest_debug == 0) {
4011                 /*
4012                  * No more DR vmexits; force a reload of the debug registers
4013                  * and reenter on this instruction.  The next vmexit will
4014                  * retrieve the full state of the debug registers.
4015                  */
4016                 clr_dr_intercepts(svm);
4017                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4018                 return 1;
4019         }
4020
4021         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4022                 return emulate_on_interception(svm);
4023
4024         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4025         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4026
4027         if (dr >= 16) { /* mov to DRn */
4028                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4029                         return 1;
4030                 val = kvm_register_read(&svm->vcpu, reg);
4031                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4032         } else {
4033                 if (!kvm_require_dr(&svm->vcpu, dr))
4034                         return 1;
4035                 kvm_get_dr(&svm->vcpu, dr, &val);
4036                 kvm_register_write(&svm->vcpu, reg, val);
4037         }
4038
4039         return kvm_skip_emulated_instruction(&svm->vcpu);
4040 }
4041
4042 static int cr8_write_interception(struct vcpu_svm *svm)
4043 {
4044         struct kvm_run *kvm_run = svm->vcpu.run;
4045         int r;
4046
4047         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4048         /* instruction emulation calls kvm_set_cr8() */
4049         r = cr_interception(svm);
4050         if (lapic_in_kernel(&svm->vcpu))
4051                 return r;
4052         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4053                 return r;
4054         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4055         return 0;
4056 }
4057
4058 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4059 {
4060         msr->data = 0;
4061
4062         switch (msr->index) {
4063         case MSR_F10H_DECFG:
4064                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4065                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4066                 break;
4067         default:
4068                 return 1;
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4075 {
4076         struct vcpu_svm *svm = to_svm(vcpu);
4077
4078         switch (msr_info->index) {
4079         case MSR_STAR:
4080                 msr_info->data = svm->vmcb->save.star;
4081                 break;
4082 #ifdef CONFIG_X86_64
4083         case MSR_LSTAR:
4084                 msr_info->data = svm->vmcb->save.lstar;
4085                 break;
4086         case MSR_CSTAR:
4087                 msr_info->data = svm->vmcb->save.cstar;
4088                 break;
4089         case MSR_KERNEL_GS_BASE:
4090                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4091                 break;
4092         case MSR_SYSCALL_MASK:
4093                 msr_info->data = svm->vmcb->save.sfmask;
4094                 break;
4095 #endif
4096         case MSR_IA32_SYSENTER_CS:
4097                 msr_info->data = svm->vmcb->save.sysenter_cs;
4098                 break;
4099         case MSR_IA32_SYSENTER_EIP:
4100                 msr_info->data = svm->sysenter_eip;
4101                 break;
4102         case MSR_IA32_SYSENTER_ESP:
4103                 msr_info->data = svm->sysenter_esp;
4104                 break;
4105         case MSR_TSC_AUX:
4106                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4107                         return 1;
4108                 msr_info->data = svm->tsc_aux;
4109                 break;
4110         /*
4111          * Nobody will change the following 5 values in the VMCB so we can
4112          * safely return them on rdmsr. They will always be 0 until LBRV is
4113          * implemented.
4114          */
4115         case MSR_IA32_DEBUGCTLMSR:
4116                 msr_info->data = svm->vmcb->save.dbgctl;
4117                 break;
4118         case MSR_IA32_LASTBRANCHFROMIP:
4119                 msr_info->data = svm->vmcb->save.br_from;
4120                 break;
4121         case MSR_IA32_LASTBRANCHTOIP:
4122                 msr_info->data = svm->vmcb->save.br_to;
4123                 break;
4124         case MSR_IA32_LASTINTFROMIP:
4125                 msr_info->data = svm->vmcb->save.last_excp_from;
4126                 break;
4127         case MSR_IA32_LASTINTTOIP:
4128                 msr_info->data = svm->vmcb->save.last_excp_to;
4129                 break;
4130         case MSR_VM_HSAVE_PA:
4131                 msr_info->data = svm->nested.hsave_msr;
4132                 break;
4133         case MSR_VM_CR:
4134                 msr_info->data = svm->nested.vm_cr_msr;
4135                 break;
4136         case MSR_IA32_SPEC_CTRL:
4137                 if (!msr_info->host_initiated &&
4138                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4139                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4140                         return 1;
4141
4142                 msr_info->data = svm->spec_ctrl;
4143                 break;
4144         case MSR_AMD64_VIRT_SPEC_CTRL:
4145                 if (!msr_info->host_initiated &&
4146                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4147                         return 1;
4148
4149                 msr_info->data = svm->virt_spec_ctrl;
4150                 break;
4151         case MSR_F15H_IC_CFG: {
4152
4153                 int family, model;
4154
4155                 family = guest_cpuid_family(vcpu);
4156                 model  = guest_cpuid_model(vcpu);
4157
4158                 if (family < 0 || model < 0)
4159                         return kvm_get_msr_common(vcpu, msr_info);
4160
4161                 msr_info->data = 0;
4162
4163                 if (family == 0x15 &&
4164                     (model >= 0x2 && model < 0x20))
4165                         msr_info->data = 0x1E;
4166                 }
4167                 break;
4168         case MSR_F10H_DECFG:
4169                 msr_info->data = svm->msr_decfg;
4170                 break;
4171         default:
4172                 return kvm_get_msr_common(vcpu, msr_info);
4173         }
4174         return 0;
4175 }
4176
4177 static int rdmsr_interception(struct vcpu_svm *svm)
4178 {
4179         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4180         struct msr_data msr_info;
4181
4182         msr_info.index = ecx;
4183         msr_info.host_initiated = false;
4184         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4185                 trace_kvm_msr_read_ex(ecx);
4186                 kvm_inject_gp(&svm->vcpu, 0);
4187                 return 1;
4188         } else {
4189                 trace_kvm_msr_read(ecx, msr_info.data);
4190
4191                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4192                                    msr_info.data & 0xffffffff);
4193                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4194                                    msr_info.data >> 32);
4195                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4196                 return kvm_skip_emulated_instruction(&svm->vcpu);
4197         }
4198 }
4199
4200 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4201 {
4202         struct vcpu_svm *svm = to_svm(vcpu);
4203         int svm_dis, chg_mask;
4204
4205         if (data & ~SVM_VM_CR_VALID_MASK)
4206                 return 1;
4207
4208         chg_mask = SVM_VM_CR_VALID_MASK;
4209
4210         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4211                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4212
4213         svm->nested.vm_cr_msr &= ~chg_mask;
4214         svm->nested.vm_cr_msr |= (data & chg_mask);
4215
4216         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4217
4218         /* check for svm_disable while efer.svme is set */
4219         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4220                 return 1;
4221
4222         return 0;
4223 }
4224
4225 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4226 {
4227         struct vcpu_svm *svm = to_svm(vcpu);
4228
4229         u32 ecx = msr->index;
4230         u64 data = msr->data;
4231         switch (ecx) {
4232         case MSR_IA32_CR_PAT:
4233                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4234                         return 1;
4235                 vcpu->arch.pat = data;
4236                 svm->vmcb->save.g_pat = data;
4237                 mark_dirty(svm->vmcb, VMCB_NPT);
4238                 break;
4239         case MSR_IA32_SPEC_CTRL:
4240                 if (!msr->host_initiated &&
4241                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4242                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4243                         return 1;
4244
4245                 /* The STIBP bit doesn't fault even if it's not advertised */
4246                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4247                         return 1;
4248
4249                 svm->spec_ctrl = data;
4250
4251                 if (!data)
4252                         break;
4253
4254                 /*
4255                  * For non-nested:
4256                  * When it's written (to non-zero) for the first time, pass
4257                  * it through.
4258                  *
4259                  * For nested:
4260                  * The handling of the MSR bitmap for L2 guests is done in
4261                  * nested_svm_vmrun_msrpm.
4262                  * We update the L1 MSR bit as well since it will end up
4263                  * touching the MSR anyway now.
4264                  */
4265                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4266                 break;
4267         case MSR_IA32_PRED_CMD:
4268                 if (!msr->host_initiated &&
4269                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4270                         return 1;
4271
4272                 if (data & ~PRED_CMD_IBPB)
4273                         return 1;
4274
4275                 if (!data)
4276                         break;
4277
4278                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4279                 if (is_guest_mode(vcpu))
4280                         break;
4281                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4282                 break;
4283         case MSR_AMD64_VIRT_SPEC_CTRL:
4284                 if (!msr->host_initiated &&
4285                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4286                         return 1;
4287
4288                 if (data & ~SPEC_CTRL_SSBD)
4289                         return 1;
4290
4291                 svm->virt_spec_ctrl = data;
4292                 break;
4293         case MSR_STAR:
4294                 svm->vmcb->save.star = data;
4295                 break;
4296 #ifdef CONFIG_X86_64
4297         case MSR_LSTAR:
4298                 svm->vmcb->save.lstar = data;
4299                 break;
4300         case MSR_CSTAR:
4301                 svm->vmcb->save.cstar = data;
4302                 break;
4303         case MSR_KERNEL_GS_BASE:
4304                 svm->vmcb->save.kernel_gs_base = data;
4305                 break;
4306         case MSR_SYSCALL_MASK:
4307                 svm->vmcb->save.sfmask = data;
4308                 break;
4309 #endif
4310         case MSR_IA32_SYSENTER_CS:
4311                 svm->vmcb->save.sysenter_cs = data;
4312                 break;
4313         case MSR_IA32_SYSENTER_EIP:
4314                 svm->sysenter_eip = data;
4315                 svm->vmcb->save.sysenter_eip = data;
4316                 break;
4317         case MSR_IA32_SYSENTER_ESP:
4318                 svm->sysenter_esp = data;
4319                 svm->vmcb->save.sysenter_esp = data;
4320                 break;
4321         case MSR_TSC_AUX:
4322                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4323                         return 1;
4324
4325                 /*
4326                  * This is rare, so we update the MSR here instead of using
4327                  * direct_access_msrs.  Doing that would require a rdmsr in
4328                  * svm_vcpu_put.
4329                  */
4330                 svm->tsc_aux = data;
4331                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4332                 break;
4333         case MSR_IA32_DEBUGCTLMSR:
4334                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4335                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4336                                     __func__, data);
4337                         break;
4338                 }
4339                 if (data & DEBUGCTL_RESERVED_BITS)
4340                         return 1;
4341
4342                 svm->vmcb->save.dbgctl = data;
4343                 mark_dirty(svm->vmcb, VMCB_LBR);
4344                 if (data & (1ULL<<0))
4345                         svm_enable_lbrv(svm);
4346                 else
4347                         svm_disable_lbrv(svm);
4348                 break;
4349         case MSR_VM_HSAVE_PA:
4350                 svm->nested.hsave_msr = data;
4351                 break;
4352         case MSR_VM_CR:
4353                 return svm_set_vm_cr(vcpu, data);
4354         case MSR_VM_IGNNE:
4355                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4356                 break;
4357         case MSR_F10H_DECFG: {
4358                 struct kvm_msr_entry msr_entry;
4359
4360                 msr_entry.index = msr->index;
4361                 if (svm_get_msr_feature(&msr_entry))
4362                         return 1;
4363
4364                 /* Check the supported bits */
4365                 if (data & ~msr_entry.data)
4366                         return 1;
4367
4368                 /* Don't allow the guest to change a bit, #GP */
4369                 if (!msr->host_initiated && (data ^ msr_entry.data))
4370                         return 1;
4371
4372                 svm->msr_decfg = data;
4373                 break;
4374         }
4375         case MSR_IA32_APICBASE:
4376                 if (kvm_vcpu_apicv_active(vcpu))
4377                         avic_update_vapic_bar(to_svm(vcpu), data);
4378                 /* Follow through */
4379         default:
4380                 return kvm_set_msr_common(vcpu, msr);
4381         }
4382         return 0;
4383 }
4384
4385 static int wrmsr_interception(struct vcpu_svm *svm)
4386 {
4387         struct msr_data msr;
4388         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4389         u64 data = kvm_read_edx_eax(&svm->vcpu);
4390
4391         msr.data = data;
4392         msr.index = ecx;
4393         msr.host_initiated = false;
4394
4395         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4396         if (kvm_set_msr(&svm->vcpu, &msr)) {
4397                 trace_kvm_msr_write_ex(ecx, data);
4398                 kvm_inject_gp(&svm->vcpu, 0);
4399                 return 1;
4400         } else {
4401                 trace_kvm_msr_write(ecx, data);
4402                 return kvm_skip_emulated_instruction(&svm->vcpu);
4403         }
4404 }
4405
4406 static int msr_interception(struct vcpu_svm *svm)
4407 {
4408         if (svm->vmcb->control.exit_info_1)
4409                 return wrmsr_interception(svm);
4410         else
4411                 return rdmsr_interception(svm);
4412 }
4413
4414 static int interrupt_window_interception(struct vcpu_svm *svm)
4415 {
4416         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4417         svm_clear_vintr(svm);
4418         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4419         mark_dirty(svm->vmcb, VMCB_INTR);
4420         ++svm->vcpu.stat.irq_window_exits;
4421         return 1;
4422 }
4423
4424 static int pause_interception(struct vcpu_svm *svm)
4425 {
4426         struct kvm_vcpu *vcpu = &svm->vcpu;
4427         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4428
4429         if (pause_filter_thresh)
4430                 grow_ple_window(vcpu);
4431
4432         kvm_vcpu_on_spin(vcpu, in_kernel);
4433         return 1;
4434 }
4435
4436 static int nop_interception(struct vcpu_svm *svm)
4437 {
4438         return kvm_skip_emulated_instruction(&(svm->vcpu));
4439 }
4440
4441 static int monitor_interception(struct vcpu_svm *svm)
4442 {
4443         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4444         return nop_interception(svm);
4445 }
4446
4447 static int mwait_interception(struct vcpu_svm *svm)
4448 {
4449         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4450         return nop_interception(svm);
4451 }
4452
4453 enum avic_ipi_failure_cause {
4454         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4455         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4456         AVIC_IPI_FAILURE_INVALID_TARGET,
4457         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4458 };
4459
4460 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4461 {
4462         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4463         u32 icrl = svm->vmcb->control.exit_info_1;
4464         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4465         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4466         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4467
4468         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4469
4470         switch (id) {
4471         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4472                 /*
4473                  * AVIC hardware handles the generation of
4474                  * IPIs when the specified Message Type is Fixed
4475                  * (also known as fixed delivery mode) and
4476                  * the Trigger Mode is edge-triggered. The hardware
4477                  * also supports self and broadcast delivery modes
4478                  * specified via the Destination Shorthand(DSH)
4479                  * field of the ICRL. Logical and physical APIC ID
4480                  * formats are supported. All other IPI types cause
4481                  * a #VMEXIT, which needs to emulated.
4482                  */
4483                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4484                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4485                 break;
4486         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4487                 int i;
4488                 struct kvm_vcpu *vcpu;
4489                 struct kvm *kvm = svm->vcpu.kvm;
4490                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4491
4492                 /*
4493                  * At this point, we expect that the AVIC HW has already
4494                  * set the appropriate IRR bits on the valid target
4495                  * vcpus. So, we just need to kick the appropriate vcpu.
4496                  */
4497                 kvm_for_each_vcpu(i, vcpu, kvm) {
4498                         bool m = kvm_apic_match_dest(vcpu, apic,
4499                                                      icrl & KVM_APIC_SHORT_MASK,
4500                                                      GET_APIC_DEST_FIELD(icrh),
4501                                                      icrl & KVM_APIC_DEST_MASK);
4502
4503                         if (m && !avic_vcpu_is_running(vcpu))
4504                                 kvm_vcpu_wake_up(vcpu);
4505                 }
4506                 break;
4507         }
4508         case AVIC_IPI_FAILURE_INVALID_TARGET:
4509                 break;
4510         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4511                 WARN_ONCE(1, "Invalid backing page\n");
4512                 break;
4513         default:
4514                 pr_err("Unknown IPI interception\n");
4515         }
4516
4517         return 1;
4518 }
4519
4520 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4521 {
4522         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4523         int index;
4524         u32 *logical_apic_id_table;
4525         int dlid = GET_APIC_LOGICAL_ID(ldr);
4526
4527         if (!dlid)
4528                 return NULL;
4529
4530         if (flat) { /* flat */
4531                 index = ffs(dlid) - 1;
4532                 if (index > 7)
4533                         return NULL;
4534         } else { /* cluster */
4535                 int cluster = (dlid & 0xf0) >> 4;
4536                 int apic = ffs(dlid & 0x0f) - 1;
4537
4538                 if ((apic < 0) || (apic > 7) ||
4539                     (cluster >= 0xf))
4540                         return NULL;
4541                 index = (cluster << 2) + apic;
4542         }
4543
4544         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4545
4546         return &logical_apic_id_table[index];
4547 }
4548
4549 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4550                           bool valid)
4551 {
4552         bool flat;
4553         u32 *entry, new_entry;
4554
4555         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4556         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4557         if (!entry)
4558                 return -EINVAL;
4559
4560         new_entry = READ_ONCE(*entry);
4561         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4562         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4563         if (valid)
4564                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4565         else
4566                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4567         WRITE_ONCE(*entry, new_entry);
4568
4569         return 0;
4570 }
4571
4572 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4573 {
4574         int ret;
4575         struct vcpu_svm *svm = to_svm(vcpu);
4576         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4577
4578         if (!ldr)
4579                 return 1;
4580
4581         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4582         if (ret && svm->ldr_reg) {
4583                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4584                 svm->ldr_reg = 0;
4585         } else {
4586                 svm->ldr_reg = ldr;
4587         }
4588         return ret;
4589 }
4590
4591 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4592 {
4593         u64 *old, *new;
4594         struct vcpu_svm *svm = to_svm(vcpu);
4595         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4596         u32 id = (apic_id_reg >> 24) & 0xff;
4597
4598         if (vcpu->vcpu_id == id)
4599                 return 0;
4600
4601         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4602         new = avic_get_physical_id_entry(vcpu, id);
4603         if (!new || !old)
4604                 return 1;
4605
4606         /* We need to move physical_id_entry to new offset */
4607         *new = *old;
4608         *old = 0ULL;
4609         to_svm(vcpu)->avic_physical_id_cache = new;
4610
4611         /*
4612          * Also update the guest physical APIC ID in the logical
4613          * APIC ID table entry if already setup the LDR.
4614          */
4615         if (svm->ldr_reg)
4616                 avic_handle_ldr_update(vcpu);
4617
4618         return 0;
4619 }
4620
4621 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4622 {
4623         struct vcpu_svm *svm = to_svm(vcpu);
4624         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4625         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4626         u32 mod = (dfr >> 28) & 0xf;
4627
4628         /*
4629          * We assume that all local APICs are using the same type.
4630          * If this changes, we need to flush the AVIC logical
4631          * APID id table.
4632          */
4633         if (kvm_svm->ldr_mode == mod)
4634                 return 0;
4635
4636         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4637         kvm_svm->ldr_mode = mod;
4638
4639         if (svm->ldr_reg)
4640                 avic_handle_ldr_update(vcpu);
4641         return 0;
4642 }
4643
4644 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4645 {
4646         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4647         u32 offset = svm->vmcb->control.exit_info_1 &
4648                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4649
4650         switch (offset) {
4651         case APIC_ID:
4652                 if (avic_handle_apic_id_update(&svm->vcpu))
4653                         return 0;
4654                 break;
4655         case APIC_LDR:
4656                 if (avic_handle_ldr_update(&svm->vcpu))
4657                         return 0;
4658                 break;
4659         case APIC_DFR:
4660                 avic_handle_dfr_update(&svm->vcpu);
4661                 break;
4662         default:
4663                 break;
4664         }
4665
4666         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4667
4668         return 1;
4669 }
4670
4671 static bool is_avic_unaccelerated_access_trap(u32 offset)
4672 {
4673         bool ret = false;
4674
4675         switch (offset) {
4676         case APIC_ID:
4677         case APIC_EOI:
4678         case APIC_RRR:
4679         case APIC_LDR:
4680         case APIC_DFR:
4681         case APIC_SPIV:
4682         case APIC_ESR:
4683         case APIC_ICR:
4684         case APIC_LVTT:
4685         case APIC_LVTTHMR:
4686         case APIC_LVTPC:
4687         case APIC_LVT0:
4688         case APIC_LVT1:
4689         case APIC_LVTERR:
4690         case APIC_TMICT:
4691         case APIC_TDCR:
4692                 ret = true;
4693                 break;
4694         default:
4695                 break;
4696         }
4697         return ret;
4698 }
4699
4700 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4701 {
4702         int ret = 0;
4703         u32 offset = svm->vmcb->control.exit_info_1 &
4704                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4705         u32 vector = svm->vmcb->control.exit_info_2 &
4706                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4707         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4708                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4709         bool trap = is_avic_unaccelerated_access_trap(offset);
4710
4711         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4712                                             trap, write, vector);
4713         if (trap) {
4714                 /* Handling Trap */
4715                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4716                 ret = avic_unaccel_trap_write(svm);
4717         } else {
4718                 /* Handling Fault */
4719                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4720         }
4721
4722         return ret;
4723 }
4724
4725 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4726         [SVM_EXIT_READ_CR0]                     = cr_interception,
4727         [SVM_EXIT_READ_CR3]                     = cr_interception,
4728         [SVM_EXIT_READ_CR4]                     = cr_interception,
4729         [SVM_EXIT_READ_CR8]                     = cr_interception,
4730         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4731         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4732         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4733         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4734         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4735         [SVM_EXIT_READ_DR0]                     = dr_interception,
4736         [SVM_EXIT_READ_DR1]                     = dr_interception,
4737         [SVM_EXIT_READ_DR2]                     = dr_interception,
4738         [SVM_EXIT_READ_DR3]                     = dr_interception,
4739         [SVM_EXIT_READ_DR4]                     = dr_interception,
4740         [SVM_EXIT_READ_DR5]                     = dr_interception,
4741         [SVM_EXIT_READ_DR6]                     = dr_interception,
4742         [SVM_EXIT_READ_DR7]                     = dr_interception,
4743         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4744         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4745         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4746         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4747         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4748         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4749         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4750         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4751         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4752         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4753         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4754         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4755         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4756         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4757         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4758         [SVM_EXIT_INTR]                         = intr_interception,
4759         [SVM_EXIT_NMI]                          = nmi_interception,
4760         [SVM_EXIT_SMI]                          = nop_on_interception,
4761         [SVM_EXIT_INIT]                         = nop_on_interception,
4762         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4763         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4764         [SVM_EXIT_CPUID]                        = cpuid_interception,
4765         [SVM_EXIT_IRET]                         = iret_interception,
4766         [SVM_EXIT_INVD]                         = emulate_on_interception,
4767         [SVM_EXIT_PAUSE]                        = pause_interception,
4768         [SVM_EXIT_HLT]                          = halt_interception,
4769         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4770         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4771         [SVM_EXIT_IOIO]                         = io_interception,
4772         [SVM_EXIT_MSR]                          = msr_interception,
4773         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4774         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4775         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4776         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4777         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4778         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4779         [SVM_EXIT_STGI]                         = stgi_interception,
4780         [SVM_EXIT_CLGI]                         = clgi_interception,
4781         [SVM_EXIT_SKINIT]                       = skinit_interception,
4782         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4783         [SVM_EXIT_MONITOR]                      = monitor_interception,
4784         [SVM_EXIT_MWAIT]                        = mwait_interception,
4785         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4786         [SVM_EXIT_NPF]                          = npf_interception,
4787         [SVM_EXIT_RSM]                          = rsm_interception,
4788         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4789         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4790 };
4791
4792 static void dump_vmcb(struct kvm_vcpu *vcpu)
4793 {
4794         struct vcpu_svm *svm = to_svm(vcpu);
4795         struct vmcb_control_area *control = &svm->vmcb->control;
4796         struct vmcb_save_area *save = &svm->vmcb->save;
4797
4798         pr_err("VMCB Control Area:\n");
4799         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4800         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4801         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4802         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4803         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4804         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4805         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4806         pr_err("%-20s%d\n", "pause filter threshold:",
4807                control->pause_filter_thresh);
4808         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4809         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4810         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4811         pr_err("%-20s%d\n", "asid:", control->asid);
4812         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4813         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4814         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4815         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4816         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4817         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4818         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4819         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4820         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4821         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4822         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4823         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4824         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4825         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4826         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4827         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4828         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4829         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4830         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4831         pr_err("VMCB State Save Area:\n");
4832         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4833                "es:",
4834                save->es.selector, save->es.attrib,
4835                save->es.limit, save->es.base);
4836         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4837                "cs:",
4838                save->cs.selector, save->cs.attrib,
4839                save->cs.limit, save->cs.base);
4840         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4841                "ss:",
4842                save->ss.selector, save->ss.attrib,
4843                save->ss.limit, save->ss.base);
4844         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4845                "ds:",
4846                save->ds.selector, save->ds.attrib,
4847                save->ds.limit, save->ds.base);
4848         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4849                "fs:",
4850                save->fs.selector, save->fs.attrib,
4851                save->fs.limit, save->fs.base);
4852         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4853                "gs:",
4854                save->gs.selector, save->gs.attrib,
4855                save->gs.limit, save->gs.base);
4856         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4857                "gdtr:",
4858                save->gdtr.selector, save->gdtr.attrib,
4859                save->gdtr.limit, save->gdtr.base);
4860         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4861                "ldtr:",
4862                save->ldtr.selector, save->ldtr.attrib,
4863                save->ldtr.limit, save->ldtr.base);
4864         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4865                "idtr:",
4866                save->idtr.selector, save->idtr.attrib,
4867                save->idtr.limit, save->idtr.base);
4868         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4869                "tr:",
4870                save->tr.selector, save->tr.attrib,
4871                save->tr.limit, save->tr.base);
4872         pr_err("cpl:            %d                efer:         %016llx\n",
4873                 save->cpl, save->efer);
4874         pr_err("%-15s %016llx %-13s %016llx\n",
4875                "cr0:", save->cr0, "cr2:", save->cr2);
4876         pr_err("%-15s %016llx %-13s %016llx\n",
4877                "cr3:", save->cr3, "cr4:", save->cr4);
4878         pr_err("%-15s %016llx %-13s %016llx\n",
4879                "dr6:", save->dr6, "dr7:", save->dr7);
4880         pr_err("%-15s %016llx %-13s %016llx\n",
4881                "rip:", save->rip, "rflags:", save->rflags);
4882         pr_err("%-15s %016llx %-13s %016llx\n",
4883                "rsp:", save->rsp, "rax:", save->rax);
4884         pr_err("%-15s %016llx %-13s %016llx\n",
4885                "star:", save->star, "lstar:", save->lstar);
4886         pr_err("%-15s %016llx %-13s %016llx\n",
4887                "cstar:", save->cstar, "sfmask:", save->sfmask);
4888         pr_err("%-15s %016llx %-13s %016llx\n",
4889                "kernel_gs_base:", save->kernel_gs_base,
4890                "sysenter_cs:", save->sysenter_cs);
4891         pr_err("%-15s %016llx %-13s %016llx\n",
4892                "sysenter_esp:", save->sysenter_esp,
4893                "sysenter_eip:", save->sysenter_eip);
4894         pr_err("%-15s %016llx %-13s %016llx\n",
4895                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4896         pr_err("%-15s %016llx %-13s %016llx\n",
4897                "br_from:", save->br_from, "br_to:", save->br_to);
4898         pr_err("%-15s %016llx %-13s %016llx\n",
4899                "excp_from:", save->last_excp_from,
4900                "excp_to:", save->last_excp_to);
4901 }
4902
4903 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4904 {
4905         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4906
4907         *info1 = control->exit_info_1;
4908         *info2 = control->exit_info_2;
4909 }
4910
4911 static int handle_exit(struct kvm_vcpu *vcpu)
4912 {
4913         struct vcpu_svm *svm = to_svm(vcpu);
4914         struct kvm_run *kvm_run = vcpu->run;
4915         u32 exit_code = svm->vmcb->control.exit_code;
4916
4917         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4918
4919         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4920                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4921         if (npt_enabled)
4922                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4923
4924         if (unlikely(svm->nested.exit_required)) {
4925                 nested_svm_vmexit(svm);
4926                 svm->nested.exit_required = false;
4927
4928                 return 1;
4929         }
4930
4931         if (is_guest_mode(vcpu)) {
4932                 int vmexit;
4933
4934                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4935                                         svm->vmcb->control.exit_info_1,
4936                                         svm->vmcb->control.exit_info_2,
4937                                         svm->vmcb->control.exit_int_info,
4938                                         svm->vmcb->control.exit_int_info_err,
4939                                         KVM_ISA_SVM);
4940
4941                 vmexit = nested_svm_exit_special(svm);
4942
4943                 if (vmexit == NESTED_EXIT_CONTINUE)
4944                         vmexit = nested_svm_exit_handled(svm);
4945
4946                 if (vmexit == NESTED_EXIT_DONE)
4947                         return 1;
4948         }
4949
4950         svm_complete_interrupts(svm);
4951
4952         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4953                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4954                 kvm_run->fail_entry.hardware_entry_failure_reason
4955                         = svm->vmcb->control.exit_code;
4956                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4957                 dump_vmcb(vcpu);
4958                 return 0;
4959         }
4960
4961         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4962             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4963             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4964             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4965                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4966                        "exit_code 0x%x\n",
4967                        __func__, svm->vmcb->control.exit_int_info,
4968                        exit_code);
4969
4970         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4971             || !svm_exit_handlers[exit_code]) {
4972                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4973                 kvm_queue_exception(vcpu, UD_VECTOR);
4974                 return 1;
4975         }
4976
4977         return svm_exit_handlers[exit_code](svm);
4978 }
4979
4980 static void reload_tss(struct kvm_vcpu *vcpu)
4981 {
4982         int cpu = raw_smp_processor_id();
4983
4984         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4985         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4986         load_TR_desc();
4987 }
4988
4989 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4990 {
4991         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4992         int asid = sev_get_asid(svm->vcpu.kvm);
4993
4994         /* Assign the asid allocated with this SEV guest */
4995         svm->vmcb->control.asid = asid;
4996
4997         /*
4998          * Flush guest TLB:
4999          *
5000          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5001          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5002          */
5003         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5004             svm->last_cpu == cpu)
5005                 return;
5006
5007         svm->last_cpu = cpu;
5008         sd->sev_vmcbs[asid] = svm->vmcb;
5009         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5010         mark_dirty(svm->vmcb, VMCB_ASID);
5011 }
5012
5013 static void pre_svm_run(struct vcpu_svm *svm)
5014 {
5015         int cpu = raw_smp_processor_id();
5016
5017         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5018
5019         if (sev_guest(svm->vcpu.kvm))
5020                 return pre_sev_run(svm, cpu);
5021
5022         /* FIXME: handle wraparound of asid_generation */
5023         if (svm->asid_generation != sd->asid_generation)
5024                 new_asid(svm, sd);
5025 }
5026
5027 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5028 {
5029         struct vcpu_svm *svm = to_svm(vcpu);
5030
5031         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5032         vcpu->arch.hflags |= HF_NMI_MASK;
5033         set_intercept(svm, INTERCEPT_IRET);
5034         ++vcpu->stat.nmi_injections;
5035 }
5036
5037 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5038 {
5039         struct vmcb_control_area *control;
5040
5041         /* The following fields are ignored when AVIC is enabled */
5042         control = &svm->vmcb->control;
5043         control->int_vector = irq;
5044         control->int_ctl &= ~V_INTR_PRIO_MASK;
5045         control->int_ctl |= V_IRQ_MASK |
5046                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5047         mark_dirty(svm->vmcb, VMCB_INTR);
5048 }
5049
5050 static void svm_set_irq(struct kvm_vcpu *vcpu)
5051 {
5052         struct vcpu_svm *svm = to_svm(vcpu);
5053
5054         BUG_ON(!(gif_set(svm)));
5055
5056         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5057         ++vcpu->stat.irq_injections;
5058
5059         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5060                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5061 }
5062
5063 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5064 {
5065         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5066 }
5067
5068 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5069 {
5070         struct vcpu_svm *svm = to_svm(vcpu);
5071
5072         if (svm_nested_virtualize_tpr(vcpu) ||
5073             kvm_vcpu_apicv_active(vcpu))
5074                 return;
5075
5076         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5077
5078         if (irr == -1)
5079                 return;
5080
5081         if (tpr >= irr)
5082                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5083 }
5084
5085 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5086 {
5087         return;
5088 }
5089
5090 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5091 {
5092         return avic && irqchip_split(vcpu->kvm);
5093 }
5094
5095 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5096 {
5097 }
5098
5099 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5100 {
5101 }
5102
5103 /* Note: Currently only used by Hyper-V. */
5104 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5105 {
5106         struct vcpu_svm *svm = to_svm(vcpu);
5107         struct vmcb *vmcb = svm->vmcb;
5108
5109         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5110                 return;
5111
5112         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5113         mark_dirty(vmcb, VMCB_INTR);
5114 }
5115
5116 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5117 {
5118         return;
5119 }
5120
5121 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5122 {
5123         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5124         smp_mb__after_atomic();
5125
5126         if (avic_vcpu_is_running(vcpu))
5127                 wrmsrl(SVM_AVIC_DOORBELL,
5128                        kvm_cpu_get_apicid(vcpu->cpu));
5129         else
5130                 kvm_vcpu_wake_up(vcpu);
5131 }
5132
5133 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5134 {
5135         unsigned long flags;
5136         struct amd_svm_iommu_ir *cur;
5137
5138         spin_lock_irqsave(&svm->ir_list_lock, flags);
5139         list_for_each_entry(cur, &svm->ir_list, node) {
5140                 if (cur->data != pi->ir_data)
5141                         continue;
5142                 list_del(&cur->node);
5143                 kfree(cur);
5144                 break;
5145         }
5146         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5147 }
5148
5149 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5150 {
5151         int ret = 0;
5152         unsigned long flags;
5153         struct amd_svm_iommu_ir *ir;
5154
5155         /**
5156          * In some cases, the existing irte is updaed and re-set,
5157          * so we need to check here if it's already been * added
5158          * to the ir_list.
5159          */
5160         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5161                 struct kvm *kvm = svm->vcpu.kvm;
5162                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5163                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5164                 struct vcpu_svm *prev_svm;
5165
5166                 if (!prev_vcpu) {
5167                         ret = -EINVAL;
5168                         goto out;
5169                 }
5170
5171                 prev_svm = to_svm(prev_vcpu);
5172                 svm_ir_list_del(prev_svm, pi);
5173         }
5174
5175         /**
5176          * Allocating new amd_iommu_pi_data, which will get
5177          * add to the per-vcpu ir_list.
5178          */
5179         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5180         if (!ir) {
5181                 ret = -ENOMEM;
5182                 goto out;
5183         }
5184         ir->data = pi->ir_data;
5185
5186         spin_lock_irqsave(&svm->ir_list_lock, flags);
5187         list_add(&ir->node, &svm->ir_list);
5188         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5189 out:
5190         return ret;
5191 }
5192
5193 /**
5194  * Note:
5195  * The HW cannot support posting multicast/broadcast
5196  * interrupts to a vCPU. So, we still use legacy interrupt
5197  * remapping for these kind of interrupts.
5198  *
5199  * For lowest-priority interrupts, we only support
5200  * those with single CPU as the destination, e.g. user
5201  * configures the interrupts via /proc/irq or uses
5202  * irqbalance to make the interrupts single-CPU.
5203  */
5204 static int
5205 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5206                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5207 {
5208         struct kvm_lapic_irq irq;
5209         struct kvm_vcpu *vcpu = NULL;
5210
5211         kvm_set_msi_irq(kvm, e, &irq);
5212
5213         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5214                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5215                          __func__, irq.vector);
5216                 return -1;
5217         }
5218
5219         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5220                  irq.vector);
5221         *svm = to_svm(vcpu);
5222         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5223         vcpu_info->vector = irq.vector;
5224
5225         return 0;
5226 }
5227
5228 /*
5229  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5230  *
5231  * @kvm: kvm
5232  * @host_irq: host irq of the interrupt
5233  * @guest_irq: gsi of the interrupt
5234  * @set: set or unset PI
5235  * returns 0 on success, < 0 on failure
5236  */
5237 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5238                               uint32_t guest_irq, bool set)
5239 {
5240         struct kvm_kernel_irq_routing_entry *e;
5241         struct kvm_irq_routing_table *irq_rt;
5242         int idx, ret = -EINVAL;
5243
5244         if (!kvm_arch_has_assigned_device(kvm) ||
5245             !irq_remapping_cap(IRQ_POSTING_CAP))
5246                 return 0;
5247
5248         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5249                  __func__, host_irq, guest_irq, set);
5250
5251         idx = srcu_read_lock(&kvm->irq_srcu);
5252         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5253         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5254
5255         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5256                 struct vcpu_data vcpu_info;
5257                 struct vcpu_svm *svm = NULL;
5258
5259                 if (e->type != KVM_IRQ_ROUTING_MSI)
5260                         continue;
5261
5262                 /**
5263                  * Here, we setup with legacy mode in the following cases:
5264                  * 1. When cannot target interrupt to a specific vcpu.
5265                  * 2. Unsetting posted interrupt.
5266                  * 3. APIC virtialization is disabled for the vcpu.
5267                  */
5268                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5269                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5270                         struct amd_iommu_pi_data pi;
5271
5272                         /* Try to enable guest_mode in IRTE */
5273                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5274                                             AVIC_HPA_MASK);
5275                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5276                                                      svm->vcpu.vcpu_id);
5277                         pi.is_guest_mode = true;
5278                         pi.vcpu_data = &vcpu_info;
5279                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5280
5281                         /**
5282                          * Here, we successfully setting up vcpu affinity in
5283                          * IOMMU guest mode. Now, we need to store the posted
5284                          * interrupt information in a per-vcpu ir_list so that
5285                          * we can reference to them directly when we update vcpu
5286                          * scheduling information in IOMMU irte.
5287                          */
5288                         if (!ret && pi.is_guest_mode)
5289                                 svm_ir_list_add(svm, &pi);
5290                 } else {
5291                         /* Use legacy mode in IRTE */
5292                         struct amd_iommu_pi_data pi;
5293
5294                         /**
5295                          * Here, pi is used to:
5296                          * - Tell IOMMU to use legacy mode for this interrupt.
5297                          * - Retrieve ga_tag of prior interrupt remapping data.
5298                          */
5299                         pi.is_guest_mode = false;
5300                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5301
5302                         /**
5303                          * Check if the posted interrupt was previously
5304                          * setup with the guest_mode by checking if the ga_tag
5305                          * was cached. If so, we need to clean up the per-vcpu
5306                          * ir_list.
5307                          */
5308                         if (!ret && pi.prev_ga_tag) {
5309                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5310                                 struct kvm_vcpu *vcpu;
5311
5312                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5313                                 if (vcpu)
5314                                         svm_ir_list_del(to_svm(vcpu), &pi);
5315                         }
5316                 }
5317
5318                 if (!ret && svm) {
5319                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5320                                                  e->gsi, vcpu_info.vector,
5321                                                  vcpu_info.pi_desc_addr, set);
5322                 }
5323
5324                 if (ret < 0) {
5325                         pr_err("%s: failed to update PI IRTE\n", __func__);
5326                         goto out;
5327                 }
5328         }
5329
5330         ret = 0;
5331 out:
5332         srcu_read_unlock(&kvm->irq_srcu, idx);
5333         return ret;
5334 }
5335
5336 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5337 {
5338         struct vcpu_svm *svm = to_svm(vcpu);
5339         struct vmcb *vmcb = svm->vmcb;
5340         int ret;
5341         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5342               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5343         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5344
5345         return ret;
5346 }
5347
5348 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5349 {
5350         struct vcpu_svm *svm = to_svm(vcpu);
5351
5352         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5353 }
5354
5355 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5356 {
5357         struct vcpu_svm *svm = to_svm(vcpu);
5358
5359         if (masked) {
5360                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5361                 set_intercept(svm, INTERCEPT_IRET);
5362         } else {
5363                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5364                 clr_intercept(svm, INTERCEPT_IRET);
5365         }
5366 }
5367
5368 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5369 {
5370         struct vcpu_svm *svm = to_svm(vcpu);
5371         struct vmcb *vmcb = svm->vmcb;
5372         int ret;
5373
5374         if (!gif_set(svm) ||
5375              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5376                 return 0;
5377
5378         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5379
5380         if (is_guest_mode(vcpu))
5381                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5382
5383         return ret;
5384 }
5385
5386 static void enable_irq_window(struct kvm_vcpu *vcpu)
5387 {
5388         struct vcpu_svm *svm = to_svm(vcpu);
5389
5390         if (kvm_vcpu_apicv_active(vcpu))
5391                 return;
5392
5393         /*
5394          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5395          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5396          * get that intercept, this function will be called again though and
5397          * we'll get the vintr intercept. However, if the vGIF feature is
5398          * enabled, the STGI interception will not occur. Enable the irq
5399          * window under the assumption that the hardware will set the GIF.
5400          */
5401         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5402                 svm_set_vintr(svm);
5403                 svm_inject_irq(svm, 0x0);
5404         }
5405 }
5406
5407 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5408 {
5409         struct vcpu_svm *svm = to_svm(vcpu);
5410
5411         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5412             == HF_NMI_MASK)
5413                 return; /* IRET will cause a vm exit */
5414
5415         if (!gif_set(svm)) {
5416                 if (vgif_enabled(svm))
5417                         set_intercept(svm, INTERCEPT_STGI);
5418                 return; /* STGI will cause a vm exit */
5419         }
5420
5421         if (svm->nested.exit_required)
5422                 return; /* we're not going to run the guest yet */
5423
5424         /*
5425          * Something prevents NMI from been injected. Single step over possible
5426          * problem (IRET or exception injection or interrupt shadow)
5427          */
5428         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5429         svm->nmi_singlestep = true;
5430         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5431 }
5432
5433 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5434 {
5435         return 0;
5436 }
5437
5438 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5439 {
5440         return 0;
5441 }
5442
5443 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5444 {
5445         struct vcpu_svm *svm = to_svm(vcpu);
5446
5447         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5448                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5449         else
5450                 svm->asid_generation--;
5451 }
5452
5453 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5454 {
5455         struct vcpu_svm *svm = to_svm(vcpu);
5456
5457         invlpga(gva, svm->vmcb->control.asid);
5458 }
5459
5460 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5461 {
5462 }
5463
5464 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5465 {
5466         struct vcpu_svm *svm = to_svm(vcpu);
5467
5468         if (svm_nested_virtualize_tpr(vcpu))
5469                 return;
5470
5471         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5472                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5473                 kvm_set_cr8(vcpu, cr8);
5474         }
5475 }
5476
5477 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5478 {
5479         struct vcpu_svm *svm = to_svm(vcpu);
5480         u64 cr8;
5481
5482         if (svm_nested_virtualize_tpr(vcpu) ||
5483             kvm_vcpu_apicv_active(vcpu))
5484                 return;
5485
5486         cr8 = kvm_get_cr8(vcpu);
5487         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5488         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5489 }
5490
5491 static void svm_complete_interrupts(struct vcpu_svm *svm)
5492 {
5493         u8 vector;
5494         int type;
5495         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5496         unsigned int3_injected = svm->int3_injected;
5497
5498         svm->int3_injected = 0;
5499
5500         /*
5501          * If we've made progress since setting HF_IRET_MASK, we've
5502          * executed an IRET and can allow NMI injection.
5503          */
5504         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5505             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5506                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5507                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5508         }
5509
5510         svm->vcpu.arch.nmi_injected = false;
5511         kvm_clear_exception_queue(&svm->vcpu);
5512         kvm_clear_interrupt_queue(&svm->vcpu);
5513
5514         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5515                 return;
5516
5517         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5518
5519         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5520         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5521
5522         switch (type) {
5523         case SVM_EXITINTINFO_TYPE_NMI:
5524                 svm->vcpu.arch.nmi_injected = true;
5525                 break;
5526         case SVM_EXITINTINFO_TYPE_EXEPT:
5527                 /*
5528                  * In case of software exceptions, do not reinject the vector,
5529                  * but re-execute the instruction instead. Rewind RIP first
5530                  * if we emulated INT3 before.
5531                  */
5532                 if (kvm_exception_is_soft(vector)) {
5533                         if (vector == BP_VECTOR && int3_injected &&
5534                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5535                                 kvm_rip_write(&svm->vcpu,
5536                                               kvm_rip_read(&svm->vcpu) -
5537                                               int3_injected);
5538                         break;
5539                 }
5540                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5541                         u32 err = svm->vmcb->control.exit_int_info_err;
5542                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5543
5544                 } else
5545                         kvm_requeue_exception(&svm->vcpu, vector);
5546                 break;
5547         case SVM_EXITINTINFO_TYPE_INTR:
5548                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5549                 break;
5550         default:
5551                 break;
5552         }
5553 }
5554
5555 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5556 {
5557         struct vcpu_svm *svm = to_svm(vcpu);
5558         struct vmcb_control_area *control = &svm->vmcb->control;
5559
5560         control->exit_int_info = control->event_inj;
5561         control->exit_int_info_err = control->event_inj_err;
5562         control->event_inj = 0;
5563         svm_complete_interrupts(svm);
5564 }
5565
5566 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5567 {
5568         struct vcpu_svm *svm = to_svm(vcpu);
5569
5570         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5571         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5572         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5573
5574         /*
5575          * A vmexit emulation is required before the vcpu can be executed
5576          * again.
5577          */
5578         if (unlikely(svm->nested.exit_required))
5579                 return;
5580
5581         /*
5582          * Disable singlestep if we're injecting an interrupt/exception.
5583          * We don't want our modified rflags to be pushed on the stack where
5584          * we might not be able to easily reset them if we disabled NMI
5585          * singlestep later.
5586          */
5587         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5588                 /*
5589                  * Event injection happens before external interrupts cause a
5590                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5591                  * is enough to force an immediate vmexit.
5592                  */
5593                 disable_nmi_singlestep(svm);
5594                 smp_send_reschedule(vcpu->cpu);
5595         }
5596
5597         pre_svm_run(svm);
5598
5599         sync_lapic_to_cr8(vcpu);
5600
5601         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5602
5603         clgi();
5604
5605         /*
5606          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5607          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5608          * is no need to worry about the conditional branch over the wrmsr
5609          * being speculatively taken.
5610          */
5611         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5612
5613         local_irq_enable();
5614
5615         asm volatile (
5616                 "push %%" _ASM_BP "; \n\t"
5617                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5618                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5619                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5620                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5621                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5622                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5623 #ifdef CONFIG_X86_64
5624                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5625                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5626                 "mov %c[r10](%[svm]), %%r10 \n\t"
5627                 "mov %c[r11](%[svm]), %%r11 \n\t"
5628                 "mov %c[r12](%[svm]), %%r12 \n\t"
5629                 "mov %c[r13](%[svm]), %%r13 \n\t"
5630                 "mov %c[r14](%[svm]), %%r14 \n\t"
5631                 "mov %c[r15](%[svm]), %%r15 \n\t"
5632 #endif
5633
5634                 /* Enter guest mode */
5635                 "push %%" _ASM_AX " \n\t"
5636                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5637                 __ex(SVM_VMLOAD) "\n\t"
5638                 __ex(SVM_VMRUN) "\n\t"
5639                 __ex(SVM_VMSAVE) "\n\t"
5640                 "pop %%" _ASM_AX " \n\t"
5641
5642                 /* Save guest registers, load host registers */
5643                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5644                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5645                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5646                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5647                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5648                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5649 #ifdef CONFIG_X86_64
5650                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5651                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5652                 "mov %%r10, %c[r10](%[svm]) \n\t"
5653                 "mov %%r11, %c[r11](%[svm]) \n\t"
5654                 "mov %%r12, %c[r12](%[svm]) \n\t"
5655                 "mov %%r13, %c[r13](%[svm]) \n\t"
5656                 "mov %%r14, %c[r14](%[svm]) \n\t"
5657                 "mov %%r15, %c[r15](%[svm]) \n\t"
5658                 /*
5659                 * Clear host registers marked as clobbered to prevent
5660                 * speculative use.
5661                 */
5662                 "xor %%r8d, %%r8d \n\t"
5663                 "xor %%r9d, %%r9d \n\t"
5664                 "xor %%r10d, %%r10d \n\t"
5665                 "xor %%r11d, %%r11d \n\t"
5666                 "xor %%r12d, %%r12d \n\t"
5667                 "xor %%r13d, %%r13d \n\t"
5668                 "xor %%r14d, %%r14d \n\t"
5669                 "xor %%r15d, %%r15d \n\t"
5670 #endif
5671                 "xor %%ebx, %%ebx \n\t"
5672                 "xor %%ecx, %%ecx \n\t"
5673                 "xor %%edx, %%edx \n\t"
5674                 "xor %%esi, %%esi \n\t"
5675                 "xor %%edi, %%edi \n\t"
5676                 "pop %%" _ASM_BP
5677                 :
5678                 : [svm]"a"(svm),
5679                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5680                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5681                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5682                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5683                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5684                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5685                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5686 #ifdef CONFIG_X86_64
5687                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5688                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5689                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5690                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5691                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5692                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5693                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5694                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5695 #endif
5696                 : "cc", "memory"
5697 #ifdef CONFIG_X86_64
5698                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5699                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5700 #else
5701                 , "ebx", "ecx", "edx", "esi", "edi"
5702 #endif
5703                 );
5704
5705         /* Eliminate branch target predictions from guest mode */
5706         vmexit_fill_RSB();
5707
5708 #ifdef CONFIG_X86_64
5709         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5710 #else
5711         loadsegment(fs, svm->host.fs);
5712 #ifndef CONFIG_X86_32_LAZY_GS
5713         loadsegment(gs, svm->host.gs);
5714 #endif
5715 #endif
5716
5717         /*
5718          * We do not use IBRS in the kernel. If this vCPU has used the
5719          * SPEC_CTRL MSR it may have left it on; save the value and
5720          * turn it off. This is much more efficient than blindly adding
5721          * it to the atomic save/restore list. Especially as the former
5722          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5723          *
5724          * For non-nested case:
5725          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5726          * save it.
5727          *
5728          * For nested case:
5729          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5730          * save it.
5731          */
5732         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5733                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5734
5735         reload_tss(vcpu);
5736
5737         local_irq_disable();
5738
5739         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5740
5741         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5742         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5743         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5744         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5745
5746         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5747                 kvm_before_interrupt(&svm->vcpu);
5748
5749         stgi();
5750
5751         /* Any pending NMI will happen here */
5752
5753         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5754                 kvm_after_interrupt(&svm->vcpu);
5755
5756         sync_cr8_to_lapic(vcpu);
5757
5758         svm->next_rip = 0;
5759
5760         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5761
5762         /* if exit due to PF check for async PF */
5763         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5764                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5765
5766         if (npt_enabled) {
5767                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5768                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5769         }
5770
5771         /*
5772          * We need to handle MC intercepts here before the vcpu has a chance to
5773          * change the physical cpu
5774          */
5775         if (unlikely(svm->vmcb->control.exit_code ==
5776                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5777                 svm_handle_mce(svm);
5778
5779         mark_all_clean(svm->vmcb);
5780 }
5781 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5782
5783 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5784 {
5785         struct vcpu_svm *svm = to_svm(vcpu);
5786
5787         svm->vmcb->save.cr3 = __sme_set(root);
5788         mark_dirty(svm->vmcb, VMCB_CR);
5789 }
5790
5791 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5792 {
5793         struct vcpu_svm *svm = to_svm(vcpu);
5794
5795         svm->vmcb->control.nested_cr3 = __sme_set(root);
5796         mark_dirty(svm->vmcb, VMCB_NPT);
5797
5798         /* Also sync guest cr3 here in case we live migrate */
5799         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5800         mark_dirty(svm->vmcb, VMCB_CR);
5801 }
5802
5803 static int is_disabled(void)
5804 {
5805         u64 vm_cr;
5806
5807         rdmsrl(MSR_VM_CR, vm_cr);
5808         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5809                 return 1;
5810
5811         return 0;
5812 }
5813
5814 static void
5815 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5816 {
5817         /*
5818          * Patch in the VMMCALL instruction:
5819          */
5820         hypercall[0] = 0x0f;
5821         hypercall[1] = 0x01;
5822         hypercall[2] = 0xd9;
5823 }
5824
5825 static void svm_check_processor_compat(void *rtn)
5826 {
5827         *(int *)rtn = 0;
5828 }
5829
5830 static bool svm_cpu_has_accelerated_tpr(void)
5831 {
5832         return false;
5833 }
5834
5835 static bool svm_has_emulated_msr(int index)
5836 {
5837         return true;
5838 }
5839
5840 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5841 {
5842         return 0;
5843 }
5844
5845 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5846 {
5847         struct vcpu_svm *svm = to_svm(vcpu);
5848
5849         /* Update nrips enabled cache */
5850         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5851
5852         if (!kvm_vcpu_apicv_active(vcpu))
5853                 return;
5854
5855         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5856 }
5857
5858 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5859 {
5860         switch (func) {
5861         case 0x1:
5862                 if (avic)
5863                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5864                 break;
5865         case 0x80000001:
5866                 if (nested)
5867                         entry->ecx |= (1 << 2); /* Set SVM bit */
5868                 break;
5869         case 0x8000000A:
5870                 entry->eax = 1; /* SVM revision 1 */
5871                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5872                                    ASID emulation to nested SVM */
5873                 entry->ecx = 0; /* Reserved */
5874                 entry->edx = 0; /* Per default do not support any
5875                                    additional features */
5876
5877                 /* Support next_rip if host supports it */
5878                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5879                         entry->edx |= SVM_FEATURE_NRIP;
5880
5881                 /* Support NPT for the guest if enabled */
5882                 if (npt_enabled)
5883                         entry->edx |= SVM_FEATURE_NPT;
5884
5885                 break;
5886         case 0x8000001F:
5887                 /* Support memory encryption cpuid if host supports it */
5888                 if (boot_cpu_has(X86_FEATURE_SEV))
5889                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5890                                 &entry->ecx, &entry->edx);
5891
5892         }
5893 }
5894
5895 static int svm_get_lpage_level(void)
5896 {
5897         return PT_PDPE_LEVEL;
5898 }
5899
5900 static bool svm_rdtscp_supported(void)
5901 {
5902         return boot_cpu_has(X86_FEATURE_RDTSCP);
5903 }
5904
5905 static bool svm_invpcid_supported(void)
5906 {
5907         return false;
5908 }
5909
5910 static bool svm_mpx_supported(void)
5911 {
5912         return false;
5913 }
5914
5915 static bool svm_xsaves_supported(void)
5916 {
5917         return false;
5918 }
5919
5920 static bool svm_umip_emulated(void)
5921 {
5922         return false;
5923 }
5924
5925 static bool svm_has_wbinvd_exit(void)
5926 {
5927         return true;
5928 }
5929
5930 #define PRE_EX(exit)  { .exit_code = (exit), \
5931                         .stage = X86_ICPT_PRE_EXCEPT, }
5932 #define POST_EX(exit) { .exit_code = (exit), \
5933                         .stage = X86_ICPT_POST_EXCEPT, }
5934 #define POST_MEM(exit) { .exit_code = (exit), \
5935                         .stage = X86_ICPT_POST_MEMACCESS, }
5936
5937 static const struct __x86_intercept {
5938         u32 exit_code;
5939         enum x86_intercept_stage stage;
5940 } x86_intercept_map[] = {
5941         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5942         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5943         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5944         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5945         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5946         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5947         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5948         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5949         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5950         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5951         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5952         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5953         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5954         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5955         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5956         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5957         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5958         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5959         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5960         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5961         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5962         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5963         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5964         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5965         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5966         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5967         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
5968         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
5969         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
5970         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
5971         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
5972         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
5973         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
5974         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
5975         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
5976         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
5977         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
5978         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
5979         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
5980         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
5981         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
5982         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
5983         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
5984         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
5985         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
5986         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
5987 };
5988
5989 #undef PRE_EX
5990 #undef POST_EX
5991 #undef POST_MEM
5992
5993 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5994                                struct x86_instruction_info *info,
5995                                enum x86_intercept_stage stage)
5996 {
5997         struct vcpu_svm *svm = to_svm(vcpu);
5998         int vmexit, ret = X86EMUL_CONTINUE;
5999         struct __x86_intercept icpt_info;
6000         struct vmcb *vmcb = svm->vmcb;
6001
6002         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6003                 goto out;
6004
6005         icpt_info = x86_intercept_map[info->intercept];
6006
6007         if (stage != icpt_info.stage)
6008                 goto out;
6009
6010         switch (icpt_info.exit_code) {
6011         case SVM_EXIT_READ_CR0:
6012                 if (info->intercept == x86_intercept_cr_read)
6013                         icpt_info.exit_code += info->modrm_reg;
6014                 break;
6015         case SVM_EXIT_WRITE_CR0: {
6016                 unsigned long cr0, val;
6017                 u64 intercept;
6018
6019                 if (info->intercept == x86_intercept_cr_write)
6020                         icpt_info.exit_code += info->modrm_reg;
6021
6022                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6023                     info->intercept == x86_intercept_clts)
6024                         break;
6025
6026                 intercept = svm->nested.intercept;
6027
6028                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6029                         break;
6030
6031                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6032                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6033
6034                 if (info->intercept == x86_intercept_lmsw) {
6035                         cr0 &= 0xfUL;
6036                         val &= 0xfUL;
6037                         /* lmsw can't clear PE - catch this here */
6038                         if (cr0 & X86_CR0_PE)
6039                                 val |= X86_CR0_PE;
6040                 }
6041
6042                 if (cr0 ^ val)
6043                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6044
6045                 break;
6046         }
6047         case SVM_EXIT_READ_DR0:
6048         case SVM_EXIT_WRITE_DR0:
6049                 icpt_info.exit_code += info->modrm_reg;
6050                 break;
6051         case SVM_EXIT_MSR:
6052                 if (info->intercept == x86_intercept_wrmsr)
6053                         vmcb->control.exit_info_1 = 1;
6054                 else
6055                         vmcb->control.exit_info_1 = 0;
6056                 break;
6057         case SVM_EXIT_PAUSE:
6058                 /*
6059                  * We get this for NOP only, but pause
6060                  * is rep not, check this here
6061                  */
6062                 if (info->rep_prefix != REPE_PREFIX)
6063                         goto out;
6064                 break;
6065         case SVM_EXIT_IOIO: {
6066                 u64 exit_info;
6067                 u32 bytes;
6068
6069                 if (info->intercept == x86_intercept_in ||
6070                     info->intercept == x86_intercept_ins) {
6071                         exit_info = ((info->src_val & 0xffff) << 16) |
6072                                 SVM_IOIO_TYPE_MASK;
6073                         bytes = info->dst_bytes;
6074                 } else {
6075                         exit_info = (info->dst_val & 0xffff) << 16;
6076                         bytes = info->src_bytes;
6077                 }
6078
6079                 if (info->intercept == x86_intercept_outs ||
6080                     info->intercept == x86_intercept_ins)
6081                         exit_info |= SVM_IOIO_STR_MASK;
6082
6083                 if (info->rep_prefix)
6084                         exit_info |= SVM_IOIO_REP_MASK;
6085
6086                 bytes = min(bytes, 4u);
6087
6088                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6089
6090                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6091
6092                 vmcb->control.exit_info_1 = exit_info;
6093                 vmcb->control.exit_info_2 = info->next_rip;
6094
6095                 break;
6096         }
6097         default:
6098                 break;
6099         }
6100
6101         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6102         if (static_cpu_has(X86_FEATURE_NRIPS))
6103                 vmcb->control.next_rip  = info->next_rip;
6104         vmcb->control.exit_code = icpt_info.exit_code;
6105         vmexit = nested_svm_exit_handled(svm);
6106
6107         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6108                                            : X86EMUL_CONTINUE;
6109
6110 out:
6111         return ret;
6112 }
6113
6114 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6115 {
6116         local_irq_enable();
6117         /*
6118          * We must have an instruction with interrupts enabled, so
6119          * the timer interrupt isn't delayed by the interrupt shadow.
6120          */
6121         asm("nop");
6122         local_irq_disable();
6123 }
6124
6125 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6126 {
6127         if (pause_filter_thresh)
6128                 shrink_ple_window(vcpu);
6129 }
6130
6131 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6132 {
6133         if (avic_handle_apic_id_update(vcpu) != 0)
6134                 return;
6135         if (avic_handle_dfr_update(vcpu) != 0)
6136                 return;
6137         avic_handle_ldr_update(vcpu);
6138 }
6139
6140 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6141 {
6142         /* [63:9] are reserved. */
6143         vcpu->arch.mcg_cap &= 0x1ff;
6144 }
6145
6146 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6147 {
6148         struct vcpu_svm *svm = to_svm(vcpu);
6149
6150         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6151         if (!gif_set(svm))
6152                 return 0;
6153
6154         if (is_guest_mode(&svm->vcpu) &&
6155             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6156                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6157                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6158                 svm->nested.exit_required = true;
6159                 return 0;
6160         }
6161
6162         return 1;
6163 }
6164
6165 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6166 {
6167         struct vcpu_svm *svm = to_svm(vcpu);
6168         int ret;
6169
6170         if (is_guest_mode(vcpu)) {
6171                 /* FED8h - SVM Guest */
6172                 put_smstate(u64, smstate, 0x7ed8, 1);
6173                 /* FEE0h - SVM Guest VMCB Physical Address */
6174                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6175
6176                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6177                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6178                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6179
6180                 ret = nested_svm_vmexit(svm);
6181                 if (ret)
6182                         return ret;
6183         }
6184         return 0;
6185 }
6186
6187 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6188 {
6189         struct vcpu_svm *svm = to_svm(vcpu);
6190         struct vmcb *nested_vmcb;
6191         struct page *page;
6192         struct {
6193                 u64 guest;
6194                 u64 vmcb;
6195         } svm_state_save;
6196         int ret;
6197
6198         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6199                                   sizeof(svm_state_save));
6200         if (ret)
6201                 return ret;
6202
6203         if (svm_state_save.guest) {
6204                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6205                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6206                 if (nested_vmcb)
6207                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6208                 else
6209                         ret = 1;
6210                 vcpu->arch.hflags |= HF_SMM_MASK;
6211         }
6212         return ret;
6213 }
6214
6215 static int enable_smi_window(struct kvm_vcpu *vcpu)
6216 {
6217         struct vcpu_svm *svm = to_svm(vcpu);
6218
6219         if (!gif_set(svm)) {
6220                 if (vgif_enabled(svm))
6221                         set_intercept(svm, INTERCEPT_STGI);
6222                 /* STGI will cause a vm exit */
6223                 return 1;
6224         }
6225         return 0;
6226 }
6227
6228 static int sev_asid_new(void)
6229 {
6230         int pos;
6231
6232         /*
6233          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6234          */
6235         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6236         if (pos >= max_sev_asid)
6237                 return -EBUSY;
6238
6239         set_bit(pos, sev_asid_bitmap);
6240         return pos + 1;
6241 }
6242
6243 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6244 {
6245         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6246         int asid, ret;
6247
6248         ret = -EBUSY;
6249         asid = sev_asid_new();
6250         if (asid < 0)
6251                 return ret;
6252
6253         ret = sev_platform_init(&argp->error);
6254         if (ret)
6255                 goto e_free;
6256
6257         sev->active = true;
6258         sev->asid = asid;
6259         INIT_LIST_HEAD(&sev->regions_list);
6260
6261         return 0;
6262
6263 e_free:
6264         __sev_asid_free(asid);
6265         return ret;
6266 }
6267
6268 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6269 {
6270         struct sev_data_activate *data;
6271         int asid = sev_get_asid(kvm);
6272         int ret;
6273
6274         wbinvd_on_all_cpus();
6275
6276         ret = sev_guest_df_flush(error);
6277         if (ret)
6278                 return ret;
6279
6280         data = kzalloc(sizeof(*data), GFP_KERNEL);
6281         if (!data)
6282                 return -ENOMEM;
6283
6284         /* activate ASID on the given handle */
6285         data->handle = handle;
6286         data->asid   = asid;
6287         ret = sev_guest_activate(data, error);
6288         kfree(data);
6289
6290         return ret;
6291 }
6292
6293 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6294 {
6295         struct fd f;
6296         int ret;
6297
6298         f = fdget(fd);
6299         if (!f.file)
6300                 return -EBADF;
6301
6302         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6303
6304         fdput(f);
6305         return ret;
6306 }
6307
6308 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6309 {
6310         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6311
6312         return __sev_issue_cmd(sev->fd, id, data, error);
6313 }
6314
6315 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6316 {
6317         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6318         struct sev_data_launch_start *start;
6319         struct kvm_sev_launch_start params;
6320         void *dh_blob, *session_blob;
6321         int *error = &argp->error;
6322         int ret;
6323
6324         if (!sev_guest(kvm))
6325                 return -ENOTTY;
6326
6327         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6328                 return -EFAULT;
6329
6330         start = kzalloc(sizeof(*start), GFP_KERNEL);
6331         if (!start)
6332                 return -ENOMEM;
6333
6334         dh_blob = NULL;
6335         if (params.dh_uaddr) {
6336                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6337                 if (IS_ERR(dh_blob)) {
6338                         ret = PTR_ERR(dh_blob);
6339                         goto e_free;
6340                 }
6341
6342                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6343                 start->dh_cert_len = params.dh_len;
6344         }
6345
6346         session_blob = NULL;
6347         if (params.session_uaddr) {
6348                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6349                 if (IS_ERR(session_blob)) {
6350                         ret = PTR_ERR(session_blob);
6351                         goto e_free_dh;
6352                 }
6353
6354                 start->session_address = __sme_set(__pa(session_blob));
6355                 start->session_len = params.session_len;
6356         }
6357
6358         start->handle = params.handle;
6359         start->policy = params.policy;
6360
6361         /* create memory encryption context */
6362         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6363         if (ret)
6364                 goto e_free_session;
6365
6366         /* Bind ASID to this guest */
6367         ret = sev_bind_asid(kvm, start->handle, error);
6368         if (ret)
6369                 goto e_free_session;
6370
6371         /* return handle to userspace */
6372         params.handle = start->handle;
6373         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6374                 sev_unbind_asid(kvm, start->handle);
6375                 ret = -EFAULT;
6376                 goto e_free_session;
6377         }
6378
6379         sev->handle = start->handle;
6380         sev->fd = argp->sev_fd;
6381
6382 e_free_session:
6383         kfree(session_blob);
6384 e_free_dh:
6385         kfree(dh_blob);
6386 e_free:
6387         kfree(start);
6388         return ret;
6389 }
6390
6391 static int get_num_contig_pages(int idx, struct page **inpages,
6392                                 unsigned long npages)
6393 {
6394         unsigned long paddr, next_paddr;
6395         int i = idx + 1, pages = 1;
6396
6397         /* find the number of contiguous pages starting from idx */
6398         paddr = __sme_page_pa(inpages[idx]);
6399         while (i < npages) {
6400                 next_paddr = __sme_page_pa(inpages[i++]);
6401                 if ((paddr + PAGE_SIZE) == next_paddr) {
6402                         pages++;
6403                         paddr = next_paddr;
6404                         continue;
6405                 }
6406                 break;
6407         }
6408
6409         return pages;
6410 }
6411
6412 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6413 {
6414         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6415         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6416         struct kvm_sev_launch_update_data params;
6417         struct sev_data_launch_update_data *data;
6418         struct page **inpages;
6419         int i, ret, pages;
6420
6421         if (!sev_guest(kvm))
6422                 return -ENOTTY;
6423
6424         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6425                 return -EFAULT;
6426
6427         data = kzalloc(sizeof(*data), GFP_KERNEL);
6428         if (!data)
6429                 return -ENOMEM;
6430
6431         vaddr = params.uaddr;
6432         size = params.len;
6433         vaddr_end = vaddr + size;
6434
6435         /* Lock the user memory. */
6436         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6437         if (!inpages) {
6438                 ret = -ENOMEM;
6439                 goto e_free;
6440         }
6441
6442         /*
6443          * The LAUNCH_UPDATE command will perform in-place encryption of the
6444          * memory content (i.e it will write the same memory region with C=1).
6445          * It's possible that the cache may contain the data with C=0, i.e.,
6446          * unencrypted so invalidate it first.
6447          */
6448         sev_clflush_pages(inpages, npages);
6449
6450         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6451                 int offset, len;
6452
6453                 /*
6454                  * If the user buffer is not page-aligned, calculate the offset
6455                  * within the page.
6456                  */
6457                 offset = vaddr & (PAGE_SIZE - 1);
6458
6459                 /* Calculate the number of pages that can be encrypted in one go. */
6460                 pages = get_num_contig_pages(i, inpages, npages);
6461
6462                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6463
6464                 data->handle = sev->handle;
6465                 data->len = len;
6466                 data->address = __sme_page_pa(inpages[i]) + offset;
6467                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6468                 if (ret)
6469                         goto e_unpin;
6470
6471                 size -= len;
6472                 next_vaddr = vaddr + len;
6473         }
6474
6475 e_unpin:
6476         /* content of memory is updated, mark pages dirty */
6477         for (i = 0; i < npages; i++) {
6478                 set_page_dirty_lock(inpages[i]);
6479                 mark_page_accessed(inpages[i]);
6480         }
6481         /* unlock the user pages */
6482         sev_unpin_memory(kvm, inpages, npages);
6483 e_free:
6484         kfree(data);
6485         return ret;
6486 }
6487
6488 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6489 {
6490         void __user *measure = (void __user *)(uintptr_t)argp->data;
6491         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6492         struct sev_data_launch_measure *data;
6493         struct kvm_sev_launch_measure params;
6494         void __user *p = NULL;
6495         void *blob = NULL;
6496         int ret;
6497
6498         if (!sev_guest(kvm))
6499                 return -ENOTTY;
6500
6501         if (copy_from_user(&params, measure, sizeof(params)))
6502                 return -EFAULT;
6503
6504         data = kzalloc(sizeof(*data), GFP_KERNEL);
6505         if (!data)
6506                 return -ENOMEM;
6507
6508         /* User wants to query the blob length */
6509         if (!params.len)
6510                 goto cmd;
6511
6512         p = (void __user *)(uintptr_t)params.uaddr;
6513         if (p) {
6514                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6515                         ret = -EINVAL;
6516                         goto e_free;
6517                 }
6518
6519                 ret = -ENOMEM;
6520                 blob = kmalloc(params.len, GFP_KERNEL);
6521                 if (!blob)
6522                         goto e_free;
6523
6524                 data->address = __psp_pa(blob);
6525                 data->len = params.len;
6526         }
6527
6528 cmd:
6529         data->handle = sev->handle;
6530         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6531
6532         /*
6533          * If we query the session length, FW responded with expected data.
6534          */
6535         if (!params.len)
6536                 goto done;
6537
6538         if (ret)
6539                 goto e_free_blob;
6540
6541         if (blob) {
6542                 if (copy_to_user(p, blob, params.len))
6543                         ret = -EFAULT;
6544         }
6545
6546 done:
6547         params.len = data->len;
6548         if (copy_to_user(measure, &params, sizeof(params)))
6549                 ret = -EFAULT;
6550 e_free_blob:
6551         kfree(blob);
6552 e_free:
6553         kfree(data);
6554         return ret;
6555 }
6556
6557 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6558 {
6559         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6560         struct sev_data_launch_finish *data;
6561         int ret;
6562
6563         if (!sev_guest(kvm))
6564                 return -ENOTTY;
6565
6566         data = kzalloc(sizeof(*data), GFP_KERNEL);
6567         if (!data)
6568                 return -ENOMEM;
6569
6570         data->handle = sev->handle;
6571         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6572
6573         kfree(data);
6574         return ret;
6575 }
6576
6577 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6578 {
6579         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6580         struct kvm_sev_guest_status params;
6581         struct sev_data_guest_status *data;
6582         int ret;
6583
6584         if (!sev_guest(kvm))
6585                 return -ENOTTY;
6586
6587         data = kzalloc(sizeof(*data), GFP_KERNEL);
6588         if (!data)
6589                 return -ENOMEM;
6590
6591         data->handle = sev->handle;
6592         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6593         if (ret)
6594                 goto e_free;
6595
6596         params.policy = data->policy;
6597         params.state = data->state;
6598         params.handle = data->handle;
6599
6600         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6601                 ret = -EFAULT;
6602 e_free:
6603         kfree(data);
6604         return ret;
6605 }
6606
6607 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6608                                unsigned long dst, int size,
6609                                int *error, bool enc)
6610 {
6611         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6612         struct sev_data_dbg *data;
6613         int ret;
6614
6615         data = kzalloc(sizeof(*data), GFP_KERNEL);
6616         if (!data)
6617                 return -ENOMEM;
6618
6619         data->handle = sev->handle;
6620         data->dst_addr = dst;
6621         data->src_addr = src;
6622         data->len = size;
6623
6624         ret = sev_issue_cmd(kvm,
6625                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6626                             data, error);
6627         kfree(data);
6628         return ret;
6629 }
6630
6631 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6632                              unsigned long dst_paddr, int sz, int *err)
6633 {
6634         int offset;
6635
6636         /*
6637          * Its safe to read more than we are asked, caller should ensure that
6638          * destination has enough space.
6639          */
6640         src_paddr = round_down(src_paddr, 16);
6641         offset = src_paddr & 15;
6642         sz = round_up(sz + offset, 16);
6643
6644         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6645 }
6646
6647 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6648                                   unsigned long __user dst_uaddr,
6649                                   unsigned long dst_paddr,
6650                                   int size, int *err)
6651 {
6652         struct page *tpage = NULL;
6653         int ret, offset;
6654
6655         /* if inputs are not 16-byte then use intermediate buffer */
6656         if (!IS_ALIGNED(dst_paddr, 16) ||
6657             !IS_ALIGNED(paddr,     16) ||
6658             !IS_ALIGNED(size,      16)) {
6659                 tpage = (void *)alloc_page(GFP_KERNEL);
6660                 if (!tpage)
6661                         return -ENOMEM;
6662
6663                 dst_paddr = __sme_page_pa(tpage);
6664         }
6665
6666         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6667         if (ret)
6668                 goto e_free;
6669
6670         if (tpage) {
6671                 offset = paddr & 15;
6672                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6673                                  page_address(tpage) + offset, size))
6674                         ret = -EFAULT;
6675         }
6676
6677 e_free:
6678         if (tpage)
6679                 __free_page(tpage);
6680
6681         return ret;
6682 }
6683
6684 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6685                                   unsigned long __user vaddr,
6686                                   unsigned long dst_paddr,
6687                                   unsigned long __user dst_vaddr,
6688                                   int size, int *error)
6689 {
6690         struct page *src_tpage = NULL;
6691         struct page *dst_tpage = NULL;
6692         int ret, len = size;
6693
6694         /* If source buffer is not aligned then use an intermediate buffer */
6695         if (!IS_ALIGNED(vaddr, 16)) {
6696                 src_tpage = alloc_page(GFP_KERNEL);
6697                 if (!src_tpage)
6698                         return -ENOMEM;
6699
6700                 if (copy_from_user(page_address(src_tpage),
6701                                 (void __user *)(uintptr_t)vaddr, size)) {
6702                         __free_page(src_tpage);
6703                         return -EFAULT;
6704                 }
6705
6706                 paddr = __sme_page_pa(src_tpage);
6707         }
6708
6709         /*
6710          *  If destination buffer or length is not aligned then do read-modify-write:
6711          *   - decrypt destination in an intermediate buffer
6712          *   - copy the source buffer in an intermediate buffer
6713          *   - use the intermediate buffer as source buffer
6714          */
6715         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6716                 int dst_offset;
6717
6718                 dst_tpage = alloc_page(GFP_KERNEL);
6719                 if (!dst_tpage) {
6720                         ret = -ENOMEM;
6721                         goto e_free;
6722                 }
6723
6724                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6725                                         __sme_page_pa(dst_tpage), size, error);
6726                 if (ret)
6727                         goto e_free;
6728
6729                 /*
6730                  *  If source is kernel buffer then use memcpy() otherwise
6731                  *  copy_from_user().
6732                  */
6733                 dst_offset = dst_paddr & 15;
6734
6735                 if (src_tpage)
6736                         memcpy(page_address(dst_tpage) + dst_offset,
6737                                page_address(src_tpage), size);
6738                 else {
6739                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6740                                            (void __user *)(uintptr_t)vaddr, size)) {
6741                                 ret = -EFAULT;
6742                                 goto e_free;
6743                         }
6744                 }
6745
6746                 paddr = __sme_page_pa(dst_tpage);
6747                 dst_paddr = round_down(dst_paddr, 16);
6748                 len = round_up(size, 16);
6749         }
6750
6751         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6752
6753 e_free:
6754         if (src_tpage)
6755                 __free_page(src_tpage);
6756         if (dst_tpage)
6757                 __free_page(dst_tpage);
6758         return ret;
6759 }
6760
6761 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6762 {
6763         unsigned long vaddr, vaddr_end, next_vaddr;
6764         unsigned long dst_vaddr;
6765         struct page **src_p, **dst_p;
6766         struct kvm_sev_dbg debug;
6767         unsigned long n;
6768         int ret, size;
6769
6770         if (!sev_guest(kvm))
6771                 return -ENOTTY;
6772
6773         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6774                 return -EFAULT;
6775
6776         vaddr = debug.src_uaddr;
6777         size = debug.len;
6778         vaddr_end = vaddr + size;
6779         dst_vaddr = debug.dst_uaddr;
6780
6781         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6782                 int len, s_off, d_off;
6783
6784                 /* lock userspace source and destination page */
6785                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6786                 if (!src_p)
6787                         return -EFAULT;
6788
6789                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6790                 if (!dst_p) {
6791                         sev_unpin_memory(kvm, src_p, n);
6792                         return -EFAULT;
6793                 }
6794
6795                 /*
6796                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6797                  * memory content (i.e it will write the same memory region with C=1).
6798                  * It's possible that the cache may contain the data with C=0, i.e.,
6799                  * unencrypted so invalidate it first.
6800                  */
6801                 sev_clflush_pages(src_p, 1);
6802                 sev_clflush_pages(dst_p, 1);
6803
6804                 /*
6805                  * Since user buffer may not be page aligned, calculate the
6806                  * offset within the page.
6807                  */
6808                 s_off = vaddr & ~PAGE_MASK;
6809                 d_off = dst_vaddr & ~PAGE_MASK;
6810                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6811
6812                 if (dec)
6813                         ret = __sev_dbg_decrypt_user(kvm,
6814                                                      __sme_page_pa(src_p[0]) + s_off,
6815                                                      dst_vaddr,
6816                                                      __sme_page_pa(dst_p[0]) + d_off,
6817                                                      len, &argp->error);
6818                 else
6819                         ret = __sev_dbg_encrypt_user(kvm,
6820                                                      __sme_page_pa(src_p[0]) + s_off,
6821                                                      vaddr,
6822                                                      __sme_page_pa(dst_p[0]) + d_off,
6823                                                      dst_vaddr,
6824                                                      len, &argp->error);
6825
6826                 sev_unpin_memory(kvm, src_p, 1);
6827                 sev_unpin_memory(kvm, dst_p, 1);
6828
6829                 if (ret)
6830                         goto err;
6831
6832                 next_vaddr = vaddr + len;
6833                 dst_vaddr = dst_vaddr + len;
6834                 size -= len;
6835         }
6836 err:
6837         return ret;
6838 }
6839
6840 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6841 {
6842         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6843         struct sev_data_launch_secret *data;
6844         struct kvm_sev_launch_secret params;
6845         struct page **pages;
6846         void *blob, *hdr;
6847         unsigned long n;
6848         int ret, offset;
6849
6850         if (!sev_guest(kvm))
6851                 return -ENOTTY;
6852
6853         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6854                 return -EFAULT;
6855
6856         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6857         if (!pages)
6858                 return -ENOMEM;
6859
6860         /*
6861          * The secret must be copied into contiguous memory region, lets verify
6862          * that userspace memory pages are contiguous before we issue command.
6863          */
6864         if (get_num_contig_pages(0, pages, n) != n) {
6865                 ret = -EINVAL;
6866                 goto e_unpin_memory;
6867         }
6868
6869         ret = -ENOMEM;
6870         data = kzalloc(sizeof(*data), GFP_KERNEL);
6871         if (!data)
6872                 goto e_unpin_memory;
6873
6874         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6875         data->guest_address = __sme_page_pa(pages[0]) + offset;
6876         data->guest_len = params.guest_len;
6877
6878         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6879         if (IS_ERR(blob)) {
6880                 ret = PTR_ERR(blob);
6881                 goto e_free;
6882         }
6883
6884         data->trans_address = __psp_pa(blob);
6885         data->trans_len = params.trans_len;
6886
6887         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6888         if (IS_ERR(hdr)) {
6889                 ret = PTR_ERR(hdr);
6890                 goto e_free_blob;
6891         }
6892         data->hdr_address = __psp_pa(hdr);
6893         data->hdr_len = params.hdr_len;
6894
6895         data->handle = sev->handle;
6896         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6897
6898         kfree(hdr);
6899
6900 e_free_blob:
6901         kfree(blob);
6902 e_free:
6903         kfree(data);
6904 e_unpin_memory:
6905         sev_unpin_memory(kvm, pages, n);
6906         return ret;
6907 }
6908
6909 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6910 {
6911         struct kvm_sev_cmd sev_cmd;
6912         int r;
6913
6914         if (!svm_sev_enabled())
6915                 return -ENOTTY;
6916
6917         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6918                 return -EFAULT;
6919
6920         mutex_lock(&kvm->lock);
6921
6922         switch (sev_cmd.id) {
6923         case KVM_SEV_INIT:
6924                 r = sev_guest_init(kvm, &sev_cmd);
6925                 break;
6926         case KVM_SEV_LAUNCH_START:
6927                 r = sev_launch_start(kvm, &sev_cmd);
6928                 break;
6929         case KVM_SEV_LAUNCH_UPDATE_DATA:
6930                 r = sev_launch_update_data(kvm, &sev_cmd);
6931                 break;
6932         case KVM_SEV_LAUNCH_MEASURE:
6933                 r = sev_launch_measure(kvm, &sev_cmd);
6934                 break;
6935         case KVM_SEV_LAUNCH_FINISH:
6936                 r = sev_launch_finish(kvm, &sev_cmd);
6937                 break;
6938         case KVM_SEV_GUEST_STATUS:
6939                 r = sev_guest_status(kvm, &sev_cmd);
6940                 break;
6941         case KVM_SEV_DBG_DECRYPT:
6942                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6943                 break;
6944         case KVM_SEV_DBG_ENCRYPT:
6945                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6946                 break;
6947         case KVM_SEV_LAUNCH_SECRET:
6948                 r = sev_launch_secret(kvm, &sev_cmd);
6949                 break;
6950         default:
6951                 r = -EINVAL;
6952                 goto out;
6953         }
6954
6955         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6956                 r = -EFAULT;
6957
6958 out:
6959         mutex_unlock(&kvm->lock);
6960         return r;
6961 }
6962
6963 static int svm_register_enc_region(struct kvm *kvm,
6964                                    struct kvm_enc_region *range)
6965 {
6966         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6967         struct enc_region *region;
6968         int ret = 0;
6969
6970         if (!sev_guest(kvm))
6971                 return -ENOTTY;
6972
6973         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
6974                 return -EINVAL;
6975
6976         region = kzalloc(sizeof(*region), GFP_KERNEL);
6977         if (!region)
6978                 return -ENOMEM;
6979
6980         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
6981         if (!region->pages) {
6982                 ret = -ENOMEM;
6983                 goto e_free;
6984         }
6985
6986         /*
6987          * The guest may change the memory encryption attribute from C=0 -> C=1
6988          * or vice versa for this memory range. Lets make sure caches are
6989          * flushed to ensure that guest data gets written into memory with
6990          * correct C-bit.
6991          */
6992         sev_clflush_pages(region->pages, region->npages);
6993
6994         region->uaddr = range->addr;
6995         region->size = range->size;
6996
6997         mutex_lock(&kvm->lock);
6998         list_add_tail(&region->list, &sev->regions_list);
6999         mutex_unlock(&kvm->lock);
7000
7001         return ret;
7002
7003 e_free:
7004         kfree(region);
7005         return ret;
7006 }
7007
7008 static struct enc_region *
7009 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7010 {
7011         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7012         struct list_head *head = &sev->regions_list;
7013         struct enc_region *i;
7014
7015         list_for_each_entry(i, head, list) {
7016                 if (i->uaddr == range->addr &&
7017                     i->size == range->size)
7018                         return i;
7019         }
7020
7021         return NULL;
7022 }
7023
7024
7025 static int svm_unregister_enc_region(struct kvm *kvm,
7026                                      struct kvm_enc_region *range)
7027 {
7028         struct enc_region *region;
7029         int ret;
7030
7031         mutex_lock(&kvm->lock);
7032
7033         if (!sev_guest(kvm)) {
7034                 ret = -ENOTTY;
7035                 goto failed;
7036         }
7037
7038         region = find_enc_region(kvm, range);
7039         if (!region) {
7040                 ret = -EINVAL;
7041                 goto failed;
7042         }
7043
7044         __unregister_enc_region_locked(kvm, region);
7045
7046         mutex_unlock(&kvm->lock);
7047         return 0;
7048
7049 failed:
7050         mutex_unlock(&kvm->lock);
7051         return ret;
7052 }
7053
7054 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7055                                    uint16_t *vmcs_version)
7056 {
7057         /* Intel-only feature */
7058         return -ENODEV;
7059 }
7060
7061 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7062         .cpu_has_kvm_support = has_svm,
7063         .disabled_by_bios = is_disabled,
7064         .hardware_setup = svm_hardware_setup,
7065         .hardware_unsetup = svm_hardware_unsetup,
7066         .check_processor_compatibility = svm_check_processor_compat,
7067         .hardware_enable = svm_hardware_enable,
7068         .hardware_disable = svm_hardware_disable,
7069         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7070         .has_emulated_msr = svm_has_emulated_msr,
7071
7072         .vcpu_create = svm_create_vcpu,
7073         .vcpu_free = svm_free_vcpu,
7074         .vcpu_reset = svm_vcpu_reset,
7075
7076         .vm_alloc = svm_vm_alloc,
7077         .vm_free = svm_vm_free,
7078         .vm_init = avic_vm_init,
7079         .vm_destroy = svm_vm_destroy,
7080
7081         .prepare_guest_switch = svm_prepare_guest_switch,
7082         .vcpu_load = svm_vcpu_load,
7083         .vcpu_put = svm_vcpu_put,
7084         .vcpu_blocking = svm_vcpu_blocking,
7085         .vcpu_unblocking = svm_vcpu_unblocking,
7086
7087         .update_bp_intercept = update_bp_intercept,
7088         .get_msr_feature = svm_get_msr_feature,
7089         .get_msr = svm_get_msr,
7090         .set_msr = svm_set_msr,
7091         .get_segment_base = svm_get_segment_base,
7092         .get_segment = svm_get_segment,
7093         .set_segment = svm_set_segment,
7094         .get_cpl = svm_get_cpl,
7095         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7096         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7097         .decache_cr3 = svm_decache_cr3,
7098         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7099         .set_cr0 = svm_set_cr0,
7100         .set_cr3 = svm_set_cr3,
7101         .set_cr4 = svm_set_cr4,
7102         .set_efer = svm_set_efer,
7103         .get_idt = svm_get_idt,
7104         .set_idt = svm_set_idt,
7105         .get_gdt = svm_get_gdt,
7106         .set_gdt = svm_set_gdt,
7107         .get_dr6 = svm_get_dr6,
7108         .set_dr6 = svm_set_dr6,
7109         .set_dr7 = svm_set_dr7,
7110         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7111         .cache_reg = svm_cache_reg,
7112         .get_rflags = svm_get_rflags,
7113         .set_rflags = svm_set_rflags,
7114
7115         .tlb_flush = svm_flush_tlb,
7116         .tlb_flush_gva = svm_flush_tlb_gva,
7117
7118         .run = svm_vcpu_run,
7119         .handle_exit = handle_exit,
7120         .skip_emulated_instruction = skip_emulated_instruction,
7121         .set_interrupt_shadow = svm_set_interrupt_shadow,
7122         .get_interrupt_shadow = svm_get_interrupt_shadow,
7123         .patch_hypercall = svm_patch_hypercall,
7124         .set_irq = svm_set_irq,
7125         .set_nmi = svm_inject_nmi,
7126         .queue_exception = svm_queue_exception,
7127         .cancel_injection = svm_cancel_injection,
7128         .interrupt_allowed = svm_interrupt_allowed,
7129         .nmi_allowed = svm_nmi_allowed,
7130         .get_nmi_mask = svm_get_nmi_mask,
7131         .set_nmi_mask = svm_set_nmi_mask,
7132         .enable_nmi_window = enable_nmi_window,
7133         .enable_irq_window = enable_irq_window,
7134         .update_cr8_intercept = update_cr8_intercept,
7135         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7136         .get_enable_apicv = svm_get_enable_apicv,
7137         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7138         .load_eoi_exitmap = svm_load_eoi_exitmap,
7139         .hwapic_irr_update = svm_hwapic_irr_update,
7140         .hwapic_isr_update = svm_hwapic_isr_update,
7141         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7142         .apicv_post_state_restore = avic_post_state_restore,
7143
7144         .set_tss_addr = svm_set_tss_addr,
7145         .set_identity_map_addr = svm_set_identity_map_addr,
7146         .get_tdp_level = get_npt_level,
7147         .get_mt_mask = svm_get_mt_mask,
7148
7149         .get_exit_info = svm_get_exit_info,
7150
7151         .get_lpage_level = svm_get_lpage_level,
7152
7153         .cpuid_update = svm_cpuid_update,
7154
7155         .rdtscp_supported = svm_rdtscp_supported,
7156         .invpcid_supported = svm_invpcid_supported,
7157         .mpx_supported = svm_mpx_supported,
7158         .xsaves_supported = svm_xsaves_supported,
7159         .umip_emulated = svm_umip_emulated,
7160
7161         .set_supported_cpuid = svm_set_supported_cpuid,
7162
7163         .has_wbinvd_exit = svm_has_wbinvd_exit,
7164
7165         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7166         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7167
7168         .set_tdp_cr3 = set_tdp_cr3,
7169
7170         .check_intercept = svm_check_intercept,
7171         .handle_external_intr = svm_handle_external_intr,
7172
7173         .request_immediate_exit = __kvm_request_immediate_exit,
7174
7175         .sched_in = svm_sched_in,
7176
7177         .pmu_ops = &amd_pmu_ops,
7178         .deliver_posted_interrupt = svm_deliver_avic_intr,
7179         .update_pi_irte = svm_update_pi_irte,
7180         .setup_mce = svm_setup_mce,
7181
7182         .smi_allowed = svm_smi_allowed,
7183         .pre_enter_smm = svm_pre_enter_smm,
7184         .pre_leave_smm = svm_pre_leave_smm,
7185         .enable_smi_window = enable_smi_window,
7186
7187         .mem_enc_op = svm_mem_enc_op,
7188         .mem_enc_reg_region = svm_register_enc_region,
7189         .mem_enc_unreg_region = svm_unregister_enc_region,
7190
7191         .nested_enable_evmcs = nested_enable_evmcs,
7192 };
7193
7194 static int __init svm_init(void)
7195 {
7196         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7197                         __alignof__(struct vcpu_svm), THIS_MODULE);
7198 }
7199
7200 static void __exit svm_exit(void)
7201 {
7202         kvm_exit();
7203 }
7204
7205 module_init(svm_init)
7206 module_exit(svm_exit)