drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 /**
   2  * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   3  *
   4  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   5  *
   6  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/stmmac.h>
  20 #include <linux/bitops.h>
  21 #include <linux/clk.h>
  22 #include <linux/phy.h>
  23 #include <linux/of_net.h>
  24 #include <linux/gpio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/delay.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33
  34 #include "stmmac_platform.h"
  35
  36 struct rk_priv_data {
  37         struct platform_device *pdev;
  38         int phy_iface;
  39         struct regulator *regulator;
  40
  41         bool clk_enabled;
  42         bool clock_input;
  43
  44         struct clk *clk_mac;
  45         struct clk *clk_mac_pll;
  46         struct clk *gmac_clkin;
  47         struct clk *mac_clk_rx;
  48         struct clk *mac_clk_tx;
  49         struct clk *clk_mac_ref;
  50         struct clk *clk_mac_refout;
  51         struct clk *aclk_mac;
  52         struct clk *pclk_mac;
  53
  54         int tx_delay;
  55         int rx_delay;
  56
  57         struct regmap *grf;
  58 };
  59
  60 #define HIWORD_UPDATE(val, mask, shift) \
  61                 ((val) << (shift) | (mask) << ((shift) + 16))
  62
  63 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  64 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  65
  66 #define RK3288_GRF_SOC_CON1     0x0248
  67 #define RK3288_GRF_SOC_CON3     0x0250
  68 #define RK3288_GRF_GPIO3D_E     0x01ec
  69 #define RK3288_GRF_GPIO4A_E     0x01f0
  70 #define RK3288_GRF_GPIO4B_E     0x01f4
  71
  72 /*RK3288_GRF_SOC_CON1*/
  73 #define GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
  74 #define GMAC_PHY_INTF_SEL_RMII  (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
  75 #define GMAC_FLOW_CTRL          GRF_BIT(9)
  76 #define GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
  77 #define GMAC_SPEED_10M          GRF_CLR_BIT(10)
  78 #define GMAC_SPEED_100M         GRF_BIT(10)
  79 #define GMAC_RMII_CLK_25M       GRF_BIT(11)
  80 #define GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
  81 #define GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
  82 #define GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
  83 #define GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
  84 #define GMAC_RMII_MODE          GRF_BIT(14)
  85 #define GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
  86
  87 /*RK3288_GRF_SOC_CON3*/
  88 #define GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
  89 #define GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
  90 #define GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
  91 #define GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
  92 #define GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
  93 #define GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
  94
  95 static void set_to_rgmii(struct rk_priv_data *bsp_priv,
  96                          int tx_delay, int rx_delay)
  97 {
  98         struct device *dev = &bsp_priv->pdev->dev;
  99
 100         if (IS_ERR(bsp_priv->grf)) {
 101                 dev_err(dev, "Missing rockchip,grf property\n");
 102                 return;
 103         }
 104
 105         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 106                      GMAC_PHY_INTF_SEL_RGMII | GMAC_RMII_MODE_CLR);
 107         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 108                      GMAC_RXCLK_DLY_ENABLE | GMAC_TXCLK_DLY_ENABLE |
 109                      GMAC_CLK_RX_DL_CFG(rx_delay) |
 110                      GMAC_CLK_TX_DL_CFG(tx_delay));
 111 }
 112
 113 static void set_to_rmii(struct rk_priv_data *bsp_priv)
 114 {
 115         struct device *dev = &bsp_priv->pdev->dev;
 116
 117         if (IS_ERR(bsp_priv->grf)) {
 118                 dev_err(dev, "Missing rockchip,grf property\n");
 119                 return;
 120         }
 121
 122         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 123                      GMAC_PHY_INTF_SEL_RMII | GMAC_RMII_MODE);
 124 }
 125
 126 static void set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 127 {
 128         struct device *dev = &bsp_priv->pdev->dev;
 129
 130         if (IS_ERR(bsp_priv->grf)) {
 131                 dev_err(dev, "Missing rockchip,grf property\n");
 132                 return;
 133         }
 134
 135         if (speed == 10)
 136                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_2_5M);
 137         else if (speed == 100)
 138                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_25M);
 139         else if (speed == 1000)
 140                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_125M);
 141         else
 142                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 143 }
 144
 145 static void set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 146 {
 147         struct device *dev = &bsp_priv->pdev->dev;
 148
 149         if (IS_ERR(bsp_priv->grf)) {
 150                 dev_err(dev, "Missing rockchip,grf property\n");
 151                 return;
 152         }
 153
 154         if (speed == 10) {
 155                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 156                              GMAC_RMII_CLK_2_5M | GMAC_SPEED_10M);
 157         } else if (speed == 100) {
 158                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 159                              GMAC_RMII_CLK_25M | GMAC_SPEED_100M);
 160         } else {
 161                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 162         }
 163 }
 164
 165 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 166 {
 167         struct device *dev = &bsp_priv->pdev->dev;
 168
 169         bsp_priv->clk_enabled = false;
 170
 171         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
 172         if (IS_ERR(bsp_priv->mac_clk_rx))
 173                 dev_err(dev, "cannot get clock %s\n",
 174                         "mac_clk_rx");
 175
 176         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
 177         if (IS_ERR(bsp_priv->mac_clk_tx))
 178                 dev_err(dev, "cannot get clock %s\n",
 179                         "mac_clk_tx");
 180
 181         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
 182         if (IS_ERR(bsp_priv->aclk_mac))
 183                 dev_err(dev, "cannot get clock %s\n",
 184                         "aclk_mac");
 185
 186         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
 187         if (IS_ERR(bsp_priv->pclk_mac))
 188                 dev_err(dev, "cannot get clock %s\n",
 189                         "pclk_mac");
 190
 191         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
 192         if (IS_ERR(bsp_priv->clk_mac))
 193                 dev_err(dev, "cannot get clock %s\n",
 194                         "stmmaceth");
 195
 196         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 197                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
 198                 if (IS_ERR(bsp_priv->clk_mac_ref))
 199                         dev_err(dev, "cannot get clock %s\n",
 200                                 "clk_mac_ref");
 201
 202                 if (!bsp_priv->clock_input) {
 203                         bsp_priv->clk_mac_refout =
 204                                 devm_clk_get(dev, "clk_mac_refout");
 205                         if (IS_ERR(bsp_priv->clk_mac_refout))
 206                                 dev_err(dev, "cannot get clock %s\n",
 207                                         "clk_mac_refout");
 208                 }
 209         }
 210
 211         if (bsp_priv->clock_input) {
 212                 dev_info(dev, "clock input from PHY\n");
 213         } else {
 214                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 215                         clk_set_rate(bsp_priv->clk_mac_pll, 50000000);
 216         }
 217
 218         return 0;
 219 }
 220
 221 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 222 {
 223         int phy_iface = phy_iface = bsp_priv->phy_iface;
 224
 225         if (enable) {
 226                 if (!bsp_priv->clk_enabled) {
 227                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 228                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 229                                         clk_prepare_enable(
 230                                                 bsp_priv->mac_clk_rx);
 231
 232                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 233                                         clk_prepare_enable(
 234                                                 bsp_priv->clk_mac_ref);
 235
 236                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 237                                         clk_prepare_enable(
 238                                                 bsp_priv->clk_mac_refout);
 239                         }
 240
 241                         if (!IS_ERR(bsp_priv->aclk_mac))
 242                                 clk_prepare_enable(bsp_priv->aclk_mac);
 243
 244                         if (!IS_ERR(bsp_priv->pclk_mac))
 245                                 clk_prepare_enable(bsp_priv->pclk_mac);
 246
 247                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 248                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
 249
 250                         /**
 251                          * if (!IS_ERR(bsp_priv->clk_mac))
 252                          *      clk_prepare_enable(bsp_priv->clk_mac);
 253                          */
 254                         mdelay(5);
 255                         bsp_priv->clk_enabled = true;
 256                 }
 257         } else {
 258                 if (bsp_priv->clk_enabled) {
 259                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 260                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 261                                         clk_disable_unprepare(
 262                                                 bsp_priv->mac_clk_rx);
 263
 264                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 265                                         clk_disable_unprepare(
 266                                                 bsp_priv->clk_mac_ref);
 267
 268                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 269                                         clk_disable_unprepare(
 270                                                 bsp_priv->clk_mac_refout);
 271                         }
 272
 273                         if (!IS_ERR(bsp_priv->aclk_mac))
 274                                 clk_disable_unprepare(bsp_priv->aclk_mac);
 275
 276                         if (!IS_ERR(bsp_priv->pclk_mac))
 277                                 clk_disable_unprepare(bsp_priv->pclk_mac);
 278
 279                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 280                                 clk_disable_unprepare(bsp_priv->mac_clk_tx);
 281                         /**
 282                          * if (!IS_ERR(bsp_priv->clk_mac))
 283                          *      clk_disable_unprepare(bsp_priv->clk_mac);
 284                          */
 285                         bsp_priv->clk_enabled = false;
 286                 }
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
 293 {
 294         struct regulator *ldo = bsp_priv->regulator;
 295         int ret;
 296         struct device *dev = &bsp_priv->pdev->dev;
 297
 298         if (!ldo) {
 299                 dev_err(dev, "no regulator found\n");
 300                 return -1;
 301         }
 302
 303         if (enable) {
 304                 ret = regulator_enable(ldo);
 305                 if (ret)
 306                         dev_err(dev, "fail to enable phy-supply\n");
 307         } else {
 308                 ret = regulator_disable(ldo);
 309                 if (ret)
 310                         dev_err(dev, "fail to disable phy-supply\n");
 311         }
 312
 313         return 0;
 314 }
 315
 316 static void *rk_gmac_setup(struct platform_device *pdev)
 317 {
 318         struct rk_priv_data *bsp_priv;
 319         struct device *dev = &pdev->dev;
 320         int ret;
 321         const char *strings = NULL;
 322         int value;
 323
 324         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
 325         if (!bsp_priv)
 326                 return ERR_PTR(-ENOMEM);
 327
 328         bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
 329
 330         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
 331         if (IS_ERR(bsp_priv->regulator)) {
 332                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
 333                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
 334                         return ERR_PTR(-EPROBE_DEFER);
 335                 }
 336                 dev_err(dev, "no regulator found\n");
 337                 bsp_priv->regulator = NULL;
 338         }
 339
 340         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
 341         if (ret) {
 342                 dev_err(dev, "Can not read property: clock_in_out.\n");
 343                 bsp_priv->clock_input = true;
 344         } else {
 345                 dev_info(dev, "clock input or output? (%s).\n",
 346                          strings);
 347                 if (!strcmp(strings, "input"))
 348                         bsp_priv->clock_input = true;
 349                 else
 350                         bsp_priv->clock_input = false;
 351         }
 352
 353         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
 354         if (ret) {
 355                 bsp_priv->tx_delay = 0x30;
 356                 dev_err(dev, "Can not read property: tx_delay.");
 357                 dev_err(dev, "set tx_delay to 0x%x\n",
 358                         bsp_priv->tx_delay);
 359         } else {
 360                 dev_info(dev, "TX delay(0x%x).\n", value);
 361                 bsp_priv->tx_delay = value;
 362         }
 363
 364         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
 365         if (ret) {
 366                 bsp_priv->rx_delay = 0x10;
 367                 dev_err(dev, "Can not read property: rx_delay.");
 368                 dev_err(dev, "set rx_delay to 0x%x\n",
 369                         bsp_priv->rx_delay);
 370         } else {
 371                 dev_info(dev, "RX delay(0x%x).\n", value);
 372                 bsp_priv->rx_delay = value;
 373         }
 374
 375         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
 376                                                         "rockchip,grf");
 377         bsp_priv->pdev = pdev;
 378
 379         /*rmii or rgmii*/
 380         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
 381                 dev_info(dev, "init for RGMII\n");
 382                 set_to_rgmii(bsp_priv, bsp_priv->tx_delay, bsp_priv->rx_delay);
 383         } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 384                 dev_info(dev, "init for RMII\n");
 385                 set_to_rmii(bsp_priv);
 386         } else {
 387                 dev_err(dev, "NO interface defined!\n");
 388         }
 389
 390         gmac_clk_init(bsp_priv);
 391
 392         return bsp_priv;
 393 }
 394
 395 static int rk_gmac_init(struct platform_device *pdev, void *priv)
 396 {
 397         struct rk_priv_data *bsp_priv = priv;
 398         int ret;
 399
 400         ret = phy_power_on(bsp_priv, true);
 401         if (ret)
 402                 return ret;
 403
 404         ret = gmac_clk_enable(bsp_priv, true);
 405         if (ret)
 406                 return ret;
 407
 408         return 0;
 409 }
 410
 411 static void rk_gmac_exit(struct platform_device *pdev, void *priv)
 412 {
 413         struct rk_priv_data *gmac = priv;
 414
 415         phy_power_on(gmac, false);
 416         gmac_clk_enable(gmac, false);
 417 }
 418
 419 static void rk_fix_speed(void *priv, unsigned int speed)
 420 {
 421         struct rk_priv_data *bsp_priv = priv;
 422         struct device *dev = &bsp_priv->pdev->dev;
 423
 424         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII)
 425                 set_rgmii_speed(bsp_priv, speed);
 426         else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 427                 set_rmii_speed(bsp_priv, speed);
 428         else
 429                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
 430 }
 431
 432 static const struct stmmac_of_data rk3288_gmac_data = {
 433         .has_gmac = 1,
 434         .fix_mac_speed = rk_fix_speed,
 435         .setup = rk_gmac_setup,
 436         .init = rk_gmac_init,
 437         .exit = rk_gmac_exit,
 438 };
 439
 440 static const struct of_device_id rk_gmac_dwmac_match[] = {
 441         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_gmac_data},
 442         { }
 443 };
 444 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
 445
 446 static struct platform_driver rk_gmac_dwmac_driver = {
 447         .probe  = stmmac_pltfr_probe,
 448         .remove = stmmac_pltfr_remove,
 449         .driver = {
 450                 .name           = "rk_gmac-dwmac",
 451                 .pm             = &stmmac_pltfr_pm_ops,
 452                 .of_match_table = rk_gmac_dwmac_match,
 453         },
 454 };
 455 module_platform_driver(rk_gmac_dwmac_driver);
 456
 457 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
 458 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
 459 MODULE_LICENSE("GPL");