drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <[email protected]>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_fourcc.h>
  36 #include <drm/drm_rect.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include "intel_drv.h"
  40 #include "intel_frontbuffer.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  45                              int usecs)
  46 {
  47         /* paranoia */
  48         if (!adjusted_mode->crtc_htotal)
  49                 return 1;
  50
  51         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  52                             1000 * adjusted_mode->crtc_htotal);
  53 }
  54
  55 /* FIXME: We should instead only take spinlocks once for the entire update
  56  * instead of once per mmio. */
  57 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
  58 #define VBLANK_EVASION_TIME_US 250
  59 #else
  60 #define VBLANK_EVASION_TIME_US 100
  61 #endif
  62
  63 /**
  64  * intel_pipe_update_start() - start update of a set of display registers
  65  * @new_crtc_state: the new crtc state
  66  *
  67  * Mark the start of an update to pipe registers that should be updated
  68  * atomically regarding vblank. If the next vblank will happens within
  69  * the next 100 us, this function waits until the vblank passes.
  70  *
  71  * After a successful call to this function, interrupts will be disabled
  72  * until a subsequent call to intel_pipe_update_end(). That is done to
  73  * avoid random delays.
  74  */
  75 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  76 {
  77         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
  78         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  79         const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
  80         long timeout = msecs_to_jiffies_timeout(1);
  81         int scanline, min, max, vblank_start;
  82         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  83         bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
  84                 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
  85         DEFINE_WAIT(wait);
  86         u32 psr_status;
  87
  88         vblank_start = adjusted_mode->crtc_vblank_start;
  89         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  90                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  91
  92         /* FIXME needs to be calibrated sensibly */
  93         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
  94                                                       VBLANK_EVASION_TIME_US);
  95         max = vblank_start - 1;
  96
  97         if (min <= 0 || max <= 0)
  98                 goto irq_disable;
  99
 100         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 101                 goto irq_disable;
 102
 103         /*
 104          * Wait for psr to idle out after enabling the VBL interrupts
 105          * VBL interrupts will start the PSR exit and prevent a PSR
 106          * re-entry as well.
 107          */
 108         if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
 109                 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
 110                           psr_status);
 111
 112         local_irq_disable();
 113
 114         crtc->debug.min_vbl = min;
 115         crtc->debug.max_vbl = max;
 116         trace_i915_pipe_update_start(crtc);
 117
 118         for (;;) {
 119                 /*
 120                  * prepare_to_wait() has a memory barrier, which guarantees
 121                  * other CPUs can see the task state update by the time we
 122                  * read the scanline.
 123                  */
 124                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 125
 126                 scanline = intel_get_crtc_scanline(crtc);
 127                 if (scanline < min || scanline > max)
 128                         break;
 129
 130                 if (!timeout) {
 131                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 132                                   pipe_name(crtc->pipe));
 133                         break;
 134                 }
 135
 136                 local_irq_enable();
 137
 138                 timeout = schedule_timeout(timeout);
 139
 140                 local_irq_disable();
 141         }
 142
 143         finish_wait(wq, &wait);
 144
 145         drm_crtc_vblank_put(&crtc->base);
 146
 147         /*
 148          * On VLV/CHV DSI the scanline counter would appear to
 149          * increment approx. 1/3 of a scanline before start of vblank.
 150          * The registers still get latched at start of vblank however.
 151          * This means we must not write any registers on the first
 152          * line of vblank (since not the whole line is actually in
 153          * vblank). And unfortunately we can't use the interrupt to
 154          * wait here since it will fire too soon. We could use the
 155          * frame start interrupt instead since it will fire after the
 156          * critical scanline, but that would require more changes
 157          * in the interrupt code. So for now we'll just do the nasty
 158          * thing and poll for the bad scanline to pass us by.
 159          *
 160          * FIXME figure out if BXT+ DSI suffers from this as well
 161          */
 162         while (need_vlv_dsi_wa && scanline == vblank_start)
 163                 scanline = intel_get_crtc_scanline(crtc);
 164
 165         crtc->debug.scanline_start = scanline;
 166         crtc->debug.start_vbl_time = ktime_get();
 167         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 168
 169         trace_i915_pipe_update_vblank_evaded(crtc);
 170         return;
 171
 172 irq_disable:
 173         local_irq_disable();
 174 }
 175
 176 /**
 177  * intel_pipe_update_end() - end update of a set of display registers
 178  * @new_crtc_state: the new crtc state
 179  *
 180  * Mark the end of an update started with intel_pipe_update_start(). This
 181  * re-enables interrupts and verifies the update was actually completed
 182  * before a vblank.
 183  */
 184 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 185 {
 186         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 187         enum pipe pipe = crtc->pipe;
 188         int scanline_end = intel_get_crtc_scanline(crtc);
 189         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 190         ktime_t end_vbl_time = ktime_get();
 191         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 192
 193         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 194
 195         /* We're still in the vblank-evade critical section, this can't race.
 196          * Would be slightly nice to just grab the vblank count and arm the
 197          * event outside of the critical section - the spinlock might spin for a
 198          * while ... */
 199         if (new_crtc_state->base.event) {
 200                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 201
 202                 spin_lock(&crtc->base.dev->event_lock);
 203                 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
 204                 spin_unlock(&crtc->base.dev->event_lock);
 205
 206                 new_crtc_state->base.event = NULL;
 207         }
 208
 209         local_irq_enable();
 210
 211         if (intel_vgpu_active(dev_priv))
 212                 return;
 213
 214         if (crtc->debug.start_vbl_count &&
 215             crtc->debug.start_vbl_count != end_vbl_count) {
 216                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 217                           pipe_name(pipe), crtc->debug.start_vbl_count,
 218                           end_vbl_count,
 219                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 220                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 221                           crtc->debug.scanline_start, scanline_end);
 222         }
 223 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
 224         else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 225                  VBLANK_EVASION_TIME_US)
 226                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 227                          pipe_name(pipe),
 228                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 229                          VBLANK_EVASION_TIME_US);
 230 #endif
 231 }
 232
 233 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 234 {
 235         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 236         const struct drm_framebuffer *fb = plane_state->base.fb;
 237         unsigned int rotation = plane_state->base.rotation;
 238         u32 stride, max_stride;
 239
 240         /* FIXME other color planes? */
 241         stride = plane_state->color_plane[0].stride;
 242         max_stride = plane->max_stride(plane, fb->format->format,
 243                                        fb->modifier, rotation);
 244
 245         if (stride > max_stride) {
 246                 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
 247                               fb->base.id, stride,
 248                               plane->base.base.id, plane->base.name, max_stride);
 249                 return -EINVAL;
 250         }
 251
 252         return 0;
 253 }
 254
 255 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 256 {
 257         const struct drm_framebuffer *fb = plane_state->base.fb;
 258         struct drm_rect *src = &plane_state->base.src;
 259         u32 src_x, src_y, src_w, src_h;
 260
 261         /*
 262          * Hardware doesn't handle subpixel coordinates.
 263          * Adjust to (macro)pixel boundary, but be careful not to
 264          * increase the source viewport size, because that could
 265          * push the downscaling factor out of bounds.
 266          */
 267         src_x = src->x1 >> 16;
 268         src_w = drm_rect_width(src) >> 16;
 269         src_y = src->y1 >> 16;
 270         src_h = drm_rect_height(src) >> 16;
 271
 272         src->x1 = src_x << 16;
 273         src->x2 = (src_x + src_w) << 16;
 274         src->y1 = src_y << 16;
 275         src->y2 = (src_y + src_h) << 16;
 276
 277         if (fb->format->is_yuv &&
 278             fb->format->format != DRM_FORMAT_NV12 &&
 279             (src_x & 1 || src_w & 1)) {
 280                 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
 281                               src_x, src_w);
 282                 return -EINVAL;
 283         }
 284
 285         return 0;
 286 }
 287
 288 unsigned int
 289 skl_plane_max_stride(struct intel_plane *plane,
 290                      u32 pixel_format, u64 modifier,
 291                      unsigned int rotation)
 292 {
 293         int cpp = drm_format_plane_cpp(pixel_format, 0);
 294
 295         /*
 296          * "The stride in bytes must not exceed the
 297          * of the size of 8K pixels and 32K bytes."
 298          */
 299         if (drm_rotation_90_or_270(rotation))
 300                 return min(8192, 32768 / cpp);
 301         else
 302                 return min(8192 * cpp, 32768);
 303 }
 304
 305 static void
 306 skl_program_scaler(struct intel_plane *plane,
 307                    const struct intel_crtc_state *crtc_state,
 308                    const struct intel_plane_state *plane_state)
 309 {
 310         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 311         enum pipe pipe = plane->pipe;
 312         int scaler_id = plane_state->scaler_id;
 313         const struct intel_scaler *scaler =
 314                 &crtc_state->scaler_state.scalers[scaler_id];
 315         int crtc_x = plane_state->base.dst.x1;
 316         int crtc_y = plane_state->base.dst.y1;
 317         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 318         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 319         u16 y_hphase, uv_rgb_hphase;
 320         u16 y_vphase, uv_rgb_vphase;
 321         int hscale, vscale;
 322
 323         hscale = drm_rect_calc_hscale(&plane_state->base.src,
 324                                       &plane_state->base.dst,
 325                                       0, INT_MAX);
 326         vscale = drm_rect_calc_vscale(&plane_state->base.src,
 327                                       &plane_state->base.dst,
 328                                       0, INT_MAX);
 329
 330         /* TODO: handle sub-pixel coordinates */
 331         if (plane_state->base.fb->format->format == DRM_FORMAT_NV12) {
 332                 y_hphase = skl_scaler_calc_phase(1, hscale, false);
 333                 y_vphase = skl_scaler_calc_phase(1, vscale, false);
 334
 335                 /* MPEG2 chroma siting convention */
 336                 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
 337                 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
 338         } else {
 339                 /* not used */
 340                 y_hphase = 0;
 341                 y_vphase = 0;
 342
 343                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
 344                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 345         }
 346
 347         I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 348                       PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
 349         I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 350         I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
 351                       PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 352         I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
 353                       PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 354         I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 355         I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
 356 }
 357
 358 void
 359 skl_update_plane(struct intel_plane *plane,
 360                  const struct intel_crtc_state *crtc_state,
 361                  const struct intel_plane_state *plane_state)
 362 {
 363         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 364         enum plane_id plane_id = plane->id;
 365         enum pipe pipe = plane->pipe;
 366         u32 plane_ctl = plane_state->ctl;
 367         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 368         u32 surf_addr = plane_state->color_plane[0].offset;
 369         u32 stride = skl_plane_stride(plane_state, 0);
 370         u32 aux_stride = skl_plane_stride(plane_state, 1);
 371         int crtc_x = plane_state->base.dst.x1;
 372         int crtc_y = plane_state->base.dst.y1;
 373         uint32_t x = plane_state->color_plane[0].x;
 374         uint32_t y = plane_state->color_plane[0].y;
 375         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 376         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 377         unsigned long irqflags;
 378
 379         /* Sizes are 0 based */
 380         src_w--;
 381         src_h--;
 382
 383         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 384
 385         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 386                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 387                               plane_state->color_ctl);
 388
 389         if (key->flags) {
 390                 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 391                 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 392                 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 393         }
 394
 395         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 396         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
 397         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 398         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 399                       (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 400         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
 401                       (plane_state->color_plane[1].y << 16) |
 402                       plane_state->color_plane[1].x);
 403
 404         if (plane_state->scaler_id >= 0) {
 405                 skl_program_scaler(plane, crtc_state, plane_state);
 406
 407                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
 408         } else {
 409                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 410         }
 411
 412         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 413         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 414                       intel_plane_ggtt_offset(plane_state) + surf_addr);
 415         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 416
 417         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 418 }
 419
 420 void
 421 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 422 {
 423         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 424         enum plane_id plane_id = plane->id;
 425         enum pipe pipe = plane->pipe;
 426         unsigned long irqflags;
 427
 428         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 429
 430         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
 431
 432         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
 433         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 434
 435         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 436 }
 437
 438 bool
 439 skl_plane_get_hw_state(struct intel_plane *plane,
 440                        enum pipe *pipe)
 441 {
 442         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 443         enum intel_display_power_domain power_domain;
 444         enum plane_id plane_id = plane->id;
 445         bool ret;
 446
 447         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 448         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 449                 return false;
 450
 451         ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 452
 453         *pipe = plane->pipe;
 454
 455         intel_display_power_put(dev_priv, power_domain);
 456
 457         return ret;
 458 }
 459
 460 static void
 461 chv_update_csc(const struct intel_plane_state *plane_state)
 462 {
 463         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 464         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 465         const struct drm_framebuffer *fb = plane_state->base.fb;
 466         enum plane_id plane_id = plane->id;
 467         /*
 468          * |r|   | c0 c1 c2 |   |cr|
 469          * |g| = | c3 c4 c5 | x |y |
 470          * |b|   | c6 c7 c8 |   |cb|
 471          *
 472          * Coefficients are s3.12.
 473          *
 474          * Cb and Cr apparently come in as signed already, and
 475          * we always get full range data in on account of CLRC0/1.
 476          */
 477         static const s16 csc_matrix[][9] = {
 478                 /* BT.601 full range YCbCr -> full range RGB */
 479                 [DRM_COLOR_YCBCR_BT601] = {
 480                          5743, 4096,     0,
 481                         -2925, 4096, -1410,
 482                             0, 4096,  7258,
 483                 },
 484                 /* BT.709 full range YCbCr -> full range RGB */
 485                 [DRM_COLOR_YCBCR_BT709] = {
 486                          6450, 4096,     0,
 487                         -1917, 4096,  -767,
 488                             0, 4096,  7601,
 489                 },
 490         };
 491         const s16 *csc = csc_matrix[plane_state->base.color_encoding];
 492
 493         /* Seems RGB data bypasses the CSC always */
 494         if (!fb->format->is_yuv)
 495                 return;
 496
 497         I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 498         I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 499         I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 500
 501         I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
 502         I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
 503         I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
 504         I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
 505         I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
 506
 507         I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
 508         I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 509         I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
 510
 511         I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 512         I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 513         I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 514 }
 515
 516 #define SIN_0 0
 517 #define COS_0 1
 518
 519 static void
 520 vlv_update_clrc(const struct intel_plane_state *plane_state)
 521 {
 522         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 523         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 524         const struct drm_framebuffer *fb = plane_state->base.fb;
 525         enum pipe pipe = plane->pipe;
 526         enum plane_id plane_id = plane->id;
 527         int contrast, brightness, sh_scale, sh_sin, sh_cos;
 528
 529         if (fb->format->is_yuv &&
 530             plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 531                 /*
 532                  * Expand limited range to full range:
 533                  * Contrast is applied first and is used to expand Y range.
 534                  * Brightness is applied second and is used to remove the
 535                  * offset from Y. Saturation/hue is used to expand CbCr range.
 536                  */
 537                 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
 538                 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
 539                 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
 540                 sh_sin = SIN_0 * sh_scale;
 541                 sh_cos = COS_0 * sh_scale;
 542         } else {
 543                 /* Pass-through everything. */
 544                 contrast = 1 << 6;
 545                 brightness = 0;
 546                 sh_scale = 1 << 7;
 547                 sh_sin = SIN_0 * sh_scale;
 548                 sh_cos = COS_0 * sh_scale;
 549         }
 550
 551         /* FIXME these register are single buffered :( */
 552         I915_WRITE_FW(SPCLRC0(pipe, plane_id),
 553                       SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
 554         I915_WRITE_FW(SPCLRC1(pipe, plane_id),
 555                       SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
 556 }
 557
 558 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 559                           const struct intel_plane_state *plane_state)
 560 {
 561         const struct drm_framebuffer *fb = plane_state->base.fb;
 562         unsigned int rotation = plane_state->base.rotation;
 563         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 564         u32 sprctl;
 565
 566         sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
 567
 568         switch (fb->format->format) {
 569         case DRM_FORMAT_YUYV:
 570                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 571                 break;
 572         case DRM_FORMAT_YVYU:
 573                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 574                 break;
 575         case DRM_FORMAT_UYVY:
 576                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 577                 break;
 578         case DRM_FORMAT_VYUY:
 579                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 580                 break;
 581         case DRM_FORMAT_RGB565:
 582                 sprctl |= SP_FORMAT_BGR565;
 583                 break;
 584         case DRM_FORMAT_XRGB8888:
 585                 sprctl |= SP_FORMAT_BGRX8888;
 586                 break;
 587         case DRM_FORMAT_ARGB8888:
 588                 sprctl |= SP_FORMAT_BGRA8888;
 589                 break;
 590         case DRM_FORMAT_XBGR2101010:
 591                 sprctl |= SP_FORMAT_RGBX1010102;
 592                 break;
 593         case DRM_FORMAT_ABGR2101010:
 594                 sprctl |= SP_FORMAT_RGBA1010102;
 595                 break;
 596         case DRM_FORMAT_XBGR8888:
 597                 sprctl |= SP_FORMAT_RGBX8888;
 598                 break;
 599         case DRM_FORMAT_ABGR8888:
 600                 sprctl |= SP_FORMAT_RGBA8888;
 601                 break;
 602         default:
 603                 MISSING_CASE(fb->format->format);
 604                 return 0;
 605         }
 606
 607         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 608                 sprctl |= SP_YUV_FORMAT_BT709;
 609
 610         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 611                 sprctl |= SP_TILED;
 612
 613         if (rotation & DRM_MODE_ROTATE_180)
 614                 sprctl |= SP_ROTATE_180;
 615
 616         if (rotation & DRM_MODE_REFLECT_X)
 617                 sprctl |= SP_MIRROR;
 618
 619         if (key->flags & I915_SET_COLORKEY_SOURCE)
 620                 sprctl |= SP_SOURCE_KEY;
 621
 622         return sprctl;
 623 }
 624
 625 static void
 626 vlv_update_plane(struct intel_plane *plane,
 627                  const struct intel_crtc_state *crtc_state,
 628                  const struct intel_plane_state *plane_state)
 629 {
 630         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 631         const struct drm_framebuffer *fb = plane_state->base.fb;
 632         enum pipe pipe = plane->pipe;
 633         enum plane_id plane_id = plane->id;
 634         u32 sprctl = plane_state->ctl;
 635         u32 sprsurf_offset = plane_state->color_plane[0].offset;
 636         u32 linear_offset;
 637         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 638         int crtc_x = plane_state->base.dst.x1;
 639         int crtc_y = plane_state->base.dst.y1;
 640         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 641         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 642         uint32_t x = plane_state->color_plane[0].x;
 643         uint32_t y = plane_state->color_plane[0].y;
 644         unsigned long irqflags;
 645
 646         /* Sizes are 0 based */
 647         crtc_w--;
 648         crtc_h--;
 649
 650         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 651
 652         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 653
 654         vlv_update_clrc(plane_state);
 655
 656         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 657                 chv_update_csc(plane_state);
 658
 659         if (key->flags) {
 660                 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
 661                 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 662                 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
 663         }
 664         I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
 665                       plane_state->color_plane[0].stride);
 666         I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 667
 668         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 669                 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 670         else
 671                 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
 672
 673         I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
 674
 675         I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 676         I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
 677         I915_WRITE_FW(SPSURF(pipe, plane_id),
 678                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 679         POSTING_READ_FW(SPSURF(pipe, plane_id));
 680
 681         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 682 }
 683
 684 static void
 685 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 686 {
 687         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 688         enum pipe pipe = plane->pipe;
 689         enum plane_id plane_id = plane->id;
 690         unsigned long irqflags;
 691
 692         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 693
 694         I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
 695
 696         I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
 697         POSTING_READ_FW(SPSURF(pipe, plane_id));
 698
 699         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 700 }
 701
 702 static bool
 703 vlv_plane_get_hw_state(struct intel_plane *plane,
 704                        enum pipe *pipe)
 705 {
 706         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 707         enum intel_display_power_domain power_domain;
 708         enum plane_id plane_id = plane->id;
 709         bool ret;
 710
 711         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 712         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 713                 return false;
 714
 715         ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
 716
 717         *pipe = plane->pipe;
 718
 719         intel_display_power_put(dev_priv, power_domain);
 720
 721         return ret;
 722 }
 723
 724 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 725                           const struct intel_plane_state *plane_state)
 726 {
 727         struct drm_i915_private *dev_priv =
 728                 to_i915(plane_state->base.plane->dev);
 729         const struct drm_framebuffer *fb = plane_state->base.fb;
 730         unsigned int rotation = plane_state->base.rotation;
 731         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 732         u32 sprctl;
 733
 734         sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
 735
 736         if (IS_IVYBRIDGE(dev_priv))
 737                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 738
 739         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 740                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 741
 742         switch (fb->format->format) {
 743         case DRM_FORMAT_XBGR8888:
 744                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 745                 break;
 746         case DRM_FORMAT_XRGB8888:
 747                 sprctl |= SPRITE_FORMAT_RGBX888;
 748                 break;
 749         case DRM_FORMAT_YUYV:
 750                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 751                 break;
 752         case DRM_FORMAT_YVYU:
 753                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 754                 break;
 755         case DRM_FORMAT_UYVY:
 756                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 757                 break;
 758         case DRM_FORMAT_VYUY:
 759                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 760                 break;
 761         default:
 762                 MISSING_CASE(fb->format->format);
 763                 return 0;
 764         }
 765
 766         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 767                 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 768
 769         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 770                 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 771
 772         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 773                 sprctl |= SPRITE_TILED;
 774
 775         if (rotation & DRM_MODE_ROTATE_180)
 776                 sprctl |= SPRITE_ROTATE_180;
 777
 778         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 779                 sprctl |= SPRITE_DEST_KEY;
 780         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 781                 sprctl |= SPRITE_SOURCE_KEY;
 782
 783         return sprctl;
 784 }
 785
 786 static void
 787 ivb_update_plane(struct intel_plane *plane,
 788                  const struct intel_crtc_state *crtc_state,
 789                  const struct intel_plane_state *plane_state)
 790 {
 791         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 792         const struct drm_framebuffer *fb = plane_state->base.fb;
 793         enum pipe pipe = plane->pipe;
 794         u32 sprctl = plane_state->ctl, sprscale = 0;
 795         u32 sprsurf_offset = plane_state->color_plane[0].offset;
 796         u32 linear_offset;
 797         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 798         int crtc_x = plane_state->base.dst.x1;
 799         int crtc_y = plane_state->base.dst.y1;
 800         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 801         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 802         uint32_t x = plane_state->color_plane[0].x;
 803         uint32_t y = plane_state->color_plane[0].y;
 804         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 805         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 806         unsigned long irqflags;
 807
 808         /* Sizes are 0 based */
 809         src_w--;
 810         src_h--;
 811         crtc_w--;
 812         crtc_h--;
 813
 814         if (crtc_w != src_w || crtc_h != src_h)
 815                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 816
 817         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 818
 819         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 820
 821         if (key->flags) {
 822                 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
 823                 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
 824                 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
 825         }
 826
 827         I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
 828         I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 829
 830         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 831          * register */
 832         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 833                 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
 834         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 835                 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
 836         else
 837                 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
 838
 839         I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 840         if (IS_IVYBRIDGE(dev_priv))
 841                 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
 842         I915_WRITE_FW(SPRCTL(pipe), sprctl);
 843         I915_WRITE_FW(SPRSURF(pipe),
 844                       intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 845         POSTING_READ_FW(SPRSURF(pipe));
 846
 847         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 848 }
 849
 850 static void
 851 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 852 {
 853         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 854         enum pipe pipe = plane->pipe;
 855         unsigned long irqflags;
 856
 857         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 858
 859         I915_WRITE_FW(SPRCTL(pipe), 0);
 860         /* Can't leave the scaler enabled... */
 861         if (IS_IVYBRIDGE(dev_priv))
 862                 I915_WRITE_FW(SPRSCALE(pipe), 0);
 863
 864         I915_WRITE_FW(SPRSURF(pipe), 0);
 865         POSTING_READ_FW(SPRSURF(pipe));
 866
 867         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 868 }
 869
 870 static bool
 871 ivb_plane_get_hw_state(struct intel_plane *plane,
 872                        enum pipe *pipe)
 873 {
 874         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 875         enum intel_display_power_domain power_domain;
 876         bool ret;
 877
 878         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 879         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 880                 return false;
 881
 882         ret =  I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
 883
 884         *pipe = plane->pipe;
 885
 886         intel_display_power_put(dev_priv, power_domain);
 887
 888         return ret;
 889 }
 890
 891 static unsigned int
 892 g4x_sprite_max_stride(struct intel_plane *plane,
 893                       u32 pixel_format, u64 modifier,
 894                       unsigned int rotation)
 895 {
 896         return 16384;
 897 }
 898
 899 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 900                           const struct intel_plane_state *plane_state)
 901 {
 902         struct drm_i915_private *dev_priv =
 903                 to_i915(plane_state->base.plane->dev);
 904         const struct drm_framebuffer *fb = plane_state->base.fb;
 905         unsigned int rotation = plane_state->base.rotation;
 906         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 907         u32 dvscntr;
 908
 909         dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
 910
 911         if (IS_GEN6(dev_priv))
 912                 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 913
 914         switch (fb->format->format) {
 915         case DRM_FORMAT_XBGR8888:
 916                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 917                 break;
 918         case DRM_FORMAT_XRGB8888:
 919                 dvscntr |= DVS_FORMAT_RGBX888;
 920                 break;
 921         case DRM_FORMAT_YUYV:
 922                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 923                 break;
 924         case DRM_FORMAT_YVYU:
 925                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 926                 break;
 927         case DRM_FORMAT_UYVY:
 928                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 929                 break;
 930         case DRM_FORMAT_VYUY:
 931                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 932                 break;
 933         default:
 934                 MISSING_CASE(fb->format->format);
 935                 return 0;
 936         }
 937
 938         if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 939                 dvscntr |= DVS_YUV_FORMAT_BT709;
 940
 941         if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 942                 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 943
 944         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 945                 dvscntr |= DVS_TILED;
 946
 947         if (rotation & DRM_MODE_ROTATE_180)
 948                 dvscntr |= DVS_ROTATE_180;
 949
 950         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 951                 dvscntr |= DVS_DEST_KEY;
 952         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 953                 dvscntr |= DVS_SOURCE_KEY;
 954
 955         return dvscntr;
 956 }
 957
 958 static void
 959 g4x_update_plane(struct intel_plane *plane,
 960                  const struct intel_crtc_state *crtc_state,
 961                  const struct intel_plane_state *plane_state)
 962 {
 963         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 964         const struct drm_framebuffer *fb = plane_state->base.fb;
 965         enum pipe pipe = plane->pipe;
 966         u32 dvscntr = plane_state->ctl, dvsscale = 0;
 967         u32 dvssurf_offset = plane_state->color_plane[0].offset;
 968         u32 linear_offset;
 969         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 970         int crtc_x = plane_state->base.dst.x1;
 971         int crtc_y = plane_state->base.dst.y1;
 972         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 973         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 974         uint32_t x = plane_state->color_plane[0].x;
 975         uint32_t y = plane_state->color_plane[0].y;
 976         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 977         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 978         unsigned long irqflags;
 979
 980         /* Sizes are 0 based */
 981         src_w--;
 982         src_h--;
 983         crtc_w--;
 984         crtc_h--;
 985
 986         if (crtc_w != src_w || crtc_h != src_h)
 987                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 988
 989         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 990
 991         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 992
 993         if (key->flags) {
 994                 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
 995                 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
 996                 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
 997         }
 998
 999         I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
1000         I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1001
1002         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1003                 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1004         else
1005                 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1006
1007         I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1008         I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1009         I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1010         I915_WRITE_FW(DVSSURF(pipe),
1011                       intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1012         POSTING_READ_FW(DVSSURF(pipe));
1013
1014         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1015 }
1016
1017 static void
1018 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
1019 {
1020         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1021         enum pipe pipe = plane->pipe;
1022         unsigned long irqflags;
1023
1024         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1025
1026         I915_WRITE_FW(DVSCNTR(pipe), 0);
1027         /* Disable the scaler */
1028         I915_WRITE_FW(DVSSCALE(pipe), 0);
1029
1030         I915_WRITE_FW(DVSSURF(pipe), 0);
1031         POSTING_READ_FW(DVSSURF(pipe));
1032
1033         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1034 }
1035
1036 static bool
1037 g4x_plane_get_hw_state(struct intel_plane *plane,
1038                        enum pipe *pipe)
1039 {
1040         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1041         enum intel_display_power_domain power_domain;
1042         bool ret;
1043
1044         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1045         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1046                 return false;
1047
1048         ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1049
1050         *pipe = plane->pipe;
1051
1052         intel_display_power_put(dev_priv, power_domain);
1053
1054         return ret;
1055 }
1056
1057 static int
1058 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1059                          struct intel_plane_state *plane_state)
1060 {
1061         const struct drm_framebuffer *fb = plane_state->base.fb;
1062         const struct drm_rect *src = &plane_state->base.src;
1063         const struct drm_rect *dst = &plane_state->base.dst;
1064         int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
1065         const struct drm_display_mode *adjusted_mode =
1066                 &crtc_state->base.adjusted_mode;
1067         unsigned int cpp = fb->format->cpp[0];
1068         unsigned int width_bytes;
1069         int min_width, min_height;
1070
1071         crtc_w = drm_rect_width(dst);
1072         crtc_h = drm_rect_height(dst);
1073
1074         src_x = src->x1 >> 16;
1075         src_y = src->y1 >> 16;
1076         src_w = drm_rect_width(src) >> 16;
1077         src_h = drm_rect_height(src) >> 16;
1078
1079         if (src_w == crtc_w && src_h == crtc_h)
1080                 return 0;
1081
1082         min_width = 3;
1083
1084         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1085                 if (src_h & 1) {
1086                         DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1087                         return -EINVAL;
1088                 }
1089                 min_height = 6;
1090         } else {
1091                 min_height = 3;
1092         }
1093
1094         width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1095
1096         if (src_w < min_width || src_h < min_height ||
1097             src_w > 2048 || src_h > 2048) {
1098                 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1099                               src_w, src_h, min_width, min_height, 2048, 2048);
1100                 return -EINVAL;
1101         }
1102
1103         if (width_bytes > 4096) {
1104                 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1105                               width_bytes, 4096);
1106                 return -EINVAL;
1107         }
1108
1109         if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1110                 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1111                               fb->pitches[0], 4096);
1112                 return -EINVAL;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static int
1119 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1120                  struct intel_plane_state *plane_state)
1121 {
1122         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1123         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1124         int max_scale, min_scale;
1125         int ret;
1126
1127         if (INTEL_GEN(dev_priv) < 7) {
1128                 min_scale = 1;
1129                 max_scale = 16 << 16;
1130         } else if (IS_IVYBRIDGE(dev_priv)) {
1131                 min_scale = 1;
1132                 max_scale = 2 << 16;
1133         } else {
1134                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1135                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
1136         }
1137
1138         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1139                                                   &crtc_state->base,
1140                                                   min_scale, max_scale,
1141                                                   true, true);
1142         if (ret)
1143                 return ret;
1144
1145         if (!plane_state->base.visible)
1146                 return 0;
1147
1148         ret = intel_plane_check_src_coordinates(plane_state);
1149         if (ret)
1150                 return ret;
1151
1152         ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1153         if (ret)
1154                 return ret;
1155
1156         ret = i9xx_check_plane_surface(plane_state);
1157         if (ret)
1158                 return ret;
1159
1160         if (INTEL_GEN(dev_priv) >= 7)
1161                 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1162         else
1163                 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1164
1165         return 0;
1166 }
1167
1168 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1169 {
1170         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1171         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1172         unsigned int rotation = plane_state->base.rotation;
1173
1174         /* CHV ignores the mirror bit when the rotate bit is set :( */
1175         if (IS_CHERRYVIEW(dev_priv) &&
1176             rotation & DRM_MODE_ROTATE_180 &&
1177             rotation & DRM_MODE_REFLECT_X) {
1178                 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1179                 return -EINVAL;
1180         }
1181
1182         return 0;
1183 }
1184
1185 static int
1186 vlv_sprite_check(struct intel_crtc_state *crtc_state,
1187                  struct intel_plane_state *plane_state)
1188 {
1189         int ret;
1190
1191         ret = chv_plane_check_rotation(plane_state);
1192         if (ret)
1193                 return ret;
1194
1195         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1196                                                   &crtc_state->base,
1197                                                   DRM_PLANE_HELPER_NO_SCALING,
1198                                                   DRM_PLANE_HELPER_NO_SCALING,
1199                                                   true, true);
1200         if (ret)
1201                 return ret;
1202
1203         if (!plane_state->base.visible)
1204                 return 0;
1205
1206         ret = intel_plane_check_src_coordinates(plane_state);
1207         if (ret)
1208                 return ret;
1209
1210         ret = i9xx_check_plane_surface(plane_state);
1211         if (ret)
1212                 return ret;
1213
1214         plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1215
1216         return 0;
1217 }
1218
1219 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1220                               const struct intel_plane_state *plane_state)
1221 {
1222         const struct drm_framebuffer *fb = plane_state->base.fb;
1223         unsigned int rotation = plane_state->base.rotation;
1224         struct drm_format_name_buf format_name;
1225
1226         if (!fb)
1227                 return 0;
1228
1229         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1230             is_ccs_modifier(fb->modifier)) {
1231                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
1232                               rotation);
1233                 return -EINVAL;
1234         }
1235
1236         if (rotation & DRM_MODE_REFLECT_X &&
1237             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1238                 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
1239                 return -EINVAL;
1240         }
1241
1242         if (drm_rotation_90_or_270(rotation)) {
1243                 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1244                     fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
1245                         DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
1246                         return -EINVAL;
1247                 }
1248
1249                 /*
1250                  * 90/270 is not allowed with RGB64 16:16:16:16,
1251                  * RGB 16-bit 5:6:5, and Indexed 8-bit.
1252                  * TBD: Add RGB64 case once its added in supported format list.
1253                  */
1254                 switch (fb->format->format) {
1255                 case DRM_FORMAT_C8:
1256                 case DRM_FORMAT_RGB565:
1257                         DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
1258                                       drm_get_format_name(fb->format->format,
1259                                                           &format_name));
1260                         return -EINVAL;
1261                 default:
1262                         break;
1263                 }
1264         }
1265
1266         /* Y-tiling is not supported in IF-ID Interlace mode */
1267         if (crtc_state->base.enable &&
1268             crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1269             (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
1270              fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
1271              fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1272              fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
1273                 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
1274                 return -EINVAL;
1275         }
1276
1277         return 0;
1278 }
1279
1280 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1281                                            const struct intel_plane_state *plane_state)
1282 {
1283         struct drm_i915_private *dev_priv =
1284                 to_i915(plane_state->base.plane->dev);
1285         int crtc_x = plane_state->base.dst.x1;
1286         int crtc_w = drm_rect_width(&plane_state->base.dst);
1287         int pipe_src_w = crtc_state->pipe_src_w;
1288
1289         /*
1290          * Display WA #1175: cnl,glk
1291          * Planes other than the cursor may cause FIFO underflow and display
1292          * corruption if starting less than 4 pixels from the right edge of
1293          * the screen.
1294          * Besides the above WA fix the similar problem, where planes other
1295          * than the cursor ending less than 4 pixels from the left edge of the
1296          * screen may cause FIFO underflow and display corruption.
1297          */
1298         if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
1299             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1300                 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
1301                               crtc_x + crtc_w < 4 ? "end" : "start",
1302                               crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1303                               4, pipe_src_w - 4);
1304                 return -ERANGE;
1305         }
1306
1307         return 0;
1308 }
1309
1310 int skl_plane_check(struct intel_crtc_state *crtc_state,
1311                     struct intel_plane_state *plane_state)
1312 {
1313         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1314         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1315         int max_scale, min_scale;
1316         int ret;
1317
1318         ret = skl_plane_check_fb(crtc_state, plane_state);
1319         if (ret)
1320                 return ret;
1321
1322         /* use scaler when colorkey is not required */
1323         if (!plane_state->ckey.flags) {
1324                 const struct drm_framebuffer *fb = plane_state->base.fb;
1325
1326                 min_scale = 1;
1327                 max_scale = skl_max_scale(crtc_state,
1328                                           fb ? fb->format->format : 0);
1329         } else {
1330                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1331                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
1332         }
1333
1334         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1335                                                   &crtc_state->base,
1336                                                   min_scale, max_scale,
1337                                                   true, true);
1338         if (ret)
1339                 return ret;
1340
1341         if (!plane_state->base.visible)
1342                 return 0;
1343
1344         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1345         if (ret)
1346                 return ret;
1347
1348         ret = intel_plane_check_src_coordinates(plane_state);
1349         if (ret)
1350                 return ret;
1351
1352         ret = skl_check_plane_surface(plane_state);
1353         if (ret)
1354                 return ret;
1355
1356         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1357
1358         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1359                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1360                                                              plane_state);
1361
1362         return 0;
1363 }
1364
1365 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1366 {
1367         return INTEL_GEN(dev_priv) >= 9;
1368 }
1369
1370 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1371                                  const struct drm_intel_sprite_colorkey *set)
1372 {
1373         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1374         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1375         struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1376
1377         *key = *set;
1378
1379         /*
1380          * We want src key enabled on the
1381          * sprite and not on the primary.
1382          */
1383         if (plane->id == PLANE_PRIMARY &&
1384             set->flags & I915_SET_COLORKEY_SOURCE)
1385                 key->flags = 0;
1386
1387         /*
1388          * On SKL+ we want dst key enabled on
1389          * the primary and not on the sprite.
1390          */
1391         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1392             set->flags & I915_SET_COLORKEY_DESTINATION)
1393                 key->flags = 0;
1394 }
1395
1396 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1397                                     struct drm_file *file_priv)
1398 {
1399         struct drm_i915_private *dev_priv = to_i915(dev);
1400         struct drm_intel_sprite_colorkey *set = data;
1401         struct drm_plane *plane;
1402         struct drm_plane_state *plane_state;
1403         struct drm_atomic_state *state;
1404         struct drm_modeset_acquire_ctx ctx;
1405         int ret = 0;
1406
1407         /* ignore the pointless "none" flag */
1408         set->flags &= ~I915_SET_COLORKEY_NONE;
1409
1410         if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1411                 return -EINVAL;
1412
1413         /* Make sure we don't try to enable both src & dest simultaneously */
1414         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1415                 return -EINVAL;
1416
1417         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1418             set->flags & I915_SET_COLORKEY_DESTINATION)
1419                 return -EINVAL;
1420
1421         plane = drm_plane_find(dev, file_priv, set->plane_id);
1422         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1423                 return -ENOENT;
1424
1425         /*
1426          * SKL+ only plane 2 can do destination keying against plane 1.
1427          * Also multiple planes can't do destination keying on the same
1428          * pipe simultaneously.
1429          */
1430         if (INTEL_GEN(dev_priv) >= 9 &&
1431             to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1432             set->flags & I915_SET_COLORKEY_DESTINATION)
1433                 return -EINVAL;
1434
1435         drm_modeset_acquire_init(&ctx, 0);
1436
1437         state = drm_atomic_state_alloc(plane->dev);
1438         if (!state) {
1439                 ret = -ENOMEM;
1440                 goto out;
1441         }
1442         state->acquire_ctx = &ctx;
1443
1444         while (1) {
1445                 plane_state = drm_atomic_get_plane_state(state, plane);
1446                 ret = PTR_ERR_OR_ZERO(plane_state);
1447                 if (!ret)
1448                         intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1449
1450                 /*
1451                  * On some platforms we have to configure
1452                  * the dst colorkey on the primary plane.
1453                  */
1454                 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1455                         struct intel_crtc *crtc =
1456                                 intel_get_crtc_for_pipe(dev_priv,
1457                                                         to_intel_plane(plane)->pipe);
1458
1459                         plane_state = drm_atomic_get_plane_state(state,
1460                                                                  crtc->base.primary);
1461                         ret = PTR_ERR_OR_ZERO(plane_state);
1462                         if (!ret)
1463                                 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1464                 }
1465
1466                 if (!ret)
1467                         ret = drm_atomic_commit(state);
1468
1469                 if (ret != -EDEADLK)
1470                         break;
1471
1472                 drm_atomic_state_clear(state);
1473                 drm_modeset_backoff(&ctx);
1474         }
1475
1476         drm_atomic_state_put(state);
1477 out:
1478         drm_modeset_drop_locks(&ctx);
1479         drm_modeset_acquire_fini(&ctx);
1480         return ret;
1481 }
1482
1483 static const uint32_t g4x_plane_formats[] = {
1484         DRM_FORMAT_XRGB8888,
1485         DRM_FORMAT_YUYV,
1486         DRM_FORMAT_YVYU,
1487         DRM_FORMAT_UYVY,
1488         DRM_FORMAT_VYUY,
1489 };
1490
1491 static const uint64_t i9xx_plane_format_modifiers[] = {
1492         I915_FORMAT_MOD_X_TILED,
1493         DRM_FORMAT_MOD_LINEAR,
1494         DRM_FORMAT_MOD_INVALID
1495 };
1496
1497 static const uint32_t snb_plane_formats[] = {
1498         DRM_FORMAT_XBGR8888,
1499         DRM_FORMAT_XRGB8888,
1500         DRM_FORMAT_YUYV,
1501         DRM_FORMAT_YVYU,
1502         DRM_FORMAT_UYVY,
1503         DRM_FORMAT_VYUY,
1504 };
1505
1506 static const uint32_t vlv_plane_formats[] = {
1507         DRM_FORMAT_RGB565,
1508         DRM_FORMAT_ABGR8888,
1509         DRM_FORMAT_ARGB8888,
1510         DRM_FORMAT_XBGR8888,
1511         DRM_FORMAT_XRGB8888,
1512         DRM_FORMAT_XBGR2101010,
1513         DRM_FORMAT_ABGR2101010,
1514         DRM_FORMAT_YUYV,
1515         DRM_FORMAT_YVYU,
1516         DRM_FORMAT_UYVY,
1517         DRM_FORMAT_VYUY,
1518 };
1519
1520 static uint32_t skl_plane_formats[] = {
1521         DRM_FORMAT_RGB565,
1522         DRM_FORMAT_ABGR8888,
1523         DRM_FORMAT_ARGB8888,
1524         DRM_FORMAT_XBGR8888,
1525         DRM_FORMAT_XRGB8888,
1526         DRM_FORMAT_YUYV,
1527         DRM_FORMAT_YVYU,
1528         DRM_FORMAT_UYVY,
1529         DRM_FORMAT_VYUY,
1530 };
1531
1532 static uint32_t skl_planar_formats[] = {
1533         DRM_FORMAT_RGB565,
1534         DRM_FORMAT_ABGR8888,
1535         DRM_FORMAT_ARGB8888,
1536         DRM_FORMAT_XBGR8888,
1537         DRM_FORMAT_XRGB8888,
1538         DRM_FORMAT_YUYV,
1539         DRM_FORMAT_YVYU,
1540         DRM_FORMAT_UYVY,
1541         DRM_FORMAT_VYUY,
1542         DRM_FORMAT_NV12,
1543 };
1544
1545 static const uint64_t skl_plane_format_modifiers_noccs[] = {
1546         I915_FORMAT_MOD_Yf_TILED,
1547         I915_FORMAT_MOD_Y_TILED,
1548         I915_FORMAT_MOD_X_TILED,
1549         DRM_FORMAT_MOD_LINEAR,
1550         DRM_FORMAT_MOD_INVALID
1551 };
1552
1553 static const uint64_t skl_plane_format_modifiers_ccs[] = {
1554         I915_FORMAT_MOD_Yf_TILED_CCS,
1555         I915_FORMAT_MOD_Y_TILED_CCS,
1556         I915_FORMAT_MOD_Yf_TILED,
1557         I915_FORMAT_MOD_Y_TILED,
1558         I915_FORMAT_MOD_X_TILED,
1559         DRM_FORMAT_MOD_LINEAR,
1560         DRM_FORMAT_MOD_INVALID
1561 };
1562
1563 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1564                                             u32 format, u64 modifier)
1565 {
1566         switch (modifier) {
1567         case DRM_FORMAT_MOD_LINEAR:
1568         case I915_FORMAT_MOD_X_TILED:
1569                 break;
1570         default:
1571                 return false;
1572         }
1573
1574         switch (format) {
1575         case DRM_FORMAT_XRGB8888:
1576         case DRM_FORMAT_YUYV:
1577         case DRM_FORMAT_YVYU:
1578         case DRM_FORMAT_UYVY:
1579         case DRM_FORMAT_VYUY:
1580                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1581                     modifier == I915_FORMAT_MOD_X_TILED)
1582                         return true;
1583                 /* fall through */
1584         default:
1585                 return false;
1586         }
1587 }
1588
1589 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1590                                             u32 format, u64 modifier)
1591 {
1592         switch (modifier) {
1593         case DRM_FORMAT_MOD_LINEAR:
1594         case I915_FORMAT_MOD_X_TILED:
1595                 break;
1596         default:
1597                 return false;
1598         }
1599
1600         switch (format) {
1601         case DRM_FORMAT_XRGB8888:
1602         case DRM_FORMAT_XBGR8888:
1603         case DRM_FORMAT_YUYV:
1604         case DRM_FORMAT_YVYU:
1605         case DRM_FORMAT_UYVY:
1606         case DRM_FORMAT_VYUY:
1607                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1608                     modifier == I915_FORMAT_MOD_X_TILED)
1609                         return true;
1610                 /* fall through */
1611         default:
1612                 return false;
1613         }
1614 }
1615
1616 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1617                                             u32 format, u64 modifier)
1618 {
1619         switch (modifier) {
1620         case DRM_FORMAT_MOD_LINEAR:
1621         case I915_FORMAT_MOD_X_TILED:
1622                 break;
1623         default:
1624                 return false;
1625         }
1626
1627         switch (format) {
1628         case DRM_FORMAT_RGB565:
1629         case DRM_FORMAT_ABGR8888:
1630         case DRM_FORMAT_ARGB8888:
1631         case DRM_FORMAT_XBGR8888:
1632         case DRM_FORMAT_XRGB8888:
1633         case DRM_FORMAT_XBGR2101010:
1634         case DRM_FORMAT_ABGR2101010:
1635         case DRM_FORMAT_YUYV:
1636         case DRM_FORMAT_YVYU:
1637         case DRM_FORMAT_UYVY:
1638         case DRM_FORMAT_VYUY:
1639                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1640                     modifier == I915_FORMAT_MOD_X_TILED)
1641                         return true;
1642                 /* fall through */
1643         default:
1644                 return false;
1645         }
1646 }
1647
1648 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1649                                            u32 format, u64 modifier)
1650 {
1651         struct intel_plane *plane = to_intel_plane(_plane);
1652
1653         switch (modifier) {
1654         case DRM_FORMAT_MOD_LINEAR:
1655         case I915_FORMAT_MOD_X_TILED:
1656         case I915_FORMAT_MOD_Y_TILED:
1657         case I915_FORMAT_MOD_Yf_TILED:
1658                 break;
1659         case I915_FORMAT_MOD_Y_TILED_CCS:
1660         case I915_FORMAT_MOD_Yf_TILED_CCS:
1661                 if (!plane->has_ccs)
1662                         return false;
1663                 break;
1664         default:
1665                 return false;
1666         }
1667
1668         switch (format) {
1669         case DRM_FORMAT_XRGB8888:
1670         case DRM_FORMAT_XBGR8888:
1671         case DRM_FORMAT_ARGB8888:
1672         case DRM_FORMAT_ABGR8888:
1673                 if (is_ccs_modifier(modifier))
1674                         return true;
1675                 /* fall through */
1676         case DRM_FORMAT_RGB565:
1677         case DRM_FORMAT_XRGB2101010:
1678         case DRM_FORMAT_XBGR2101010:
1679         case DRM_FORMAT_YUYV:
1680         case DRM_FORMAT_YVYU:
1681         case DRM_FORMAT_UYVY:
1682         case DRM_FORMAT_VYUY:
1683         case DRM_FORMAT_NV12:
1684                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1685                         return true;
1686                 /* fall through */
1687         case DRM_FORMAT_C8:
1688                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1689                     modifier == I915_FORMAT_MOD_X_TILED ||
1690                     modifier == I915_FORMAT_MOD_Y_TILED)
1691                         return true;
1692                 /* fall through */
1693         default:
1694                 return false;
1695         }
1696 }
1697
1698 static const struct drm_plane_funcs g4x_sprite_funcs = {
1699         .update_plane = drm_atomic_helper_update_plane,
1700         .disable_plane = drm_atomic_helper_disable_plane,
1701         .destroy = intel_plane_destroy,
1702         .atomic_get_property = intel_plane_atomic_get_property,
1703         .atomic_set_property = intel_plane_atomic_set_property,
1704         .atomic_duplicate_state = intel_plane_duplicate_state,
1705         .atomic_destroy_state = intel_plane_destroy_state,
1706         .format_mod_supported = g4x_sprite_format_mod_supported,
1707 };
1708
1709 static const struct drm_plane_funcs snb_sprite_funcs = {
1710         .update_plane = drm_atomic_helper_update_plane,
1711         .disable_plane = drm_atomic_helper_disable_plane,
1712         .destroy = intel_plane_destroy,
1713         .atomic_get_property = intel_plane_atomic_get_property,
1714         .atomic_set_property = intel_plane_atomic_set_property,
1715         .atomic_duplicate_state = intel_plane_duplicate_state,
1716         .atomic_destroy_state = intel_plane_destroy_state,
1717         .format_mod_supported = snb_sprite_format_mod_supported,
1718 };
1719
1720 static const struct drm_plane_funcs vlv_sprite_funcs = {
1721         .update_plane = drm_atomic_helper_update_plane,
1722         .disable_plane = drm_atomic_helper_disable_plane,
1723         .destroy = intel_plane_destroy,
1724         .atomic_get_property = intel_plane_atomic_get_property,
1725         .atomic_set_property = intel_plane_atomic_set_property,
1726         .atomic_duplicate_state = intel_plane_duplicate_state,
1727         .atomic_destroy_state = intel_plane_destroy_state,
1728         .format_mod_supported = vlv_sprite_format_mod_supported,
1729 };
1730
1731 static const struct drm_plane_funcs skl_plane_funcs = {
1732         .update_plane = drm_atomic_helper_update_plane,
1733         .disable_plane = drm_atomic_helper_disable_plane,
1734         .destroy = intel_plane_destroy,
1735         .atomic_get_property = intel_plane_atomic_get_property,
1736         .atomic_set_property = intel_plane_atomic_set_property,
1737         .atomic_duplicate_state = intel_plane_duplicate_state,
1738         .atomic_destroy_state = intel_plane_destroy_state,
1739         .format_mod_supported = skl_plane_format_mod_supported,
1740 };
1741
1742 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1743                        enum pipe pipe, enum plane_id plane_id)
1744 {
1745         if (plane_id == PLANE_CURSOR)
1746                 return false;
1747
1748         if (INTEL_GEN(dev_priv) >= 10)
1749                 return true;
1750
1751         if (IS_GEMINILAKE(dev_priv))
1752                 return pipe != PIPE_C;
1753
1754         return pipe != PIPE_C &&
1755                 (plane_id == PLANE_PRIMARY ||
1756                  plane_id == PLANE_SPRITE0);
1757 }
1758
1759 struct intel_plane *
1760 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1761                           enum pipe pipe, int plane)
1762 {
1763         struct intel_plane *intel_plane = NULL;
1764         struct intel_plane_state *state = NULL;
1765         const struct drm_plane_funcs *plane_funcs;
1766         unsigned long possible_crtcs;
1767         const uint32_t *plane_formats;
1768         const uint64_t *modifiers;
1769         unsigned int supported_rotations;
1770         int num_plane_formats;
1771         int ret;
1772
1773         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1774         if (!intel_plane) {
1775                 ret = -ENOMEM;
1776                 goto fail;
1777         }
1778
1779         state = intel_create_plane_state(&intel_plane->base);
1780         if (!state) {
1781                 ret = -ENOMEM;
1782                 goto fail;
1783         }
1784         intel_plane->base.state = &state->base;
1785
1786         if (INTEL_GEN(dev_priv) >= 9) {
1787                 state->scaler_id = -1;
1788
1789                 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1790                                                          PLANE_SPRITE0 + plane);
1791
1792                 intel_plane->max_stride = skl_plane_max_stride;
1793                 intel_plane->update_plane = skl_update_plane;
1794                 intel_plane->disable_plane = skl_disable_plane;
1795                 intel_plane->get_hw_state = skl_plane_get_hw_state;
1796                 intel_plane->check_plane = skl_plane_check;
1797
1798                 if (skl_plane_has_planar(dev_priv, pipe,
1799                                          PLANE_SPRITE0 + plane)) {
1800                         plane_formats = skl_planar_formats;
1801                         num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1802                 } else {
1803                         plane_formats = skl_plane_formats;
1804                         num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1805                 }
1806
1807                 if (intel_plane->has_ccs)
1808                         modifiers = skl_plane_format_modifiers_ccs;
1809                 else
1810                         modifiers = skl_plane_format_modifiers_noccs;
1811
1812                 plane_funcs = &skl_plane_funcs;
1813         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1814                 intel_plane->max_stride = i9xx_plane_max_stride;
1815                 intel_plane->update_plane = vlv_update_plane;
1816                 intel_plane->disable_plane = vlv_disable_plane;
1817                 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1818                 intel_plane->check_plane = vlv_sprite_check;
1819
1820                 plane_formats = vlv_plane_formats;
1821                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1822                 modifiers = i9xx_plane_format_modifiers;
1823
1824                 plane_funcs = &vlv_sprite_funcs;
1825         } else if (INTEL_GEN(dev_priv) >= 7) {
1826                 intel_plane->max_stride = g4x_sprite_max_stride;
1827                 intel_plane->update_plane = ivb_update_plane;
1828                 intel_plane->disable_plane = ivb_disable_plane;
1829                 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1830                 intel_plane->check_plane = g4x_sprite_check;
1831
1832                 plane_formats = snb_plane_formats;
1833                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1834                 modifiers = i9xx_plane_format_modifiers;
1835
1836                 plane_funcs = &snb_sprite_funcs;
1837         } else {
1838                 intel_plane->max_stride = g4x_sprite_max_stride;
1839                 intel_plane->update_plane = g4x_update_plane;
1840                 intel_plane->disable_plane = g4x_disable_plane;
1841                 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1842                 intel_plane->check_plane = g4x_sprite_check;
1843
1844                 modifiers = i9xx_plane_format_modifiers;
1845                 if (IS_GEN6(dev_priv)) {
1846                         plane_formats = snb_plane_formats;
1847                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1848
1849                         plane_funcs = &snb_sprite_funcs;
1850                 } else {
1851                         plane_formats = g4x_plane_formats;
1852                         num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1853
1854                         plane_funcs = &g4x_sprite_funcs;
1855                 }
1856         }
1857
1858         if (INTEL_GEN(dev_priv) >= 9) {
1859                 supported_rotations =
1860                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1861                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1862         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1863                 supported_rotations =
1864                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1865                         DRM_MODE_REFLECT_X;
1866         } else {
1867                 supported_rotations =
1868                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1869         }
1870
1871         intel_plane->pipe = pipe;
1872         intel_plane->i9xx_plane = plane;
1873         intel_plane->id = PLANE_SPRITE0 + plane;
1874         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
1875
1876         possible_crtcs = (1 << pipe);
1877
1878         if (INTEL_GEN(dev_priv) >= 9)
1879                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1880                                                possible_crtcs, plane_funcs,
1881                                                plane_formats, num_plane_formats,
1882                                                modifiers,
1883                                                DRM_PLANE_TYPE_OVERLAY,
1884                                                "plane %d%c", plane + 2, pipe_name(pipe));
1885         else
1886                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1887                                                possible_crtcs, plane_funcs,
1888                                                plane_formats, num_plane_formats,
1889                                                modifiers,
1890                                                DRM_PLANE_TYPE_OVERLAY,
1891                                                "sprite %c", sprite_name(pipe, plane));
1892         if (ret)
1893                 goto fail;
1894
1895         drm_plane_create_rotation_property(&intel_plane->base,
1896                                            DRM_MODE_ROTATE_0,
1897                                            supported_rotations);
1898
1899         drm_plane_create_color_properties(&intel_plane->base,
1900                                           BIT(DRM_COLOR_YCBCR_BT601) |
1901                                           BIT(DRM_COLOR_YCBCR_BT709),
1902                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1903                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1904                                           DRM_COLOR_YCBCR_BT709,
1905                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1906
1907         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1908
1909         return intel_plane;
1910
1911 fail:
1912         kfree(state);
1913         kfree(intel_plane);
1914
1915         return ERR_PTR(ret);
1916 }