drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <drm/drm_atomic_uapi.h>
  50 #include <linux/dma_remapping.h>
  51 #include <linux/reservation.h>
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t i8xx_primary_formats[] = {
  55         DRM_FORMAT_C8,
  56         DRM_FORMAT_RGB565,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_XRGB8888,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t i965_primary_formats[] = {
  63         DRM_FORMAT_C8,
  64         DRM_FORMAT_RGB565,
  65         DRM_FORMAT_XRGB8888,
  66         DRM_FORMAT_XBGR8888,
  67         DRM_FORMAT_XRGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69 };
  70
  71 static const uint64_t i9xx_format_modifiers[] = {
  72         I915_FORMAT_MOD_X_TILED,
  73         DRM_FORMAT_MOD_LINEAR,
  74         DRM_FORMAT_MOD_INVALID
  75 };
  76
  77 static const uint32_t skl_primary_formats[] = {
  78         DRM_FORMAT_C8,
  79         DRM_FORMAT_RGB565,
  80         DRM_FORMAT_XRGB8888,
  81         DRM_FORMAT_XBGR8888,
  82         DRM_FORMAT_ARGB8888,
  83         DRM_FORMAT_ABGR8888,
  84         DRM_FORMAT_XRGB2101010,
  85         DRM_FORMAT_XBGR2101010,
  86         DRM_FORMAT_YUYV,
  87         DRM_FORMAT_YVYU,
  88         DRM_FORMAT_UYVY,
  89         DRM_FORMAT_VYUY,
  90 };
  91
  92 static const uint32_t skl_pri_planar_formats[] = {
  93         DRM_FORMAT_C8,
  94         DRM_FORMAT_RGB565,
  95         DRM_FORMAT_XRGB8888,
  96         DRM_FORMAT_XBGR8888,
  97         DRM_FORMAT_ARGB8888,
  98         DRM_FORMAT_ABGR8888,
  99         DRM_FORMAT_XRGB2101010,
 100         DRM_FORMAT_XBGR2101010,
 101         DRM_FORMAT_YUYV,
 102         DRM_FORMAT_YVYU,
 103         DRM_FORMAT_UYVY,
 104         DRM_FORMAT_VYUY,
 105         DRM_FORMAT_NV12,
 106 };
 107
 108 static const uint64_t skl_format_modifiers_noccs[] = {
 109         I915_FORMAT_MOD_Yf_TILED,
 110         I915_FORMAT_MOD_Y_TILED,
 111         I915_FORMAT_MOD_X_TILED,
 112         DRM_FORMAT_MOD_LINEAR,
 113         DRM_FORMAT_MOD_INVALID
 114 };
 115
 116 static const uint64_t skl_format_modifiers_ccs[] = {
 117         I915_FORMAT_MOD_Yf_TILED_CCS,
 118         I915_FORMAT_MOD_Y_TILED_CCS,
 119         I915_FORMAT_MOD_Yf_TILED,
 120         I915_FORMAT_MOD_Y_TILED,
 121         I915_FORMAT_MOD_X_TILED,
 122         DRM_FORMAT_MOD_LINEAR,
 123         DRM_FORMAT_MOD_INVALID
 124 };
 125
 126 /* Cursor formats */
 127 static const uint32_t intel_cursor_formats[] = {
 128         DRM_FORMAT_ARGB8888,
 129 };
 130
 131 static const uint64_t cursor_format_modifiers[] = {
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 137                                 struct intel_crtc_state *pipe_config);
 138 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 139                                    struct intel_crtc_state *pipe_config);
 140
 141 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 142                                   struct drm_i915_gem_object *obj,
 143                                   struct drm_mode_fb_cmd2 *mode_cmd);
 144 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 145 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 146 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 147 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 148                                          struct intel_link_m_n *m_n,
 149                                          struct intel_link_m_n *m2_n2);
 150 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 151 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 152 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 153 static void vlv_prepare_pll(struct intel_crtc *crtc,
 154                             const struct intel_crtc_state *pipe_config);
 155 static void chv_prepare_pll(struct intel_crtc *crtc,
 156                             const struct intel_crtc_state *pipe_config);
 157 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 158 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 159 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 160                                     struct intel_crtc_state *crtc_state);
 161 static void skylake_pfit_enable(struct intel_crtc *crtc);
 162 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 163 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 164 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 165                                          struct drm_modeset_acquire_ctx *ctx);
 166 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 167
 168 struct intel_limit {
 169         struct {
 170                 int min, max;
 171         } dot, vco, n, m, m1, m2, p, p1;
 172
 173         struct {
 174                 int dot_limit;
 175                 int p2_slow, p2_fast;
 176         } p2;
 177 };
 178
 179 /* returns HPLL frequency in kHz */
 180 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 183
 184         /* Obtain SKU information */
 185         mutex_lock(&dev_priv->sb_lock);
 186         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 187                 CCK_FUSE_HPLL_FREQ_MASK;
 188         mutex_unlock(&dev_priv->sb_lock);
 189
 190         return vco_freq[hpll_freq] * 1000;
 191 }
 192
 193 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 194                       const char *name, u32 reg, int ref_freq)
 195 {
 196         u32 val;
 197         int divider;
 198
 199         mutex_lock(&dev_priv->sb_lock);
 200         val = vlv_cck_read(dev_priv, reg);
 201         mutex_unlock(&dev_priv->sb_lock);
 202
 203         divider = val & CCK_FREQUENCY_VALUES;
 204
 205         WARN((val & CCK_FREQUENCY_STATUS) !=
 206              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 207              "%s change in progress\n", name);
 208
 209         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 210 }
 211
 212 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 213                            const char *name, u32 reg)
 214 {
 215         if (dev_priv->hpll_freq == 0)
 216                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 217
 218         return vlv_get_cck_clock(dev_priv, name, reg,
 219                                  dev_priv->hpll_freq);
 220 }
 221
 222 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 223 {
 224         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 225                 return;
 226
 227         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 228                                                       CCK_CZ_CLOCK_CONTROL);
 229
 230         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 231 }
 232
 233 static inline u32 /* units of 100MHz */
 234 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 235                     const struct intel_crtc_state *pipe_config)
 236 {
 237         if (HAS_DDI(dev_priv))
 238                 return pipe_config->port_clock; /* SPLL */
 239         else
 240                 return dev_priv->fdi_pll_freq;
 241 }
 242
 243 static const struct intel_limit intel_limits_i8xx_dac = {
 244         .dot = { .min = 25000, .max = 350000 },
 245         .vco = { .min = 908000, .max = 1512000 },
 246         .n = { .min = 2, .max = 16 },
 247         .m = { .min = 96, .max = 140 },
 248         .m1 = { .min = 18, .max = 26 },
 249         .m2 = { .min = 6, .max = 16 },
 250         .p = { .min = 4, .max = 128 },
 251         .p1 = { .min = 2, .max = 33 },
 252         .p2 = { .dot_limit = 165000,
 253                 .p2_slow = 4, .p2_fast = 2 },
 254 };
 255
 256 static const struct intel_limit intel_limits_i8xx_dvo = {
 257         .dot = { .min = 25000, .max = 350000 },
 258         .vco = { .min = 908000, .max = 1512000 },
 259         .n = { .min = 2, .max = 16 },
 260         .m = { .min = 96, .max = 140 },
 261         .m1 = { .min = 18, .max = 26 },
 262         .m2 = { .min = 6, .max = 16 },
 263         .p = { .min = 4, .max = 128 },
 264         .p1 = { .min = 2, .max = 33 },
 265         .p2 = { .dot_limit = 165000,
 266                 .p2_slow = 4, .p2_fast = 4 },
 267 };
 268
 269 static const struct intel_limit intel_limits_i8xx_lvds = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 908000, .max = 1512000 },
 272         .n = { .min = 2, .max = 16 },
 273         .m = { .min = 96, .max = 140 },
 274         .m1 = { .min = 18, .max = 26 },
 275         .m2 = { .min = 6, .max = 16 },
 276         .p = { .min = 4, .max = 128 },
 277         .p1 = { .min = 1, .max = 6 },
 278         .p2 = { .dot_limit = 165000,
 279                 .p2_slow = 14, .p2_fast = 7 },
 280 };
 281
 282 static const struct intel_limit intel_limits_i9xx_sdvo = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1400000, .max = 2800000 },
 285         .n = { .min = 1, .max = 6 },
 286         .m = { .min = 70, .max = 120 },
 287         .m1 = { .min = 8, .max = 18 },
 288         .m2 = { .min = 3, .max = 7 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 200000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293 };
 294
 295 static const struct intel_limit intel_limits_i9xx_lvds = {
 296         .dot = { .min = 20000, .max = 400000 },
 297         .vco = { .min = 1400000, .max = 2800000 },
 298         .n = { .min = 1, .max = 6 },
 299         .m = { .min = 70, .max = 120 },
 300         .m1 = { .min = 8, .max = 18 },
 301         .m2 = { .min = 3, .max = 7 },
 302         .p = { .min = 7, .max = 98 },
 303         .p1 = { .min = 1, .max = 8 },
 304         .p2 = { .dot_limit = 112000,
 305                 .p2_slow = 14, .p2_fast = 7 },
 306 };
 307
 308
 309 static const struct intel_limit intel_limits_g4x_sdvo = {
 310         .dot = { .min = 25000, .max = 270000 },
 311         .vco = { .min = 1750000, .max = 3500000},
 312         .n = { .min = 1, .max = 4 },
 313         .m = { .min = 104, .max = 138 },
 314         .m1 = { .min = 17, .max = 23 },
 315         .m2 = { .min = 5, .max = 11 },
 316         .p = { .min = 10, .max = 30 },
 317         .p1 = { .min = 1, .max = 3},
 318         .p2 = { .dot_limit = 270000,
 319                 .p2_slow = 10,
 320                 .p2_fast = 10
 321         },
 322 };
 323
 324 static const struct intel_limit intel_limits_g4x_hdmi = {
 325         .dot = { .min = 22000, .max = 400000 },
 326         .vco = { .min = 1750000, .max = 3500000},
 327         .n = { .min = 1, .max = 4 },
 328         .m = { .min = 104, .max = 138 },
 329         .m1 = { .min = 16, .max = 23 },
 330         .m2 = { .min = 5, .max = 11 },
 331         .p = { .min = 5, .max = 80 },
 332         .p1 = { .min = 1, .max = 8},
 333         .p2 = { .dot_limit = 165000,
 334                 .p2_slow = 10, .p2_fast = 5 },
 335 };
 336
 337 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 338         .dot = { .min = 20000, .max = 115000 },
 339         .vco = { .min = 1750000, .max = 3500000 },
 340         .n = { .min = 1, .max = 3 },
 341         .m = { .min = 104, .max = 138 },
 342         .m1 = { .min = 17, .max = 23 },
 343         .m2 = { .min = 5, .max = 11 },
 344         .p = { .min = 28, .max = 112 },
 345         .p1 = { .min = 2, .max = 8 },
 346         .p2 = { .dot_limit = 0,
 347                 .p2_slow = 14, .p2_fast = 14
 348         },
 349 };
 350
 351 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 352         .dot = { .min = 80000, .max = 224000 },
 353         .vco = { .min = 1750000, .max = 3500000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 104, .max = 138 },
 356         .m1 = { .min = 17, .max = 23 },
 357         .m2 = { .min = 5, .max = 11 },
 358         .p = { .min = 14, .max = 42 },
 359         .p1 = { .min = 2, .max = 6 },
 360         .p2 = { .dot_limit = 0,
 361                 .p2_slow = 7, .p2_fast = 7
 362         },
 363 };
 364
 365 static const struct intel_limit intel_limits_pineview_sdvo = {
 366         .dot = { .min = 20000, .max = 400000},
 367         .vco = { .min = 1700000, .max = 3500000 },
 368         /* Pineview's Ncounter is a ring counter */
 369         .n = { .min = 3, .max = 6 },
 370         .m = { .min = 2, .max = 256 },
 371         /* Pineview only has one combined m divider, which we treat as m2. */
 372         .m1 = { .min = 0, .max = 0 },
 373         .m2 = { .min = 0, .max = 254 },
 374         .p = { .min = 5, .max = 80 },
 375         .p1 = { .min = 1, .max = 8 },
 376         .p2 = { .dot_limit = 200000,
 377                 .p2_slow = 10, .p2_fast = 5 },
 378 };
 379
 380 static const struct intel_limit intel_limits_pineview_lvds = {
 381         .dot = { .min = 20000, .max = 400000 },
 382         .vco = { .min = 1700000, .max = 3500000 },
 383         .n = { .min = 3, .max = 6 },
 384         .m = { .min = 2, .max = 256 },
 385         .m1 = { .min = 0, .max = 0 },
 386         .m2 = { .min = 0, .max = 254 },
 387         .p = { .min = 7, .max = 112 },
 388         .p1 = { .min = 1, .max = 8 },
 389         .p2 = { .dot_limit = 112000,
 390                 .p2_slow = 14, .p2_fast = 14 },
 391 };
 392
 393 /* Ironlake / Sandybridge
 394  *
 395  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 396  * the range value for them is (actual_value - 2).
 397  */
 398 static const struct intel_limit intel_limits_ironlake_dac = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 5 },
 402         .m = { .min = 79, .max = 127 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 5, .max = 80 },
 406         .p1 = { .min = 1, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 10, .p2_fast = 5 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 118 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 28, .max = 112 },
 419         .p1 = { .min = 2, .max = 8 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 14, .p2_fast = 14 },
 422 };
 423
 424 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 425         .dot = { .min = 25000, .max = 350000 },
 426         .vco = { .min = 1760000, .max = 3510000 },
 427         .n = { .min = 1, .max = 3 },
 428         .m = { .min = 79, .max = 127 },
 429         .m1 = { .min = 12, .max = 22 },
 430         .m2 = { .min = 5, .max = 9 },
 431         .p = { .min = 14, .max = 56 },
 432         .p1 = { .min = 2, .max = 8 },
 433         .p2 = { .dot_limit = 225000,
 434                 .p2_slow = 7, .p2_fast = 7 },
 435 };
 436
 437 /* LVDS 100mhz refclk limits. */
 438 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 439         .dot = { .min = 25000, .max = 350000 },
 440         .vco = { .min = 1760000, .max = 3510000 },
 441         .n = { .min = 1, .max = 2 },
 442         .m = { .min = 79, .max = 126 },
 443         .m1 = { .min = 12, .max = 22 },
 444         .m2 = { .min = 5, .max = 9 },
 445         .p = { .min = 28, .max = 112 },
 446         .p1 = { .min = 2, .max = 8 },
 447         .p2 = { .dot_limit = 225000,
 448                 .p2_slow = 14, .p2_fast = 14 },
 449 };
 450
 451 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 452         .dot = { .min = 25000, .max = 350000 },
 453         .vco = { .min = 1760000, .max = 3510000 },
 454         .n = { .min = 1, .max = 3 },
 455         .m = { .min = 79, .max = 126 },
 456         .m1 = { .min = 12, .max = 22 },
 457         .m2 = { .min = 5, .max = 9 },
 458         .p = { .min = 14, .max = 42 },
 459         .p1 = { .min = 2, .max = 6 },
 460         .p2 = { .dot_limit = 225000,
 461                 .p2_slow = 7, .p2_fast = 7 },
 462 };
 463
 464 static const struct intel_limit intel_limits_vlv = {
 465          /*
 466           * These are the data rate limits (measured in fast clocks)
 467           * since those are the strictest limits we have. The fast
 468           * clock and actual rate limits are more relaxed, so checking
 469           * them would make no difference.
 470           */
 471         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 472         .vco = { .min = 4000000, .max = 6000000 },
 473         .n = { .min = 1, .max = 7 },
 474         .m1 = { .min = 2, .max = 3 },
 475         .m2 = { .min = 11, .max = 156 },
 476         .p1 = { .min = 2, .max = 3 },
 477         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 478 };
 479
 480 static const struct intel_limit intel_limits_chv = {
 481         /*
 482          * These are the data rate limits (measured in fast clocks)
 483          * since those are the strictest limits we have.  The fast
 484          * clock and actual rate limits are more relaxed, so checking
 485          * them would make no difference.
 486          */
 487         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 488         .vco = { .min = 4800000, .max = 6480000 },
 489         .n = { .min = 1, .max = 1 },
 490         .m1 = { .min = 2, .max = 2 },
 491         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 492         .p1 = { .min = 2, .max = 4 },
 493         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 494 };
 495
 496 static const struct intel_limit intel_limits_bxt = {
 497         /* FIXME: find real dot limits */
 498         .dot = { .min = 0, .max = INT_MAX },
 499         .vco = { .min = 4800000, .max = 6700000 },
 500         .n = { .min = 1, .max = 1 },
 501         .m1 = { .min = 2, .max = 2 },
 502         /* FIXME: find real m2 limits */
 503         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 504         .p1 = { .min = 2, .max = 4 },
 505         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 506 };
 507
 508 static void
 509 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
 510 {
 511         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 512                 return;
 513
 514         if (enable)
 515                 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
 516         else
 517                 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
 518 }
 519
 520 static void
 521 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 522 {
 523         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 524                 return;
 525
 526         if (enable)
 527                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 528                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 529         else
 530                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 531                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 532                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 533 }
 534
 535 static bool
 536 needs_modeset(const struct drm_crtc_state *state)
 537 {
 538         return drm_atomic_crtc_needs_modeset(state);
 539 }
 540
 541 /*
 542  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 543  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 544  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 545  * The helpers' return value is the rate of the clock that is fed to the
 546  * display engine's pipe which can be the above fast dot clock rate or a
 547  * divided-down version of it.
 548  */
 549 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 550 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 551 {
 552         clock->m = clock->m2 + 2;
 553         clock->p = clock->p1 * clock->p2;
 554         if (WARN_ON(clock->n == 0 || clock->p == 0))
 555                 return 0;
 556         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558
 559         return clock->dot;
 560 }
 561
 562 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 563 {
 564         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 565 }
 566
 567 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 568 {
 569         clock->m = i9xx_dpll_compute_m(clock);
 570         clock->p = clock->p1 * clock->p2;
 571         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 572                 return 0;
 573         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 574         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 575
 576         return clock->dot;
 577 }
 578
 579 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 580 {
 581         clock->m = clock->m1 * clock->m2;
 582         clock->p = clock->p1 * clock->p2;
 583         if (WARN_ON(clock->n == 0 || clock->p == 0))
 584                 return 0;
 585         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 586         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 587
 588         return clock->dot / 5;
 589 }
 590
 591 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 592 {
 593         clock->m = clock->m1 * clock->m2;
 594         clock->p = clock->p1 * clock->p2;
 595         if (WARN_ON(clock->n == 0 || clock->p == 0))
 596                 return 0;
 597         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 598                         clock->n << 22);
 599         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 600
 601         return clock->dot / 5;
 602 }
 603
 604 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 605
 606 /*
 607  * Returns whether the given set of divisors are valid for a given refclk with
 608  * the given connectors.
 609  */
 610 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 611                                const struct intel_limit *limit,
 612                                const struct dpll *clock)
 613 {
 614         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 615                 INTELPllInvalid("n out of range\n");
 616         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 617                 INTELPllInvalid("p1 out of range\n");
 618         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 619                 INTELPllInvalid("m2 out of range\n");
 620         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 621                 INTELPllInvalid("m1 out of range\n");
 622
 623         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 624             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 625                 if (clock->m1 <= clock->m2)
 626                         INTELPllInvalid("m1 <= m2\n");
 627
 628         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 629             !IS_GEN9_LP(dev_priv)) {
 630                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 631                         INTELPllInvalid("p out of range\n");
 632                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 633                         INTELPllInvalid("m out of range\n");
 634         }
 635
 636         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 637                 INTELPllInvalid("vco out of range\n");
 638         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 639          * connector, etc., rather than just a single range.
 640          */
 641         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 642                 INTELPllInvalid("dot out of range\n");
 643
 644         return true;
 645 }
 646
 647 static int
 648 i9xx_select_p2_div(const struct intel_limit *limit,
 649                    const struct intel_crtc_state *crtc_state,
 650                    int target)
 651 {
 652         struct drm_device *dev = crtc_state->base.crtc->dev;
 653
 654         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 655                 /*
 656                  * For LVDS just rely on its current settings for dual-channel.
 657                  * We haven't figured out how to reliably set up different
 658                  * single/dual channel state, if we even can.
 659                  */
 660                 if (intel_is_dual_link_lvds(dev))
 661                         return limit->p2.p2_fast;
 662                 else
 663                         return limit->p2.p2_slow;
 664         } else {
 665                 if (target < limit->p2.dot_limit)
 666                         return limit->p2.p2_slow;
 667                 else
 668                         return limit->p2.p2_fast;
 669         }
 670 }
 671
 672 /*
 673  * Returns a set of divisors for the desired target clock with the given
 674  * refclk, or FALSE.  The returned values represent the clock equation:
 675  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 676  *
 677  * Target and reference clocks are specified in kHz.
 678  *
 679  * If match_clock is provided, then best_clock P divider must match the P
 680  * divider from @match_clock used for LVDS downclocking.
 681  */
 682 static bool
 683 i9xx_find_best_dpll(const struct intel_limit *limit,
 684                     struct intel_crtc_state *crtc_state,
 685                     int target, int refclk, struct dpll *match_clock,
 686                     struct dpll *best_clock)
 687 {
 688         struct drm_device *dev = crtc_state->base.crtc->dev;
 689         struct dpll clock;
 690         int err = target;
 691
 692         memset(best_clock, 0, sizeof(*best_clock));
 693
 694         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 695
 696         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 697              clock.m1++) {
 698                 for (clock.m2 = limit->m2.min;
 699                      clock.m2 <= limit->m2.max; clock.m2++) {
 700                         if (clock.m2 >= clock.m1)
 701                                 break;
 702                         for (clock.n = limit->n.min;
 703                              clock.n <= limit->n.max; clock.n++) {
 704                                 for (clock.p1 = limit->p1.min;
 705                                         clock.p1 <= limit->p1.max; clock.p1++) {
 706                                         int this_err;
 707
 708                                         i9xx_calc_dpll_params(refclk, &clock);
 709                                         if (!intel_PLL_is_valid(to_i915(dev),
 710                                                                 limit,
 711                                                                 &clock))
 712                                                 continue;
 713                                         if (match_clock &&
 714                                             clock.p != match_clock->p)
 715                                                 continue;
 716
 717                                         this_err = abs(clock.dot - target);
 718                                         if (this_err < err) {
 719                                                 *best_clock = clock;
 720                                                 err = this_err;
 721                                         }
 722                                 }
 723                         }
 724                 }
 725         }
 726
 727         return (err != target);
 728 }
 729
 730 /*
 731  * Returns a set of divisors for the desired target clock with the given
 732  * refclk, or FALSE.  The returned values represent the clock equation:
 733  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 734  *
 735  * Target and reference clocks are specified in kHz.
 736  *
 737  * If match_clock is provided, then best_clock P divider must match the P
 738  * divider from @match_clock used for LVDS downclocking.
 739  */
 740 static bool
 741 pnv_find_best_dpll(const struct intel_limit *limit,
 742                    struct intel_crtc_state *crtc_state,
 743                    int target, int refclk, struct dpll *match_clock,
 744                    struct dpll *best_clock)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747         struct dpll clock;
 748         int err = target;
 749
 750         memset(best_clock, 0, sizeof(*best_clock));
 751
 752         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 753
 754         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 755              clock.m1++) {
 756                 for (clock.m2 = limit->m2.min;
 757                      clock.m2 <= limit->m2.max; clock.m2++) {
 758                         for (clock.n = limit->n.min;
 759                              clock.n <= limit->n.max; clock.n++) {
 760                                 for (clock.p1 = limit->p1.min;
 761                                         clock.p1 <= limit->p1.max; clock.p1++) {
 762                                         int this_err;
 763
 764                                         pnv_calc_dpll_params(refclk, &clock);
 765                                         if (!intel_PLL_is_valid(to_i915(dev),
 766                                                                 limit,
 767                                                                 &clock))
 768                                                 continue;
 769                                         if (match_clock &&
 770                                             clock.p != match_clock->p)
 771                                                 continue;
 772
 773                                         this_err = abs(clock.dot - target);
 774                                         if (this_err < err) {
 775                                                 *best_clock = clock;
 776                                                 err = this_err;
 777                                         }
 778                                 }
 779                         }
 780                 }
 781         }
 782
 783         return (err != target);
 784 }
 785
 786 /*
 787  * Returns a set of divisors for the desired target clock with the given
 788  * refclk, or FALSE.  The returned values represent the clock equation:
 789  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 790  *
 791  * Target and reference clocks are specified in kHz.
 792  *
 793  * If match_clock is provided, then best_clock P divider must match the P
 794  * divider from @match_clock used for LVDS downclocking.
 795  */
 796 static bool
 797 g4x_find_best_dpll(const struct intel_limit *limit,
 798                    struct intel_crtc_state *crtc_state,
 799                    int target, int refclk, struct dpll *match_clock,
 800                    struct dpll *best_clock)
 801 {
 802         struct drm_device *dev = crtc_state->base.crtc->dev;
 803         struct dpll clock;
 804         int max_n;
 805         bool found = false;
 806         /* approximately equals target * 0.00585 */
 807         int err_most = (target >> 8) + (target >> 9);
 808
 809         memset(best_clock, 0, sizeof(*best_clock));
 810
 811         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 812
 813         max_n = limit->n.max;
 814         /* based on hardware requirement, prefer smaller n to precision */
 815         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 816                 /* based on hardware requirement, prefere larger m1,m2 */
 817                 for (clock.m1 = limit->m1.max;
 818                      clock.m1 >= limit->m1.min; clock.m1--) {
 819                         for (clock.m2 = limit->m2.max;
 820                              clock.m2 >= limit->m2.min; clock.m2--) {
 821                                 for (clock.p1 = limit->p1.max;
 822                                      clock.p1 >= limit->p1.min; clock.p1--) {
 823                                         int this_err;
 824
 825                                         i9xx_calc_dpll_params(refclk, &clock);
 826                                         if (!intel_PLL_is_valid(to_i915(dev),
 827                                                                 limit,
 828                                                                 &clock))
 829                                                 continue;
 830
 831                                         this_err = abs(clock.dot - target);
 832                                         if (this_err < err_most) {
 833                                                 *best_clock = clock;
 834                                                 err_most = this_err;
 835                                                 max_n = clock.n;
 836                                                 found = true;
 837                                         }
 838                                 }
 839                         }
 840                 }
 841         }
 842         return found;
 843 }
 844
 845 /*
 846  * Check if the calculated PLL configuration is more optimal compared to the
 847  * best configuration and error found so far. Return the calculated error.
 848  */
 849 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 850                                const struct dpll *calculated_clock,
 851                                const struct dpll *best_clock,
 852                                unsigned int best_error_ppm,
 853                                unsigned int *error_ppm)
 854 {
 855         /*
 856          * For CHV ignore the error and consider only the P value.
 857          * Prefer a bigger P value based on HW requirements.
 858          */
 859         if (IS_CHERRYVIEW(to_i915(dev))) {
 860                 *error_ppm = 0;
 861
 862                 return calculated_clock->p > best_clock->p;
 863         }
 864
 865         if (WARN_ON_ONCE(!target_freq))
 866                 return false;
 867
 868         *error_ppm = div_u64(1000000ULL *
 869                                 abs(target_freq - calculated_clock->dot),
 870                              target_freq);
 871         /*
 872          * Prefer a better P value over a better (smaller) error if the error
 873          * is small. Ensure this preference for future configurations too by
 874          * setting the error to 0.
 875          */
 876         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 877                 *error_ppm = 0;
 878
 879                 return true;
 880         }
 881
 882         return *error_ppm + 10 < best_error_ppm;
 883 }
 884
 885 /*
 886  * Returns a set of divisors for the desired target clock with the given
 887  * refclk, or FALSE.  The returned values represent the clock equation:
 888  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 889  */
 890 static bool
 891 vlv_find_best_dpll(const struct intel_limit *limit,
 892                    struct intel_crtc_state *crtc_state,
 893                    int target, int refclk, struct dpll *match_clock,
 894                    struct dpll *best_clock)
 895 {
 896         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 897         struct drm_device *dev = crtc->base.dev;
 898         struct dpll clock;
 899         unsigned int bestppm = 1000000;
 900         /* min update 19.2 MHz */
 901         int max_n = min(limit->n.max, refclk / 19200);
 902         bool found = false;
 903
 904         target *= 5; /* fast clock */
 905
 906         memset(best_clock, 0, sizeof(*best_clock));
 907
 908         /* based on hardware requirement, prefer smaller n to precision */
 909         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 910                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 911                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 912                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 913                                 clock.p = clock.p1 * clock.p2;
 914                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 915                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 916                                         unsigned int ppm;
 917
 918                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 919                                                                      refclk * clock.m1);
 920
 921                                         vlv_calc_dpll_params(refclk, &clock);
 922
 923                                         if (!intel_PLL_is_valid(to_i915(dev),
 924                                                                 limit,
 925                                                                 &clock))
 926                                                 continue;
 927
 928                                         if (!vlv_PLL_is_optimal(dev, target,
 929                                                                 &clock,
 930                                                                 best_clock,
 931                                                                 bestppm, &ppm))
 932                                                 continue;
 933
 934                                         *best_clock = clock;
 935                                         bestppm = ppm;
 936                                         found = true;
 937                                 }
 938                         }
 939                 }
 940         }
 941
 942         return found;
 943 }
 944
 945 /*
 946  * Returns a set of divisors for the desired target clock with the given
 947  * refclk, or FALSE.  The returned values represent the clock equation:
 948  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 949  */
 950 static bool
 951 chv_find_best_dpll(const struct intel_limit *limit,
 952                    struct intel_crtc_state *crtc_state,
 953                    int target, int refclk, struct dpll *match_clock,
 954                    struct dpll *best_clock)
 955 {
 956         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 957         struct drm_device *dev = crtc->base.dev;
 958         unsigned int best_error_ppm;
 959         struct dpll clock;
 960         uint64_t m2;
 961         int found = false;
 962
 963         memset(best_clock, 0, sizeof(*best_clock));
 964         best_error_ppm = 1000000;
 965
 966         /*
 967          * Based on hardware doc, the n always set to 1, and m1 always
 968          * set to 2.  If requires to support 200Mhz refclk, we need to
 969          * revisit this because n may not 1 anymore.
 970          */
 971         clock.n = 1, clock.m1 = 2;
 972         target *= 5;    /* fast clock */
 973
 974         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 975                 for (clock.p2 = limit->p2.p2_fast;
 976                                 clock.p2 >= limit->p2.p2_slow;
 977                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 978                         unsigned int error_ppm;
 979
 980                         clock.p = clock.p1 * clock.p2;
 981
 982                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 983                                         clock.n) << 22, refclk * clock.m1);
 984
 985                         if (m2 > INT_MAX/clock.m1)
 986                                 continue;
 987
 988                         clock.m2 = m2;
 989
 990                         chv_calc_dpll_params(refclk, &clock);
 991
 992                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 993                                 continue;
 994
 995                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 996                                                 best_error_ppm, &error_ppm))
 997                                 continue;
 998
 999                         *best_clock = clock;
1000                         best_error_ppm = error_ppm;
1001                         found = true;
1002                 }
1003         }
1004
1005         return found;
1006 }
1007
1008 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1009                         struct dpll *best_clock)
1010 {
1011         int refclk = 100000;
1012         const struct intel_limit *limit = &intel_limits_bxt;
1013
1014         return chv_find_best_dpll(limit, crtc_state,
1015                                   target_clock, refclk, NULL, best_clock);
1016 }
1017
1018 bool intel_crtc_active(struct intel_crtc *crtc)
1019 {
1020         /* Be paranoid as we can arrive here with only partial
1021          * state retrieved from the hardware during setup.
1022          *
1023          * We can ditch the adjusted_mode.crtc_clock check as soon
1024          * as Haswell has gained clock readout/fastboot support.
1025          *
1026          * We can ditch the crtc->primary->state->fb check as soon as we can
1027          * properly reconstruct framebuffers.
1028          *
1029          * FIXME: The intel_crtc->active here should be switched to
1030          * crtc->state->active once we have proper CRTC states wired up
1031          * for atomic.
1032          */
1033         return crtc->active && crtc->base.primary->state->fb &&
1034                 crtc->config->base.adjusted_mode.crtc_clock;
1035 }
1036
1037 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1038                                              enum pipe pipe)
1039 {
1040         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1041
1042         return crtc->config->cpu_transcoder;
1043 }
1044
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1046                                     enum pipe pipe)
1047 {
1048         i915_reg_t reg = PIPEDSL(pipe);
1049         u32 line1, line2;
1050         u32 line_mask;
1051
1052         if (IS_GEN2(dev_priv))
1053                 line_mask = DSL_LINEMASK_GEN2;
1054         else
1055                 line_mask = DSL_LINEMASK_GEN3;
1056
1057         line1 = I915_READ(reg) & line_mask;
1058         msleep(5);
1059         line2 = I915_READ(reg) & line_mask;
1060
1061         return line1 != line2;
1062 }
1063
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1065 {
1066         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067         enum pipe pipe = crtc->pipe;
1068
1069         /* Wait for the display line to settle/start moving */
1070         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1072                           pipe_name(pipe), onoff(state));
1073 }
1074
1075 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1076 {
1077         wait_for_pipe_scanline_moving(crtc, false);
1078 }
1079
1080 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1081 {
1082         wait_for_pipe_scanline_moving(crtc, true);
1083 }
1084
1085 static void
1086 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1087 {
1088         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1089         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1090
1091         if (INTEL_GEN(dev_priv) >= 4) {
1092                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1093                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1094
1095                 /* Wait for the Pipe State to go off */
1096                 if (intel_wait_for_register(dev_priv,
1097                                             reg, I965_PIPECONF_ACTIVE, 0,
1098                                             100))
1099                         WARN(1, "pipe_off wait timed out\n");
1100         } else {
1101                 intel_wait_for_pipe_scanline_stopped(crtc);
1102         }
1103 }
1104
1105 /* Only for pre-ILK configs */
1106 void assert_pll(struct drm_i915_private *dev_priv,
1107                 enum pipe pipe, bool state)
1108 {
1109         u32 val;
1110         bool cur_state;
1111
1112         val = I915_READ(DPLL(pipe));
1113         cur_state = !!(val & DPLL_VCO_ENABLE);
1114         I915_STATE_WARN(cur_state != state,
1115              "PLL state assertion failure (expected %s, current %s)\n",
1116                         onoff(state), onoff(cur_state));
1117 }
1118
1119 /* XXX: the dsi pll is shared between MIPI DSI ports */
1120 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1121 {
1122         u32 val;
1123         bool cur_state;
1124
1125         mutex_lock(&dev_priv->sb_lock);
1126         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1127         mutex_unlock(&dev_priv->sb_lock);
1128
1129         cur_state = val & DSI_PLL_VCO_EN;
1130         I915_STATE_WARN(cur_state != state,
1131              "DSI PLL state assertion failure (expected %s, current %s)\n",
1132                         onoff(state), onoff(cur_state));
1133 }
1134
1135 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1136                           enum pipe pipe, bool state)
1137 {
1138         bool cur_state;
1139         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1140                                                                       pipe);
1141
1142         if (HAS_DDI(dev_priv)) {
1143                 /* DDI does not have a specific FDI_TX register */
1144                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1145                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1146         } else {
1147                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1148                 cur_state = !!(val & FDI_TX_ENABLE);
1149         }
1150         I915_STATE_WARN(cur_state != state,
1151              "FDI TX state assertion failure (expected %s, current %s)\n",
1152                         onoff(state), onoff(cur_state));
1153 }
1154 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1155 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1156
1157 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1158                           enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(FDI_RX_CTL(pipe));
1164         cur_state = !!(val & FDI_RX_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "FDI RX state assertion failure (expected %s, current %s)\n",
1167                         onoff(state), onoff(cur_state));
1168 }
1169 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1170 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1171
1172 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1173                                       enum pipe pipe)
1174 {
1175         u32 val;
1176
1177         /* ILK FDI PLL is always enabled */
1178         if (IS_GEN5(dev_priv))
1179                 return;
1180
1181         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1182         if (HAS_DDI(dev_priv))
1183                 return;
1184
1185         val = I915_READ(FDI_TX_CTL(pipe));
1186         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1187 }
1188
1189 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1190                        enum pipe pipe, bool state)
1191 {
1192         u32 val;
1193         bool cur_state;
1194
1195         val = I915_READ(FDI_RX_CTL(pipe));
1196         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1197         I915_STATE_WARN(cur_state != state,
1198              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1199                         onoff(state), onoff(cur_state));
1200 }
1201
1202 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1203 {
1204         i915_reg_t pp_reg;
1205         u32 val;
1206         enum pipe panel_pipe = INVALID_PIPE;
1207         bool locked = true;
1208
1209         if (WARN_ON(HAS_DDI(dev_priv)))
1210                 return;
1211
1212         if (HAS_PCH_SPLIT(dev_priv)) {
1213                 u32 port_sel;
1214
1215                 pp_reg = PP_CONTROL(0);
1216                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1217
1218                 switch (port_sel) {
1219                 case PANEL_PORT_SELECT_LVDS:
1220                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1221                         break;
1222                 case PANEL_PORT_SELECT_DPA:
1223                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1224                         break;
1225                 case PANEL_PORT_SELECT_DPC:
1226                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1227                         break;
1228                 case PANEL_PORT_SELECT_DPD:
1229                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1230                         break;
1231                 default:
1232                         MISSING_CASE(port_sel);
1233                         break;
1234                 }
1235         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1236                 /* presumably write lock depends on pipe, not port select */
1237                 pp_reg = PP_CONTROL(pipe);
1238                 panel_pipe = pipe;
1239         } else {
1240                 u32 port_sel;
1241
1242                 pp_reg = PP_CONTROL(0);
1243                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1244
1245                 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1246                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1247         }
1248
1249         val = I915_READ(pp_reg);
1250         if (!(val & PANEL_POWER_ON) ||
1251             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1252                 locked = false;
1253
1254         I915_STATE_WARN(panel_pipe == pipe && locked,
1255              "panel assertion failure, pipe %c regs locked\n",
1256              pipe_name(pipe));
1257 }
1258
1259 void assert_pipe(struct drm_i915_private *dev_priv,
1260                  enum pipe pipe, bool state)
1261 {
1262         bool cur_state;
1263         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1264                                                                       pipe);
1265         enum intel_display_power_domain power_domain;
1266
1267         /* we keep both pipes enabled on 830 */
1268         if (IS_I830(dev_priv))
1269                 state = true;
1270
1271         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1272         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1273                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1274                 cur_state = !!(val & PIPECONF_ENABLE);
1275
1276                 intel_display_power_put(dev_priv, power_domain);
1277         } else {
1278                 cur_state = false;
1279         }
1280
1281         I915_STATE_WARN(cur_state != state,
1282              "pipe %c assertion failure (expected %s, current %s)\n",
1283                         pipe_name(pipe), onoff(state), onoff(cur_state));
1284 }
1285
1286 static void assert_plane(struct intel_plane *plane, bool state)
1287 {
1288         enum pipe pipe;
1289         bool cur_state;
1290
1291         cur_state = plane->get_hw_state(plane, &pipe);
1292
1293         I915_STATE_WARN(cur_state != state,
1294                         "%s assertion failure (expected %s, current %s)\n",
1295                         plane->base.name, onoff(state), onoff(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(p) assert_plane(p, true)
1299 #define assert_plane_disabled(p) assert_plane(p, false)
1300
1301 static void assert_planes_disabled(struct intel_crtc *crtc)
1302 {
1303         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1304         struct intel_plane *plane;
1305
1306         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1307                 assert_plane_disabled(plane);
1308 }
1309
1310 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 {
1312         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1313                 drm_crtc_vblank_put(crtc);
1314 }
1315
1316 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         u32 val;
1320         bool enabled;
1321
1322         val = I915_READ(PCH_TRANSCONF(pipe));
1323         enabled = !!(val & TRANS_ENABLE);
1324         I915_STATE_WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1330                                    enum pipe pipe, enum port port,
1331                                    i915_reg_t dp_reg)
1332 {
1333         enum pipe port_pipe;
1334         bool state;
1335
1336         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1337
1338         I915_STATE_WARN(state && port_pipe == pipe,
1339                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1340                         port_name(port), pipe_name(pipe));
1341
1342         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1343                         "IBX PCH DP %c still using transcoder B\n",
1344                         port_name(port));
1345 }
1346
1347 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1348                                      enum pipe pipe, enum port port,
1349                                      i915_reg_t hdmi_reg)
1350 {
1351         enum pipe port_pipe;
1352         bool state;
1353
1354         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1355
1356         I915_STATE_WARN(state && port_pipe == pipe,
1357                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1358                         port_name(port), pipe_name(pipe));
1359
1360         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1361                         "IBX PCH HDMI %c still using transcoder B\n",
1362                         port_name(port));
1363 }
1364
1365 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1366                                       enum pipe pipe)
1367 {
1368         enum pipe port_pipe;
1369
1370         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1371         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1372         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1373
1374         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1375                         port_pipe == pipe,
1376                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1377                         pipe_name(pipe));
1378
1379         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1380                         port_pipe == pipe,
1381                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1382                         pipe_name(pipe));
1383
1384         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1385         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1386         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1387 }
1388
1389 static void _vlv_enable_pll(struct intel_crtc *crtc,
1390                             const struct intel_crtc_state *pipe_config)
1391 {
1392         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1393         enum pipe pipe = crtc->pipe;
1394
1395         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1396         POSTING_READ(DPLL(pipe));
1397         udelay(150);
1398
1399         if (intel_wait_for_register(dev_priv,
1400                                     DPLL(pipe),
1401                                     DPLL_LOCK_VLV,
1402                                     DPLL_LOCK_VLV,
1403                                     1))
1404                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1405 }
1406
1407 static void vlv_enable_pll(struct intel_crtc *crtc,
1408                            const struct intel_crtc_state *pipe_config)
1409 {
1410         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1411         enum pipe pipe = crtc->pipe;
1412
1413         assert_pipe_disabled(dev_priv, pipe);
1414
1415         /* PLL is protected by panel, make sure we can write it */
1416         assert_panel_unlocked(dev_priv, pipe);
1417
1418         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1419                 _vlv_enable_pll(crtc, pipe_config);
1420
1421         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1422         POSTING_READ(DPLL_MD(pipe));
1423 }
1424
1425
1426 static void _chv_enable_pll(struct intel_crtc *crtc,
1427                             const struct intel_crtc_state *pipe_config)
1428 {
1429         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1430         enum pipe pipe = crtc->pipe;
1431         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1432         u32 tmp;
1433
1434         mutex_lock(&dev_priv->sb_lock);
1435
1436         /* Enable back the 10bit clock to display controller */
1437         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1438         tmp |= DPIO_DCLKP_EN;
1439         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1440
1441         mutex_unlock(&dev_priv->sb_lock);
1442
1443         /*
1444          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1445          */
1446         udelay(1);
1447
1448         /* Enable PLL */
1449         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1450
1451         /* Check PLL is locked */
1452         if (intel_wait_for_register(dev_priv,
1453                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1454                                     1))
1455                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1456 }
1457
1458 static void chv_enable_pll(struct intel_crtc *crtc,
1459                            const struct intel_crtc_state *pipe_config)
1460 {
1461         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1462         enum pipe pipe = crtc->pipe;
1463
1464         assert_pipe_disabled(dev_priv, pipe);
1465
1466         /* PLL is protected by panel, make sure we can write it */
1467         assert_panel_unlocked(dev_priv, pipe);
1468
1469         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1470                 _chv_enable_pll(crtc, pipe_config);
1471
1472         if (pipe != PIPE_A) {
1473                 /*
1474                  * WaPixelRepeatModeFixForC0:chv
1475                  *
1476                  * DPLLCMD is AWOL. Use chicken bits to propagate
1477                  * the value from DPLLBMD to either pipe B or C.
1478                  */
1479                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1480                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1481                 I915_WRITE(CBR4_VLV, 0);
1482                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1483
1484                 /*
1485                  * DPLLB VGA mode also seems to cause problems.
1486                  * We should always have it disabled.
1487                  */
1488                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1489         } else {
1490                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1491                 POSTING_READ(DPLL_MD(pipe));
1492         }
1493 }
1494
1495 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1496 {
1497         struct intel_crtc *crtc;
1498         int count = 0;
1499
1500         for_each_intel_crtc(&dev_priv->drm, crtc) {
1501                 count += crtc->base.state->active &&
1502                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1503         }
1504
1505         return count;
1506 }
1507
1508 static void i9xx_enable_pll(struct intel_crtc *crtc,
1509                             const struct intel_crtc_state *crtc_state)
1510 {
1511         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1512         i915_reg_t reg = DPLL(crtc->pipe);
1513         u32 dpll = crtc_state->dpll_hw_state.dpll;
1514         int i;
1515
1516         assert_pipe_disabled(dev_priv, crtc->pipe);
1517
1518         /* PLL is protected by panel, make sure we can write it */
1519         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1520                 assert_panel_unlocked(dev_priv, crtc->pipe);
1521
1522         /* Enable DVO 2x clock on both PLLs if necessary */
1523         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1524                 /*
1525                  * It appears to be important that we don't enable this
1526                  * for the current pipe before otherwise configuring the
1527                  * PLL. No idea how this should be handled if multiple
1528                  * DVO outputs are enabled simultaneosly.
1529                  */
1530                 dpll |= DPLL_DVO_2X_MODE;
1531                 I915_WRITE(DPLL(!crtc->pipe),
1532                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1533         }
1534
1535         /*
1536          * Apparently we need to have VGA mode enabled prior to changing
1537          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1538          * dividers, even though the register value does change.
1539          */
1540         I915_WRITE(reg, 0);
1541
1542         I915_WRITE(reg, dpll);
1543
1544         /* Wait for the clocks to stabilize. */
1545         POSTING_READ(reg);
1546         udelay(150);
1547
1548         if (INTEL_GEN(dev_priv) >= 4) {
1549                 I915_WRITE(DPLL_MD(crtc->pipe),
1550                            crtc_state->dpll_hw_state.dpll_md);
1551         } else {
1552                 /* The pixel multiplier can only be updated once the
1553                  * DPLL is enabled and the clocks are stable.
1554                  *
1555                  * So write it again.
1556                  */
1557                 I915_WRITE(reg, dpll);
1558         }
1559
1560         /* We do this three times for luck */
1561         for (i = 0; i < 3; i++) {
1562                 I915_WRITE(reg, dpll);
1563                 POSTING_READ(reg);
1564                 udelay(150); /* wait for warmup */
1565         }
1566 }
1567
1568 static void i9xx_disable_pll(struct intel_crtc *crtc)
1569 {
1570         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1571         enum pipe pipe = crtc->pipe;
1572
1573         /* Disable DVO 2x clock on both PLLs if necessary */
1574         if (IS_I830(dev_priv) &&
1575             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1576             !intel_num_dvo_pipes(dev_priv)) {
1577                 I915_WRITE(DPLL(PIPE_B),
1578                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1579                 I915_WRITE(DPLL(PIPE_A),
1580                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1581         }
1582
1583         /* Don't disable pipe or pipe PLLs if needed */
1584         if (IS_I830(dev_priv))
1585                 return;
1586
1587         /* Make sure the pipe isn't still relying on us */
1588         assert_pipe_disabled(dev_priv, pipe);
1589
1590         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1591         POSTING_READ(DPLL(pipe));
1592 }
1593
1594 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1595 {
1596         u32 val;
1597
1598         /* Make sure the pipe isn't still relying on us */
1599         assert_pipe_disabled(dev_priv, pipe);
1600
1601         val = DPLL_INTEGRATED_REF_CLK_VLV |
1602                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1603         if (pipe != PIPE_A)
1604                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1605
1606         I915_WRITE(DPLL(pipe), val);
1607         POSTING_READ(DPLL(pipe));
1608 }
1609
1610 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1611 {
1612         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1613         u32 val;
1614
1615         /* Make sure the pipe isn't still relying on us */
1616         assert_pipe_disabled(dev_priv, pipe);
1617
1618         val = DPLL_SSC_REF_CLK_CHV |
1619                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1620         if (pipe != PIPE_A)
1621                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1622
1623         I915_WRITE(DPLL(pipe), val);
1624         POSTING_READ(DPLL(pipe));
1625
1626         mutex_lock(&dev_priv->sb_lock);
1627
1628         /* Disable 10bit clock to display controller */
1629         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1630         val &= ~DPIO_DCLKP_EN;
1631         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1632
1633         mutex_unlock(&dev_priv->sb_lock);
1634 }
1635
1636 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1637                          struct intel_digital_port *dport,
1638                          unsigned int expected_mask)
1639 {
1640         u32 port_mask;
1641         i915_reg_t dpll_reg;
1642
1643         switch (dport->base.port) {
1644         case PORT_B:
1645                 port_mask = DPLL_PORTB_READY_MASK;
1646                 dpll_reg = DPLL(0);
1647                 break;
1648         case PORT_C:
1649                 port_mask = DPLL_PORTC_READY_MASK;
1650                 dpll_reg = DPLL(0);
1651                 expected_mask <<= 4;
1652                 break;
1653         case PORT_D:
1654                 port_mask = DPLL_PORTD_READY_MASK;
1655                 dpll_reg = DPIO_PHY_STATUS;
1656                 break;
1657         default:
1658                 BUG();
1659         }
1660
1661         if (intel_wait_for_register(dev_priv,
1662                                     dpll_reg, port_mask, expected_mask,
1663                                     1000))
1664                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1665                      port_name(dport->base.port),
1666                      I915_READ(dpll_reg) & port_mask, expected_mask);
1667 }
1668
1669 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1670                                            enum pipe pipe)
1671 {
1672         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1673                                                                 pipe);
1674         i915_reg_t reg;
1675         uint32_t val, pipeconf_val;
1676
1677         /* Make sure PCH DPLL is enabled */
1678         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, pipe);
1682         assert_fdi_rx_enabled(dev_priv, pipe);
1683
1684         if (HAS_PCH_CPT(dev_priv)) {
1685                 /* Workaround: Set the timing override bit before enabling the
1686                  * pch transcoder. */
1687                 reg = TRANS_CHICKEN2(pipe);
1688                 val = I915_READ(reg);
1689                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1690                 I915_WRITE(reg, val);
1691         }
1692
1693         reg = PCH_TRANSCONF(pipe);
1694         val = I915_READ(reg);
1695         pipeconf_val = I915_READ(PIPECONF(pipe));
1696
1697         if (HAS_PCH_IBX(dev_priv)) {
1698                 /*
1699                  * Make the BPC in transcoder be consistent with
1700                  * that in pipeconf reg. For HDMI we must use 8bpc
1701                  * here for both 8bpc and 12bpc.
1702                  */
1703                 val &= ~PIPECONF_BPC_MASK;
1704                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1705                         val |= PIPECONF_8BPC;
1706                 else
1707                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1708         }
1709
1710         val &= ~TRANS_INTERLACE_MASK;
1711         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1712                 if (HAS_PCH_IBX(dev_priv) &&
1713                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1714                         val |= TRANS_LEGACY_INTERLACED_ILK;
1715                 else
1716                         val |= TRANS_INTERLACED;
1717         else
1718                 val |= TRANS_PROGRESSIVE;
1719
1720         I915_WRITE(reg, val | TRANS_ENABLE);
1721         if (intel_wait_for_register(dev_priv,
1722                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1723                                     100))
1724                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1725 }
1726
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728                                       enum transcoder cpu_transcoder)
1729 {
1730         u32 val, pipeconf_val;
1731
1732         /* FDI must be feeding us bits for PCH ports */
1733         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1734         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1735
1736         /* Workaround: set timing override bit. */
1737         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1738         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1739         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1740
1741         val = TRANS_ENABLE;
1742         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1743
1744         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1745             PIPECONF_INTERLACED_ILK)
1746                 val |= TRANS_INTERLACED;
1747         else
1748                 val |= TRANS_PROGRESSIVE;
1749
1750         I915_WRITE(LPT_TRANSCONF, val);
1751         if (intel_wait_for_register(dev_priv,
1752                                     LPT_TRANSCONF,
1753                                     TRANS_STATE_ENABLE,
1754                                     TRANS_STATE_ENABLE,
1755                                     100))
1756                 DRM_ERROR("Failed to enable PCH transcoder\n");
1757 }
1758
1759 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1760                                             enum pipe pipe)
1761 {
1762         i915_reg_t reg;
1763         uint32_t val;
1764
1765         /* FDI relies on the transcoder */
1766         assert_fdi_tx_disabled(dev_priv, pipe);
1767         assert_fdi_rx_disabled(dev_priv, pipe);
1768
1769         /* Ports must be off as well */
1770         assert_pch_ports_disabled(dev_priv, pipe);
1771
1772         reg = PCH_TRANSCONF(pipe);
1773         val = I915_READ(reg);
1774         val &= ~TRANS_ENABLE;
1775         I915_WRITE(reg, val);
1776         /* wait for PCH transcoder off, transcoder state */
1777         if (intel_wait_for_register(dev_priv,
1778                                     reg, TRANS_STATE_ENABLE, 0,
1779                                     50))
1780                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1781
1782         if (HAS_PCH_CPT(dev_priv)) {
1783                 /* Workaround: Clear the timing override chicken bit again. */
1784                 reg = TRANS_CHICKEN2(pipe);
1785                 val = I915_READ(reg);
1786                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1787                 I915_WRITE(reg, val);
1788         }
1789 }
1790
1791 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1792 {
1793         u32 val;
1794
1795         val = I915_READ(LPT_TRANSCONF);
1796         val &= ~TRANS_ENABLE;
1797         I915_WRITE(LPT_TRANSCONF, val);
1798         /* wait for PCH transcoder off, transcoder state */
1799         if (intel_wait_for_register(dev_priv,
1800                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1801                                     50))
1802                 DRM_ERROR("Failed to disable PCH transcoder\n");
1803
1804         /* Workaround: clear timing override bit. */
1805         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1806         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1807         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1808 }
1809
1810 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1811 {
1812         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1813
1814         if (HAS_PCH_LPT(dev_priv))
1815                 return PIPE_A;
1816         else
1817                 return crtc->pipe;
1818 }
1819
1820 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1821 {
1822         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1823         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1824         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1825         enum pipe pipe = crtc->pipe;
1826         i915_reg_t reg;
1827         u32 val;
1828
1829         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1830
1831         assert_planes_disabled(crtc);
1832
1833         /*
1834          * A pipe without a PLL won't actually be able to drive bits from
1835          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1836          * need the check.
1837          */
1838         if (HAS_GMCH_DISPLAY(dev_priv)) {
1839                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1840                         assert_dsi_pll_enabled(dev_priv);
1841                 else
1842                         assert_pll_enabled(dev_priv, pipe);
1843         } else {
1844                 if (new_crtc_state->has_pch_encoder) {
1845                         /* if driving the PCH, we need FDI enabled */
1846                         assert_fdi_rx_pll_enabled(dev_priv,
1847                                                   intel_crtc_pch_transcoder(crtc));
1848                         assert_fdi_tx_pll_enabled(dev_priv,
1849                                                   (enum pipe) cpu_transcoder);
1850                 }
1851                 /* FIXME: assert CPU port conditions for SNB+ */
1852         }
1853
1854         reg = PIPECONF(cpu_transcoder);
1855         val = I915_READ(reg);
1856         if (val & PIPECONF_ENABLE) {
1857                 /* we keep both pipes enabled on 830 */
1858                 WARN_ON(!IS_I830(dev_priv));
1859                 return;
1860         }
1861
1862         I915_WRITE(reg, val | PIPECONF_ENABLE);
1863         POSTING_READ(reg);
1864
1865         /*
1866          * Until the pipe starts PIPEDSL reads will return a stale value,
1867          * which causes an apparent vblank timestamp jump when PIPEDSL
1868          * resets to its proper value. That also messes up the frame count
1869          * when it's derived from the timestamps. So let's wait for the
1870          * pipe to start properly before we call drm_crtc_vblank_on()
1871          */
1872         if (dev_priv->drm.max_vblank_count == 0)
1873                 intel_wait_for_pipe_scanline_moving(crtc);
1874 }
1875
1876 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1877 {
1878         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1879         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1880         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1881         enum pipe pipe = crtc->pipe;
1882         i915_reg_t reg;
1883         u32 val;
1884
1885         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1886
1887         /*
1888          * Make sure planes won't keep trying to pump pixels to us,
1889          * or we might hang the display.
1890          */
1891         assert_planes_disabled(crtc);
1892
1893         reg = PIPECONF(cpu_transcoder);
1894         val = I915_READ(reg);
1895         if ((val & PIPECONF_ENABLE) == 0)
1896                 return;
1897
1898         /*
1899          * Double wide has implications for planes
1900          * so best keep it disabled when not needed.
1901          */
1902         if (old_crtc_state->double_wide)
1903                 val &= ~PIPECONF_DOUBLE_WIDE;
1904
1905         /* Don't disable pipe or pipe PLLs if needed */
1906         if (!IS_I830(dev_priv))
1907                 val &= ~PIPECONF_ENABLE;
1908
1909         I915_WRITE(reg, val);
1910         if ((val & PIPECONF_ENABLE) == 0)
1911                 intel_wait_for_pipe_off(old_crtc_state);
1912 }
1913
1914 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1915 {
1916         return IS_GEN2(dev_priv) ? 2048 : 4096;
1917 }
1918
1919 static unsigned int
1920 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1921 {
1922         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1923         unsigned int cpp = fb->format->cpp[color_plane];
1924
1925         switch (fb->modifier) {
1926         case DRM_FORMAT_MOD_LINEAR:
1927                 return cpp;
1928         case I915_FORMAT_MOD_X_TILED:
1929                 if (IS_GEN2(dev_priv))
1930                         return 128;
1931                 else
1932                         return 512;
1933         case I915_FORMAT_MOD_Y_TILED_CCS:
1934                 if (color_plane == 1)
1935                         return 128;
1936                 /* fall through */
1937         case I915_FORMAT_MOD_Y_TILED:
1938                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1939                         return 128;
1940                 else
1941                         return 512;
1942         case I915_FORMAT_MOD_Yf_TILED_CCS:
1943                 if (color_plane == 1)
1944                         return 128;
1945                 /* fall through */
1946         case I915_FORMAT_MOD_Yf_TILED:
1947                 switch (cpp) {
1948                 case 1:
1949                         return 64;
1950                 case 2:
1951                 case 4:
1952                         return 128;
1953                 case 8:
1954                 case 16:
1955                         return 256;
1956                 default:
1957                         MISSING_CASE(cpp);
1958                         return cpp;
1959                 }
1960                 break;
1961         default:
1962                 MISSING_CASE(fb->modifier);
1963                 return cpp;
1964         }
1965 }
1966
1967 static unsigned int
1968 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1969 {
1970         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1971                 return 1;
1972         else
1973                 return intel_tile_size(to_i915(fb->dev)) /
1974                         intel_tile_width_bytes(fb, color_plane);
1975 }
1976
1977 /* Return the tile dimensions in pixel units */
1978 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1979                             unsigned int *tile_width,
1980                             unsigned int *tile_height)
1981 {
1982         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1983         unsigned int cpp = fb->format->cpp[color_plane];
1984
1985         *tile_width = tile_width_bytes / cpp;
1986         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1987 }
1988
1989 unsigned int
1990 intel_fb_align_height(const struct drm_framebuffer *fb,
1991                       int color_plane, unsigned int height)
1992 {
1993         unsigned int tile_height = intel_tile_height(fb, color_plane);
1994
1995         return ALIGN(height, tile_height);
1996 }
1997
1998 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1999 {
2000         unsigned int size = 0;
2001         int i;
2002
2003         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2004                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2005
2006         return size;
2007 }
2008
2009 static void
2010 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2011                         const struct drm_framebuffer *fb,
2012                         unsigned int rotation)
2013 {
2014         view->type = I915_GGTT_VIEW_NORMAL;
2015         if (drm_rotation_90_or_270(rotation)) {
2016                 view->type = I915_GGTT_VIEW_ROTATED;
2017                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2018         }
2019 }
2020
2021 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2022 {
2023         if (IS_I830(dev_priv))
2024                 return 16 * 1024;
2025         else if (IS_I85X(dev_priv))
2026                 return 256;
2027         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2028                 return 32;
2029         else
2030                 return 4 * 1024;
2031 }
2032
2033 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2034 {
2035         if (INTEL_GEN(dev_priv) >= 9)
2036                 return 256 * 1024;
2037         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2038                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2039                 return 128 * 1024;
2040         else if (INTEL_GEN(dev_priv) >= 4)
2041                 return 4 * 1024;
2042         else
2043                 return 0;
2044 }
2045
2046 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2047                                          int color_plane)
2048 {
2049         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2050
2051         /* AUX_DIST needs only 4K alignment */
2052         if (color_plane == 1)
2053                 return 4096;
2054
2055         switch (fb->modifier) {
2056         case DRM_FORMAT_MOD_LINEAR:
2057                 return intel_linear_alignment(dev_priv);
2058         case I915_FORMAT_MOD_X_TILED:
2059                 if (INTEL_GEN(dev_priv) >= 9)
2060                         return 256 * 1024;
2061                 return 0;
2062         case I915_FORMAT_MOD_Y_TILED_CCS:
2063         case I915_FORMAT_MOD_Yf_TILED_CCS:
2064         case I915_FORMAT_MOD_Y_TILED:
2065         case I915_FORMAT_MOD_Yf_TILED:
2066                 return 1 * 1024 * 1024;
2067         default:
2068                 MISSING_CASE(fb->modifier);
2069                 return 0;
2070         }
2071 }
2072
2073 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2074 {
2075         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2076         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2077
2078         return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2079 }
2080
2081 struct i915_vma *
2082 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2083                            const struct i915_ggtt_view *view,
2084                            bool uses_fence,
2085                            unsigned long *out_flags)
2086 {
2087         struct drm_device *dev = fb->dev;
2088         struct drm_i915_private *dev_priv = to_i915(dev);
2089         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2090         struct i915_vma *vma;
2091         unsigned int pinctl;
2092         u32 alignment;
2093
2094         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2095
2096         alignment = intel_surf_alignment(fb, 0);
2097
2098         /* Note that the w/a also requires 64 PTE of padding following the
2099          * bo. We currently fill all unused PTE with the shadow page and so
2100          * we should always have valid PTE following the scanout preventing
2101          * the VT-d warning.
2102          */
2103         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2104                 alignment = 256 * 1024;
2105
2106         /*
2107          * Global gtt pte registers are special registers which actually forward
2108          * writes to a chunk of system memory. Which means that there is no risk
2109          * that the register values disappear as soon as we call
2110          * intel_runtime_pm_put(), so it is correct to wrap only the
2111          * pin/unpin/fence and not more.
2112          */
2113         intel_runtime_pm_get(dev_priv);
2114
2115         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2116
2117         pinctl = 0;
2118
2119         /* Valleyview is definitely limited to scanning out the first
2120          * 512MiB. Lets presume this behaviour was inherited from the
2121          * g4x display engine and that all earlier gen are similarly
2122          * limited. Testing suggests that it is a little more
2123          * complicated than this. For example, Cherryview appears quite
2124          * happy to scanout from anywhere within its global aperture.
2125          */
2126         if (HAS_GMCH_DISPLAY(dev_priv))
2127                 pinctl |= PIN_MAPPABLE;
2128
2129         vma = i915_gem_object_pin_to_display_plane(obj,
2130                                                    alignment, view, pinctl);
2131         if (IS_ERR(vma))
2132                 goto err;
2133
2134         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2135                 int ret;
2136
2137                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2138                  * fence, whereas 965+ only requires a fence if using
2139                  * framebuffer compression.  For simplicity, we always, when
2140                  * possible, install a fence as the cost is not that onerous.
2141                  *
2142                  * If we fail to fence the tiled scanout, then either the
2143                  * modeset will reject the change (which is highly unlikely as
2144                  * the affected systems, all but one, do not have unmappable
2145                  * space) or we will not be able to enable full powersaving
2146                  * techniques (also likely not to apply due to various limits
2147                  * FBC and the like impose on the size of the buffer, which
2148                  * presumably we violated anyway with this unmappable buffer).
2149                  * Anyway, it is presumably better to stumble onwards with
2150                  * something and try to run the system in a "less than optimal"
2151                  * mode that matches the user configuration.
2152                  */
2153                 ret = i915_vma_pin_fence(vma);
2154                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2155                         i915_gem_object_unpin_from_display_plane(vma);
2156                         vma = ERR_PTR(ret);
2157                         goto err;
2158                 }
2159
2160                 if (ret == 0 && vma->fence)
2161                         *out_flags |= PLANE_HAS_FENCE;
2162         }
2163
2164         i915_vma_get(vma);
2165 err:
2166         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2167
2168         intel_runtime_pm_put(dev_priv);
2169         return vma;
2170 }
2171
2172 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2173 {
2174         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2175
2176         if (flags & PLANE_HAS_FENCE)
2177                 i915_vma_unpin_fence(vma);
2178         i915_gem_object_unpin_from_display_plane(vma);
2179         i915_vma_put(vma);
2180 }
2181
2182 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2183                           unsigned int rotation)
2184 {
2185         if (drm_rotation_90_or_270(rotation))
2186                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2187         else
2188                 return fb->pitches[color_plane];
2189 }
2190
2191 /*
2192  * Convert the x/y offsets into a linear offset.
2193  * Only valid with 0/180 degree rotation, which is fine since linear
2194  * offset is only used with linear buffers on pre-hsw and tiled buffers
2195  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2196  */
2197 u32 intel_fb_xy_to_linear(int x, int y,
2198                           const struct intel_plane_state *state,
2199                           int color_plane)
2200 {
2201         const struct drm_framebuffer *fb = state->base.fb;
2202         unsigned int cpp = fb->format->cpp[color_plane];
2203         unsigned int pitch = state->color_plane[color_plane].stride;
2204
2205         return y * pitch + x * cpp;
2206 }
2207
2208 /*
2209  * Add the x/y offsets derived from fb->offsets[] to the user
2210  * specified plane src x/y offsets. The resulting x/y offsets
2211  * specify the start of scanout from the beginning of the gtt mapping.
2212  */
2213 void intel_add_fb_offsets(int *x, int *y,
2214                           const struct intel_plane_state *state,
2215                           int color_plane)
2216
2217 {
2218         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2219         unsigned int rotation = state->base.rotation;
2220
2221         if (drm_rotation_90_or_270(rotation)) {
2222                 *x += intel_fb->rotated[color_plane].x;
2223                 *y += intel_fb->rotated[color_plane].y;
2224         } else {
2225                 *x += intel_fb->normal[color_plane].x;
2226                 *y += intel_fb->normal[color_plane].y;
2227         }
2228 }
2229
2230 static u32 intel_adjust_tile_offset(int *x, int *y,
2231                                     unsigned int tile_width,
2232                                     unsigned int tile_height,
2233                                     unsigned int tile_size,
2234                                     unsigned int pitch_tiles,
2235                                     u32 old_offset,
2236                                     u32 new_offset)
2237 {
2238         unsigned int pitch_pixels = pitch_tiles * tile_width;
2239         unsigned int tiles;
2240
2241         WARN_ON(old_offset & (tile_size - 1));
2242         WARN_ON(new_offset & (tile_size - 1));
2243         WARN_ON(new_offset > old_offset);
2244
2245         tiles = (old_offset - new_offset) / tile_size;
2246
2247         *y += tiles / pitch_tiles * tile_height;
2248         *x += tiles % pitch_tiles * tile_width;
2249
2250         /* minimize x in case it got needlessly big */
2251         *y += *x / pitch_pixels * tile_height;
2252         *x %= pitch_pixels;
2253
2254         return new_offset;
2255 }
2256
2257 static u32 intel_adjust_aligned_offset(int *x, int *y,
2258                                        const struct drm_framebuffer *fb,
2259                                        int color_plane,
2260                                        unsigned int rotation,
2261                                        unsigned int pitch,
2262                                        u32 old_offset, u32 new_offset)
2263 {
2264         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2265         unsigned int cpp = fb->format->cpp[color_plane];
2266
2267         WARN_ON(new_offset > old_offset);
2268
2269         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2270                 unsigned int tile_size, tile_width, tile_height;
2271                 unsigned int pitch_tiles;
2272
2273                 tile_size = intel_tile_size(dev_priv);
2274                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2275
2276                 if (drm_rotation_90_or_270(rotation)) {
2277                         pitch_tiles = pitch / tile_height;
2278                         swap(tile_width, tile_height);
2279                 } else {
2280                         pitch_tiles = pitch / (tile_width * cpp);
2281                 }
2282
2283                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2284                                          tile_size, pitch_tiles,
2285                                          old_offset, new_offset);
2286         } else {
2287                 old_offset += *y * pitch + *x * cpp;
2288
2289                 *y = (old_offset - new_offset) / pitch;
2290                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2291         }
2292
2293         return new_offset;
2294 }
2295
2296 /*
2297  * Adjust the tile offset by moving the difference into
2298  * the x/y offsets.
2299  */
2300 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2301                                              const struct intel_plane_state *state,
2302                                              int color_plane,
2303                                              u32 old_offset, u32 new_offset)
2304 {
2305         return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2306                                            state->base.rotation,
2307                                            state->color_plane[color_plane].stride,
2308                                            old_offset, new_offset);
2309 }
2310
2311 /*
2312  * Computes the aligned offset to the base tile and adjusts
2313  * x, y. bytes per pixel is assumed to be a power-of-two.
2314  *
2315  * In the 90/270 rotated case, x and y are assumed
2316  * to be already rotated to match the rotated GTT view, and
2317  * pitch is the tile_height aligned framebuffer height.
2318  *
2319  * This function is used when computing the derived information
2320  * under intel_framebuffer, so using any of that information
2321  * here is not allowed. Anything under drm_framebuffer can be
2322  * used. This is why the user has to pass in the pitch since it
2323  * is specified in the rotated orientation.
2324  */
2325 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2326                                         int *x, int *y,
2327                                         const struct drm_framebuffer *fb,
2328                                         int color_plane,
2329                                         unsigned int pitch,
2330                                         unsigned int rotation,
2331                                         u32 alignment)
2332 {
2333         uint64_t fb_modifier = fb->modifier;
2334         unsigned int cpp = fb->format->cpp[color_plane];
2335         u32 offset, offset_aligned;
2336
2337         if (alignment)
2338                 alignment--;
2339
2340         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2341                 unsigned int tile_size, tile_width, tile_height;
2342                 unsigned int tile_rows, tiles, pitch_tiles;
2343
2344                 tile_size = intel_tile_size(dev_priv);
2345                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2346
2347                 if (drm_rotation_90_or_270(rotation)) {
2348                         pitch_tiles = pitch / tile_height;
2349                         swap(tile_width, tile_height);
2350                 } else {
2351                         pitch_tiles = pitch / (tile_width * cpp);
2352                 }
2353
2354                 tile_rows = *y / tile_height;
2355                 *y %= tile_height;
2356
2357                 tiles = *x / tile_width;
2358                 *x %= tile_width;
2359
2360                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2361                 offset_aligned = offset & ~alignment;
2362
2363                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2364                                          tile_size, pitch_tiles,
2365                                          offset, offset_aligned);
2366         } else {
2367                 offset = *y * pitch + *x * cpp;
2368                 offset_aligned = offset & ~alignment;
2369
2370                 *y = (offset & alignment) / pitch;
2371                 *x = ((offset & alignment) - *y * pitch) / cpp;
2372         }
2373
2374         return offset_aligned;
2375 }
2376
2377 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2378                                               const struct intel_plane_state *state,
2379                                               int color_plane)
2380 {
2381         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2382         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2383         const struct drm_framebuffer *fb = state->base.fb;
2384         unsigned int rotation = state->base.rotation;
2385         int pitch = state->color_plane[color_plane].stride;
2386         u32 alignment;
2387
2388         if (intel_plane->id == PLANE_CURSOR)
2389                 alignment = intel_cursor_alignment(dev_priv);
2390         else
2391                 alignment = intel_surf_alignment(fb, color_plane);
2392
2393         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2394                                             pitch, rotation, alignment);
2395 }
2396
2397 /* Convert the fb->offset[] into x/y offsets */
2398 static int intel_fb_offset_to_xy(int *x, int *y,
2399                                  const struct drm_framebuffer *fb,
2400                                  int color_plane)
2401 {
2402         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2403
2404         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2405             fb->offsets[color_plane] % intel_tile_size(dev_priv))
2406                 return -EINVAL;
2407
2408         *x = 0;
2409         *y = 0;
2410
2411         intel_adjust_aligned_offset(x, y,
2412                                     fb, color_plane, DRM_MODE_ROTATE_0,
2413                                     fb->pitches[color_plane],
2414                                     fb->offsets[color_plane], 0);
2415
2416         return 0;
2417 }
2418
2419 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2420 {
2421         switch (fb_modifier) {
2422         case I915_FORMAT_MOD_X_TILED:
2423                 return I915_TILING_X;
2424         case I915_FORMAT_MOD_Y_TILED:
2425         case I915_FORMAT_MOD_Y_TILED_CCS:
2426                 return I915_TILING_Y;
2427         default:
2428                 return I915_TILING_NONE;
2429         }
2430 }
2431
2432 /*
2433  * From the Sky Lake PRM:
2434  * "The Color Control Surface (CCS) contains the compression status of
2435  *  the cache-line pairs. The compression state of the cache-line pair
2436  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2437  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2438  *  cache-line-pairs. CCS is always Y tiled."
2439  *
2440  * Since cache line pairs refers to horizontally adjacent cache lines,
2441  * each cache line in the CCS corresponds to an area of 32x16 cache
2442  * lines on the main surface. Since each pixel is 4 bytes, this gives
2443  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2444  * main surface.
2445  */
2446 static const struct drm_format_info ccs_formats[] = {
2447         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2448         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2449         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2450         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2451 };
2452
2453 static const struct drm_format_info *
2454 lookup_format_info(const struct drm_format_info formats[],
2455                    int num_formats, u32 format)
2456 {
2457         int i;
2458
2459         for (i = 0; i < num_formats; i++) {
2460                 if (formats[i].format == format)
2461                         return &formats[i];
2462         }
2463
2464         return NULL;
2465 }
2466
2467 static const struct drm_format_info *
2468 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2469 {
2470         switch (cmd->modifier[0]) {
2471         case I915_FORMAT_MOD_Y_TILED_CCS:
2472         case I915_FORMAT_MOD_Yf_TILED_CCS:
2473                 return lookup_format_info(ccs_formats,
2474                                           ARRAY_SIZE(ccs_formats),
2475                                           cmd->pixel_format);
2476         default:
2477                 return NULL;
2478         }
2479 }
2480
2481 bool is_ccs_modifier(u64 modifier)
2482 {
2483         return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2484                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2485 }
2486
2487 static int
2488 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2489                    struct drm_framebuffer *fb)
2490 {
2491         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2492         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2493         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2494         u32 gtt_offset_rotated = 0;
2495         unsigned int max_size = 0;
2496         int i, num_planes = fb->format->num_planes;
2497         unsigned int tile_size = intel_tile_size(dev_priv);
2498
2499         for (i = 0; i < num_planes; i++) {
2500                 unsigned int width, height;
2501                 unsigned int cpp, size;
2502                 u32 offset;
2503                 int x, y;
2504                 int ret;
2505
2506                 cpp = fb->format->cpp[i];
2507                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2508                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2509
2510                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2511                 if (ret) {
2512                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2513                                       i, fb->offsets[i]);
2514                         return ret;
2515                 }
2516
2517                 if (is_ccs_modifier(fb->modifier) && i == 1) {
2518                         int hsub = fb->format->hsub;
2519                         int vsub = fb->format->vsub;
2520                         int tile_width, tile_height;
2521                         int main_x, main_y;
2522                         int ccs_x, ccs_y;
2523
2524                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2525                         tile_width *= hsub;
2526                         tile_height *= vsub;
2527
2528                         ccs_x = (x * hsub) % tile_width;
2529                         ccs_y = (y * vsub) % tile_height;
2530                         main_x = intel_fb->normal[0].x % tile_width;
2531                         main_y = intel_fb->normal[0].y % tile_height;
2532
2533                         /*
2534                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2535                          * x/y offsets must match between CCS and the main surface.
2536                          */
2537                         if (main_x != ccs_x || main_y != ccs_y) {
2538                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2539                                               main_x, main_y,
2540                                               ccs_x, ccs_y,
2541                                               intel_fb->normal[0].x,
2542                                               intel_fb->normal[0].y,
2543                                               x, y);
2544                                 return -EINVAL;
2545                         }
2546                 }
2547
2548                 /*
2549                  * The fence (if used) is aligned to the start of the object
2550                  * so having the framebuffer wrap around across the edge of the
2551                  * fenced region doesn't really work. We have no API to configure
2552                  * the fence start offset within the object (nor could we probably
2553                  * on gen2/3). So it's just easier if we just require that the
2554                  * fb layout agrees with the fence layout. We already check that the
2555                  * fb stride matches the fence stride elsewhere.
2556                  */
2557                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2558                     (x + width) * cpp > fb->pitches[i]) {
2559                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2560                                       i, fb->offsets[i]);
2561                         return -EINVAL;
2562                 }
2563
2564                 /*
2565                  * First pixel of the framebuffer from
2566                  * the start of the normal gtt mapping.
2567                  */
2568                 intel_fb->normal[i].x = x;
2569                 intel_fb->normal[i].y = y;
2570
2571                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2572                                                       fb->pitches[i],
2573                                                       DRM_MODE_ROTATE_0,
2574                                                       tile_size);
2575                 offset /= tile_size;
2576
2577                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2578                         unsigned int tile_width, tile_height;
2579                         unsigned int pitch_tiles;
2580                         struct drm_rect r;
2581
2582                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2583
2584                         rot_info->plane[i].offset = offset;
2585                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2586                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2587                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2588
2589                         intel_fb->rotated[i].pitch =
2590                                 rot_info->plane[i].height * tile_height;
2591
2592                         /* how many tiles does this plane need */
2593                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2594                         /*
2595                          * If the plane isn't horizontally tile aligned,
2596                          * we need one more tile.
2597                          */
2598                         if (x != 0)
2599                                 size++;
2600
2601                         /* rotate the x/y offsets to match the GTT view */
2602                         r.x1 = x;
2603                         r.y1 = y;
2604                         r.x2 = x + width;
2605                         r.y2 = y + height;
2606                         drm_rect_rotate(&r,
2607                                         rot_info->plane[i].width * tile_width,
2608                                         rot_info->plane[i].height * tile_height,
2609                                         DRM_MODE_ROTATE_270);
2610                         x = r.x1;
2611                         y = r.y1;
2612
2613                         /* rotate the tile dimensions to match the GTT view */
2614                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2615                         swap(tile_width, tile_height);
2616
2617                         /*
2618                          * We only keep the x/y offsets, so push all of the
2619                          * gtt offset into the x/y offsets.
2620                          */
2621                         intel_adjust_tile_offset(&x, &y,
2622                                                  tile_width, tile_height,
2623                                                  tile_size, pitch_tiles,
2624                                                  gtt_offset_rotated * tile_size, 0);
2625
2626                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2627
2628                         /*
2629                          * First pixel of the framebuffer from
2630                          * the start of the rotated gtt mapping.
2631                          */
2632                         intel_fb->rotated[i].x = x;
2633                         intel_fb->rotated[i].y = y;
2634                 } else {
2635                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2636                                             x * cpp, tile_size);
2637                 }
2638
2639                 /* how many tiles in total needed in the bo */
2640                 max_size = max(max_size, offset + size);
2641         }
2642
2643         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2644                 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2645                               mul_u32_u32(max_size, tile_size), obj->base.size);
2646                 return -EINVAL;
2647         }
2648
2649         return 0;
2650 }
2651
2652 static int i9xx_format_to_fourcc(int format)
2653 {
2654         switch (format) {
2655         case DISPPLANE_8BPP:
2656                 return DRM_FORMAT_C8;
2657         case DISPPLANE_BGRX555:
2658                 return DRM_FORMAT_XRGB1555;
2659         case DISPPLANE_BGRX565:
2660                 return DRM_FORMAT_RGB565;
2661         default:
2662         case DISPPLANE_BGRX888:
2663                 return DRM_FORMAT_XRGB8888;
2664         case DISPPLANE_RGBX888:
2665                 return DRM_FORMAT_XBGR8888;
2666         case DISPPLANE_BGRX101010:
2667                 return DRM_FORMAT_XRGB2101010;
2668         case DISPPLANE_RGBX101010:
2669                 return DRM_FORMAT_XBGR2101010;
2670         }
2671 }
2672
2673 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2674 {
2675         switch (format) {
2676         case PLANE_CTL_FORMAT_RGB_565:
2677                 return DRM_FORMAT_RGB565;
2678         case PLANE_CTL_FORMAT_NV12:
2679                 return DRM_FORMAT_NV12;
2680         default:
2681         case PLANE_CTL_FORMAT_XRGB_8888:
2682                 if (rgb_order) {
2683                         if (alpha)
2684                                 return DRM_FORMAT_ABGR8888;
2685                         else
2686                                 return DRM_FORMAT_XBGR8888;
2687                 } else {
2688                         if (alpha)
2689                                 return DRM_FORMAT_ARGB8888;
2690                         else
2691                                 return DRM_FORMAT_XRGB8888;
2692                 }
2693         case PLANE_CTL_FORMAT_XRGB_2101010:
2694                 if (rgb_order)
2695                         return DRM_FORMAT_XBGR2101010;
2696                 else
2697                         return DRM_FORMAT_XRGB2101010;
2698         }
2699 }
2700
2701 static bool
2702 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2703                               struct intel_initial_plane_config *plane_config)
2704 {
2705         struct drm_device *dev = crtc->base.dev;
2706         struct drm_i915_private *dev_priv = to_i915(dev);
2707         struct drm_i915_gem_object *obj = NULL;
2708         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2709         struct drm_framebuffer *fb = &plane_config->fb->base;
2710         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2711         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2712                                     PAGE_SIZE);
2713
2714         size_aligned -= base_aligned;
2715
2716         if (plane_config->size == 0)
2717                 return false;
2718
2719         /* If the FB is too big, just don't use it since fbdev is not very
2720          * important and we should probably use that space with FBC or other
2721          * features. */
2722         if (size_aligned * 2 > dev_priv->stolen_usable_size)
2723                 return false;
2724
2725         switch (fb->modifier) {
2726         case DRM_FORMAT_MOD_LINEAR:
2727         case I915_FORMAT_MOD_X_TILED:
2728         case I915_FORMAT_MOD_Y_TILED:
2729                 break;
2730         default:
2731                 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
2732                                  fb->modifier);
2733                 return false;
2734         }
2735
2736         mutex_lock(&dev->struct_mutex);
2737         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2738                                                              base_aligned,
2739                                                              base_aligned,
2740                                                              size_aligned);
2741         mutex_unlock(&dev->struct_mutex);
2742         if (!obj)
2743                 return false;
2744
2745         switch (plane_config->tiling) {
2746         case I915_TILING_NONE:
2747                 break;
2748         case I915_TILING_X:
2749         case I915_TILING_Y:
2750                 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
2751                 break;
2752         default:
2753                 MISSING_CASE(plane_config->tiling);
2754                 return false;
2755         }
2756
2757         mode_cmd.pixel_format = fb->format->format;
2758         mode_cmd.width = fb->width;
2759         mode_cmd.height = fb->height;
2760         mode_cmd.pitches[0] = fb->pitches[0];
2761         mode_cmd.modifier[0] = fb->modifier;
2762         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2763
2764         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2765                 DRM_DEBUG_KMS("intel fb init failed\n");
2766                 goto out_unref_obj;
2767         }
2768
2769
2770         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2771         return true;
2772
2773 out_unref_obj:
2774         i915_gem_object_put(obj);
2775         return false;
2776 }
2777
2778 static void
2779 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2780                         struct intel_plane_state *plane_state,
2781                         bool visible)
2782 {
2783         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2784
2785         plane_state->base.visible = visible;
2786
2787         if (visible)
2788                 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2789         else
2790                 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2791
2792         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2793                       crtc_state->base.crtc->name,
2794                       crtc_state->active_planes);
2795 }
2796
2797 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
2798 {
2799         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2800         struct drm_plane *plane;
2801
2802         /*
2803          * Active_planes aliases if multiple "primary" or cursor planes
2804          * have been used on the same (or wrong) pipe. plane_mask uses
2805          * unique ids, hence we can use that to reconstruct active_planes.
2806          */
2807         crtc_state->active_planes = 0;
2808
2809         drm_for_each_plane_mask(plane, &dev_priv->drm,
2810                                 crtc_state->base.plane_mask)
2811                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
2812 }
2813
2814 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2815                                          struct intel_plane *plane)
2816 {
2817         struct intel_crtc_state *crtc_state =
2818                 to_intel_crtc_state(crtc->base.state);
2819         struct intel_plane_state *plane_state =
2820                 to_intel_plane_state(plane->base.state);
2821
2822         intel_set_plane_visible(crtc_state, plane_state, false);
2823         fixup_active_planes(crtc_state);
2824
2825         if (plane->id == PLANE_PRIMARY)
2826                 intel_pre_disable_primary_noatomic(&crtc->base);
2827
2828         trace_intel_disable_plane(&plane->base, crtc);
2829         plane->disable_plane(plane, crtc);
2830 }
2831
2832 static void
2833 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2834                              struct intel_initial_plane_config *plane_config)
2835 {
2836         struct drm_device *dev = intel_crtc->base.dev;
2837         struct drm_i915_private *dev_priv = to_i915(dev);
2838         struct drm_crtc *c;
2839         struct drm_i915_gem_object *obj;
2840         struct drm_plane *primary = intel_crtc->base.primary;
2841         struct drm_plane_state *plane_state = primary->state;
2842         struct intel_plane *intel_plane = to_intel_plane(primary);
2843         struct intel_plane_state *intel_state =
2844                 to_intel_plane_state(plane_state);
2845         struct drm_framebuffer *fb;
2846
2847         if (!plane_config->fb)
2848                 return;
2849
2850         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2851                 fb = &plane_config->fb->base;
2852                 goto valid_fb;
2853         }
2854
2855         kfree(plane_config->fb);
2856
2857         /*
2858          * Failed to alloc the obj, check to see if we should share
2859          * an fb with another CRTC instead
2860          */
2861         for_each_crtc(dev, c) {
2862                 struct intel_plane_state *state;
2863
2864                 if (c == &intel_crtc->base)
2865                         continue;
2866
2867                 if (!to_intel_crtc(c)->active)
2868                         continue;
2869
2870                 state = to_intel_plane_state(c->primary->state);
2871                 if (!state->vma)
2872                         continue;
2873
2874                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2875                         fb = state->base.fb;
2876                         drm_framebuffer_get(fb);
2877                         goto valid_fb;
2878                 }
2879         }
2880
2881         /*
2882          * We've failed to reconstruct the BIOS FB.  Current display state
2883          * indicates that the primary plane is visible, but has a NULL FB,
2884          * which will lead to problems later if we don't fix it up.  The
2885          * simplest solution is to just disable the primary plane now and
2886          * pretend the BIOS never had it enabled.
2887          */
2888         intel_plane_disable_noatomic(intel_crtc, intel_plane);
2889
2890         return;
2891
2892 valid_fb:
2893         intel_state->base.rotation = plane_config->rotation;
2894         intel_fill_fb_ggtt_view(&intel_state->view, fb,
2895                                 intel_state->base.rotation);
2896         intel_state->color_plane[0].stride =
2897                 intel_fb_pitch(fb, 0, intel_state->base.rotation);
2898
2899         mutex_lock(&dev->struct_mutex);
2900         intel_state->vma =
2901                 intel_pin_and_fence_fb_obj(fb,
2902                                            &intel_state->view,
2903                                            intel_plane_uses_fence(intel_state),
2904                                            &intel_state->flags);
2905         mutex_unlock(&dev->struct_mutex);
2906         if (IS_ERR(intel_state->vma)) {
2907                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2908                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2909
2910                 intel_state->vma = NULL;
2911                 drm_framebuffer_put(fb);
2912                 return;
2913         }
2914
2915         obj = intel_fb_obj(fb);
2916         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2917
2918         plane_state->src_x = 0;
2919         plane_state->src_y = 0;
2920         plane_state->src_w = fb->width << 16;
2921         plane_state->src_h = fb->height << 16;
2922
2923         plane_state->crtc_x = 0;
2924         plane_state->crtc_y = 0;
2925         plane_state->crtc_w = fb->width;
2926         plane_state->crtc_h = fb->height;
2927
2928         intel_state->base.src = drm_plane_state_src(plane_state);
2929         intel_state->base.dst = drm_plane_state_dest(plane_state);
2930
2931         if (i915_gem_object_is_tiled(obj))
2932                 dev_priv->preserve_bios_swizzle = true;
2933
2934         plane_state->fb = fb;
2935         plane_state->crtc = &intel_crtc->base;
2936
2937         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2938                   &obj->frontbuffer_bits);
2939 }
2940
2941 static int skl_max_plane_width(const struct drm_framebuffer *fb,
2942                                int color_plane,
2943                                unsigned int rotation)
2944 {
2945         int cpp = fb->format->cpp[color_plane];
2946
2947         switch (fb->modifier) {
2948         case DRM_FORMAT_MOD_LINEAR:
2949         case I915_FORMAT_MOD_X_TILED:
2950                 switch (cpp) {
2951                 case 8:
2952                         return 4096;
2953                 case 4:
2954                 case 2:
2955                 case 1:
2956                         return 8192;
2957                 default:
2958                         MISSING_CASE(cpp);
2959                         break;
2960                 }
2961                 break;
2962         case I915_FORMAT_MOD_Y_TILED_CCS:
2963         case I915_FORMAT_MOD_Yf_TILED_CCS:
2964                 /* FIXME AUX plane? */
2965         case I915_FORMAT_MOD_Y_TILED:
2966         case I915_FORMAT_MOD_Yf_TILED:
2967                 switch (cpp) {
2968                 case 8:
2969                         return 2048;
2970                 case 4:
2971                         return 4096;
2972                 case 2:
2973                 case 1:
2974                         return 8192;
2975                 default:
2976                         MISSING_CASE(cpp);
2977                         break;
2978                 }
2979                 break;
2980         default:
2981                 MISSING_CASE(fb->modifier);
2982         }
2983
2984         return 2048;
2985 }
2986
2987 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2988                                            int main_x, int main_y, u32 main_offset)
2989 {
2990         const struct drm_framebuffer *fb = plane_state->base.fb;
2991         int hsub = fb->format->hsub;
2992         int vsub = fb->format->vsub;
2993         int aux_x = plane_state->color_plane[1].x;
2994         int aux_y = plane_state->color_plane[1].y;
2995         u32 aux_offset = plane_state->color_plane[1].offset;
2996         u32 alignment = intel_surf_alignment(fb, 1);
2997
2998         while (aux_offset >= main_offset && aux_y <= main_y) {
2999                 int x, y;
3000
3001                 if (aux_x == main_x && aux_y == main_y)
3002                         break;
3003
3004                 if (aux_offset == 0)
3005                         break;
3006
3007                 x = aux_x / hsub;
3008                 y = aux_y / vsub;
3009                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3010                                                                aux_offset, aux_offset - alignment);
3011                 aux_x = x * hsub + aux_x % hsub;
3012                 aux_y = y * vsub + aux_y % vsub;
3013         }
3014
3015         if (aux_x != main_x || aux_y != main_y)
3016                 return false;
3017
3018         plane_state->color_plane[1].offset = aux_offset;
3019         plane_state->color_plane[1].x = aux_x;
3020         plane_state->color_plane[1].y = aux_y;
3021
3022         return true;
3023 }
3024
3025 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3026 {
3027         const struct drm_framebuffer *fb = plane_state->base.fb;
3028         unsigned int rotation = plane_state->base.rotation;
3029         int x = plane_state->base.src.x1 >> 16;
3030         int y = plane_state->base.src.y1 >> 16;
3031         int w = drm_rect_width(&plane_state->base.src) >> 16;
3032         int h = drm_rect_height(&plane_state->base.src) >> 16;
3033         int max_width = skl_max_plane_width(fb, 0, rotation);
3034         int max_height = 4096;
3035         u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3036
3037         if (w > max_width || h > max_height) {
3038                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3039                               w, h, max_width, max_height);
3040                 return -EINVAL;
3041         }
3042
3043         intel_add_fb_offsets(&x, &y, plane_state, 0);
3044         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3045         alignment = intel_surf_alignment(fb, 0);
3046
3047         /*
3048          * AUX surface offset is specified as the distance from the
3049          * main surface offset, and it must be non-negative. Make
3050          * sure that is what we will get.
3051          */
3052         if (offset > aux_offset)
3053                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3054                                                            offset, aux_offset & ~(alignment - 1));
3055
3056         /*
3057          * When using an X-tiled surface, the plane blows up
3058          * if the x offset + width exceed the stride.
3059          *
3060          * TODO: linear and Y-tiled seem fine, Yf untested,
3061          */
3062         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3063                 int cpp = fb->format->cpp[0];
3064
3065                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3066                         if (offset == 0) {
3067                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3068                                 return -EINVAL;
3069                         }
3070
3071                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3072                                                                    offset, offset - alignment);
3073                 }
3074         }
3075
3076         /*
3077          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3078          * they match with the main surface x/y offsets.
3079          */
3080         if (is_ccs_modifier(fb->modifier)) {
3081                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3082                         if (offset == 0)
3083                                 break;
3084
3085                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3086                                                                    offset, offset - alignment);
3087                 }
3088
3089                 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3090                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3091                         return -EINVAL;
3092                 }
3093         }
3094
3095         plane_state->color_plane[0].offset = offset;
3096         plane_state->color_plane[0].x = x;
3097         plane_state->color_plane[0].y = y;
3098
3099         return 0;
3100 }
3101
3102 static int
3103 skl_check_nv12_surface(struct intel_plane_state *plane_state)
3104 {
3105         /* Display WA #1106 */
3106         if (plane_state->base.rotation !=
3107             (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3108             plane_state->base.rotation != DRM_MODE_ROTATE_270)
3109                 return 0;
3110
3111         /*
3112          * src coordinates are rotated here.
3113          * We check height but report it as width
3114          */
3115         if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3116                 DRM_DEBUG_KMS("src width must be multiple "
3117                               "of 4 for rotated NV12\n");
3118                 return -EINVAL;
3119         }
3120
3121         return 0;
3122 }
3123
3124 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3125 {
3126         const struct drm_framebuffer *fb = plane_state->base.fb;
3127         unsigned int rotation = plane_state->base.rotation;
3128         int max_width = skl_max_plane_width(fb, 1, rotation);
3129         int max_height = 4096;
3130         int x = plane_state->base.src.x1 >> 17;
3131         int y = plane_state->base.src.y1 >> 17;
3132         int w = drm_rect_width(&plane_state->base.src) >> 17;
3133         int h = drm_rect_height(&plane_state->base.src) >> 17;
3134         u32 offset;
3135
3136         intel_add_fb_offsets(&x, &y, plane_state, 1);
3137         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3138
3139         /* FIXME not quite sure how/if these apply to the chroma plane */
3140         if (w > max_width || h > max_height) {
3141                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3142                               w, h, max_width, max_height);
3143                 return -EINVAL;
3144         }
3145
3146         plane_state->color_plane[1].offset = offset;
3147         plane_state->color_plane[1].x = x;
3148         plane_state->color_plane[1].y = y;
3149
3150         return 0;
3151 }
3152
3153 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3154 {
3155         const struct drm_framebuffer *fb = plane_state->base.fb;
3156         int src_x = plane_state->base.src.x1 >> 16;
3157         int src_y = plane_state->base.src.y1 >> 16;
3158         int hsub = fb->format->hsub;
3159         int vsub = fb->format->vsub;
3160         int x = src_x / hsub;
3161         int y = src_y / vsub;
3162         u32 offset;
3163
3164         intel_add_fb_offsets(&x, &y, plane_state, 1);
3165         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3166
3167         plane_state->color_plane[1].offset = offset;
3168         plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3169         plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3170
3171         return 0;
3172 }
3173
3174 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3175 {
3176         const struct drm_framebuffer *fb = plane_state->base.fb;
3177         unsigned int rotation = plane_state->base.rotation;
3178         int ret;
3179
3180         intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3181         plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3182         plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
3183
3184         ret = intel_plane_check_stride(plane_state);
3185         if (ret)
3186                 return ret;
3187
3188         if (!plane_state->base.visible)
3189                 return 0;
3190
3191         /* Rotate src coordinates to match rotated GTT view */
3192         if (drm_rotation_90_or_270(rotation))
3193                 drm_rect_rotate(&plane_state->base.src,
3194                                 fb->width << 16, fb->height << 16,
3195                                 DRM_MODE_ROTATE_270);
3196
3197         /*
3198          * Handle the AUX surface first since
3199          * the main surface setup depends on it.
3200          */
3201         if (fb->format->format == DRM_FORMAT_NV12) {
3202                 ret = skl_check_nv12_surface(plane_state);
3203                 if (ret)
3204                         return ret;
3205                 ret = skl_check_nv12_aux_surface(plane_state);
3206                 if (ret)
3207                         return ret;
3208         } else if (is_ccs_modifier(fb->modifier)) {
3209                 ret = skl_check_ccs_aux_surface(plane_state);
3210                 if (ret)
3211                         return ret;
3212         } else {
3213                 plane_state->color_plane[1].offset = ~0xfff;
3214                 plane_state->color_plane[1].x = 0;
3215                 plane_state->color_plane[1].y = 0;
3216         }
3217
3218         ret = skl_check_main_surface(plane_state);
3219         if (ret)
3220                 return ret;
3221
3222         return 0;
3223 }
3224
3225 unsigned int
3226 i9xx_plane_max_stride(struct intel_plane *plane,
3227                       u32 pixel_format, u64 modifier,
3228                       unsigned int rotation)
3229 {
3230         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3231
3232         if (!HAS_GMCH_DISPLAY(dev_priv)) {
3233                 return 32*1024;
3234         } else if (INTEL_GEN(dev_priv) >= 4) {
3235                 if (modifier == I915_FORMAT_MOD_X_TILED)
3236                         return 16*1024;
3237                 else
3238                         return 32*1024;
3239         } else if (INTEL_GEN(dev_priv) >= 3) {
3240                 if (modifier == I915_FORMAT_MOD_X_TILED)
3241                         return 8*1024;
3242                 else
3243                         return 16*1024;
3244         } else {
3245                 if (plane->i9xx_plane == PLANE_C)
3246                         return 4*1024;
3247                 else
3248                         return 8*1024;
3249         }
3250 }
3251
3252 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3253                           const struct intel_plane_state *plane_state)
3254 {
3255         struct drm_i915_private *dev_priv =
3256                 to_i915(plane_state->base.plane->dev);
3257         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3258         const struct drm_framebuffer *fb = plane_state->base.fb;
3259         unsigned int rotation = plane_state->base.rotation;
3260         u32 dspcntr;
3261
3262         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3263
3264         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3265             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3266                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3267
3268         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3269                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3270
3271         if (INTEL_GEN(dev_priv) < 5)
3272                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3273
3274         switch (fb->format->format) {
3275         case DRM_FORMAT_C8:
3276                 dspcntr |= DISPPLANE_8BPP;
3277                 break;
3278         case DRM_FORMAT_XRGB1555:
3279                 dspcntr |= DISPPLANE_BGRX555;
3280                 break;
3281         case DRM_FORMAT_RGB565:
3282                 dspcntr |= DISPPLANE_BGRX565;
3283                 break;
3284         case DRM_FORMAT_XRGB8888:
3285                 dspcntr |= DISPPLANE_BGRX888;
3286                 break;
3287         case DRM_FORMAT_XBGR8888:
3288                 dspcntr |= DISPPLANE_RGBX888;
3289                 break;
3290         case DRM_FORMAT_XRGB2101010:
3291                 dspcntr |= DISPPLANE_BGRX101010;
3292                 break;
3293         case DRM_FORMAT_XBGR2101010:
3294                 dspcntr |= DISPPLANE_RGBX101010;
3295                 break;
3296         default:
3297                 MISSING_CASE(fb->format->format);
3298                 return 0;
3299         }
3300
3301         if (INTEL_GEN(dev_priv) >= 4 &&
3302             fb->modifier == I915_FORMAT_MOD_X_TILED)
3303                 dspcntr |= DISPPLANE_TILED;
3304
3305         if (rotation & DRM_MODE_ROTATE_180)
3306                 dspcntr |= DISPPLANE_ROTATE_180;
3307
3308         if (rotation & DRM_MODE_REFLECT_X)
3309                 dspcntr |= DISPPLANE_MIRROR;
3310
3311         return dspcntr;
3312 }
3313
3314 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3315 {
3316         struct drm_i915_private *dev_priv =
3317                 to_i915(plane_state->base.plane->dev);
3318         const struct drm_framebuffer *fb = plane_state->base.fb;
3319         unsigned int rotation = plane_state->base.rotation;
3320         int src_x = plane_state->base.src.x1 >> 16;
3321         int src_y = plane_state->base.src.y1 >> 16;
3322         u32 offset;
3323         int ret;
3324
3325         intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
3326         plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
3327
3328         ret = intel_plane_check_stride(plane_state);
3329         if (ret)
3330                 return ret;
3331
3332         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3333
3334         if (INTEL_GEN(dev_priv) >= 4)
3335                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3336                                                             plane_state, 0);
3337         else
3338                 offset = 0;
3339
3340         /* HSW/BDW do this automagically in hardware */
3341         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3342                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3343                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3344
3345                 if (rotation & DRM_MODE_ROTATE_180) {
3346                         src_x += src_w - 1;
3347                         src_y += src_h - 1;
3348                 } else if (rotation & DRM_MODE_REFLECT_X) {
3349                         src_x += src_w - 1;
3350                 }
3351         }
3352
3353         plane_state->color_plane[0].offset = offset;
3354         plane_state->color_plane[0].x = src_x;
3355         plane_state->color_plane[0].y = src_y;
3356
3357         return 0;
3358 }
3359
3360 static int
3361 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3362                  struct intel_plane_state *plane_state)
3363 {
3364         int ret;
3365
3366         ret = chv_plane_check_rotation(plane_state);
3367         if (ret)
3368                 return ret;
3369
3370         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3371                                                   &crtc_state->base,
3372                                                   DRM_PLANE_HELPER_NO_SCALING,
3373                                                   DRM_PLANE_HELPER_NO_SCALING,
3374                                                   false, true);
3375         if (ret)
3376                 return ret;
3377
3378         if (!plane_state->base.visible)
3379                 return 0;
3380
3381         ret = intel_plane_check_src_coordinates(plane_state);
3382         if (ret)
3383                 return ret;
3384
3385         ret = i9xx_check_plane_surface(plane_state);
3386         if (ret)
3387                 return ret;
3388
3389         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3390
3391         return 0;
3392 }
3393
3394 static void i9xx_update_plane(struct intel_plane *plane,
3395                               const struct intel_crtc_state *crtc_state,
3396                               const struct intel_plane_state *plane_state)
3397 {
3398         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3399         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3400         u32 linear_offset;
3401         u32 dspcntr = plane_state->ctl;
3402         i915_reg_t reg = DSPCNTR(i9xx_plane);
3403         int x = plane_state->color_plane[0].x;
3404         int y = plane_state->color_plane[0].y;
3405         unsigned long irqflags;
3406         u32 dspaddr_offset;
3407
3408         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3409
3410         if (INTEL_GEN(dev_priv) >= 4)
3411                 dspaddr_offset = plane_state->color_plane[0].offset;
3412         else
3413                 dspaddr_offset = linear_offset;
3414
3415         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3416
3417         if (INTEL_GEN(dev_priv) < 4) {
3418                 /* pipesrc and dspsize control the size that is scaled from,
3419                  * which should always be the user's requested size.
3420                  */
3421                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3422                               ((crtc_state->pipe_src_h - 1) << 16) |
3423                               (crtc_state->pipe_src_w - 1));
3424                 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3425         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3426                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3427                               ((crtc_state->pipe_src_h - 1) << 16) |
3428                               (crtc_state->pipe_src_w - 1));
3429                 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3430                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3431         }
3432
3433         I915_WRITE_FW(reg, dspcntr);
3434
3435         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3436         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3437                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3438                               intel_plane_ggtt_offset(plane_state) +
3439                               dspaddr_offset);
3440                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3441         } else if (INTEL_GEN(dev_priv) >= 4) {
3442                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3443                               intel_plane_ggtt_offset(plane_state) +
3444                               dspaddr_offset);
3445                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3446                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3447         } else {
3448                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3449                               intel_plane_ggtt_offset(plane_state) +
3450                               dspaddr_offset);
3451         }
3452         POSTING_READ_FW(reg);
3453
3454         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3455 }
3456
3457 static void i9xx_disable_plane(struct intel_plane *plane,
3458                                struct intel_crtc *crtc)
3459 {
3460         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3461         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3462         unsigned long irqflags;
3463
3464         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3465
3466         I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3467         if (INTEL_GEN(dev_priv) >= 4)
3468                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3469         else
3470                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3471         POSTING_READ_FW(DSPCNTR(i9xx_plane));
3472
3473         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3474 }
3475
3476 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3477                                     enum pipe *pipe)
3478 {
3479         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3480         enum intel_display_power_domain power_domain;
3481         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3482         bool ret;
3483         u32 val;
3484
3485         /*
3486          * Not 100% correct for planes that can move between pipes,
3487          * but that's only the case for gen2-4 which don't have any
3488          * display power wells.
3489          */
3490         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3491         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3492                 return false;
3493
3494         val = I915_READ(DSPCNTR(i9xx_plane));
3495
3496         ret = val & DISPLAY_PLANE_ENABLE;
3497
3498         if (INTEL_GEN(dev_priv) >= 5)
3499                 *pipe = plane->pipe;
3500         else
3501                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3502                         DISPPLANE_SEL_PIPE_SHIFT;
3503
3504         intel_display_power_put(dev_priv, power_domain);
3505
3506         return ret;
3507 }
3508
3509 static u32
3510 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
3511 {
3512         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3513                 return 64;
3514         else
3515                 return intel_tile_width_bytes(fb, color_plane);
3516 }
3517
3518 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3519 {
3520         struct drm_device *dev = intel_crtc->base.dev;
3521         struct drm_i915_private *dev_priv = to_i915(dev);
3522
3523         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3524         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3525         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3526 }
3527
3528 /*
3529  * This function detaches (aka. unbinds) unused scalers in hardware
3530  */
3531 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3532 {
3533         struct intel_crtc_scaler_state *scaler_state;
3534         int i;
3535
3536         scaler_state = &intel_crtc->config->scaler_state;
3537
3538         /* loop through and disable scalers that aren't in use */
3539         for (i = 0; i < intel_crtc->num_scalers; i++) {
3540                 if (!scaler_state->scalers[i].in_use)
3541                         skl_detach_scaler(intel_crtc, i);
3542         }
3543 }
3544
3545 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3546                      int color_plane)
3547 {
3548         const struct drm_framebuffer *fb = plane_state->base.fb;
3549         unsigned int rotation = plane_state->base.rotation;
3550         u32 stride = plane_state->color_plane[color_plane].stride;
3551
3552         if (color_plane >= fb->format->num_planes)
3553                 return 0;
3554
3555         /*
3556          * The stride is either expressed as a multiple of 64 bytes chunks for
3557          * linear buffers or in number of tiles for tiled buffers.
3558          */
3559         if (drm_rotation_90_or_270(rotation))
3560                 stride /= intel_tile_height(fb, color_plane);
3561         else
3562                 stride /= intel_fb_stride_alignment(fb, color_plane);
3563
3564         return stride;
3565 }
3566
3567 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3568 {
3569         switch (pixel_format) {
3570         case DRM_FORMAT_C8:
3571                 return PLANE_CTL_FORMAT_INDEXED;
3572         case DRM_FORMAT_RGB565:
3573                 return PLANE_CTL_FORMAT_RGB_565;
3574         case DRM_FORMAT_XBGR8888:
3575         case DRM_FORMAT_ABGR8888:
3576                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3577         case DRM_FORMAT_XRGB8888:
3578         case DRM_FORMAT_ARGB8888:
3579                 return PLANE_CTL_FORMAT_XRGB_8888;
3580         case DRM_FORMAT_XRGB2101010:
3581                 return PLANE_CTL_FORMAT_XRGB_2101010;
3582         case DRM_FORMAT_XBGR2101010:
3583                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3584         case DRM_FORMAT_YUYV:
3585                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3586         case DRM_FORMAT_YVYU:
3587                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3588         case DRM_FORMAT_UYVY:
3589                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3590         case DRM_FORMAT_VYUY:
3591                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3592         case DRM_FORMAT_NV12:
3593                 return PLANE_CTL_FORMAT_NV12;
3594         default:
3595                 MISSING_CASE(pixel_format);
3596         }
3597
3598         return 0;
3599 }
3600
3601 /*
3602  * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3603  * to be already pre-multiplied. We need to add a knob (or a different
3604  * DRM_FORMAT) for user-space to configure that.
3605  */
3606 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3607 {
3608         switch (pixel_format) {
3609         case DRM_FORMAT_ABGR8888:
3610         case DRM_FORMAT_ARGB8888:
3611                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3612         default:
3613                 return PLANE_CTL_ALPHA_DISABLE;
3614         }
3615 }
3616
3617 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3618 {
3619         switch (pixel_format) {
3620         case DRM_FORMAT_ABGR8888:
3621         case DRM_FORMAT_ARGB8888:
3622                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3623         default:
3624                 return PLANE_COLOR_ALPHA_DISABLE;
3625         }
3626 }
3627
3628 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3629 {
3630         switch (fb_modifier) {
3631         case DRM_FORMAT_MOD_LINEAR:
3632                 break;
3633         case I915_FORMAT_MOD_X_TILED:
3634                 return PLANE_CTL_TILED_X;
3635         case I915_FORMAT_MOD_Y_TILED:
3636                 return PLANE_CTL_TILED_Y;
3637         case I915_FORMAT_MOD_Y_TILED_CCS:
3638                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3639         case I915_FORMAT_MOD_Yf_TILED:
3640                 return PLANE_CTL_TILED_YF;
3641         case I915_FORMAT_MOD_Yf_TILED_CCS:
3642                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
3643         default:
3644                 MISSING_CASE(fb_modifier);
3645         }
3646
3647         return 0;
3648 }
3649
3650 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3651 {
3652         switch (rotate) {
3653         case DRM_MODE_ROTATE_0:
3654                 break;
3655         /*
3656          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3657          * while i915 HW rotation is clockwise, thats why this swapping.
3658          */
3659         case DRM_MODE_ROTATE_90:
3660                 return PLANE_CTL_ROTATE_270;
3661         case DRM_MODE_ROTATE_180:
3662                 return PLANE_CTL_ROTATE_180;
3663         case DRM_MODE_ROTATE_270:
3664                 return PLANE_CTL_ROTATE_90;
3665         default:
3666                 MISSING_CASE(rotate);
3667         }
3668
3669         return 0;
3670 }
3671
3672 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3673 {
3674         switch (reflect) {
3675         case 0:
3676                 break;
3677         case DRM_MODE_REFLECT_X:
3678                 return PLANE_CTL_FLIP_HORIZONTAL;
3679         case DRM_MODE_REFLECT_Y:
3680         default:
3681                 MISSING_CASE(reflect);
3682         }
3683
3684         return 0;
3685 }
3686
3687 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3688                   const struct intel_plane_state *plane_state)
3689 {
3690         struct drm_i915_private *dev_priv =
3691                 to_i915(plane_state->base.plane->dev);
3692         const struct drm_framebuffer *fb = plane_state->base.fb;
3693         unsigned int rotation = plane_state->base.rotation;
3694         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3695         u32 plane_ctl;
3696
3697         plane_ctl = PLANE_CTL_ENABLE;
3698
3699         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3700                 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3701                 plane_ctl |=
3702                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3703                         PLANE_CTL_PIPE_CSC_ENABLE |
3704                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3705
3706                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3707                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3708
3709                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3710                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3711         }
3712
3713         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3714         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3715         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3716
3717         if (INTEL_GEN(dev_priv) >= 10)
3718                 plane_ctl |= cnl_plane_ctl_flip(rotation &
3719                                                 DRM_MODE_REFLECT_MASK);
3720
3721         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3722                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3723         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3724                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3725
3726         return plane_ctl;
3727 }
3728
3729 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3730                         const struct intel_plane_state *plane_state)
3731 {
3732         struct drm_i915_private *dev_priv =
3733                 to_i915(plane_state->base.plane->dev);
3734         const struct drm_framebuffer *fb = plane_state->base.fb;
3735         u32 plane_color_ctl = 0;
3736
3737         if (INTEL_GEN(dev_priv) < 11) {
3738                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3739                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3740         }
3741         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3742         plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3743
3744         if (fb->format->is_yuv) {
3745                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3746                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3747                 else
3748                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3749
3750                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3751                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3752         }
3753
3754         return plane_color_ctl;
3755 }
3756
3757 static int
3758 __intel_display_resume(struct drm_device *dev,
3759                        struct drm_atomic_state *state,
3760                        struct drm_modeset_acquire_ctx *ctx)
3761 {
3762         struct drm_crtc_state *crtc_state;
3763         struct drm_crtc *crtc;
3764         int i, ret;
3765
3766         intel_modeset_setup_hw_state(dev, ctx);
3767         i915_redisable_vga(to_i915(dev));
3768
3769         if (!state)
3770                 return 0;
3771
3772         /*
3773          * We've duplicated the state, pointers to the old state are invalid.
3774          *
3775          * Don't attempt to use the old state until we commit the duplicated state.
3776          */
3777         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3778                 /*
3779                  * Force recalculation even if we restore
3780                  * current state. With fast modeset this may not result
3781                  * in a modeset when the state is compatible.
3782                  */
3783                 crtc_state->mode_changed = true;
3784         }
3785
3786         /* ignore any reset values/BIOS leftovers in the WM registers */
3787         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3788                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3789
3790         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3791
3792         WARN_ON(ret == -EDEADLK);
3793         return ret;
3794 }
3795
3796 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3797 {
3798         return intel_has_gpu_reset(dev_priv) &&
3799                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3800 }
3801
3802 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3803 {
3804         struct drm_device *dev = &dev_priv->drm;
3805         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3806         struct drm_atomic_state *state;
3807         int ret;
3808
3809         /* reset doesn't touch the display */
3810         if (!i915_modparams.force_reset_modeset_test &&
3811             !gpu_reset_clobbers_display(dev_priv))
3812                 return;
3813
3814         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3815         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3816         wake_up_all(&dev_priv->gpu_error.wait_queue);
3817
3818         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3819                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3820                 i915_gem_set_wedged(dev_priv);
3821         }
3822
3823         /*
3824          * Need mode_config.mutex so that we don't
3825          * trample ongoing ->detect() and whatnot.
3826          */
3827         mutex_lock(&dev->mode_config.mutex);
3828         drm_modeset_acquire_init(ctx, 0);
3829         while (1) {
3830                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3831                 if (ret != -EDEADLK)
3832                         break;
3833
3834                 drm_modeset_backoff(ctx);
3835         }
3836         /*
3837          * Disabling the crtcs gracefully seems nicer. Also the
3838          * g33 docs say we should at least disable all the planes.
3839          */
3840         state = drm_atomic_helper_duplicate_state(dev, ctx);
3841         if (IS_ERR(state)) {
3842                 ret = PTR_ERR(state);
3843                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3844                 return;
3845         }
3846
3847         ret = drm_atomic_helper_disable_all(dev, ctx);
3848         if (ret) {
3849                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3850                 drm_atomic_state_put(state);
3851                 return;
3852         }
3853
3854         dev_priv->modeset_restore_state = state;
3855         state->acquire_ctx = ctx;
3856 }
3857
3858 void intel_finish_reset(struct drm_i915_private *dev_priv)
3859 {
3860         struct drm_device *dev = &dev_priv->drm;
3861         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3862         struct drm_atomic_state *state;
3863         int ret;
3864
3865         /* reset doesn't touch the display */
3866         if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3867                 return;
3868
3869         state = fetch_and_zero(&dev_priv->modeset_restore_state);
3870         if (!state)
3871                 goto unlock;
3872
3873         /* reset doesn't touch the display */
3874         if (!gpu_reset_clobbers_display(dev_priv)) {
3875                 /* for testing only restore the display */
3876                 ret = __intel_display_resume(dev, state, ctx);
3877                 if (ret)
3878                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3879         } else {
3880                 /*
3881                  * The display has been reset as well,
3882                  * so need a full re-initialization.
3883                  */
3884                 intel_runtime_pm_disable_interrupts(dev_priv);
3885                 intel_runtime_pm_enable_interrupts(dev_priv);
3886
3887                 intel_pps_unlock_regs_wa(dev_priv);
3888                 intel_modeset_init_hw(dev);
3889                 intel_init_clock_gating(dev_priv);
3890
3891                 spin_lock_irq(&dev_priv->irq_lock);
3892                 if (dev_priv->display.hpd_irq_setup)
3893                         dev_priv->display.hpd_irq_setup(dev_priv);
3894                 spin_unlock_irq(&dev_priv->irq_lock);
3895
3896                 ret = __intel_display_resume(dev, state, ctx);
3897                 if (ret)
3898                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3899
3900                 intel_hpd_init(dev_priv);
3901         }
3902
3903         drm_atomic_state_put(state);
3904 unlock:
3905         drm_modeset_drop_locks(ctx);
3906         drm_modeset_acquire_fini(ctx);
3907         mutex_unlock(&dev->mode_config.mutex);
3908
3909         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3910 }
3911
3912 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3913                                      const struct intel_crtc_state *new_crtc_state)
3914 {
3915         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3916         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3917
3918         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3919         crtc->base.mode = new_crtc_state->base.mode;
3920
3921         /*
3922          * Update pipe size and adjust fitter if needed: the reason for this is
3923          * that in compute_mode_changes we check the native mode (not the pfit
3924          * mode) to see if we can flip rather than do a full mode set. In the
3925          * fastboot case, we'll flip, but if we don't update the pipesrc and
3926          * pfit state, we'll end up with a big fb scanned out into the wrong
3927          * sized surface.
3928          */
3929
3930         I915_WRITE(PIPESRC(crtc->pipe),
3931                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3932                    (new_crtc_state->pipe_src_h - 1));
3933
3934         /* on skylake this is done by detaching scalers */
3935         if (INTEL_GEN(dev_priv) >= 9) {
3936                 skl_detach_scalers(crtc);
3937
3938                 if (new_crtc_state->pch_pfit.enabled)
3939                         skylake_pfit_enable(crtc);
3940         } else if (HAS_PCH_SPLIT(dev_priv)) {
3941                 if (new_crtc_state->pch_pfit.enabled)
3942                         ironlake_pfit_enable(crtc);
3943                 else if (old_crtc_state->pch_pfit.enabled)
3944                         ironlake_pfit_disable(crtc, true);
3945         }
3946 }
3947
3948 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3949 {
3950         struct drm_device *dev = crtc->base.dev;
3951         struct drm_i915_private *dev_priv = to_i915(dev);
3952         int pipe = crtc->pipe;
3953         i915_reg_t reg;
3954         u32 temp;
3955
3956         /* enable normal train */
3957         reg = FDI_TX_CTL(pipe);
3958         temp = I915_READ(reg);
3959         if (IS_IVYBRIDGE(dev_priv)) {
3960                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3961                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3962         } else {
3963                 temp &= ~FDI_LINK_TRAIN_NONE;
3964                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3965         }
3966         I915_WRITE(reg, temp);
3967
3968         reg = FDI_RX_CTL(pipe);
3969         temp = I915_READ(reg);
3970         if (HAS_PCH_CPT(dev_priv)) {
3971                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3972                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3973         } else {
3974                 temp &= ~FDI_LINK_TRAIN_NONE;
3975                 temp |= FDI_LINK_TRAIN_NONE;
3976         }
3977         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3978
3979         /* wait one idle pattern time */
3980         POSTING_READ(reg);
3981         udelay(1000);
3982
3983         /* IVB wants error correction enabled */
3984         if (IS_IVYBRIDGE(dev_priv))
3985                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3986                            FDI_FE_ERRC_ENABLE);
3987 }
3988
3989 /* The FDI link training functions for ILK/Ibexpeak. */
3990 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3991                                     const struct intel_crtc_state *crtc_state)
3992 {
3993         struct drm_device *dev = crtc->base.dev;
3994         struct drm_i915_private *dev_priv = to_i915(dev);
3995         int pipe = crtc->pipe;
3996         i915_reg_t reg;
3997         u32 temp, tries;
3998
3999         /* FDI needs bits from pipe first */
4000         assert_pipe_enabled(dev_priv, pipe);
4001
4002         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4003            for train result */
4004         reg = FDI_RX_IMR(pipe);
4005         temp = I915_READ(reg);
4006         temp &= ~FDI_RX_SYMBOL_LOCK;
4007         temp &= ~FDI_RX_BIT_LOCK;
4008         I915_WRITE(reg, temp);
4009         I915_READ(reg);
4010         udelay(150);
4011
4012         /* enable CPU FDI TX and PCH FDI RX */
4013         reg = FDI_TX_CTL(pipe);
4014         temp = I915_READ(reg);
4015         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4016         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4017         temp &= ~FDI_LINK_TRAIN_NONE;
4018         temp |= FDI_LINK_TRAIN_PATTERN_1;
4019         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4020
4021         reg = FDI_RX_CTL(pipe);
4022         temp = I915_READ(reg);
4023         temp &= ~FDI_LINK_TRAIN_NONE;
4024         temp |= FDI_LINK_TRAIN_PATTERN_1;
4025         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4026
4027         POSTING_READ(reg);
4028         udelay(150);
4029
4030         /* Ironlake workaround, enable clock pointer after FDI enable*/
4031         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4032         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4033                    FDI_RX_PHASE_SYNC_POINTER_EN);
4034
4035         reg = FDI_RX_IIR(pipe);
4036         for (tries = 0; tries < 5; tries++) {
4037                 temp = I915_READ(reg);
4038                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4039
4040                 if ((temp & FDI_RX_BIT_LOCK)) {
4041                         DRM_DEBUG_KMS("FDI train 1 done.\n");
4042                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4043                         break;
4044                 }
4045         }
4046         if (tries == 5)
4047                 DRM_ERROR("FDI train 1 fail!\n");
4048
4049         /* Train 2 */
4050         reg = FDI_TX_CTL(pipe);
4051         temp = I915_READ(reg);
4052         temp &= ~FDI_LINK_TRAIN_NONE;
4053         temp |= FDI_LINK_TRAIN_PATTERN_2;
4054         I915_WRITE(reg, temp);
4055
4056         reg = FDI_RX_CTL(pipe);
4057         temp = I915_READ(reg);
4058         temp &= ~FDI_LINK_TRAIN_NONE;
4059         temp |= FDI_LINK_TRAIN_PATTERN_2;
4060         I915_WRITE(reg, temp);
4061
4062         POSTING_READ(reg);
4063         udelay(150);
4064
4065         reg = FDI_RX_IIR(pipe);
4066         for (tries = 0; tries < 5; tries++) {
4067                 temp = I915_READ(reg);
4068                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4069
4070                 if (temp & FDI_RX_SYMBOL_LOCK) {
4071                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4072                         DRM_DEBUG_KMS("FDI train 2 done.\n");
4073                         break;
4074                 }
4075         }
4076         if (tries == 5)
4077                 DRM_ERROR("FDI train 2 fail!\n");
4078
4079         DRM_DEBUG_KMS("FDI train done\n");
4080
4081 }
4082
4083 static const int snb_b_fdi_train_param[] = {
4084         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4085         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4086         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4087         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4088 };
4089
4090 /* The FDI link training functions for SNB/Cougarpoint. */
4091 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4092                                 const struct intel_crtc_state *crtc_state)
4093 {
4094         struct drm_device *dev = crtc->base.dev;
4095         struct drm_i915_private *dev_priv = to_i915(dev);
4096         int pipe = crtc->pipe;
4097         i915_reg_t reg;
4098         u32 temp, i, retry;
4099
4100         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4101            for train result */
4102         reg = FDI_RX_IMR(pipe);
4103         temp = I915_READ(reg);
4104         temp &= ~FDI_RX_SYMBOL_LOCK;
4105         temp &= ~FDI_RX_BIT_LOCK;
4106         I915_WRITE(reg, temp);
4107
4108         POSTING_READ(reg);
4109         udelay(150);
4110
4111         /* enable CPU FDI TX and PCH FDI RX */
4112         reg = FDI_TX_CTL(pipe);
4113         temp = I915_READ(reg);
4114         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4115         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4116         temp &= ~FDI_LINK_TRAIN_NONE;
4117         temp |= FDI_LINK_TRAIN_PATTERN_1;
4118         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4119         /* SNB-B */
4120         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4121         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4122
4123         I915_WRITE(FDI_RX_MISC(pipe),
4124                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4125
4126         reg = FDI_RX_CTL(pipe);
4127         temp = I915_READ(reg);
4128         if (HAS_PCH_CPT(dev_priv)) {
4129                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4130                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4131         } else {
4132                 temp &= ~FDI_LINK_TRAIN_NONE;
4133                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4134         }
4135         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4136
4137         POSTING_READ(reg);
4138         udelay(150);
4139
4140         for (i = 0; i < 4; i++) {
4141                 reg = FDI_TX_CTL(pipe);
4142                 temp = I915_READ(reg);
4143                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4144                 temp |= snb_b_fdi_train_param[i];
4145                 I915_WRITE(reg, temp);
4146
4147                 POSTING_READ(reg);
4148                 udelay(500);
4149
4150                 for (retry = 0; retry < 5; retry++) {
4151                         reg = FDI_RX_IIR(pipe);
4152                         temp = I915_READ(reg);
4153                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4154                         if (temp & FDI_RX_BIT_LOCK) {
4155                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4156                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4157                                 break;
4158                         }
4159                         udelay(50);
4160                 }
4161                 if (retry < 5)
4162                         break;
4163         }
4164         if (i == 4)
4165                 DRM_ERROR("FDI train 1 fail!\n");
4166
4167         /* Train 2 */
4168         reg = FDI_TX_CTL(pipe);
4169         temp = I915_READ(reg);
4170         temp &= ~FDI_LINK_TRAIN_NONE;
4171         temp |= FDI_LINK_TRAIN_PATTERN_2;
4172         if (IS_GEN6(dev_priv)) {
4173                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4174                 /* SNB-B */
4175                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4176         }
4177         I915_WRITE(reg, temp);
4178
4179         reg = FDI_RX_CTL(pipe);
4180         temp = I915_READ(reg);
4181         if (HAS_PCH_CPT(dev_priv)) {
4182                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4183                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4184         } else {
4185                 temp &= ~FDI_LINK_TRAIN_NONE;
4186                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4187         }
4188         I915_WRITE(reg, temp);
4189
4190         POSTING_READ(reg);
4191         udelay(150);
4192
4193         for (i = 0; i < 4; i++) {
4194                 reg = FDI_TX_CTL(pipe);
4195                 temp = I915_READ(reg);
4196                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4197                 temp |= snb_b_fdi_train_param[i];
4198                 I915_WRITE(reg, temp);
4199
4200                 POSTING_READ(reg);
4201                 udelay(500);
4202
4203                 for (retry = 0; retry < 5; retry++) {
4204                         reg = FDI_RX_IIR(pipe);
4205                         temp = I915_READ(reg);
4206                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4207                         if (temp & FDI_RX_SYMBOL_LOCK) {
4208                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4209                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4210                                 break;
4211                         }
4212                         udelay(50);
4213                 }
4214                 if (retry < 5)
4215                         break;
4216         }
4217         if (i == 4)
4218                 DRM_ERROR("FDI train 2 fail!\n");
4219
4220         DRM_DEBUG_KMS("FDI train done.\n");
4221 }
4222
4223 /* Manual link training for Ivy Bridge A0 parts */
4224 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4225                                       const struct intel_crtc_state *crtc_state)
4226 {
4227         struct drm_device *dev = crtc->base.dev;
4228         struct drm_i915_private *dev_priv = to_i915(dev);
4229         int pipe = crtc->pipe;
4230         i915_reg_t reg;
4231         u32 temp, i, j;
4232
4233         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4234            for train result */
4235         reg = FDI_RX_IMR(pipe);
4236         temp = I915_READ(reg);
4237         temp &= ~FDI_RX_SYMBOL_LOCK;
4238         temp &= ~FDI_RX_BIT_LOCK;
4239         I915_WRITE(reg, temp);
4240
4241         POSTING_READ(reg);
4242         udelay(150);
4243
4244         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4245                       I915_READ(FDI_RX_IIR(pipe)));
4246
4247         /* Try each vswing and preemphasis setting twice before moving on */
4248         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4249                 /* disable first in case we need to retry */
4250                 reg = FDI_TX_CTL(pipe);
4251                 temp = I915_READ(reg);
4252                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4253                 temp &= ~FDI_TX_ENABLE;
4254                 I915_WRITE(reg, temp);
4255
4256                 reg = FDI_RX_CTL(pipe);
4257                 temp = I915_READ(reg);
4258                 temp &= ~FDI_LINK_TRAIN_AUTO;
4259                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4260                 temp &= ~FDI_RX_ENABLE;
4261                 I915_WRITE(reg, temp);
4262
4263                 /* enable CPU FDI TX and PCH FDI RX */
4264                 reg = FDI_TX_CTL(pipe);
4265                 temp = I915_READ(reg);
4266                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4267                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4268                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4269                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4270                 temp |= snb_b_fdi_train_param[j/2];
4271                 temp |= FDI_COMPOSITE_SYNC;
4272                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4273
4274                 I915_WRITE(FDI_RX_MISC(pipe),
4275                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4276
4277                 reg = FDI_RX_CTL(pipe);
4278                 temp = I915_READ(reg);
4279                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4280                 temp |= FDI_COMPOSITE_SYNC;
4281                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4282
4283                 POSTING_READ(reg);
4284                 udelay(1); /* should be 0.5us */
4285
4286                 for (i = 0; i < 4; i++) {
4287                         reg = FDI_RX_IIR(pipe);
4288                         temp = I915_READ(reg);
4289                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4290
4291                         if (temp & FDI_RX_BIT_LOCK ||
4292                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4293                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4294                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4295                                               i);
4296                                 break;
4297                         }
4298                         udelay(1); /* should be 0.5us */
4299                 }
4300                 if (i == 4) {
4301                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4302                         continue;
4303                 }
4304
4305                 /* Train 2 */
4306                 reg = FDI_TX_CTL(pipe);
4307                 temp = I915_READ(reg);
4308                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4309                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4310                 I915_WRITE(reg, temp);
4311
4312                 reg = FDI_RX_CTL(pipe);
4313                 temp = I915_READ(reg);
4314                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4315                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4316                 I915_WRITE(reg, temp);
4317
4318                 POSTING_READ(reg);
4319                 udelay(2); /* should be 1.5us */
4320
4321                 for (i = 0; i < 4; i++) {
4322                         reg = FDI_RX_IIR(pipe);
4323                         temp = I915_READ(reg);
4324                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4325
4326                         if (temp & FDI_RX_SYMBOL_LOCK ||
4327                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4328                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4329                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4330                                               i);
4331                                 goto train_done;
4332                         }
4333                         udelay(2); /* should be 1.5us */
4334                 }
4335                 if (i == 4)
4336                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4337         }
4338
4339 train_done:
4340         DRM_DEBUG_KMS("FDI train done.\n");
4341 }
4342
4343 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4344 {
4345         struct drm_device *dev = intel_crtc->base.dev;
4346         struct drm_i915_private *dev_priv = to_i915(dev);
4347         int pipe = intel_crtc->pipe;
4348         i915_reg_t reg;
4349         u32 temp;
4350
4351         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4352         reg = FDI_RX_CTL(pipe);
4353         temp = I915_READ(reg);
4354         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4355         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4356         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4357         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4358
4359         POSTING_READ(reg);
4360         udelay(200);
4361
4362         /* Switch from Rawclk to PCDclk */
4363         temp = I915_READ(reg);
4364         I915_WRITE(reg, temp | FDI_PCDCLK);
4365
4366         POSTING_READ(reg);
4367         udelay(200);
4368
4369         /* Enable CPU FDI TX PLL, always on for Ironlake */
4370         reg = FDI_TX_CTL(pipe);
4371         temp = I915_READ(reg);
4372         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4373                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4374
4375                 POSTING_READ(reg);
4376                 udelay(100);
4377         }
4378 }
4379
4380 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4381 {
4382         struct drm_device *dev = intel_crtc->base.dev;
4383         struct drm_i915_private *dev_priv = to_i915(dev);
4384         int pipe = intel_crtc->pipe;
4385         i915_reg_t reg;
4386         u32 temp;
4387
4388         /* Switch from PCDclk to Rawclk */
4389         reg = FDI_RX_CTL(pipe);
4390         temp = I915_READ(reg);
4391         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4392
4393         /* Disable CPU FDI TX PLL */
4394         reg = FDI_TX_CTL(pipe);
4395         temp = I915_READ(reg);
4396         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4397
4398         POSTING_READ(reg);
4399         udelay(100);
4400
4401         reg = FDI_RX_CTL(pipe);
4402         temp = I915_READ(reg);
4403         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4404
4405         /* Wait for the clocks to turn off. */
4406         POSTING_READ(reg);
4407         udelay(100);
4408 }
4409
4410 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4411 {
4412         struct drm_device *dev = crtc->dev;
4413         struct drm_i915_private *dev_priv = to_i915(dev);
4414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4415         int pipe = intel_crtc->pipe;
4416         i915_reg_t reg;
4417         u32 temp;
4418
4419         /* disable CPU FDI tx and PCH FDI rx */
4420         reg = FDI_TX_CTL(pipe);
4421         temp = I915_READ(reg);
4422         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4423         POSTING_READ(reg);
4424
4425         reg = FDI_RX_CTL(pipe);
4426         temp = I915_READ(reg);
4427         temp &= ~(0x7 << 16);
4428         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4429         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4430
4431         POSTING_READ(reg);
4432         udelay(100);
4433
4434         /* Ironlake workaround, disable clock pointer after downing FDI */
4435         if (HAS_PCH_IBX(dev_priv))
4436                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4437
4438         /* still set train pattern 1 */
4439         reg = FDI_TX_CTL(pipe);
4440         temp = I915_READ(reg);
4441         temp &= ~FDI_LINK_TRAIN_NONE;
4442         temp |= FDI_LINK_TRAIN_PATTERN_1;
4443         I915_WRITE(reg, temp);
4444
4445         reg = FDI_RX_CTL(pipe);
4446         temp = I915_READ(reg);
4447         if (HAS_PCH_CPT(dev_priv)) {
4448                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4449                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4450         } else {
4451                 temp &= ~FDI_LINK_TRAIN_NONE;
4452                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4453         }
4454         /* BPC in FDI rx is consistent with that in PIPECONF */
4455         temp &= ~(0x07 << 16);
4456         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4457         I915_WRITE(reg, temp);
4458
4459         POSTING_READ(reg);
4460         udelay(100);
4461 }
4462
4463 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4464 {
4465         struct drm_crtc *crtc;
4466         bool cleanup_done;
4467
4468         drm_for_each_crtc(crtc, &dev_priv->drm) {
4469                 struct drm_crtc_commit *commit;
4470                 spin_lock(&crtc->commit_lock);
4471                 commit = list_first_entry_or_null(&crtc->commit_list,
4472                                                   struct drm_crtc_commit, commit_entry);
4473                 cleanup_done = commit ?
4474                         try_wait_for_completion(&commit->cleanup_done) : true;
4475                 spin_unlock(&crtc->commit_lock);
4476
4477                 if (cleanup_done)
4478                         continue;
4479
4480                 drm_crtc_wait_one_vblank(crtc);
4481
4482                 return true;
4483         }
4484
4485         return false;
4486 }
4487
4488 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4489 {
4490         u32 temp;
4491
4492         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4493
4494         mutex_lock(&dev_priv->sb_lock);
4495
4496         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4497         temp |= SBI_SSCCTL_DISABLE;
4498         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4499
4500         mutex_unlock(&dev_priv->sb_lock);
4501 }
4502
4503 /* Program iCLKIP clock to the desired frequency */
4504 static void lpt_program_iclkip(struct intel_crtc *crtc)
4505 {
4506         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4507         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4508         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4509         u32 temp;
4510
4511         lpt_disable_iclkip(dev_priv);
4512
4513         /* The iCLK virtual clock root frequency is in MHz,
4514          * but the adjusted_mode->crtc_clock in in KHz. To get the
4515          * divisors, it is necessary to divide one by another, so we
4516          * convert the virtual clock precision to KHz here for higher
4517          * precision.
4518          */
4519         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4520                 u32 iclk_virtual_root_freq = 172800 * 1000;
4521                 u32 iclk_pi_range = 64;
4522                 u32 desired_divisor;
4523
4524                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4525                                                     clock << auxdiv);
4526                 divsel = (desired_divisor / iclk_pi_range) - 2;
4527                 phaseinc = desired_divisor % iclk_pi_range;
4528
4529                 /*
4530                  * Near 20MHz is a corner case which is
4531                  * out of range for the 7-bit divisor
4532                  */
4533                 if (divsel <= 0x7f)
4534                         break;
4535         }
4536
4537         /* This should not happen with any sane values */
4538         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4539                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4540         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4541                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4542
4543         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4544                         clock,
4545                         auxdiv,
4546                         divsel,
4547                         phasedir,
4548                         phaseinc);
4549
4550         mutex_lock(&dev_priv->sb_lock);
4551
4552         /* Program SSCDIVINTPHASE6 */
4553         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4554         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4555         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4556         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4557         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4558         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4559         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4560         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4561
4562         /* Program SSCAUXDIV */
4563         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4564         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4565         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4566         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4567
4568         /* Enable modulator and associated divider */
4569         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4570         temp &= ~SBI_SSCCTL_DISABLE;
4571         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4572
4573         mutex_unlock(&dev_priv->sb_lock);
4574
4575         /* Wait for initialization time */
4576         udelay(24);
4577
4578         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4579 }
4580
4581 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4582 {
4583         u32 divsel, phaseinc, auxdiv;
4584         u32 iclk_virtual_root_freq = 172800 * 1000;
4585         u32 iclk_pi_range = 64;
4586         u32 desired_divisor;
4587         u32 temp;
4588
4589         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4590                 return 0;
4591
4592         mutex_lock(&dev_priv->sb_lock);
4593
4594         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4595         if (temp & SBI_SSCCTL_DISABLE) {
4596                 mutex_unlock(&dev_priv->sb_lock);
4597                 return 0;
4598         }
4599
4600         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4601         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4602                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4603         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4604                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4605
4606         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4607         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4608                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4609
4610         mutex_unlock(&dev_priv->sb_lock);
4611
4612         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4613
4614         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4615                                  desired_divisor << auxdiv);
4616 }
4617
4618 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4619                                                 enum pipe pch_transcoder)
4620 {
4621         struct drm_device *dev = crtc->base.dev;
4622         struct drm_i915_private *dev_priv = to_i915(dev);
4623         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4624
4625         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4626                    I915_READ(HTOTAL(cpu_transcoder)));
4627         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4628                    I915_READ(HBLANK(cpu_transcoder)));
4629         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4630                    I915_READ(HSYNC(cpu_transcoder)));
4631
4632         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4633                    I915_READ(VTOTAL(cpu_transcoder)));
4634         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4635                    I915_READ(VBLANK(cpu_transcoder)));
4636         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4637                    I915_READ(VSYNC(cpu_transcoder)));
4638         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4639                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4640 }
4641
4642 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4643 {
4644         struct drm_i915_private *dev_priv = to_i915(dev);
4645         uint32_t temp;
4646
4647         temp = I915_READ(SOUTH_CHICKEN1);
4648         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4649                 return;
4650
4651         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4652         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4653
4654         temp &= ~FDI_BC_BIFURCATION_SELECT;
4655         if (enable)
4656                 temp |= FDI_BC_BIFURCATION_SELECT;
4657
4658         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4659         I915_WRITE(SOUTH_CHICKEN1, temp);
4660         POSTING_READ(SOUTH_CHICKEN1);
4661 }
4662
4663 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4664 {
4665         struct drm_device *dev = intel_crtc->base.dev;
4666
4667         switch (intel_crtc->pipe) {
4668         case PIPE_A:
4669                 break;
4670         case PIPE_B:
4671                 if (intel_crtc->config->fdi_lanes > 2)
4672                         cpt_set_fdi_bc_bifurcation(dev, false);
4673                 else
4674                         cpt_set_fdi_bc_bifurcation(dev, true);
4675
4676                 break;
4677         case PIPE_C:
4678                 cpt_set_fdi_bc_bifurcation(dev, true);
4679
4680                 break;
4681         default:
4682                 BUG();
4683         }
4684 }
4685
4686 /*
4687  * Finds the encoder associated with the given CRTC. This can only be
4688  * used when we know that the CRTC isn't feeding multiple encoders!
4689  */
4690 static struct intel_encoder *
4691 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4692                            const struct intel_crtc_state *crtc_state)
4693 {
4694         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4695         const struct drm_connector_state *connector_state;
4696         const struct drm_connector *connector;
4697         struct intel_encoder *encoder = NULL;
4698         int num_encoders = 0;
4699         int i;
4700
4701         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4702                 if (connector_state->crtc != &crtc->base)
4703                         continue;
4704
4705                 encoder = to_intel_encoder(connector_state->best_encoder);
4706                 num_encoders++;
4707         }
4708
4709         WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4710              num_encoders, pipe_name(crtc->pipe));
4711
4712         return encoder;
4713 }
4714
4715 /*
4716  * Enable PCH resources required for PCH ports:
4717  *   - PCH PLLs
4718  *   - FDI training & RX/TX
4719  *   - update transcoder timings
4720  *   - DP transcoding bits
4721  *   - transcoder
4722  */
4723 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4724                                 const struct intel_crtc_state *crtc_state)
4725 {
4726         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4727         struct drm_device *dev = crtc->base.dev;
4728         struct drm_i915_private *dev_priv = to_i915(dev);
4729         int pipe = crtc->pipe;
4730         u32 temp;
4731
4732         assert_pch_transcoder_disabled(dev_priv, pipe);
4733
4734         if (IS_IVYBRIDGE(dev_priv))
4735                 ivybridge_update_fdi_bc_bifurcation(crtc);
4736
4737         /* Write the TU size bits before fdi link training, so that error
4738          * detection works. */
4739         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4740                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4741
4742         /* For PCH output, training FDI link */
4743         dev_priv->display.fdi_link_train(crtc, crtc_state);
4744
4745         /* We need to program the right clock selection before writing the pixel
4746          * mutliplier into the DPLL. */
4747         if (HAS_PCH_CPT(dev_priv)) {
4748                 u32 sel;
4749
4750                 temp = I915_READ(PCH_DPLL_SEL);
4751                 temp |= TRANS_DPLL_ENABLE(pipe);
4752                 sel = TRANS_DPLLB_SEL(pipe);
4753                 if (crtc_state->shared_dpll ==
4754                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4755                         temp |= sel;
4756                 else
4757                         temp &= ~sel;
4758                 I915_WRITE(PCH_DPLL_SEL, temp);
4759         }
4760
4761         /* XXX: pch pll's can be enabled any time before we enable the PCH
4762          * transcoder, and we actually should do this to not upset any PCH
4763          * transcoder that already use the clock when we share it.
4764          *
4765          * Note that enable_shared_dpll tries to do the right thing, but
4766          * get_shared_dpll unconditionally resets the pll - we need that to have
4767          * the right LVDS enable sequence. */
4768         intel_enable_shared_dpll(crtc);
4769
4770         /* set transcoder timing, panel must allow it */
4771         assert_panel_unlocked(dev_priv, pipe);
4772         ironlake_pch_transcoder_set_timings(crtc, pipe);
4773
4774         intel_fdi_normal_train(crtc);
4775
4776         /* For PCH DP, enable TRANS_DP_CTL */
4777         if (HAS_PCH_CPT(dev_priv) &&
4778             intel_crtc_has_dp_encoder(crtc_state)) {
4779                 const struct drm_display_mode *adjusted_mode =
4780                         &crtc_state->base.adjusted_mode;
4781                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4782                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4783                 enum port port;
4784
4785                 temp = I915_READ(reg);
4786                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4787                           TRANS_DP_SYNC_MASK |
4788                           TRANS_DP_BPC_MASK);
4789                 temp |= TRANS_DP_OUTPUT_ENABLE;
4790                 temp |= bpc << 9; /* same format but at 11:9 */
4791
4792                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4793                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4794                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4795                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4796
4797                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4798                 WARN_ON(port < PORT_B || port > PORT_D);
4799                 temp |= TRANS_DP_PORT_SEL(port);
4800
4801                 I915_WRITE(reg, temp);
4802         }
4803
4804         ironlake_enable_pch_transcoder(dev_priv, pipe);
4805 }
4806
4807 static void lpt_pch_enable(const struct intel_atomic_state *state,
4808                            const struct intel_crtc_state *crtc_state)
4809 {
4810         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4811         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4812         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4813
4814         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4815
4816         lpt_program_iclkip(crtc);
4817
4818         /* Set transcoder timing. */
4819         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4820
4821         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4822 }
4823
4824 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4825 {
4826         struct drm_i915_private *dev_priv = to_i915(dev);
4827         i915_reg_t dslreg = PIPEDSL(pipe);
4828         u32 temp;
4829
4830         temp = I915_READ(dslreg);
4831         udelay(500);
4832         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4833                 if (wait_for(I915_READ(dslreg) != temp, 5))
4834                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4835         }
4836 }
4837
4838 /*
4839  * The hardware phase 0.0 refers to the center of the pixel.
4840  * We want to start from the top/left edge which is phase
4841  * -0.5. That matches how the hardware calculates the scaling
4842  * factors (from top-left of the first pixel to bottom-right
4843  * of the last pixel, as opposed to the pixel centers).
4844  *
4845  * For 4:2:0 subsampled chroma planes we obviously have to
4846  * adjust that so that the chroma sample position lands in
4847  * the right spot.
4848  *
4849  * Note that for packed YCbCr 4:2:2 formats there is no way to
4850  * control chroma siting. The hardware simply replicates the
4851  * chroma samples for both of the luma samples, and thus we don't
4852  * actually get the expected MPEG2 chroma siting convention :(
4853  * The same behaviour is observed on pre-SKL platforms as well.
4854  *
4855  * Theory behind the formula (note that we ignore sub-pixel
4856  * source coordinates):
4857  * s = source sample position
4858  * d = destination sample position
4859  *
4860  * Downscaling 4:1:
4861  * -0.5
4862  * | 0.0
4863  * | |     1.5 (initial phase)
4864  * | |     |
4865  * v v     v
4866  * | s | s | s | s |
4867  * |       d       |
4868  *
4869  * Upscaling 1:4:
4870  * -0.5
4871  * | -0.375 (initial phase)
4872  * | |     0.0
4873  * | |     |
4874  * v v     v
4875  * |       s       |
4876  * | d | d | d | d |
4877  */
4878 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
4879 {
4880         int phase = -0x8000;
4881         u16 trip = 0;
4882
4883         if (chroma_cosited)
4884                 phase += (sub - 1) * 0x8000 / sub;
4885
4886         phase += scale / (2 * sub);
4887
4888         /*
4889          * Hardware initial phase limited to [-0.5:1.5].
4890          * Since the max hardware scale factor is 3.0, we
4891          * should never actually excdeed 1.0 here.
4892          */
4893         WARN_ON(phase < -0x8000 || phase > 0x18000);
4894
4895         if (phase < 0)
4896                 phase = 0x10000 + phase;
4897         else
4898                 trip = PS_PHASE_TRIP;
4899
4900         return ((phase >> 2) & PS_PHASE_MASK) | trip;
4901 }
4902
4903 static int
4904 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4905                   unsigned int scaler_user, int *scaler_id,
4906                   int src_w, int src_h, int dst_w, int dst_h,
4907                   bool plane_scaler_check,
4908                   uint32_t pixel_format)
4909 {
4910         struct intel_crtc_scaler_state *scaler_state =
4911                 &crtc_state->scaler_state;
4912         struct intel_crtc *intel_crtc =
4913                 to_intel_crtc(crtc_state->base.crtc);
4914         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4915         const struct drm_display_mode *adjusted_mode =
4916                 &crtc_state->base.adjusted_mode;
4917         int need_scaling;
4918
4919         /*
4920          * Src coordinates are already rotated by 270 degrees for
4921          * the 90/270 degree plane rotation cases (to match the
4922          * GTT mapping), hence no need to account for rotation here.
4923          */
4924         need_scaling = src_w != dst_w || src_h != dst_h;
4925
4926         if (plane_scaler_check)
4927                 if (pixel_format == DRM_FORMAT_NV12)
4928                         need_scaling = true;
4929
4930         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4931                 need_scaling = true;
4932
4933         /*
4934          * Scaling/fitting not supported in IF-ID mode in GEN9+
4935          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4936          * Once NV12 is enabled, handle it here while allocating scaler
4937          * for NV12.
4938          */
4939         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4940             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4941                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4942                 return -EINVAL;
4943         }
4944
4945         /*
4946          * if plane is being disabled or scaler is no more required or force detach
4947          *  - free scaler binded to this plane/crtc
4948          *  - in order to do this, update crtc->scaler_usage
4949          *
4950          * Here scaler state in crtc_state is set free so that
4951          * scaler can be assigned to other user. Actual register
4952          * update to free the scaler is done in plane/panel-fit programming.
4953          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4954          */
4955         if (force_detach || !need_scaling) {
4956                 if (*scaler_id >= 0) {
4957                         scaler_state->scaler_users &= ~(1 << scaler_user);
4958                         scaler_state->scalers[*scaler_id].in_use = 0;
4959
4960                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4961                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4962                                 intel_crtc->pipe, scaler_user, *scaler_id,
4963                                 scaler_state->scaler_users);
4964                         *scaler_id = -1;
4965                 }
4966                 return 0;
4967         }
4968
4969         if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4970             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4971                 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4972                 return -EINVAL;
4973         }
4974
4975         /* range checks */
4976         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4977             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4978             (IS_GEN11(dev_priv) &&
4979              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4980               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4981             (!IS_GEN11(dev_priv) &&
4982              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4983               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4984                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4985                         "size is out of scaler range\n",
4986                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4987                 return -EINVAL;
4988         }
4989
4990         /* mark this plane as a scaler user in crtc_state */
4991         scaler_state->scaler_users |= (1 << scaler_user);
4992         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4993                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4994                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4995                 scaler_state->scaler_users);
4996
4997         return 0;
4998 }
4999
5000 /**
5001  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5002  *
5003  * @state: crtc's scaler state
5004  *
5005  * Return
5006  *     0 - scaler_usage updated successfully
5007  *    error - requested scaling cannot be supported or other error condition
5008  */
5009 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5010 {
5011         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5012
5013         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5014                                  &state->scaler_state.scaler_id,
5015                                  state->pipe_src_w, state->pipe_src_h,
5016                                  adjusted_mode->crtc_hdisplay,
5017                                  adjusted_mode->crtc_vdisplay, false, 0);
5018 }
5019
5020 /**
5021  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5022  * @crtc_state: crtc's scaler state
5023  * @plane_state: atomic plane state to update
5024  *
5025  * Return
5026  *     0 - scaler_usage updated successfully
5027  *    error - requested scaling cannot be supported or other error condition
5028  */
5029 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5030                                    struct intel_plane_state *plane_state)
5031 {
5032
5033         struct intel_plane *intel_plane =
5034                 to_intel_plane(plane_state->base.plane);
5035         struct drm_framebuffer *fb = plane_state->base.fb;
5036         int ret;
5037
5038         bool force_detach = !fb || !plane_state->base.visible;
5039
5040         ret = skl_update_scaler(crtc_state, force_detach,
5041                                 drm_plane_index(&intel_plane->base),
5042                                 &plane_state->scaler_id,
5043                                 drm_rect_width(&plane_state->base.src) >> 16,
5044                                 drm_rect_height(&plane_state->base.src) >> 16,
5045                                 drm_rect_width(&plane_state->base.dst),
5046                                 drm_rect_height(&plane_state->base.dst),
5047                                 fb ? true : false, fb ? fb->format->format : 0);
5048
5049         if (ret || plane_state->scaler_id < 0)
5050                 return ret;
5051
5052         /* check colorkey */
5053         if (plane_state->ckey.flags) {
5054                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5055                               intel_plane->base.base.id,
5056                               intel_plane->base.name);
5057                 return -EINVAL;
5058         }
5059
5060         /* Check src format */
5061         switch (fb->format->format) {
5062         case DRM_FORMAT_RGB565:
5063         case DRM_FORMAT_XBGR8888:
5064         case DRM_FORMAT_XRGB8888:
5065         case DRM_FORMAT_ABGR8888:
5066         case DRM_FORMAT_ARGB8888:
5067         case DRM_FORMAT_XRGB2101010:
5068         case DRM_FORMAT_XBGR2101010:
5069         case DRM_FORMAT_YUYV:
5070         case DRM_FORMAT_YVYU:
5071         case DRM_FORMAT_UYVY:
5072         case DRM_FORMAT_VYUY:
5073         case DRM_FORMAT_NV12:
5074                 break;
5075         default:
5076                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5077                               intel_plane->base.base.id, intel_plane->base.name,
5078                               fb->base.id, fb->format->format);
5079                 return -EINVAL;
5080         }
5081
5082         return 0;
5083 }
5084
5085 static void skylake_scaler_disable(struct intel_crtc *crtc)
5086 {
5087         int i;
5088
5089         for (i = 0; i < crtc->num_scalers; i++)
5090                 skl_detach_scaler(crtc, i);
5091 }
5092
5093 static void skylake_pfit_enable(struct intel_crtc *crtc)
5094 {
5095         struct drm_device *dev = crtc->base.dev;
5096         struct drm_i915_private *dev_priv = to_i915(dev);
5097         int pipe = crtc->pipe;
5098         struct intel_crtc_scaler_state *scaler_state =
5099                 &crtc->config->scaler_state;
5100
5101         if (crtc->config->pch_pfit.enabled) {
5102                 u16 uv_rgb_hphase, uv_rgb_vphase;
5103                 int pfit_w, pfit_h, hscale, vscale;
5104                 int id;
5105
5106                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
5107                         return;
5108
5109                 pfit_w = (crtc->config->pch_pfit.size >> 16) & 0xFFFF;
5110                 pfit_h = crtc->config->pch_pfit.size & 0xFFFF;
5111
5112                 hscale = (crtc->config->pipe_src_w << 16) / pfit_w;
5113                 vscale = (crtc->config->pipe_src_h << 16) / pfit_h;
5114
5115                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5116                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5117
5118                 id = scaler_state->scaler_id;
5119                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5120                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5121                 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5122                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5123                 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5124                               PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5125                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
5126                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
5127         }
5128 }
5129
5130 static void ironlake_pfit_enable(struct intel_crtc *crtc)
5131 {
5132         struct drm_device *dev = crtc->base.dev;
5133         struct drm_i915_private *dev_priv = to_i915(dev);
5134         int pipe = crtc->pipe;
5135
5136         if (crtc->config->pch_pfit.enabled) {
5137                 /* Force use of hard-coded filter coefficients
5138                  * as some pre-programmed values are broken,
5139                  * e.g. x201.
5140                  */
5141                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5142                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5143                                                  PF_PIPE_SEL_IVB(pipe));
5144                 else
5145                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5146                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
5147                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
5148         }
5149 }
5150
5151 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5152 {
5153         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5154         struct drm_device *dev = crtc->base.dev;
5155         struct drm_i915_private *dev_priv = to_i915(dev);
5156
5157         if (!crtc_state->ips_enabled)
5158                 return;
5159
5160         /*
5161          * We can only enable IPS after we enable a plane and wait for a vblank
5162          * This function is called from post_plane_update, which is run after
5163          * a vblank wait.
5164          */
5165         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5166
5167         if (IS_BROADWELL(dev_priv)) {
5168                 mutex_lock(&dev_priv->pcu_lock);
5169                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5170                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
5171                 mutex_unlock(&dev_priv->pcu_lock);
5172                 /* Quoting Art Runyan: "its not safe to expect any particular
5173                  * value in IPS_CTL bit 31 after enabling IPS through the
5174                  * mailbox." Moreover, the mailbox may return a bogus state,
5175                  * so we need to just enable it and continue on.
5176                  */
5177         } else {
5178                 I915_WRITE(IPS_CTL, IPS_ENABLE);
5179                 /* The bit only becomes 1 in the next vblank, so this wait here
5180                  * is essentially intel_wait_for_vblank. If we don't have this
5181                  * and don't wait for vblanks until the end of crtc_enable, then
5182                  * the HW state readout code will complain that the expected
5183                  * IPS_CTL value is not the one we read. */
5184                 if (intel_wait_for_register(dev_priv,
5185                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5186                                             50))
5187                         DRM_ERROR("Timed out waiting for IPS enable\n");
5188         }
5189 }
5190
5191 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5192 {
5193         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5194         struct drm_device *dev = crtc->base.dev;
5195         struct drm_i915_private *dev_priv = to_i915(dev);
5196
5197         if (!crtc_state->ips_enabled)
5198                 return;
5199
5200         if (IS_BROADWELL(dev_priv)) {
5201                 mutex_lock(&dev_priv->pcu_lock);
5202                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5203                 mutex_unlock(&dev_priv->pcu_lock);
5204                 /*
5205                  * Wait for PCODE to finish disabling IPS. The BSpec specified
5206                  * 42ms timeout value leads to occasional timeouts so use 100ms
5207                  * instead.
5208                  */
5209                 if (intel_wait_for_register(dev_priv,
5210                                             IPS_CTL, IPS_ENABLE, 0,
5211                                             100))
5212                         DRM_ERROR("Timed out waiting for IPS disable\n");
5213         } else {
5214                 I915_WRITE(IPS_CTL, 0);
5215                 POSTING_READ(IPS_CTL);
5216         }
5217
5218         /* We need to wait for a vblank before we can disable the plane. */
5219         intel_wait_for_vblank(dev_priv, crtc->pipe);
5220 }
5221
5222 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5223 {
5224         if (intel_crtc->overlay) {
5225                 struct drm_device *dev = intel_crtc->base.dev;
5226
5227                 mutex_lock(&dev->struct_mutex);
5228                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5229                 mutex_unlock(&dev->struct_mutex);
5230         }
5231
5232         /* Let userspace switch the overlay on again. In most cases userspace
5233          * has to recompute where to put it anyway.
5234          */
5235 }
5236
5237 /**
5238  * intel_post_enable_primary - Perform operations after enabling primary plane
5239  * @crtc: the CRTC whose primary plane was just enabled
5240  * @new_crtc_state: the enabling state
5241  *
5242  * Performs potentially sleeping operations that must be done after the primary
5243  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5244  * called due to an explicit primary plane update, or due to an implicit
5245  * re-enable that is caused when a sprite plane is updated to no longer
5246  * completely hide the primary plane.
5247  */
5248 static void
5249 intel_post_enable_primary(struct drm_crtc *crtc,
5250                           const struct intel_crtc_state *new_crtc_state)
5251 {
5252         struct drm_device *dev = crtc->dev;
5253         struct drm_i915_private *dev_priv = to_i915(dev);
5254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5255         int pipe = intel_crtc->pipe;
5256
5257         /*
5258          * Gen2 reports pipe underruns whenever all planes are disabled.
5259          * So don't enable underrun reporting before at least some planes
5260          * are enabled.
5261          * FIXME: Need to fix the logic to work when we turn off all planes
5262          * but leave the pipe running.
5263          */
5264         if (IS_GEN2(dev_priv))
5265                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5266
5267         /* Underruns don't always raise interrupts, so check manually. */
5268         intel_check_cpu_fifo_underruns(dev_priv);
5269         intel_check_pch_fifo_underruns(dev_priv);
5270 }
5271
5272 /* FIXME get rid of this and use pre_plane_update */
5273 static void
5274 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5275 {
5276         struct drm_device *dev = crtc->dev;
5277         struct drm_i915_private *dev_priv = to_i915(dev);
5278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5279         int pipe = intel_crtc->pipe;
5280
5281         /*
5282          * Gen2 reports pipe underruns whenever all planes are disabled.
5283          * So disable underrun reporting before all the planes get disabled.
5284          */
5285         if (IS_GEN2(dev_priv))
5286                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5287
5288         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5289
5290         /*
5291          * Vblank time updates from the shadow to live plane control register
5292          * are blocked if the memory self-refresh mode is active at that
5293          * moment. So to make sure the plane gets truly disabled, disable
5294          * first the self-refresh mode. The self-refresh enable bit in turn
5295          * will be checked/applied by the HW only at the next frame start
5296          * event which is after the vblank start event, so we need to have a
5297          * wait-for-vblank between disabling the plane and the pipe.
5298          */
5299         if (HAS_GMCH_DISPLAY(dev_priv) &&
5300             intel_set_memory_cxsr(dev_priv, false))
5301                 intel_wait_for_vblank(dev_priv, pipe);
5302 }
5303
5304 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5305                                        const struct intel_crtc_state *new_crtc_state)
5306 {
5307         if (!old_crtc_state->ips_enabled)
5308                 return false;
5309
5310         if (needs_modeset(&new_crtc_state->base))
5311                 return true;
5312
5313         return !new_crtc_state->ips_enabled;
5314 }
5315
5316 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5317                                        const struct intel_crtc_state *new_crtc_state)
5318 {
5319         if (!new_crtc_state->ips_enabled)
5320                 return false;
5321
5322         if (needs_modeset(&new_crtc_state->base))
5323                 return true;
5324
5325         /*
5326          * We can't read out IPS on broadwell, assume the worst and
5327          * forcibly enable IPS on the first fastset.
5328          */
5329         if (new_crtc_state->update_pipe &&
5330             old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5331                 return true;
5332
5333         return !old_crtc_state->ips_enabled;
5334 }
5335
5336 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5337                           const struct intel_crtc_state *crtc_state)
5338 {
5339         if (!crtc_state->nv12_planes)
5340                 return false;
5341
5342         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
5343                 return false;
5344
5345         if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5346             IS_CANNONLAKE(dev_priv))
5347                 return true;
5348
5349         return false;
5350 }
5351
5352 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5353 {
5354         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5355         struct drm_device *dev = crtc->base.dev;
5356         struct drm_i915_private *dev_priv = to_i915(dev);
5357         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5358         struct intel_crtc_state *pipe_config =
5359                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5360                                                 crtc);
5361         struct drm_plane *primary = crtc->base.primary;
5362         struct drm_plane_state *old_primary_state =
5363                 drm_atomic_get_old_plane_state(old_state, primary);
5364
5365         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5366
5367         if (pipe_config->update_wm_post && pipe_config->base.active)
5368                 intel_update_watermarks(crtc);
5369
5370         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5371                 hsw_enable_ips(pipe_config);
5372
5373         if (old_primary_state) {
5374                 struct drm_plane_state *new_primary_state =
5375                         drm_atomic_get_new_plane_state(old_state, primary);
5376
5377                 intel_fbc_post_update(crtc);
5378
5379                 if (new_primary_state->visible &&
5380                     (needs_modeset(&pipe_config->base) ||
5381                      !old_primary_state->visible))
5382                         intel_post_enable_primary(&crtc->base, pipe_config);
5383         }
5384
5385         /* Display WA 827 */
5386         if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5387             !needs_nv12_wa(dev_priv, pipe_config)) {
5388                 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5389                 skl_wa_528(dev_priv, crtc->pipe, false);
5390         }
5391 }
5392
5393 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5394                                    struct intel_crtc_state *pipe_config)
5395 {
5396         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5397         struct drm_device *dev = crtc->base.dev;
5398         struct drm_i915_private *dev_priv = to_i915(dev);
5399         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5400         struct drm_plane *primary = crtc->base.primary;
5401         struct drm_plane_state *old_primary_state =
5402                 drm_atomic_get_old_plane_state(old_state, primary);
5403         bool modeset = needs_modeset(&pipe_config->base);
5404         struct intel_atomic_state *old_intel_state =
5405                 to_intel_atomic_state(old_state);
5406
5407         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5408                 hsw_disable_ips(old_crtc_state);
5409
5410         if (old_primary_state) {
5411                 struct intel_plane_state *new_primary_state =
5412                         intel_atomic_get_new_plane_state(old_intel_state,
5413                                                          to_intel_plane(primary));
5414
5415                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5416                 /*
5417                  * Gen2 reports pipe underruns whenever all planes are disabled.
5418                  * So disable underrun reporting before all the planes get disabled.
5419                  */
5420                 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5421                     (modeset || !new_primary_state->base.visible))
5422                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5423         }
5424
5425         /* Display WA 827 */
5426         if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5427             needs_nv12_wa(dev_priv, pipe_config)) {
5428                 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5429                 skl_wa_528(dev_priv, crtc->pipe, true);
5430         }
5431
5432         /*
5433          * Vblank time updates from the shadow to live plane control register
5434          * are blocked if the memory self-refresh mode is active at that
5435          * moment. So to make sure the plane gets truly disabled, disable
5436          * first the self-refresh mode. The self-refresh enable bit in turn
5437          * will be checked/applied by the HW only at the next frame start
5438          * event which is after the vblank start event, so we need to have a
5439          * wait-for-vblank between disabling the plane and the pipe.
5440          */
5441         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5442             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5443                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5444
5445         /*
5446          * IVB workaround: must disable low power watermarks for at least
5447          * one frame before enabling scaling.  LP watermarks can be re-enabled
5448          * when scaling is disabled.
5449          *
5450          * WaCxSRDisabledForSpriteScaling:ivb
5451          */
5452         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5453                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5454
5455         /*
5456          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5457          * watermark programming here.
5458          */
5459         if (needs_modeset(&pipe_config->base))
5460                 return;
5461
5462         /*
5463          * For platforms that support atomic watermarks, program the
5464          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5465          * will be the intermediate values that are safe for both pre- and
5466          * post- vblank; when vblank happens, the 'active' values will be set
5467          * to the final 'target' values and we'll do this again to get the
5468          * optimal watermarks.  For gen9+ platforms, the values we program here
5469          * will be the final target values which will get automatically latched
5470          * at vblank time; no further programming will be necessary.
5471          *
5472          * If a platform hasn't been transitioned to atomic watermarks yet,
5473          * we'll continue to update watermarks the old way, if flags tell
5474          * us to.
5475          */
5476         if (dev_priv->display.initial_watermarks != NULL)
5477                 dev_priv->display.initial_watermarks(old_intel_state,
5478                                                      pipe_config);
5479         else if (pipe_config->update_wm_pre)
5480                 intel_update_watermarks(crtc);
5481 }
5482
5483 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5484 {
5485         struct drm_device *dev = crtc->dev;
5486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5487         struct drm_plane *p;
5488         int pipe = intel_crtc->pipe;
5489
5490         intel_crtc_dpms_overlay_disable(intel_crtc);
5491
5492         drm_for_each_plane_mask(p, dev, plane_mask)
5493                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5494
5495         /*
5496          * FIXME: Once we grow proper nuclear flip support out of this we need
5497          * to compute the mask of flip planes precisely. For the time being
5498          * consider this a flip to a NULL plane.
5499          */
5500         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5501 }
5502
5503 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5504                                           struct intel_crtc_state *crtc_state,
5505                                           struct drm_atomic_state *old_state)
5506 {
5507         struct drm_connector_state *conn_state;
5508         struct drm_connector *conn;
5509         int i;
5510
5511         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5512                 struct intel_encoder *encoder =
5513                         to_intel_encoder(conn_state->best_encoder);
5514
5515                 if (conn_state->crtc != crtc)
5516                         continue;
5517
5518                 if (encoder->pre_pll_enable)
5519                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5520         }
5521 }
5522
5523 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5524                                       struct intel_crtc_state *crtc_state,
5525                                       struct drm_atomic_state *old_state)
5526 {
5527         struct drm_connector_state *conn_state;
5528         struct drm_connector *conn;
5529         int i;
5530
5531         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5532                 struct intel_encoder *encoder =
5533                         to_intel_encoder(conn_state->best_encoder);
5534
5535                 if (conn_state->crtc != crtc)
5536                         continue;
5537
5538                 if (encoder->pre_enable)
5539                         encoder->pre_enable(encoder, crtc_state, conn_state);
5540         }
5541 }
5542
5543 static void intel_encoders_enable(struct drm_crtc *crtc,
5544                                   struct intel_crtc_state *crtc_state,
5545                                   struct drm_atomic_state *old_state)
5546 {
5547         struct drm_connector_state *conn_state;
5548         struct drm_connector *conn;
5549         int i;
5550
5551         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5552                 struct intel_encoder *encoder =
5553                         to_intel_encoder(conn_state->best_encoder);
5554
5555                 if (conn_state->crtc != crtc)
5556                         continue;
5557
5558                 encoder->enable(encoder, crtc_state, conn_state);
5559                 intel_opregion_notify_encoder(encoder, true);
5560         }
5561 }
5562
5563 static void intel_encoders_disable(struct drm_crtc *crtc,
5564                                    struct intel_crtc_state *old_crtc_state,
5565                                    struct drm_atomic_state *old_state)
5566 {
5567         struct drm_connector_state *old_conn_state;
5568         struct drm_connector *conn;
5569         int i;
5570
5571         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5572                 struct intel_encoder *encoder =
5573                         to_intel_encoder(old_conn_state->best_encoder);
5574
5575                 if (old_conn_state->crtc != crtc)
5576                         continue;
5577
5578                 intel_opregion_notify_encoder(encoder, false);
5579                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5580         }
5581 }
5582
5583 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5584                                         struct intel_crtc_state *old_crtc_state,
5585                                         struct drm_atomic_state *old_state)
5586 {
5587         struct drm_connector_state *old_conn_state;
5588         struct drm_connector *conn;
5589         int i;
5590
5591         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5592                 struct intel_encoder *encoder =
5593                         to_intel_encoder(old_conn_state->best_encoder);
5594
5595                 if (old_conn_state->crtc != crtc)
5596                         continue;
5597
5598                 if (encoder->post_disable)
5599                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5600         }
5601 }
5602
5603 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5604                                             struct intel_crtc_state *old_crtc_state,
5605                                             struct drm_atomic_state *old_state)
5606 {
5607         struct drm_connector_state *old_conn_state;
5608         struct drm_connector *conn;
5609         int i;
5610
5611         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5612                 struct intel_encoder *encoder =
5613                         to_intel_encoder(old_conn_state->best_encoder);
5614
5615                 if (old_conn_state->crtc != crtc)
5616                         continue;
5617
5618                 if (encoder->post_pll_disable)
5619                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5620         }
5621 }
5622
5623 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5624                                  struct drm_atomic_state *old_state)
5625 {
5626         struct drm_crtc *crtc = pipe_config->base.crtc;
5627         struct drm_device *dev = crtc->dev;
5628         struct drm_i915_private *dev_priv = to_i915(dev);
5629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5630         int pipe = intel_crtc->pipe;
5631         struct intel_atomic_state *old_intel_state =
5632                 to_intel_atomic_state(old_state);
5633
5634         if (WARN_ON(intel_crtc->active))
5635                 return;
5636
5637         /*
5638          * Sometimes spurious CPU pipe underruns happen during FDI
5639          * training, at least with VGA+HDMI cloning. Suppress them.
5640          *
5641          * On ILK we get an occasional spurious CPU pipe underruns
5642          * between eDP port A enable and vdd enable. Also PCH port
5643          * enable seems to result in the occasional CPU pipe underrun.
5644          *
5645          * Spurious PCH underruns also occur during PCH enabling.
5646          */
5647         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5648         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5649
5650         if (intel_crtc->config->has_pch_encoder)
5651                 intel_prepare_shared_dpll(intel_crtc);
5652
5653         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5654                 intel_dp_set_m_n(intel_crtc, M1_N1);
5655
5656         intel_set_pipe_timings(intel_crtc);
5657         intel_set_pipe_src_size(intel_crtc);
5658
5659         if (intel_crtc->config->has_pch_encoder) {
5660                 intel_cpu_transcoder_set_m_n(intel_crtc,
5661                                      &intel_crtc->config->fdi_m_n, NULL);
5662         }
5663
5664         ironlake_set_pipeconf(crtc);
5665
5666         intel_crtc->active = true;
5667
5668         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5669
5670         if (intel_crtc->config->has_pch_encoder) {
5671                 /* Note: FDI PLL enabling _must_ be done before we enable the
5672                  * cpu pipes, hence this is separate from all the other fdi/pch
5673                  * enabling. */
5674                 ironlake_fdi_pll_enable(intel_crtc);
5675         } else {
5676                 assert_fdi_tx_disabled(dev_priv, pipe);
5677                 assert_fdi_rx_disabled(dev_priv, pipe);
5678         }
5679
5680         ironlake_pfit_enable(intel_crtc);
5681
5682         /*
5683          * On ILK+ LUT must be loaded before the pipe is running but with
5684          * clocks enabled
5685          */
5686         intel_color_load_luts(&pipe_config->base);
5687
5688         if (dev_priv->display.initial_watermarks != NULL)
5689                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5690         intel_enable_pipe(pipe_config);
5691
5692         if (intel_crtc->config->has_pch_encoder)
5693                 ironlake_pch_enable(old_intel_state, pipe_config);
5694
5695         assert_vblank_disabled(crtc);
5696         drm_crtc_vblank_on(crtc);
5697
5698         intel_encoders_enable(crtc, pipe_config, old_state);
5699
5700         if (HAS_PCH_CPT(dev_priv))
5701                 cpt_verify_modeset(dev, intel_crtc->pipe);
5702
5703         /*
5704          * Must wait for vblank to avoid spurious PCH FIFO underruns.
5705          * And a second vblank wait is needed at least on ILK with
5706          * some interlaced HDMI modes. Let's do the double wait always
5707          * in case there are more corner cases we don't know about.
5708          */
5709         if (intel_crtc->config->has_pch_encoder) {
5710                 intel_wait_for_vblank(dev_priv, pipe);
5711                 intel_wait_for_vblank(dev_priv, pipe);
5712         }
5713         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5714         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5715 }
5716
5717 /* IPS only exists on ULT machines and is tied to pipe A. */
5718 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5719 {
5720         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5721 }
5722
5723 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5724                                             enum pipe pipe, bool apply)
5725 {
5726         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5727         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5728
5729         if (apply)
5730                 val |= mask;
5731         else
5732                 val &= ~mask;
5733
5734         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5735 }
5736
5737 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5738 {
5739         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5740         enum pipe pipe = crtc->pipe;
5741         uint32_t val;
5742
5743         val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5744
5745         /* Program B credit equally to all pipes */
5746         val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5747
5748         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5749 }
5750
5751 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5752                                 struct drm_atomic_state *old_state)
5753 {
5754         struct drm_crtc *crtc = pipe_config->base.crtc;
5755         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5757         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5758         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5759         struct intel_atomic_state *old_intel_state =
5760                 to_intel_atomic_state(old_state);
5761         bool psl_clkgate_wa;
5762         u32 pipe_chicken;
5763
5764         if (WARN_ON(intel_crtc->active))
5765                 return;
5766
5767         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5768
5769         if (intel_crtc->config->shared_dpll)
5770                 intel_enable_shared_dpll(intel_crtc);
5771
5772         if (INTEL_GEN(dev_priv) >= 11)
5773                 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5774
5775         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5776
5777         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5778                 intel_dp_set_m_n(intel_crtc, M1_N1);
5779
5780         if (!transcoder_is_dsi(cpu_transcoder))
5781                 intel_set_pipe_timings(intel_crtc);
5782
5783         intel_set_pipe_src_size(intel_crtc);
5784
5785         if (cpu_transcoder != TRANSCODER_EDP &&
5786             !transcoder_is_dsi(cpu_transcoder)) {
5787                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5788                            intel_crtc->config->pixel_multiplier - 1);
5789         }
5790
5791         if (intel_crtc->config->has_pch_encoder) {
5792                 intel_cpu_transcoder_set_m_n(intel_crtc,
5793                                      &intel_crtc->config->fdi_m_n, NULL);
5794         }
5795
5796         if (!transcoder_is_dsi(cpu_transcoder))
5797                 haswell_set_pipeconf(crtc);
5798
5799         haswell_set_pipemisc(crtc);
5800
5801         intel_color_set_csc(&pipe_config->base);
5802
5803         intel_crtc->active = true;
5804
5805         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5806         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5807                          intel_crtc->config->pch_pfit.enabled;
5808         if (psl_clkgate_wa)
5809                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5810
5811         if (INTEL_GEN(dev_priv) >= 9)
5812                 skylake_pfit_enable(intel_crtc);
5813         else
5814                 ironlake_pfit_enable(intel_crtc);
5815
5816         /*
5817          * On ILK+ LUT must be loaded before the pipe is running but with
5818          * clocks enabled
5819          */
5820         intel_color_load_luts(&pipe_config->base);
5821
5822         /*
5823          * Display WA #1153: enable hardware to bypass the alpha math
5824          * and rounding for per-pixel values 00 and 0xff
5825          */
5826         if (INTEL_GEN(dev_priv) >= 11) {
5827                 pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
5828                 if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
5829                         I915_WRITE_FW(PIPE_CHICKEN(pipe),
5830                                       pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
5831         }
5832
5833         intel_ddi_set_pipe_settings(pipe_config);
5834         if (!transcoder_is_dsi(cpu_transcoder))
5835                 intel_ddi_enable_transcoder_func(pipe_config);
5836
5837         if (dev_priv->display.initial_watermarks != NULL)
5838                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5839
5840         if (INTEL_GEN(dev_priv) >= 11)
5841                 icl_pipe_mbus_enable(intel_crtc);
5842
5843         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5844         if (!transcoder_is_dsi(cpu_transcoder))
5845                 intel_enable_pipe(pipe_config);
5846
5847         if (intel_crtc->config->has_pch_encoder)
5848                 lpt_pch_enable(old_intel_state, pipe_config);
5849
5850         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5851                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5852
5853         assert_vblank_disabled(crtc);
5854         drm_crtc_vblank_on(crtc);
5855
5856         intel_encoders_enable(crtc, pipe_config, old_state);
5857
5858         if (psl_clkgate_wa) {
5859                 intel_wait_for_vblank(dev_priv, pipe);
5860                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5861         }
5862
5863         /* If we change the relative order between pipe/planes enabling, we need
5864          * to change the workaround. */
5865         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5866         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5867                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5868                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5869         }
5870 }
5871
5872 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5873 {
5874         struct drm_device *dev = crtc->base.dev;
5875         struct drm_i915_private *dev_priv = to_i915(dev);
5876         int pipe = crtc->pipe;
5877
5878         /* To avoid upsetting the power well on haswell only disable the pfit if
5879          * it's in use. The hw state code will make sure we get this right. */
5880         if (force || crtc->config->pch_pfit.enabled) {
5881                 I915_WRITE(PF_CTL(pipe), 0);
5882                 I915_WRITE(PF_WIN_POS(pipe), 0);
5883                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5884         }
5885 }
5886
5887 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5888                                   struct drm_atomic_state *old_state)
5889 {
5890         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5891         struct drm_device *dev = crtc->dev;
5892         struct drm_i915_private *dev_priv = to_i915(dev);
5893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5894         int pipe = intel_crtc->pipe;
5895
5896         /*
5897          * Sometimes spurious CPU pipe underruns happen when the
5898          * pipe is already disabled, but FDI RX/TX is still enabled.
5899          * Happens at least with VGA+HDMI cloning. Suppress them.
5900          */
5901         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5902         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5903
5904         intel_encoders_disable(crtc, old_crtc_state, old_state);
5905
5906         drm_crtc_vblank_off(crtc);
5907         assert_vblank_disabled(crtc);
5908
5909         intel_disable_pipe(old_crtc_state);
5910
5911         ironlake_pfit_disable(intel_crtc, false);
5912
5913         if (intel_crtc->config->has_pch_encoder)
5914                 ironlake_fdi_disable(crtc);
5915
5916         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5917
5918         if (intel_crtc->config->has_pch_encoder) {
5919                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5920
5921                 if (HAS_PCH_CPT(dev_priv)) {
5922                         i915_reg_t reg;
5923                         u32 temp;
5924
5925                         /* disable TRANS_DP_CTL */
5926                         reg = TRANS_DP_CTL(pipe);
5927                         temp = I915_READ(reg);
5928                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5929                                   TRANS_DP_PORT_SEL_MASK);
5930                         temp |= TRANS_DP_PORT_SEL_NONE;
5931                         I915_WRITE(reg, temp);
5932
5933                         /* disable DPLL_SEL */
5934                         temp = I915_READ(PCH_DPLL_SEL);
5935                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5936                         I915_WRITE(PCH_DPLL_SEL, temp);
5937                 }
5938
5939                 ironlake_fdi_pll_disable(intel_crtc);
5940         }
5941
5942         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5943         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5944 }
5945
5946 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5947                                  struct drm_atomic_state *old_state)
5948 {
5949         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5950         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
5953
5954         intel_encoders_disable(crtc, old_crtc_state, old_state);
5955
5956         drm_crtc_vblank_off(crtc);
5957         assert_vblank_disabled(crtc);
5958
5959         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5960         if (!transcoder_is_dsi(cpu_transcoder))
5961                 intel_disable_pipe(old_crtc_state);
5962
5963         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
5964                 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
5965
5966         if (!transcoder_is_dsi(cpu_transcoder))
5967                 intel_ddi_disable_transcoder_func(old_crtc_state);
5968
5969         if (INTEL_GEN(dev_priv) >= 9)
5970                 skylake_scaler_disable(intel_crtc);
5971         else
5972                 ironlake_pfit_disable(intel_crtc, false);
5973
5974         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5975
5976         if (INTEL_GEN(dev_priv) >= 11)
5977                 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5978 }
5979
5980 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5981 {
5982         struct drm_device *dev = crtc->base.dev;
5983         struct drm_i915_private *dev_priv = to_i915(dev);
5984         struct intel_crtc_state *pipe_config = crtc->config;
5985
5986         if (!pipe_config->gmch_pfit.control)
5987                 return;
5988
5989         /*
5990          * The panel fitter should only be adjusted whilst the pipe is disabled,
5991          * according to register description and PRM.
5992          */
5993         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5994         assert_pipe_disabled(dev_priv, crtc->pipe);
5995
5996         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5997         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5998
5999         /* Border color in case we don't scale up to the full screen. Black by
6000          * default, change to something else for debugging. */
6001         I915_WRITE(BCLRPAT(crtc->pipe), 0);
6002 }
6003
6004 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
6005 {
6006         if (port == PORT_NONE)
6007                 return false;
6008
6009         if (IS_ICELAKE(dev_priv))
6010                 return port <= PORT_B;
6011
6012         return false;
6013 }
6014
6015 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
6016 {
6017         if (IS_ICELAKE(dev_priv))
6018                 return port >= PORT_C && port <= PORT_F;
6019
6020         return false;
6021 }
6022
6023 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6024 {
6025         if (!intel_port_is_tc(dev_priv, port))
6026                 return PORT_TC_NONE;
6027
6028         return port - PORT_C;
6029 }
6030
6031 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6032 {
6033         switch (port) {
6034         case PORT_A:
6035                 return POWER_DOMAIN_PORT_DDI_A_LANES;
6036         case PORT_B:
6037                 return POWER_DOMAIN_PORT_DDI_B_LANES;
6038         case PORT_C:
6039                 return POWER_DOMAIN_PORT_DDI_C_LANES;
6040         case PORT_D:
6041                 return POWER_DOMAIN_PORT_DDI_D_LANES;
6042         case PORT_E:
6043                 return POWER_DOMAIN_PORT_DDI_E_LANES;
6044         case PORT_F:
6045                 return POWER_DOMAIN_PORT_DDI_F_LANES;
6046         default:
6047                 MISSING_CASE(port);
6048                 return POWER_DOMAIN_PORT_OTHER;
6049         }
6050 }
6051
6052 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
6053                                   struct intel_crtc_state *crtc_state)
6054 {
6055         struct drm_device *dev = crtc->dev;
6056         struct drm_i915_private *dev_priv = to_i915(dev);
6057         struct drm_encoder *encoder;
6058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059         enum pipe pipe = intel_crtc->pipe;
6060         u64 mask;
6061         enum transcoder transcoder = crtc_state->cpu_transcoder;
6062
6063         if (!crtc_state->base.active)
6064                 return 0;
6065
6066         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6067         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6068         if (crtc_state->pch_pfit.enabled ||
6069             crtc_state->pch_pfit.force_thru)
6070                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6071
6072         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
6073                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6074
6075                 mask |= BIT_ULL(intel_encoder->power_domain);
6076         }
6077
6078         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6079                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6080
6081         if (crtc_state->shared_dpll)
6082                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
6083
6084         return mask;
6085 }
6086
6087 static u64
6088 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
6089                                struct intel_crtc_state *crtc_state)
6090 {
6091         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6093         enum intel_display_power_domain domain;
6094         u64 domains, new_domains, old_domains;
6095
6096         old_domains = intel_crtc->enabled_power_domains;
6097         intel_crtc->enabled_power_domains = new_domains =
6098                 get_crtc_power_domains(crtc, crtc_state);
6099
6100         domains = new_domains & ~old_domains;
6101
6102         for_each_power_domain(domain, domains)
6103                 intel_display_power_get(dev_priv, domain);
6104
6105         return old_domains & ~new_domains;
6106 }
6107
6108 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6109                                       u64 domains)
6110 {
6111         enum intel_display_power_domain domain;
6112
6113         for_each_power_domain(domain, domains)
6114                 intel_display_power_put(dev_priv, domain);
6115 }
6116
6117 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6118                                    struct drm_atomic_state *old_state)
6119 {
6120         struct intel_atomic_state *old_intel_state =
6121                 to_intel_atomic_state(old_state);
6122         struct drm_crtc *crtc = pipe_config->base.crtc;
6123         struct drm_device *dev = crtc->dev;
6124         struct drm_i915_private *dev_priv = to_i915(dev);
6125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6126         int pipe = intel_crtc->pipe;
6127
6128         if (WARN_ON(intel_crtc->active))
6129                 return;
6130
6131         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6132                 intel_dp_set_m_n(intel_crtc, M1_N1);
6133
6134         intel_set_pipe_timings(intel_crtc);
6135         intel_set_pipe_src_size(intel_crtc);
6136
6137         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6138                 struct drm_i915_private *dev_priv = to_i915(dev);
6139
6140                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6141                 I915_WRITE(CHV_CANVAS(pipe), 0);
6142         }
6143
6144         i9xx_set_pipeconf(intel_crtc);
6145
6146         intel_color_set_csc(&pipe_config->base);
6147
6148         intel_crtc->active = true;
6149
6150         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6151
6152         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6153
6154         if (IS_CHERRYVIEW(dev_priv)) {
6155                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6156                 chv_enable_pll(intel_crtc, intel_crtc->config);
6157         } else {
6158                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6159                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6160         }
6161
6162         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6163
6164         i9xx_pfit_enable(intel_crtc);
6165
6166         intel_color_load_luts(&pipe_config->base);
6167
6168         dev_priv->display.initial_watermarks(old_intel_state,
6169                                              pipe_config);
6170         intel_enable_pipe(pipe_config);
6171
6172         assert_vblank_disabled(crtc);
6173         drm_crtc_vblank_on(crtc);
6174
6175         intel_encoders_enable(crtc, pipe_config, old_state);
6176 }
6177
6178 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6179 {
6180         struct drm_device *dev = crtc->base.dev;
6181         struct drm_i915_private *dev_priv = to_i915(dev);
6182
6183         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6184         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6185 }
6186
6187 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6188                              struct drm_atomic_state *old_state)
6189 {
6190         struct intel_atomic_state *old_intel_state =
6191                 to_intel_atomic_state(old_state);
6192         struct drm_crtc *crtc = pipe_config->base.crtc;
6193         struct drm_device *dev = crtc->dev;
6194         struct drm_i915_private *dev_priv = to_i915(dev);
6195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196         enum pipe pipe = intel_crtc->pipe;
6197
6198         if (WARN_ON(intel_crtc->active))
6199                 return;
6200
6201         i9xx_set_pll_dividers(intel_crtc);
6202
6203         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6204                 intel_dp_set_m_n(intel_crtc, M1_N1);
6205
6206         intel_set_pipe_timings(intel_crtc);
6207         intel_set_pipe_src_size(intel_crtc);
6208
6209         i9xx_set_pipeconf(intel_crtc);
6210
6211         intel_crtc->active = true;
6212
6213         if (!IS_GEN2(dev_priv))
6214                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6215
6216         intel_encoders_pre_enable(crtc, pipe_config, old_state);
6217
6218         i9xx_enable_pll(intel_crtc, pipe_config);
6219
6220         i9xx_pfit_enable(intel_crtc);
6221
6222         intel_color_load_luts(&pipe_config->base);
6223
6224         if (dev_priv->display.initial_watermarks != NULL)
6225                 dev_priv->display.initial_watermarks(old_intel_state,
6226                                                      intel_crtc->config);
6227         else
6228                 intel_update_watermarks(intel_crtc);
6229         intel_enable_pipe(pipe_config);
6230
6231         assert_vblank_disabled(crtc);
6232         drm_crtc_vblank_on(crtc);
6233
6234         intel_encoders_enable(crtc, pipe_config, old_state);
6235 }
6236
6237 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6238 {
6239         struct drm_device *dev = crtc->base.dev;
6240         struct drm_i915_private *dev_priv = to_i915(dev);
6241
6242         if (!crtc->config->gmch_pfit.control)
6243                 return;
6244
6245         assert_pipe_disabled(dev_priv, crtc->pipe);
6246
6247         DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6248                       I915_READ(PFIT_CONTROL));
6249         I915_WRITE(PFIT_CONTROL, 0);
6250 }
6251
6252 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6253                               struct drm_atomic_state *old_state)
6254 {
6255         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6256         struct drm_device *dev = crtc->dev;
6257         struct drm_i915_private *dev_priv = to_i915(dev);
6258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259         int pipe = intel_crtc->pipe;
6260
6261         /*
6262          * On gen2 planes are double buffered but the pipe isn't, so we must
6263          * wait for planes to fully turn off before disabling the pipe.
6264          */
6265         if (IS_GEN2(dev_priv))
6266                 intel_wait_for_vblank(dev_priv, pipe);
6267
6268         intel_encoders_disable(crtc, old_crtc_state, old_state);
6269
6270         drm_crtc_vblank_off(crtc);
6271         assert_vblank_disabled(crtc);
6272
6273         intel_disable_pipe(old_crtc_state);
6274
6275         i9xx_pfit_disable(intel_crtc);
6276
6277         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6278
6279         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6280                 if (IS_CHERRYVIEW(dev_priv))
6281                         chv_disable_pll(dev_priv, pipe);
6282                 else if (IS_VALLEYVIEW(dev_priv))
6283                         vlv_disable_pll(dev_priv, pipe);
6284                 else
6285                         i9xx_disable_pll(intel_crtc);
6286         }
6287
6288         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6289
6290         if (!IS_GEN2(dev_priv))
6291                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6292
6293         if (!dev_priv->display.initial_watermarks)
6294                 intel_update_watermarks(intel_crtc);
6295
6296         /* clock the pipe down to 640x480@60 to potentially save power */
6297         if (IS_I830(dev_priv))
6298                 i830_enable_pipe(dev_priv, pipe);
6299 }
6300
6301 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6302                                         struct drm_modeset_acquire_ctx *ctx)
6303 {
6304         struct intel_encoder *encoder;
6305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6307         enum intel_display_power_domain domain;
6308         struct intel_plane *plane;
6309         u64 domains;
6310         struct drm_atomic_state *state;
6311         struct intel_crtc_state *crtc_state;
6312         int ret;
6313
6314         if (!intel_crtc->active)
6315                 return;
6316
6317         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6318                 const struct intel_plane_state *plane_state =
6319                         to_intel_plane_state(plane->base.state);
6320
6321                 if (plane_state->base.visible)
6322                         intel_plane_disable_noatomic(intel_crtc, plane);
6323         }
6324
6325         state = drm_atomic_state_alloc(crtc->dev);
6326         if (!state) {
6327                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6328                               crtc->base.id, crtc->name);
6329                 return;
6330         }
6331
6332         state->acquire_ctx = ctx;
6333
6334         /* Everything's already locked, -EDEADLK can't happen. */
6335         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6336         ret = drm_atomic_add_affected_connectors(state, crtc);
6337
6338         WARN_ON(IS_ERR(crtc_state) || ret);
6339
6340         dev_priv->display.crtc_disable(crtc_state, state);
6341
6342         drm_atomic_state_put(state);
6343
6344         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6345                       crtc->base.id, crtc->name);
6346
6347         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6348         crtc->state->active = false;
6349         intel_crtc->active = false;
6350         crtc->enabled = false;
6351         crtc->state->connector_mask = 0;
6352         crtc->state->encoder_mask = 0;
6353
6354         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6355                 encoder->base.crtc = NULL;
6356
6357         intel_fbc_disable(intel_crtc);
6358         intel_update_watermarks(intel_crtc);
6359         intel_disable_shared_dpll(intel_crtc);
6360
6361         domains = intel_crtc->enabled_power_domains;
6362         for_each_power_domain(domain, domains)
6363                 intel_display_power_put(dev_priv, domain);
6364         intel_crtc->enabled_power_domains = 0;
6365
6366         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6367         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6368         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6369 }
6370
6371 /*
6372  * turn all crtc's off, but do not adjust state
6373  * This has to be paired with a call to intel_modeset_setup_hw_state.
6374  */
6375 int intel_display_suspend(struct drm_device *dev)
6376 {
6377         struct drm_i915_private *dev_priv = to_i915(dev);
6378         struct drm_atomic_state *state;
6379         int ret;
6380
6381         state = drm_atomic_helper_suspend(dev);
6382         ret = PTR_ERR_OR_ZERO(state);
6383         if (ret)
6384                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6385         else
6386                 dev_priv->modeset_restore_state = state;
6387         return ret;
6388 }
6389
6390 void intel_encoder_destroy(struct drm_encoder *encoder)
6391 {
6392         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6393
6394         drm_encoder_cleanup(encoder);
6395         kfree(intel_encoder);
6396 }
6397
6398 /* Cross check the actual hw state with our own modeset state tracking (and it's
6399  * internal consistency). */
6400 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6401                                          struct drm_connector_state *conn_state)
6402 {
6403         struct intel_connector *connector = to_intel_connector(conn_state->connector);
6404
6405         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6406                       connector->base.base.id,
6407                       connector->base.name);
6408
6409         if (connector->get_hw_state(connector)) {
6410                 struct intel_encoder *encoder = connector->encoder;
6411
6412                 I915_STATE_WARN(!crtc_state,
6413                          "connector enabled without attached crtc\n");
6414
6415                 if (!crtc_state)
6416                         return;
6417
6418                 I915_STATE_WARN(!crtc_state->active,
6419                       "connector is active, but attached crtc isn't\n");
6420
6421                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6422                         return;
6423
6424                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6425                         "atomic encoder doesn't match attached encoder\n");
6426
6427                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6428                         "attached encoder crtc differs from connector crtc\n");
6429         } else {
6430                 I915_STATE_WARN(crtc_state && crtc_state->active,
6431                         "attached crtc is active, but connector isn't\n");
6432                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6433                         "best encoder set without crtc!\n");
6434         }
6435 }
6436
6437 int intel_connector_init(struct intel_connector *connector)
6438 {
6439         struct intel_digital_connector_state *conn_state;
6440
6441         /*
6442          * Allocate enough memory to hold intel_digital_connector_state,
6443          * This might be a few bytes too many, but for connectors that don't
6444          * need it we'll free the state and allocate a smaller one on the first
6445          * succesful commit anyway.
6446          */
6447         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6448         if (!conn_state)
6449                 return -ENOMEM;
6450
6451         __drm_atomic_helper_connector_reset(&connector->base,
6452                                             &conn_state->base);
6453
6454         return 0;
6455 }
6456
6457 struct intel_connector *intel_connector_alloc(void)
6458 {
6459         struct intel_connector *connector;
6460
6461         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6462         if (!connector)
6463                 return NULL;
6464
6465         if (intel_connector_init(connector) < 0) {
6466                 kfree(connector);
6467                 return NULL;
6468         }
6469
6470         return connector;
6471 }
6472
6473 /*
6474  * Free the bits allocated by intel_connector_alloc.
6475  * This should only be used after intel_connector_alloc has returned
6476  * successfully, and before drm_connector_init returns successfully.
6477  * Otherwise the destroy callbacks for the connector and the state should
6478  * take care of proper cleanup/free
6479  */
6480 void intel_connector_free(struct intel_connector *connector)
6481 {
6482         kfree(to_intel_digital_connector_state(connector->base.state));
6483         kfree(connector);
6484 }
6485
6486 /* Simple connector->get_hw_state implementation for encoders that support only
6487  * one connector and no cloning and hence the encoder state determines the state
6488  * of the connector. */
6489 bool intel_connector_get_hw_state(struct intel_connector *connector)
6490 {
6491         enum pipe pipe = 0;
6492         struct intel_encoder *encoder = connector->encoder;
6493
6494         return encoder->get_hw_state(encoder, &pipe);
6495 }
6496
6497 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6498 {
6499         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6500                 return crtc_state->fdi_lanes;
6501
6502         return 0;
6503 }
6504
6505 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6506                                      struct intel_crtc_state *pipe_config)
6507 {
6508         struct drm_i915_private *dev_priv = to_i915(dev);
6509         struct drm_atomic_state *state = pipe_config->base.state;
6510         struct intel_crtc *other_crtc;
6511         struct intel_crtc_state *other_crtc_state;
6512
6513         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6514                       pipe_name(pipe), pipe_config->fdi_lanes);
6515         if (pipe_config->fdi_lanes > 4) {
6516                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6517                               pipe_name(pipe), pipe_config->fdi_lanes);
6518                 return -EINVAL;
6519         }
6520
6521         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6522                 if (pipe_config->fdi_lanes > 2) {
6523                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6524                                       pipe_config->fdi_lanes);
6525                         return -EINVAL;
6526                 } else {
6527                         return 0;
6528                 }
6529         }
6530
6531         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6532                 return 0;
6533
6534         /* Ivybridge 3 pipe is really complicated */
6535         switch (pipe) {
6536         case PIPE_A:
6537                 return 0;
6538         case PIPE_B:
6539                 if (pipe_config->fdi_lanes <= 2)
6540                         return 0;
6541
6542                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6543                 other_crtc_state =
6544                         intel_atomic_get_crtc_state(state, other_crtc);
6545                 if (IS_ERR(other_crtc_state))
6546                         return PTR_ERR(other_crtc_state);
6547
6548                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6549                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6550                                       pipe_name(pipe), pipe_config->fdi_lanes);
6551                         return -EINVAL;
6552                 }
6553                 return 0;
6554         case PIPE_C:
6555                 if (pipe_config->fdi_lanes > 2) {
6556                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6557                                       pipe_name(pipe), pipe_config->fdi_lanes);
6558                         return -EINVAL;
6559                 }
6560
6561                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6562                 other_crtc_state =
6563                         intel_atomic_get_crtc_state(state, other_crtc);
6564                 if (IS_ERR(other_crtc_state))
6565                         return PTR_ERR(other_crtc_state);
6566
6567                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6568                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6569                         return -EINVAL;
6570                 }
6571                 return 0;
6572         default:
6573                 BUG();
6574         }
6575 }
6576
6577 #define RETRY 1
6578 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6579                                        struct intel_crtc_state *pipe_config)
6580 {
6581         struct drm_device *dev = intel_crtc->base.dev;
6582         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6583         int lane, link_bw, fdi_dotclock, ret;
6584         bool needs_recompute = false;
6585
6586 retry:
6587         /* FDI is a binary signal running at ~2.7GHz, encoding
6588          * each output octet as 10 bits. The actual frequency
6589          * is stored as a divider into a 100MHz clock, and the
6590          * mode pixel clock is stored in units of 1KHz.
6591          * Hence the bw of each lane in terms of the mode signal
6592          * is:
6593          */
6594         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6595
6596         fdi_dotclock = adjusted_mode->crtc_clock;
6597
6598         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6599                                            pipe_config->pipe_bpp);
6600
6601         pipe_config->fdi_lanes = lane;
6602
6603         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6604                                link_bw, &pipe_config->fdi_m_n, false);
6605
6606         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6607         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6608                 pipe_config->pipe_bpp -= 2*3;
6609                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6610                               pipe_config->pipe_bpp);
6611                 needs_recompute = true;
6612                 pipe_config->bw_constrained = true;
6613
6614                 goto retry;
6615         }
6616
6617         if (needs_recompute)
6618                 return RETRY;
6619
6620         return ret;
6621 }
6622
6623 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6624 {
6625         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6626         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6627
6628         /* IPS only exists on ULT machines and is tied to pipe A. */
6629         if (!hsw_crtc_supports_ips(crtc))
6630                 return false;
6631
6632         if (!i915_modparams.enable_ips)
6633                 return false;
6634
6635         if (crtc_state->pipe_bpp > 24)
6636                 return false;
6637
6638         /*
6639          * We compare against max which means we must take
6640          * the increased cdclk requirement into account when
6641          * calculating the new cdclk.
6642          *
6643          * Should measure whether using a lower cdclk w/o IPS
6644          */
6645         if (IS_BROADWELL(dev_priv) &&
6646             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6647                 return false;
6648
6649         return true;
6650 }
6651
6652 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6653 {
6654         struct drm_i915_private *dev_priv =
6655                 to_i915(crtc_state->base.crtc->dev);
6656         struct intel_atomic_state *intel_state =
6657                 to_intel_atomic_state(crtc_state->base.state);
6658
6659         if (!hsw_crtc_state_ips_capable(crtc_state))
6660                 return false;
6661
6662         if (crtc_state->ips_force_disable)
6663                 return false;
6664
6665         /* IPS should be fine as long as at least one plane is enabled. */
6666         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6667                 return false;
6668
6669         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6670         if (IS_BROADWELL(dev_priv) &&
6671             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6672                 return false;
6673
6674         return true;
6675 }
6676
6677 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6678 {
6679         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6680
6681         /* GDG double wide on either pipe, otherwise pipe A only */
6682         return INTEL_GEN(dev_priv) < 4 &&
6683                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6684 }
6685
6686 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6687 {
6688         uint32_t pixel_rate;
6689
6690         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6691
6692         /*
6693          * We only use IF-ID interlacing. If we ever use
6694          * PF-ID we'll need to adjust the pixel_rate here.
6695          */
6696
6697         if (pipe_config->pch_pfit.enabled) {
6698                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6699                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6700
6701                 pipe_w = pipe_config->pipe_src_w;
6702                 pipe_h = pipe_config->pipe_src_h;
6703
6704                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6705                 pfit_h = pfit_size & 0xFFFF;
6706                 if (pipe_w < pfit_w)
6707                         pipe_w = pfit_w;
6708                 if (pipe_h < pfit_h)
6709                         pipe_h = pfit_h;
6710
6711                 if (WARN_ON(!pfit_w || !pfit_h))
6712                         return pixel_rate;
6713
6714                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6715                                      pfit_w * pfit_h);
6716         }
6717
6718         return pixel_rate;
6719 }
6720
6721 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6722 {
6723         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6724
6725         if (HAS_GMCH_DISPLAY(dev_priv))
6726                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6727                 crtc_state->pixel_rate =
6728                         crtc_state->base.adjusted_mode.crtc_clock;
6729         else
6730                 crtc_state->pixel_rate =
6731                         ilk_pipe_pixel_rate(crtc_state);
6732 }
6733
6734 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6735                                      struct intel_crtc_state *pipe_config)
6736 {
6737         struct drm_device *dev = crtc->base.dev;
6738         struct drm_i915_private *dev_priv = to_i915(dev);
6739         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6740         int clock_limit = dev_priv->max_dotclk_freq;
6741
6742         if (INTEL_GEN(dev_priv) < 4) {
6743                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6744
6745                 /*
6746                  * Enable double wide mode when the dot clock
6747                  * is > 90% of the (display) core speed.
6748                  */
6749                 if (intel_crtc_supports_double_wide(crtc) &&
6750                     adjusted_mode->crtc_clock > clock_limit) {
6751                         clock_limit = dev_priv->max_dotclk_freq;
6752                         pipe_config->double_wide = true;
6753                 }
6754         }
6755
6756         if (adjusted_mode->crtc_clock > clock_limit) {
6757                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6758                               adjusted_mode->crtc_clock, clock_limit,
6759                               yesno(pipe_config->double_wide));
6760                 return -EINVAL;
6761         }
6762
6763         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6764                 /*
6765                  * There is only one pipe CSC unit per pipe, and we need that
6766                  * for output conversion from RGB->YCBCR. So if CTM is already
6767                  * applied we can't support YCBCR420 output.
6768                  */
6769                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6770                 return -EINVAL;
6771         }
6772
6773         /*
6774          * Pipe horizontal size must be even in:
6775          * - DVO ganged mode
6776          * - LVDS dual channel mode
6777          * - Double wide pipe
6778          */
6779         if (pipe_config->pipe_src_w & 1) {
6780                 if (pipe_config->double_wide) {
6781                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6782                         return -EINVAL;
6783                 }
6784
6785                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6786                     intel_is_dual_link_lvds(dev)) {
6787                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6788                         return -EINVAL;
6789                 }
6790         }
6791
6792         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6793          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6794          */
6795         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6796                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6797                 return -EINVAL;
6798
6799         intel_crtc_compute_pixel_rate(pipe_config);
6800
6801         if (pipe_config->has_pch_encoder)
6802                 return ironlake_fdi_compute_config(crtc, pipe_config);
6803
6804         return 0;
6805 }
6806
6807 static void
6808 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6809 {
6810         while (*num > DATA_LINK_M_N_MASK ||
6811                *den > DATA_LINK_M_N_MASK) {
6812                 *num >>= 1;
6813                 *den >>= 1;
6814         }
6815 }
6816
6817 static void compute_m_n(unsigned int m, unsigned int n,
6818                         uint32_t *ret_m, uint32_t *ret_n,
6819                         bool constant_n)
6820 {
6821         /*
6822          * Several DP dongles in particular seem to be fussy about
6823          * too large link M/N values. Give N value as 0x8000 that
6824          * should be acceptable by specific devices. 0x8000 is the
6825          * specified fixed N value for asynchronous clock mode,
6826          * which the devices expect also in synchronous clock mode.
6827          */
6828         if (constant_n)
6829                 *ret_n = 0x8000;
6830         else
6831                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6832
6833         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6834         intel_reduce_m_n_ratio(ret_m, ret_n);
6835 }
6836
6837 void
6838 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6839                        int pixel_clock, int link_clock,
6840                        struct intel_link_m_n *m_n,
6841                        bool constant_n)
6842 {
6843         m_n->tu = 64;
6844
6845         compute_m_n(bits_per_pixel * pixel_clock,
6846                     link_clock * nlanes * 8,
6847                     &m_n->gmch_m, &m_n->gmch_n,
6848                     constant_n);
6849
6850         compute_m_n(pixel_clock, link_clock,
6851                     &m_n->link_m, &m_n->link_n,
6852                     constant_n);
6853 }
6854
6855 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6856 {
6857         if (i915_modparams.panel_use_ssc >= 0)
6858                 return i915_modparams.panel_use_ssc != 0;
6859         return dev_priv->vbt.lvds_use_ssc
6860                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6861 }
6862
6863 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6864 {
6865         return (1 << dpll->n) << 16 | dpll->m2;
6866 }
6867
6868 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6869 {
6870         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6871 }
6872
6873 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6874                                      struct intel_crtc_state *crtc_state,
6875                                      struct dpll *reduced_clock)
6876 {
6877         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6878         u32 fp, fp2 = 0;
6879
6880         if (IS_PINEVIEW(dev_priv)) {
6881                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6882                 if (reduced_clock)
6883                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6884         } else {
6885                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6886                 if (reduced_clock)
6887                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6888         }
6889
6890         crtc_state->dpll_hw_state.fp0 = fp;
6891
6892         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6893             reduced_clock) {
6894                 crtc_state->dpll_hw_state.fp1 = fp2;
6895         } else {
6896                 crtc_state->dpll_hw_state.fp1 = fp;
6897         }
6898 }
6899
6900 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6901                 pipe)
6902 {
6903         u32 reg_val;
6904
6905         /*
6906          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6907          * and set it to a reasonable value instead.
6908          */
6909         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6910         reg_val &= 0xffffff00;
6911         reg_val |= 0x00000030;
6912         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6913
6914         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6915         reg_val &= 0x00ffffff;
6916         reg_val |= 0x8c000000;
6917         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6918
6919         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6920         reg_val &= 0xffffff00;
6921         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6922
6923         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6924         reg_val &= 0x00ffffff;
6925         reg_val |= 0xb0000000;
6926         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6927 }
6928
6929 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6930                                          struct intel_link_m_n *m_n)
6931 {
6932         struct drm_device *dev = crtc->base.dev;
6933         struct drm_i915_private *dev_priv = to_i915(dev);
6934         int pipe = crtc->pipe;
6935
6936         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6937         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6938         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6939         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6940 }
6941
6942 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6943                                          struct intel_link_m_n *m_n,
6944                                          struct intel_link_m_n *m2_n2)
6945 {
6946         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6947         int pipe = crtc->pipe;
6948         enum transcoder transcoder = crtc->config->cpu_transcoder;
6949
6950         if (INTEL_GEN(dev_priv) >= 5) {
6951                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6952                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6953                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6954                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6955                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6956                  * for gen < 8) and if DRRS is supported (to make sure the
6957                  * registers are not unnecessarily accessed).
6958                  */
6959                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6960                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6961                         I915_WRITE(PIPE_DATA_M2(transcoder),
6962                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6963                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6964                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6965                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6966                 }
6967         } else {
6968                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6969                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6970                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6971                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6972         }
6973 }
6974
6975 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6976 {
6977         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6978
6979         if (m_n == M1_N1) {
6980                 dp_m_n = &crtc->config->dp_m_n;
6981                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6982         } else if (m_n == M2_N2) {
6983
6984                 /*
6985                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6986                  * needs to be programmed into M1_N1.
6987                  */
6988                 dp_m_n = &crtc->config->dp_m2_n2;
6989         } else {
6990                 DRM_ERROR("Unsupported divider value\n");
6991                 return;
6992         }
6993
6994         if (crtc->config->has_pch_encoder)
6995                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6996         else
6997                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6998 }
6999
7000 static void vlv_compute_dpll(struct intel_crtc *crtc,
7001                              struct intel_crtc_state *pipe_config)
7002 {
7003         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7004                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7005         if (crtc->pipe != PIPE_A)
7006                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7007
7008         /* DPLL not used with DSI, but still need the rest set up */
7009         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7010                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7011                         DPLL_EXT_BUFFER_ENABLE_VLV;
7012
7013         pipe_config->dpll_hw_state.dpll_md =
7014                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7015 }
7016
7017 static void chv_compute_dpll(struct intel_crtc *crtc,
7018                              struct intel_crtc_state *pipe_config)
7019 {
7020         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7021                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7022         if (crtc->pipe != PIPE_A)
7023                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7024
7025         /* DPLL not used with DSI, but still need the rest set up */
7026         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7027                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7028
7029         pipe_config->dpll_hw_state.dpll_md =
7030                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7031 }
7032
7033 static void vlv_prepare_pll(struct intel_crtc *crtc,
7034                             const struct intel_crtc_state *pipe_config)
7035 {
7036         struct drm_device *dev = crtc->base.dev;
7037         struct drm_i915_private *dev_priv = to_i915(dev);
7038         enum pipe pipe = crtc->pipe;
7039         u32 mdiv;
7040         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7041         u32 coreclk, reg_val;
7042
7043         /* Enable Refclk */
7044         I915_WRITE(DPLL(pipe),
7045                    pipe_config->dpll_hw_state.dpll &
7046                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7047
7048         /* No need to actually set up the DPLL with DSI */
7049         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7050                 return;
7051
7052         mutex_lock(&dev_priv->sb_lock);
7053
7054         bestn = pipe_config->dpll.n;
7055         bestm1 = pipe_config->dpll.m1;
7056         bestm2 = pipe_config->dpll.m2;
7057         bestp1 = pipe_config->dpll.p1;
7058         bestp2 = pipe_config->dpll.p2;
7059
7060         /* See eDP HDMI DPIO driver vbios notes doc */
7061
7062         /* PLL B needs special handling */
7063         if (pipe == PIPE_B)
7064                 vlv_pllb_recal_opamp(dev_priv, pipe);
7065
7066         /* Set up Tx target for periodic Rcomp update */
7067         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7068
7069         /* Disable target IRef on PLL */
7070         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7071         reg_val &= 0x00ffffff;
7072         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7073
7074         /* Disable fast lock */
7075         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7076
7077         /* Set idtafcrecal before PLL is enabled */
7078         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7079         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7080         mdiv |= ((bestn << DPIO_N_SHIFT));
7081         mdiv |= (1 << DPIO_K_SHIFT);
7082
7083         /*
7084          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7085          * but we don't support that).
7086          * Note: don't use the DAC post divider as it seems unstable.
7087          */
7088         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7089         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7090
7091         mdiv |= DPIO_ENABLE_CALIBRATION;
7092         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7093
7094         /* Set HBR and RBR LPF coefficients */
7095         if (pipe_config->port_clock == 162000 ||
7096             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7097             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7098                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7099                                  0x009f0003);
7100         else
7101                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7102                                  0x00d0000f);
7103
7104         if (intel_crtc_has_dp_encoder(pipe_config)) {
7105                 /* Use SSC source */
7106                 if (pipe == PIPE_A)
7107                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7108                                          0x0df40000);
7109                 else
7110                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7111                                          0x0df70000);
7112         } else { /* HDMI or VGA */
7113                 /* Use bend source */
7114                 if (pipe == PIPE_A)
7115                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7116                                          0x0df70000);
7117                 else
7118                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7119                                          0x0df40000);
7120         }
7121
7122         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7123         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7124         if (intel_crtc_has_dp_encoder(crtc->config))
7125                 coreclk |= 0x01000000;
7126         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7127
7128         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7129         mutex_unlock(&dev_priv->sb_lock);
7130 }
7131
7132 static void chv_prepare_pll(struct intel_crtc *crtc,
7133                             const struct intel_crtc_state *pipe_config)
7134 {
7135         struct drm_device *dev = crtc->base.dev;
7136         struct drm_i915_private *dev_priv = to_i915(dev);
7137         enum pipe pipe = crtc->pipe;
7138         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7139         u32 loopfilter, tribuf_calcntr;
7140         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7141         u32 dpio_val;
7142         int vco;
7143
7144         /* Enable Refclk and SSC */
7145         I915_WRITE(DPLL(pipe),
7146                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7147
7148         /* No need to actually set up the DPLL with DSI */
7149         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7150                 return;
7151
7152         bestn = pipe_config->dpll.n;
7153         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7154         bestm1 = pipe_config->dpll.m1;
7155         bestm2 = pipe_config->dpll.m2 >> 22;
7156         bestp1 = pipe_config->dpll.p1;
7157         bestp2 = pipe_config->dpll.p2;
7158         vco = pipe_config->dpll.vco;
7159         dpio_val = 0;
7160         loopfilter = 0;
7161
7162         mutex_lock(&dev_priv->sb_lock);
7163
7164         /* p1 and p2 divider */
7165         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7166                         5 << DPIO_CHV_S1_DIV_SHIFT |
7167                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7168                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7169                         1 << DPIO_CHV_K_DIV_SHIFT);
7170
7171         /* Feedback post-divider - m2 */
7172         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7173
7174         /* Feedback refclk divider - n and m1 */
7175         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7176                         DPIO_CHV_M1_DIV_BY_2 |
7177                         1 << DPIO_CHV_N_DIV_SHIFT);
7178
7179         /* M2 fraction division */
7180         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7181
7182         /* M2 fraction division enable */
7183         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7184         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7185         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7186         if (bestm2_frac)
7187                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7188         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7189
7190         /* Program digital lock detect threshold */
7191         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7192         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7193                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7194         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7195         if (!bestm2_frac)
7196                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7197         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7198
7199         /* Loop filter */
7200         if (vco == 5400000) {
7201                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7202                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7203                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7204                 tribuf_calcntr = 0x9;
7205         } else if (vco <= 6200000) {
7206                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7207                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7208                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7209                 tribuf_calcntr = 0x9;
7210         } else if (vco <= 6480000) {
7211                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7212                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7213                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7214                 tribuf_calcntr = 0x8;
7215         } else {
7216                 /* Not supported. Apply the same limits as in the max case */
7217                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7218                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7219                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7220                 tribuf_calcntr = 0;
7221         }
7222         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7223
7224         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7225         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7226         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7227         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7228
7229         /* AFC Recal */
7230         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7231                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7232                         DPIO_AFC_RECAL);
7233
7234         mutex_unlock(&dev_priv->sb_lock);
7235 }
7236
7237 /**
7238  * vlv_force_pll_on - forcibly enable just the PLL
7239  * @dev_priv: i915 private structure
7240  * @pipe: pipe PLL to enable
7241  * @dpll: PLL configuration
7242  *
7243  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7244  * in cases where we need the PLL enabled even when @pipe is not going to
7245  * be enabled.
7246  */
7247 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7248                      const struct dpll *dpll)
7249 {
7250         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7251         struct intel_crtc_state *pipe_config;
7252
7253         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7254         if (!pipe_config)
7255                 return -ENOMEM;
7256
7257         pipe_config->base.crtc = &crtc->base;
7258         pipe_config->pixel_multiplier = 1;
7259         pipe_config->dpll = *dpll;
7260
7261         if (IS_CHERRYVIEW(dev_priv)) {
7262                 chv_compute_dpll(crtc, pipe_config);
7263                 chv_prepare_pll(crtc, pipe_config);
7264                 chv_enable_pll(crtc, pipe_config);
7265         } else {
7266                 vlv_compute_dpll(crtc, pipe_config);
7267                 vlv_prepare_pll(crtc, pipe_config);
7268                 vlv_enable_pll(crtc, pipe_config);
7269         }
7270
7271         kfree(pipe_config);
7272
7273         return 0;
7274 }
7275
7276 /**
7277  * vlv_force_pll_off - forcibly disable just the PLL
7278  * @dev_priv: i915 private structure
7279  * @pipe: pipe PLL to disable
7280  *
7281  * Disable the PLL for @pipe. To be used in cases where we need
7282  * the PLL enabled even when @pipe is not going to be enabled.
7283  */
7284 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7285 {
7286         if (IS_CHERRYVIEW(dev_priv))
7287                 chv_disable_pll(dev_priv, pipe);
7288         else
7289                 vlv_disable_pll(dev_priv, pipe);
7290 }
7291
7292 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7293                               struct intel_crtc_state *crtc_state,
7294                               struct dpll *reduced_clock)
7295 {
7296         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7297         u32 dpll;
7298         struct dpll *clock = &crtc_state->dpll;
7299
7300         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7301
7302         dpll = DPLL_VGA_MODE_DIS;
7303
7304         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7305                 dpll |= DPLLB_MODE_LVDS;
7306         else
7307                 dpll |= DPLLB_MODE_DAC_SERIAL;
7308
7309         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7310             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7311                 dpll |= (crtc_state->pixel_multiplier - 1)
7312                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7313         }
7314
7315         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7316             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7317                 dpll |= DPLL_SDVO_HIGH_SPEED;
7318
7319         if (intel_crtc_has_dp_encoder(crtc_state))
7320                 dpll |= DPLL_SDVO_HIGH_SPEED;
7321
7322         /* compute bitmask from p1 value */
7323         if (IS_PINEVIEW(dev_priv))
7324                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7325         else {
7326                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7327                 if (IS_G4X(dev_priv) && reduced_clock)
7328                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7329         }
7330         switch (clock->p2) {
7331         case 5:
7332                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7333                 break;
7334         case 7:
7335                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7336                 break;
7337         case 10:
7338                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7339                 break;
7340         case 14:
7341                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7342                 break;
7343         }
7344         if (INTEL_GEN(dev_priv) >= 4)
7345                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7346
7347         if (crtc_state->sdvo_tv_clock)
7348                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7349         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7350                  intel_panel_use_ssc(dev_priv))
7351                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7352         else
7353                 dpll |= PLL_REF_INPUT_DREFCLK;
7354
7355         dpll |= DPLL_VCO_ENABLE;
7356         crtc_state->dpll_hw_state.dpll = dpll;
7357
7358         if (INTEL_GEN(dev_priv) >= 4) {
7359                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7360                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7361                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7362         }
7363 }
7364
7365 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7366                               struct intel_crtc_state *crtc_state,
7367                               struct dpll *reduced_clock)
7368 {
7369         struct drm_device *dev = crtc->base.dev;
7370         struct drm_i915_private *dev_priv = to_i915(dev);
7371         u32 dpll;
7372         struct dpll *clock = &crtc_state->dpll;
7373
7374         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7375
7376         dpll = DPLL_VGA_MODE_DIS;
7377
7378         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7379                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7380         } else {
7381                 if (clock->p1 == 2)
7382                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7383                 else
7384                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7385                 if (clock->p2 == 4)
7386                         dpll |= PLL_P2_DIVIDE_BY_4;
7387         }
7388
7389         if (!IS_I830(dev_priv) &&
7390             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7391                 dpll |= DPLL_DVO_2X_MODE;
7392
7393         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7394             intel_panel_use_ssc(dev_priv))
7395                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7396         else
7397                 dpll |= PLL_REF_INPUT_DREFCLK;
7398
7399         dpll |= DPLL_VCO_ENABLE;
7400         crtc_state->dpll_hw_state.dpll = dpll;
7401 }
7402
7403 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7404 {
7405         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7406         enum pipe pipe = intel_crtc->pipe;
7407         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7408         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7409         uint32_t crtc_vtotal, crtc_vblank_end;
7410         int vsyncshift = 0;
7411
7412         /* We need to be careful not to changed the adjusted mode, for otherwise
7413          * the hw state checker will get angry at the mismatch. */
7414         crtc_vtotal = adjusted_mode->crtc_vtotal;
7415         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7416
7417         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7418                 /* the chip adds 2 halflines automatically */
7419                 crtc_vtotal -= 1;
7420                 crtc_vblank_end -= 1;
7421
7422                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7423                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7424                 else
7425                         vsyncshift = adjusted_mode->crtc_hsync_start -
7426                                 adjusted_mode->crtc_htotal / 2;
7427                 if (vsyncshift < 0)
7428                         vsyncshift += adjusted_mode->crtc_htotal;
7429         }
7430
7431         if (INTEL_GEN(dev_priv) > 3)
7432                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7433
7434         I915_WRITE(HTOTAL(cpu_transcoder),
7435                    (adjusted_mode->crtc_hdisplay - 1) |
7436                    ((adjusted_mode->crtc_htotal - 1) << 16));
7437         I915_WRITE(HBLANK(cpu_transcoder),
7438                    (adjusted_mode->crtc_hblank_start - 1) |
7439                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7440         I915_WRITE(HSYNC(cpu_transcoder),
7441                    (adjusted_mode->crtc_hsync_start - 1) |
7442                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7443
7444         I915_WRITE(VTOTAL(cpu_transcoder),
7445                    (adjusted_mode->crtc_vdisplay - 1) |
7446                    ((crtc_vtotal - 1) << 16));
7447         I915_WRITE(VBLANK(cpu_transcoder),
7448                    (adjusted_mode->crtc_vblank_start - 1) |
7449                    ((crtc_vblank_end - 1) << 16));
7450         I915_WRITE(VSYNC(cpu_transcoder),
7451                    (adjusted_mode->crtc_vsync_start - 1) |
7452                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7453
7454         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7455          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7456          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7457          * bits. */
7458         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7459             (pipe == PIPE_B || pipe == PIPE_C))
7460                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7461
7462 }
7463
7464 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7465 {
7466         struct drm_device *dev = intel_crtc->base.dev;
7467         struct drm_i915_private *dev_priv = to_i915(dev);
7468         enum pipe pipe = intel_crtc->pipe;
7469
7470         /* pipesrc controls the size that is scaled from, which should
7471          * always be the user's requested size.
7472          */
7473         I915_WRITE(PIPESRC(pipe),
7474                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7475                    (intel_crtc->config->pipe_src_h - 1));
7476 }
7477
7478 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7479                                    struct intel_crtc_state *pipe_config)
7480 {
7481         struct drm_device *dev = crtc->base.dev;
7482         struct drm_i915_private *dev_priv = to_i915(dev);
7483         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7484         uint32_t tmp;
7485
7486         tmp = I915_READ(HTOTAL(cpu_transcoder));
7487         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7488         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7489         tmp = I915_READ(HBLANK(cpu_transcoder));
7490         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7491         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7492         tmp = I915_READ(HSYNC(cpu_transcoder));
7493         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7494         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7495
7496         tmp = I915_READ(VTOTAL(cpu_transcoder));
7497         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7498         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7499         tmp = I915_READ(VBLANK(cpu_transcoder));
7500         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7501         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7502         tmp = I915_READ(VSYNC(cpu_transcoder));
7503         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7504         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7505
7506         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7507                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7508                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7509                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7510         }
7511 }
7512
7513 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7514                                     struct intel_crtc_state *pipe_config)
7515 {
7516         struct drm_device *dev = crtc->base.dev;
7517         struct drm_i915_private *dev_priv = to_i915(dev);
7518         u32 tmp;
7519
7520         tmp = I915_READ(PIPESRC(crtc->pipe));
7521         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7522         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7523
7524         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7525         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7526 }
7527
7528 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7529                                  struct intel_crtc_state *pipe_config)
7530 {
7531         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7532         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7533         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7534         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7535
7536         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7537         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7538         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7539         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7540
7541         mode->flags = pipe_config->base.adjusted_mode.flags;
7542         mode->type = DRM_MODE_TYPE_DRIVER;
7543
7544         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7545
7546         mode->hsync = drm_mode_hsync(mode);
7547         mode->vrefresh = drm_mode_vrefresh(mode);
7548         drm_mode_set_name(mode);
7549 }
7550
7551 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7552 {
7553         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7554         uint32_t pipeconf;
7555
7556         pipeconf = 0;
7557
7558         /* we keep both pipes enabled on 830 */
7559         if (IS_I830(dev_priv))
7560                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7561
7562         if (intel_crtc->config->double_wide)
7563                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7564
7565         /* only g4x and later have fancy bpc/dither controls */
7566         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7567             IS_CHERRYVIEW(dev_priv)) {
7568                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7569                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7570                         pipeconf |= PIPECONF_DITHER_EN |
7571                                     PIPECONF_DITHER_TYPE_SP;
7572
7573                 switch (intel_crtc->config->pipe_bpp) {
7574                 case 18:
7575                         pipeconf |= PIPECONF_6BPC;
7576                         break;
7577                 case 24:
7578                         pipeconf |= PIPECONF_8BPC;
7579                         break;
7580                 case 30:
7581                         pipeconf |= PIPECONF_10BPC;
7582                         break;
7583                 default:
7584                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7585                         BUG();
7586                 }
7587         }
7588
7589         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7590                 if (INTEL_GEN(dev_priv) < 4 ||
7591                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7592                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7593                 else
7594                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7595         } else
7596                 pipeconf |= PIPECONF_PROGRESSIVE;
7597
7598         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7599              intel_crtc->config->limited_color_range)
7600                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7601
7602         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7603         POSTING_READ(PIPECONF(intel_crtc->pipe));
7604 }
7605
7606 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7607                                    struct intel_crtc_state *crtc_state)
7608 {
7609         struct drm_device *dev = crtc->base.dev;
7610         struct drm_i915_private *dev_priv = to_i915(dev);
7611         const struct intel_limit *limit;
7612         int refclk = 48000;
7613
7614         memset(&crtc_state->dpll_hw_state, 0,
7615                sizeof(crtc_state->dpll_hw_state));
7616
7617         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7618                 if (intel_panel_use_ssc(dev_priv)) {
7619                         refclk = dev_priv->vbt.lvds_ssc_freq;
7620                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7621                 }
7622
7623                 limit = &intel_limits_i8xx_lvds;
7624         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7625                 limit = &intel_limits_i8xx_dvo;
7626         } else {
7627                 limit = &intel_limits_i8xx_dac;
7628         }
7629
7630         if (!crtc_state->clock_set &&
7631             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7632                                  refclk, NULL, &crtc_state->dpll)) {
7633                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7634                 return -EINVAL;
7635         }
7636
7637         i8xx_compute_dpll(crtc, crtc_state, NULL);
7638
7639         return 0;
7640 }
7641
7642 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7643                                   struct intel_crtc_state *crtc_state)
7644 {
7645         struct drm_device *dev = crtc->base.dev;
7646         struct drm_i915_private *dev_priv = to_i915(dev);
7647         const struct intel_limit *limit;
7648         int refclk = 96000;
7649
7650         memset(&crtc_state->dpll_hw_state, 0,
7651                sizeof(crtc_state->dpll_hw_state));
7652
7653         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7654                 if (intel_panel_use_ssc(dev_priv)) {
7655                         refclk = dev_priv->vbt.lvds_ssc_freq;
7656                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7657                 }
7658
7659                 if (intel_is_dual_link_lvds(dev))
7660                         limit = &intel_limits_g4x_dual_channel_lvds;
7661                 else
7662                         limit = &intel_limits_g4x_single_channel_lvds;
7663         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7664                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7665                 limit = &intel_limits_g4x_hdmi;
7666         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7667                 limit = &intel_limits_g4x_sdvo;
7668         } else {
7669                 /* The option is for other outputs */
7670                 limit = &intel_limits_i9xx_sdvo;
7671         }
7672
7673         if (!crtc_state->clock_set &&
7674             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7675                                 refclk, NULL, &crtc_state->dpll)) {
7676                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7677                 return -EINVAL;
7678         }
7679
7680         i9xx_compute_dpll(crtc, crtc_state, NULL);
7681
7682         return 0;
7683 }
7684
7685 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7686                                   struct intel_crtc_state *crtc_state)
7687 {
7688         struct drm_device *dev = crtc->base.dev;
7689         struct drm_i915_private *dev_priv = to_i915(dev);
7690         const struct intel_limit *limit;
7691         int refclk = 96000;
7692
7693         memset(&crtc_state->dpll_hw_state, 0,
7694                sizeof(crtc_state->dpll_hw_state));
7695
7696         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7697                 if (intel_panel_use_ssc(dev_priv)) {
7698                         refclk = dev_priv->vbt.lvds_ssc_freq;
7699                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7700                 }
7701
7702                 limit = &intel_limits_pineview_lvds;
7703         } else {
7704                 limit = &intel_limits_pineview_sdvo;
7705         }
7706
7707         if (!crtc_state->clock_set &&
7708             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7709                                 refclk, NULL, &crtc_state->dpll)) {
7710                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7711                 return -EINVAL;
7712         }
7713
7714         i9xx_compute_dpll(crtc, crtc_state, NULL);
7715
7716         return 0;
7717 }
7718
7719 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7720                                    struct intel_crtc_state *crtc_state)
7721 {
7722         struct drm_device *dev = crtc->base.dev;
7723         struct drm_i915_private *dev_priv = to_i915(dev);
7724         const struct intel_limit *limit;
7725         int refclk = 96000;
7726
7727         memset(&crtc_state->dpll_hw_state, 0,
7728                sizeof(crtc_state->dpll_hw_state));
7729
7730         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7731                 if (intel_panel_use_ssc(dev_priv)) {
7732                         refclk = dev_priv->vbt.lvds_ssc_freq;
7733                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7734                 }
7735
7736                 limit = &intel_limits_i9xx_lvds;
7737         } else {
7738                 limit = &intel_limits_i9xx_sdvo;
7739         }
7740
7741         if (!crtc_state->clock_set &&
7742             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7743                                  refclk, NULL, &crtc_state->dpll)) {
7744                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7745                 return -EINVAL;
7746         }
7747
7748         i9xx_compute_dpll(crtc, crtc_state, NULL);
7749
7750         return 0;
7751 }
7752
7753 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7754                                   struct intel_crtc_state *crtc_state)
7755 {
7756         int refclk = 100000;
7757         const struct intel_limit *limit = &intel_limits_chv;
7758
7759         memset(&crtc_state->dpll_hw_state, 0,
7760                sizeof(crtc_state->dpll_hw_state));
7761
7762         if (!crtc_state->clock_set &&
7763             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7764                                 refclk, NULL, &crtc_state->dpll)) {
7765                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7766                 return -EINVAL;
7767         }
7768
7769         chv_compute_dpll(crtc, crtc_state);
7770
7771         return 0;
7772 }
7773
7774 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7775                                   struct intel_crtc_state *crtc_state)
7776 {
7777         int refclk = 100000;
7778         const struct intel_limit *limit = &intel_limits_vlv;
7779
7780         memset(&crtc_state->dpll_hw_state, 0,
7781                sizeof(crtc_state->dpll_hw_state));
7782
7783         if (!crtc_state->clock_set &&
7784             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7785                                 refclk, NULL, &crtc_state->dpll)) {
7786                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7787                 return -EINVAL;
7788         }
7789
7790         vlv_compute_dpll(crtc, crtc_state);
7791
7792         return 0;
7793 }
7794
7795 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7796                                  struct intel_crtc_state *pipe_config)
7797 {
7798         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7799         uint32_t tmp;
7800
7801         if (INTEL_GEN(dev_priv) <= 3 &&
7802             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7803                 return;
7804
7805         tmp = I915_READ(PFIT_CONTROL);
7806         if (!(tmp & PFIT_ENABLE))
7807                 return;
7808
7809         /* Check whether the pfit is attached to our pipe. */
7810         if (INTEL_GEN(dev_priv) < 4) {
7811                 if (crtc->pipe != PIPE_B)
7812                         return;
7813         } else {
7814                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7815                         return;
7816         }
7817
7818         pipe_config->gmch_pfit.control = tmp;
7819         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7820 }
7821
7822 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7823                                struct intel_crtc_state *pipe_config)
7824 {
7825         struct drm_device *dev = crtc->base.dev;
7826         struct drm_i915_private *dev_priv = to_i915(dev);
7827         int pipe = pipe_config->cpu_transcoder;
7828         struct dpll clock;
7829         u32 mdiv;
7830         int refclk = 100000;
7831
7832         /* In case of DSI, DPLL will not be used */
7833         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7834                 return;
7835
7836         mutex_lock(&dev_priv->sb_lock);
7837         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7838         mutex_unlock(&dev_priv->sb_lock);
7839
7840         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7841         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7842         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7843         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7844         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7845
7846         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7847 }
7848
7849 static void
7850 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7851                               struct intel_initial_plane_config *plane_config)
7852 {
7853         struct drm_device *dev = crtc->base.dev;
7854         struct drm_i915_private *dev_priv = to_i915(dev);
7855         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7856         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7857         enum pipe pipe;
7858         u32 val, base, offset;
7859         int fourcc, pixel_format;
7860         unsigned int aligned_height;
7861         struct drm_framebuffer *fb;
7862         struct intel_framebuffer *intel_fb;
7863
7864         if (!plane->get_hw_state(plane, &pipe))
7865                 return;
7866
7867         WARN_ON(pipe != crtc->pipe);
7868
7869         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7870         if (!intel_fb) {
7871                 DRM_DEBUG_KMS("failed to alloc fb\n");
7872                 return;
7873         }
7874
7875         fb = &intel_fb->base;
7876
7877         fb->dev = dev;
7878
7879         val = I915_READ(DSPCNTR(i9xx_plane));
7880
7881         if (INTEL_GEN(dev_priv) >= 4) {
7882                 if (val & DISPPLANE_TILED) {
7883                         plane_config->tiling = I915_TILING_X;
7884                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7885                 }
7886
7887                 if (val & DISPPLANE_ROTATE_180)
7888                         plane_config->rotation = DRM_MODE_ROTATE_180;
7889         }
7890
7891         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
7892             val & DISPPLANE_MIRROR)
7893                 plane_config->rotation |= DRM_MODE_REFLECT_X;
7894
7895         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7896         fourcc = i9xx_format_to_fourcc(pixel_format);
7897         fb->format = drm_format_info(fourcc);
7898
7899         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7900                 offset = I915_READ(DSPOFFSET(i9xx_plane));
7901                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7902         } else if (INTEL_GEN(dev_priv) >= 4) {
7903                 if (plane_config->tiling)
7904                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
7905                 else
7906                         offset = I915_READ(DSPLINOFF(i9xx_plane));
7907                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7908         } else {
7909                 base = I915_READ(DSPADDR(i9xx_plane));
7910         }
7911         plane_config->base = base;
7912
7913         val = I915_READ(PIPESRC(pipe));
7914         fb->width = ((val >> 16) & 0xfff) + 1;
7915         fb->height = ((val >> 0) & 0xfff) + 1;
7916
7917         val = I915_READ(DSPSTRIDE(i9xx_plane));
7918         fb->pitches[0] = val & 0xffffffc0;
7919
7920         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7921
7922         plane_config->size = fb->pitches[0] * aligned_height;
7923
7924         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7925                       crtc->base.name, plane->base.name, fb->width, fb->height,
7926                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7927                       plane_config->size);
7928
7929         plane_config->fb = intel_fb;
7930 }
7931
7932 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7933                                struct intel_crtc_state *pipe_config)
7934 {
7935         struct drm_device *dev = crtc->base.dev;
7936         struct drm_i915_private *dev_priv = to_i915(dev);
7937         int pipe = pipe_config->cpu_transcoder;
7938         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7939         struct dpll clock;
7940         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7941         int refclk = 100000;
7942
7943         /* In case of DSI, DPLL will not be used */
7944         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7945                 return;
7946
7947         mutex_lock(&dev_priv->sb_lock);
7948         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7949         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7950         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7951         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7952         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7953         mutex_unlock(&dev_priv->sb_lock);
7954
7955         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7956         clock.m2 = (pll_dw0 & 0xff) << 22;
7957         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7958                 clock.m2 |= pll_dw2 & 0x3fffff;
7959         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7960         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7961         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7962
7963         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7964 }
7965
7966 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7967                                  struct intel_crtc_state *pipe_config)
7968 {
7969         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7970         enum intel_display_power_domain power_domain;
7971         uint32_t tmp;
7972         bool ret;
7973
7974         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7975         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7976                 return false;
7977
7978         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7979         pipe_config->shared_dpll = NULL;
7980
7981         ret = false;
7982
7983         tmp = I915_READ(PIPECONF(crtc->pipe));
7984         if (!(tmp & PIPECONF_ENABLE))
7985                 goto out;
7986
7987         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7988             IS_CHERRYVIEW(dev_priv)) {
7989                 switch (tmp & PIPECONF_BPC_MASK) {
7990                 case PIPECONF_6BPC:
7991                         pipe_config->pipe_bpp = 18;
7992                         break;
7993                 case PIPECONF_8BPC:
7994                         pipe_config->pipe_bpp = 24;
7995                         break;
7996                 case PIPECONF_10BPC:
7997                         pipe_config->pipe_bpp = 30;
7998                         break;
7999                 default:
8000                         break;
8001                 }
8002         }
8003
8004         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8005             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8006                 pipe_config->limited_color_range = true;
8007
8008         if (INTEL_GEN(dev_priv) < 4)
8009                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8010
8011         intel_get_pipe_timings(crtc, pipe_config);
8012         intel_get_pipe_src_size(crtc, pipe_config);
8013
8014         i9xx_get_pfit_config(crtc, pipe_config);
8015
8016         if (INTEL_GEN(dev_priv) >= 4) {
8017                 /* No way to read it out on pipes B and C */
8018                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8019                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8020                 else
8021                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8022                 pipe_config->pixel_multiplier =
8023                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8024                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8025                 pipe_config->dpll_hw_state.dpll_md = tmp;
8026         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8027                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8028                 tmp = I915_READ(DPLL(crtc->pipe));
8029                 pipe_config->pixel_multiplier =
8030                         ((tmp & SDVO_MULTIPLIER_MASK)
8031                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8032         } else {
8033                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8034                  * port and will be fixed up in the encoder->get_config
8035                  * function. */
8036                 pipe_config->pixel_multiplier = 1;
8037         }
8038         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8039         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8040                 /*
8041                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8042                  * on 830. Filter it out here so that we don't
8043                  * report errors due to that.
8044                  */
8045                 if (IS_I830(dev_priv))
8046                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8047
8048                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8049                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8050         } else {
8051                 /* Mask out read-only status bits. */
8052                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8053                                                      DPLL_PORTC_READY_MASK |
8054                                                      DPLL_PORTB_READY_MASK);
8055         }
8056
8057         if (IS_CHERRYVIEW(dev_priv))
8058                 chv_crtc_clock_get(crtc, pipe_config);
8059         else if (IS_VALLEYVIEW(dev_priv))
8060                 vlv_crtc_clock_get(crtc, pipe_config);
8061         else
8062                 i9xx_crtc_clock_get(crtc, pipe_config);
8063
8064         /*
8065          * Normally the dotclock is filled in by the encoder .get_config()
8066          * but in case the pipe is enabled w/o any ports we need a sane
8067          * default.
8068          */
8069         pipe_config->base.adjusted_mode.crtc_clock =
8070                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8071
8072         ret = true;
8073
8074 out:
8075         intel_display_power_put(dev_priv, power_domain);
8076
8077         return ret;
8078 }
8079
8080 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8081 {
8082         struct intel_encoder *encoder;
8083         int i;
8084         u32 val, final;
8085         bool has_lvds = false;
8086         bool has_cpu_edp = false;
8087         bool has_panel = false;
8088         bool has_ck505 = false;
8089         bool can_ssc = false;
8090         bool using_ssc_source = false;
8091
8092         /* We need to take the global config into account */
8093         for_each_intel_encoder(&dev_priv->drm, encoder) {
8094                 switch (encoder->type) {
8095                 case INTEL_OUTPUT_LVDS:
8096                         has_panel = true;
8097                         has_lvds = true;
8098                         break;
8099                 case INTEL_OUTPUT_EDP:
8100                         has_panel = true;
8101                         if (encoder->port == PORT_A)
8102                                 has_cpu_edp = true;
8103                         break;
8104                 default:
8105                         break;
8106                 }
8107         }
8108
8109         if (HAS_PCH_IBX(dev_priv)) {
8110                 has_ck505 = dev_priv->vbt.display_clock_mode;
8111                 can_ssc = has_ck505;
8112         } else {
8113                 has_ck505 = false;
8114                 can_ssc = true;
8115         }
8116
8117         /* Check if any DPLLs are using the SSC source */
8118         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8119                 u32 temp = I915_READ(PCH_DPLL(i));
8120
8121                 if (!(temp & DPLL_VCO_ENABLE))
8122                         continue;
8123
8124                 if ((temp & PLL_REF_INPUT_MASK) ==
8125                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8126                         using_ssc_source = true;
8127                         break;
8128                 }
8129         }
8130
8131         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8132                       has_panel, has_lvds, has_ck505, using_ssc_source);
8133
8134         /* Ironlake: try to setup display ref clock before DPLL
8135          * enabling. This is only under driver's control after
8136          * PCH B stepping, previous chipset stepping should be
8137          * ignoring this setting.
8138          */
8139         val = I915_READ(PCH_DREF_CONTROL);
8140
8141         /* As we must carefully and slowly disable/enable each source in turn,
8142          * compute the final state we want first and check if we need to
8143          * make any changes at all.
8144          */
8145         final = val;
8146         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8147         if (has_ck505)
8148                 final |= DREF_NONSPREAD_CK505_ENABLE;
8149         else
8150                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8151
8152         final &= ~DREF_SSC_SOURCE_MASK;
8153         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8154         final &= ~DREF_SSC1_ENABLE;
8155
8156         if (has_panel) {
8157                 final |= DREF_SSC_SOURCE_ENABLE;
8158
8159                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8160                         final |= DREF_SSC1_ENABLE;
8161
8162                 if (has_cpu_edp) {
8163                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8164                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8165                         else
8166                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8167                 } else
8168                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8169         } else if (using_ssc_source) {
8170                 final |= DREF_SSC_SOURCE_ENABLE;
8171                 final |= DREF_SSC1_ENABLE;
8172         }
8173
8174         if (final == val)
8175                 return;
8176
8177         /* Always enable nonspread source */
8178         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8179
8180         if (has_ck505)
8181                 val |= DREF_NONSPREAD_CK505_ENABLE;
8182         else
8183                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8184
8185         if (has_panel) {
8186                 val &= ~DREF_SSC_SOURCE_MASK;
8187                 val |= DREF_SSC_SOURCE_ENABLE;
8188
8189                 /* SSC must be turned on before enabling the CPU output  */
8190                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8191                         DRM_DEBUG_KMS("Using SSC on panel\n");
8192                         val |= DREF_SSC1_ENABLE;
8193                 } else
8194                         val &= ~DREF_SSC1_ENABLE;
8195
8196                 /* Get SSC going before enabling the outputs */
8197                 I915_WRITE(PCH_DREF_CONTROL, val);
8198                 POSTING_READ(PCH_DREF_CONTROL);
8199                 udelay(200);
8200
8201                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8202
8203                 /* Enable CPU source on CPU attached eDP */
8204                 if (has_cpu_edp) {
8205                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8206                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8207                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8208                         } else
8209                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8210                 } else
8211                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8212
8213                 I915_WRITE(PCH_DREF_CONTROL, val);
8214                 POSTING_READ(PCH_DREF_CONTROL);
8215                 udelay(200);
8216         } else {
8217                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8218
8219                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8220
8221                 /* Turn off CPU output */
8222                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8223
8224                 I915_WRITE(PCH_DREF_CONTROL, val);
8225                 POSTING_READ(PCH_DREF_CONTROL);
8226                 udelay(200);
8227
8228                 if (!using_ssc_source) {
8229                         DRM_DEBUG_KMS("Disabling SSC source\n");
8230
8231                         /* Turn off the SSC source */
8232                         val &= ~DREF_SSC_SOURCE_MASK;
8233                         val |= DREF_SSC_SOURCE_DISABLE;
8234
8235                         /* Turn off SSC1 */
8236                         val &= ~DREF_SSC1_ENABLE;
8237
8238                         I915_WRITE(PCH_DREF_CONTROL, val);
8239                         POSTING_READ(PCH_DREF_CONTROL);
8240                         udelay(200);
8241                 }
8242         }
8243
8244         BUG_ON(val != final);
8245 }
8246
8247 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8248 {
8249         uint32_t tmp;
8250
8251         tmp = I915_READ(SOUTH_CHICKEN2);
8252         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8253         I915_WRITE(SOUTH_CHICKEN2, tmp);
8254
8255         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8256                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8257                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8258
8259         tmp = I915_READ(SOUTH_CHICKEN2);
8260         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8261         I915_WRITE(SOUTH_CHICKEN2, tmp);
8262
8263         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8264                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8265                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8266 }
8267
8268 /* WaMPhyProgramming:hsw */
8269 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8270 {
8271         uint32_t tmp;
8272
8273         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8274         tmp &= ~(0xFF << 24);
8275         tmp |= (0x12 << 24);
8276         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8277
8278         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8279         tmp |= (1 << 11);
8280         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8281
8282         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8283         tmp |= (1 << 11);
8284         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8285
8286         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8287         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8288         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8289
8290         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8291         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8292         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8293
8294         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8295         tmp &= ~(7 << 13);
8296         tmp |= (5 << 13);
8297         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8298
8299         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8300         tmp &= ~(7 << 13);
8301         tmp |= (5 << 13);
8302         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8303
8304         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8305         tmp &= ~0xFF;
8306         tmp |= 0x1C;
8307         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8308
8309         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8310         tmp &= ~0xFF;
8311         tmp |= 0x1C;
8312         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8313
8314         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8315         tmp &= ~(0xFF << 16);
8316         tmp |= (0x1C << 16);
8317         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8318
8319         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8320         tmp &= ~(0xFF << 16);
8321         tmp |= (0x1C << 16);
8322         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8323
8324         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8325         tmp |= (1 << 27);
8326         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8327
8328         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8329         tmp |= (1 << 27);
8330         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8331
8332         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8333         tmp &= ~(0xF << 28);
8334         tmp |= (4 << 28);
8335         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8336
8337         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8338         tmp &= ~(0xF << 28);
8339         tmp |= (4 << 28);
8340         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8341 }
8342
8343 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8344  * Programming" based on the parameters passed:
8345  * - Sequence to enable CLKOUT_DP
8346  * - Sequence to enable CLKOUT_DP without spread
8347  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8348  */
8349 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8350                                  bool with_spread, bool with_fdi)
8351 {
8352         uint32_t reg, tmp;
8353
8354         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8355                 with_spread = true;
8356         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8357             with_fdi, "LP PCH doesn't have FDI\n"))
8358                 with_fdi = false;
8359
8360         mutex_lock(&dev_priv->sb_lock);
8361
8362         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8363         tmp &= ~SBI_SSCCTL_DISABLE;
8364         tmp |= SBI_SSCCTL_PATHALT;
8365         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8366
8367         udelay(24);
8368
8369         if (with_spread) {
8370                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8371                 tmp &= ~SBI_SSCCTL_PATHALT;
8372                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8373
8374                 if (with_fdi) {
8375                         lpt_reset_fdi_mphy(dev_priv);
8376                         lpt_program_fdi_mphy(dev_priv);
8377                 }
8378         }
8379
8380         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8381         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8382         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8383         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8384
8385         mutex_unlock(&dev_priv->sb_lock);
8386 }
8387
8388 /* Sequence to disable CLKOUT_DP */
8389 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8390 {
8391         uint32_t reg, tmp;
8392
8393         mutex_lock(&dev_priv->sb_lock);
8394
8395         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8396         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8397         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8398         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8399
8400         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8401         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8402                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8403                         tmp |= SBI_SSCCTL_PATHALT;
8404                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8405                         udelay(32);
8406                 }
8407                 tmp |= SBI_SSCCTL_DISABLE;
8408                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8409         }
8410
8411         mutex_unlock(&dev_priv->sb_lock);
8412 }
8413
8414 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8415
8416 static const uint16_t sscdivintphase[] = {
8417         [BEND_IDX( 50)] = 0x3B23,
8418         [BEND_IDX( 45)] = 0x3B23,
8419         [BEND_IDX( 40)] = 0x3C23,
8420         [BEND_IDX( 35)] = 0x3C23,
8421         [BEND_IDX( 30)] = 0x3D23,
8422         [BEND_IDX( 25)] = 0x3D23,
8423         [BEND_IDX( 20)] = 0x3E23,
8424         [BEND_IDX( 15)] = 0x3E23,
8425         [BEND_IDX( 10)] = 0x3F23,
8426         [BEND_IDX(  5)] = 0x3F23,
8427         [BEND_IDX(  0)] = 0x0025,
8428         [BEND_IDX( -5)] = 0x0025,
8429         [BEND_IDX(-10)] = 0x0125,
8430         [BEND_IDX(-15)] = 0x0125,
8431         [BEND_IDX(-20)] = 0x0225,
8432         [BEND_IDX(-25)] = 0x0225,
8433         [BEND_IDX(-30)] = 0x0325,
8434         [BEND_IDX(-35)] = 0x0325,
8435         [BEND_IDX(-40)] = 0x0425,
8436         [BEND_IDX(-45)] = 0x0425,
8437         [BEND_IDX(-50)] = 0x0525,
8438 };
8439
8440 /*
8441  * Bend CLKOUT_DP
8442  * steps -50 to 50 inclusive, in steps of 5
8443  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8444  * change in clock period = -(steps / 10) * 5.787 ps
8445  */
8446 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8447 {
8448         uint32_t tmp;
8449         int idx = BEND_IDX(steps);
8450
8451         if (WARN_ON(steps % 5 != 0))
8452                 return;
8453
8454         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8455                 return;
8456
8457         mutex_lock(&dev_priv->sb_lock);
8458
8459         if (steps % 10 != 0)
8460                 tmp = 0xAAAAAAAB;
8461         else
8462                 tmp = 0x00000000;
8463         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8464
8465         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8466         tmp &= 0xffff0000;
8467         tmp |= sscdivintphase[idx];
8468         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8469
8470         mutex_unlock(&dev_priv->sb_lock);
8471 }
8472
8473 #undef BEND_IDX
8474
8475 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8476 {
8477         struct intel_encoder *encoder;
8478         bool has_vga = false;
8479
8480         for_each_intel_encoder(&dev_priv->drm, encoder) {
8481                 switch (encoder->type) {
8482                 case INTEL_OUTPUT_ANALOG:
8483                         has_vga = true;
8484                         break;
8485                 default:
8486                         break;
8487                 }
8488         }
8489
8490         if (has_vga) {
8491                 lpt_bend_clkout_dp(dev_priv, 0);
8492                 lpt_enable_clkout_dp(dev_priv, true, true);
8493         } else {
8494                 lpt_disable_clkout_dp(dev_priv);
8495         }
8496 }
8497
8498 /*
8499  * Initialize reference clocks when the driver loads
8500  */
8501 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8502 {
8503         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8504                 ironlake_init_pch_refclk(dev_priv);
8505         else if (HAS_PCH_LPT(dev_priv))
8506                 lpt_init_pch_refclk(dev_priv);
8507 }
8508
8509 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8510 {
8511         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8513         int pipe = intel_crtc->pipe;
8514         uint32_t val;
8515
8516         val = 0;
8517
8518         switch (intel_crtc->config->pipe_bpp) {
8519         case 18:
8520                 val |= PIPECONF_6BPC;
8521                 break;
8522         case 24:
8523                 val |= PIPECONF_8BPC;
8524                 break;
8525         case 30:
8526                 val |= PIPECONF_10BPC;
8527                 break;
8528         case 36:
8529                 val |= PIPECONF_12BPC;
8530                 break;
8531         default:
8532                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8533                 BUG();
8534         }
8535
8536         if (intel_crtc->config->dither)
8537                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8538
8539         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8540                 val |= PIPECONF_INTERLACED_ILK;
8541         else
8542                 val |= PIPECONF_PROGRESSIVE;
8543
8544         if (intel_crtc->config->limited_color_range)
8545                 val |= PIPECONF_COLOR_RANGE_SELECT;
8546
8547         I915_WRITE(PIPECONF(pipe), val);
8548         POSTING_READ(PIPECONF(pipe));
8549 }
8550
8551 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8552 {
8553         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8555         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8556         u32 val = 0;
8557
8558         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8559                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8560
8561         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8562                 val |= PIPECONF_INTERLACED_ILK;
8563         else
8564                 val |= PIPECONF_PROGRESSIVE;
8565
8566         I915_WRITE(PIPECONF(cpu_transcoder), val);
8567         POSTING_READ(PIPECONF(cpu_transcoder));
8568 }
8569
8570 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8571 {
8572         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8574         struct intel_crtc_state *config = intel_crtc->config;
8575
8576         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8577                 u32 val = 0;
8578
8579                 switch (intel_crtc->config->pipe_bpp) {
8580                 case 18:
8581                         val |= PIPEMISC_DITHER_6_BPC;
8582                         break;
8583                 case 24:
8584                         val |= PIPEMISC_DITHER_8_BPC;
8585                         break;
8586                 case 30:
8587                         val |= PIPEMISC_DITHER_10_BPC;
8588                         break;
8589                 case 36:
8590                         val |= PIPEMISC_DITHER_12_BPC;
8591                         break;
8592                 default:
8593                         /* Case prevented by pipe_config_set_bpp. */
8594                         BUG();
8595                 }
8596
8597                 if (intel_crtc->config->dither)
8598                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8599
8600                 if (config->ycbcr420) {
8601                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8602                                 PIPEMISC_YUV420_ENABLE |
8603                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8604                 }
8605
8606                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8607         }
8608 }
8609
8610 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8611 {
8612         /*
8613          * Account for spread spectrum to avoid
8614          * oversubscribing the link. Max center spread
8615          * is 2.5%; use 5% for safety's sake.
8616          */
8617         u32 bps = target_clock * bpp * 21 / 20;
8618         return DIV_ROUND_UP(bps, link_bw * 8);
8619 }
8620
8621 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8622 {
8623         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8624 }
8625
8626 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8627                                   struct intel_crtc_state *crtc_state,
8628                                   struct dpll *reduced_clock)
8629 {
8630         struct drm_crtc *crtc = &intel_crtc->base;
8631         struct drm_device *dev = crtc->dev;
8632         struct drm_i915_private *dev_priv = to_i915(dev);
8633         u32 dpll, fp, fp2;
8634         int factor;
8635
8636         /* Enable autotuning of the PLL clock (if permissible) */
8637         factor = 21;
8638         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8639                 if ((intel_panel_use_ssc(dev_priv) &&
8640                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8641                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8642                         factor = 25;
8643         } else if (crtc_state->sdvo_tv_clock)
8644                 factor = 20;
8645
8646         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8647
8648         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8649                 fp |= FP_CB_TUNE;
8650
8651         if (reduced_clock) {
8652                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8653
8654                 if (reduced_clock->m < factor * reduced_clock->n)
8655                         fp2 |= FP_CB_TUNE;
8656         } else {
8657                 fp2 = fp;
8658         }
8659
8660         dpll = 0;
8661
8662         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8663                 dpll |= DPLLB_MODE_LVDS;
8664         else
8665                 dpll |= DPLLB_MODE_DAC_SERIAL;
8666
8667         dpll |= (crtc_state->pixel_multiplier - 1)
8668                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8669
8670         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8671             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8672                 dpll |= DPLL_SDVO_HIGH_SPEED;
8673
8674         if (intel_crtc_has_dp_encoder(crtc_state))
8675                 dpll |= DPLL_SDVO_HIGH_SPEED;
8676
8677         /*
8678          * The high speed IO clock is only really required for
8679          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8680          * possible to share the DPLL between CRT and HDMI. Enabling
8681          * the clock needlessly does no real harm, except use up a
8682          * bit of power potentially.
8683          *
8684          * We'll limit this to IVB with 3 pipes, since it has only two
8685          * DPLLs and so DPLL sharing is the only way to get three pipes
8686          * driving PCH ports at the same time. On SNB we could do this,
8687          * and potentially avoid enabling the second DPLL, but it's not
8688          * clear if it''s a win or loss power wise. No point in doing
8689          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8690          */
8691         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8692             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8693                 dpll |= DPLL_SDVO_HIGH_SPEED;
8694
8695         /* compute bitmask from p1 value */
8696         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8697         /* also FPA1 */
8698         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8699
8700         switch (crtc_state->dpll.p2) {
8701         case 5:
8702                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8703                 break;
8704         case 7:
8705                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8706                 break;
8707         case 10:
8708                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8709                 break;
8710         case 14:
8711                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8712                 break;
8713         }
8714
8715         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8716             intel_panel_use_ssc(dev_priv))
8717                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8718         else
8719                 dpll |= PLL_REF_INPUT_DREFCLK;
8720
8721         dpll |= DPLL_VCO_ENABLE;
8722
8723         crtc_state->dpll_hw_state.dpll = dpll;
8724         crtc_state->dpll_hw_state.fp0 = fp;
8725         crtc_state->dpll_hw_state.fp1 = fp2;
8726 }
8727
8728 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8729                                        struct intel_crtc_state *crtc_state)
8730 {
8731         struct drm_device *dev = crtc->base.dev;
8732         struct drm_i915_private *dev_priv = to_i915(dev);
8733         const struct intel_limit *limit;
8734         int refclk = 120000;
8735
8736         memset(&crtc_state->dpll_hw_state, 0,
8737                sizeof(crtc_state->dpll_hw_state));
8738
8739         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8740         if (!crtc_state->has_pch_encoder)
8741                 return 0;
8742
8743         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8744                 if (intel_panel_use_ssc(dev_priv)) {
8745                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8746                                       dev_priv->vbt.lvds_ssc_freq);
8747                         refclk = dev_priv->vbt.lvds_ssc_freq;
8748                 }
8749
8750                 if (intel_is_dual_link_lvds(dev)) {
8751                         if (refclk == 100000)
8752                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8753                         else
8754                                 limit = &intel_limits_ironlake_dual_lvds;
8755                 } else {
8756                         if (refclk == 100000)
8757                                 limit = &intel_limits_ironlake_single_lvds_100m;
8758                         else
8759                                 limit = &intel_limits_ironlake_single_lvds;
8760                 }
8761         } else {
8762                 limit = &intel_limits_ironlake_dac;
8763         }
8764
8765         if (!crtc_state->clock_set &&
8766             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8767                                 refclk, NULL, &crtc_state->dpll)) {
8768                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8769                 return -EINVAL;
8770         }
8771
8772         ironlake_compute_dpll(crtc, crtc_state, NULL);
8773
8774         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8775                 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
8776                               pipe_name(crtc->pipe));
8777                 return -EINVAL;
8778         }
8779
8780         return 0;
8781 }
8782
8783 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8784                                          struct intel_link_m_n *m_n)
8785 {
8786         struct drm_device *dev = crtc->base.dev;
8787         struct drm_i915_private *dev_priv = to_i915(dev);
8788         enum pipe pipe = crtc->pipe;
8789
8790         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8791         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8792         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8793                 & ~TU_SIZE_MASK;
8794         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8795         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8796                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8797 }
8798
8799 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8800                                          enum transcoder transcoder,
8801                                          struct intel_link_m_n *m_n,
8802                                          struct intel_link_m_n *m2_n2)
8803 {
8804         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8805         enum pipe pipe = crtc->pipe;
8806
8807         if (INTEL_GEN(dev_priv) >= 5) {
8808                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8809                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8810                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8811                         & ~TU_SIZE_MASK;
8812                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8813                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8814                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8815                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8816                  * gen < 8) and if DRRS is supported (to make sure the
8817                  * registers are not unnecessarily read).
8818                  */
8819                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8820                         crtc->config->has_drrs) {
8821                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8822                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8823                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8824                                         & ~TU_SIZE_MASK;
8825                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8826                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8827                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8828                 }
8829         } else {
8830                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8831                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8832                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8833                         & ~TU_SIZE_MASK;
8834                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8835                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8836                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8837         }
8838 }
8839
8840 void intel_dp_get_m_n(struct intel_crtc *crtc,
8841                       struct intel_crtc_state *pipe_config)
8842 {
8843         if (pipe_config->has_pch_encoder)
8844                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8845         else
8846                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8847                                              &pipe_config->dp_m_n,
8848                                              &pipe_config->dp_m2_n2);
8849 }
8850
8851 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8852                                         struct intel_crtc_state *pipe_config)
8853 {
8854         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8855                                      &pipe_config->fdi_m_n, NULL);
8856 }
8857
8858 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8859                                     struct intel_crtc_state *pipe_config)
8860 {
8861         struct drm_device *dev = crtc->base.dev;
8862         struct drm_i915_private *dev_priv = to_i915(dev);
8863         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8864         uint32_t ps_ctrl = 0;
8865         int id = -1;
8866         int i;
8867
8868         /* find scaler attached to this pipe */
8869         for (i = 0; i < crtc->num_scalers; i++) {
8870                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8871                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8872                         id = i;
8873                         pipe_config->pch_pfit.enabled = true;
8874                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8875                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8876                         break;
8877                 }
8878         }
8879
8880         scaler_state->scaler_id = id;
8881         if (id >= 0) {
8882                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8883         } else {
8884                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8885         }
8886 }
8887
8888 static void
8889 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8890                                  struct intel_initial_plane_config *plane_config)
8891 {
8892         struct drm_device *dev = crtc->base.dev;
8893         struct drm_i915_private *dev_priv = to_i915(dev);
8894         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8895         enum plane_id plane_id = plane->id;
8896         enum pipe pipe;
8897         u32 val, base, offset, stride_mult, tiling, alpha;
8898         int fourcc, pixel_format;
8899         unsigned int aligned_height;
8900         struct drm_framebuffer *fb;
8901         struct intel_framebuffer *intel_fb;
8902
8903         if (!plane->get_hw_state(plane, &pipe))
8904                 return;
8905
8906         WARN_ON(pipe != crtc->pipe);
8907
8908         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8909         if (!intel_fb) {
8910                 DRM_DEBUG_KMS("failed to alloc fb\n");
8911                 return;
8912         }
8913
8914         fb = &intel_fb->base;
8915
8916         fb->dev = dev;
8917
8918         val = I915_READ(PLANE_CTL(pipe, plane_id));
8919
8920         if (INTEL_GEN(dev_priv) >= 11)
8921                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8922         else
8923                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8924
8925         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8926                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8927                 alpha &= PLANE_COLOR_ALPHA_MASK;
8928         } else {
8929                 alpha = val & PLANE_CTL_ALPHA_MASK;
8930         }
8931
8932         fourcc = skl_format_to_fourcc(pixel_format,
8933                                       val & PLANE_CTL_ORDER_RGBX, alpha);
8934         fb->format = drm_format_info(fourcc);
8935
8936         tiling = val & PLANE_CTL_TILED_MASK;
8937         switch (tiling) {
8938         case PLANE_CTL_TILED_LINEAR:
8939                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8940                 break;
8941         case PLANE_CTL_TILED_X:
8942                 plane_config->tiling = I915_TILING_X;
8943                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8944                 break;
8945         case PLANE_CTL_TILED_Y:
8946                 plane_config->tiling = I915_TILING_Y;
8947                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8948                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8949                 else
8950                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8951                 break;
8952         case PLANE_CTL_TILED_YF:
8953                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
8954                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8955                 else
8956                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8957                 break;
8958         default:
8959                 MISSING_CASE(tiling);
8960                 goto error;
8961         }
8962
8963         /*
8964          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
8965          * while i915 HW rotation is clockwise, thats why this swapping.
8966          */
8967         switch (val & PLANE_CTL_ROTATE_MASK) {
8968         case PLANE_CTL_ROTATE_0:
8969                 plane_config->rotation = DRM_MODE_ROTATE_0;
8970                 break;
8971         case PLANE_CTL_ROTATE_90:
8972                 plane_config->rotation = DRM_MODE_ROTATE_270;
8973                 break;
8974         case PLANE_CTL_ROTATE_180:
8975                 plane_config->rotation = DRM_MODE_ROTATE_180;
8976                 break;
8977         case PLANE_CTL_ROTATE_270:
8978                 plane_config->rotation = DRM_MODE_ROTATE_90;
8979                 break;
8980         }
8981
8982         if (INTEL_GEN(dev_priv) >= 10 &&
8983             val & PLANE_CTL_FLIP_HORIZONTAL)
8984                 plane_config->rotation |= DRM_MODE_REFLECT_X;
8985
8986         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8987         plane_config->base = base;
8988
8989         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8990
8991         val = I915_READ(PLANE_SIZE(pipe, plane_id));
8992         fb->height = ((val >> 16) & 0xfff) + 1;
8993         fb->width = ((val >> 0) & 0x1fff) + 1;
8994
8995         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8996         stride_mult = intel_fb_stride_alignment(fb, 0);
8997         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8998
8999         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9000
9001         plane_config->size = fb->pitches[0] * aligned_height;
9002
9003         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9004                       crtc->base.name, plane->base.name, fb->width, fb->height,
9005                       fb->format->cpp[0] * 8, base, fb->pitches[0],
9006                       plane_config->size);
9007
9008         plane_config->fb = intel_fb;
9009         return;
9010
9011 error:
9012         kfree(intel_fb);
9013 }
9014
9015 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9016                                      struct intel_crtc_state *pipe_config)
9017 {
9018         struct drm_device *dev = crtc->base.dev;
9019         struct drm_i915_private *dev_priv = to_i915(dev);
9020         uint32_t tmp;
9021
9022         tmp = I915_READ(PF_CTL(crtc->pipe));
9023
9024         if (tmp & PF_ENABLE) {
9025                 pipe_config->pch_pfit.enabled = true;
9026                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9027                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9028
9029                 /* We currently do not free assignements of panel fitters on
9030                  * ivb/hsw (since we don't use the higher upscaling modes which
9031                  * differentiates them) so just WARN about this case for now. */
9032                 if (IS_GEN7(dev_priv)) {
9033                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9034                                 PF_PIPE_SEL_IVB(crtc->pipe));
9035                 }
9036         }
9037 }
9038
9039 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9040                                      struct intel_crtc_state *pipe_config)
9041 {
9042         struct drm_device *dev = crtc->base.dev;
9043         struct drm_i915_private *dev_priv = to_i915(dev);
9044         enum intel_display_power_domain power_domain;
9045         uint32_t tmp;
9046         bool ret;
9047
9048         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9049         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9050                 return false;
9051
9052         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9053         pipe_config->shared_dpll = NULL;
9054
9055         ret = false;
9056         tmp = I915_READ(PIPECONF(crtc->pipe));
9057         if (!(tmp & PIPECONF_ENABLE))
9058                 goto out;
9059
9060         switch (tmp & PIPECONF_BPC_MASK) {
9061         case PIPECONF_6BPC:
9062                 pipe_config->pipe_bpp = 18;
9063                 break;
9064         case PIPECONF_8BPC:
9065                 pipe_config->pipe_bpp = 24;
9066                 break;
9067         case PIPECONF_10BPC:
9068                 pipe_config->pipe_bpp = 30;
9069                 break;
9070         case PIPECONF_12BPC:
9071                 pipe_config->pipe_bpp = 36;
9072                 break;
9073         default:
9074                 break;
9075         }
9076
9077         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9078                 pipe_config->limited_color_range = true;
9079
9080         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9081                 struct intel_shared_dpll *pll;
9082                 enum intel_dpll_id pll_id;
9083
9084                 pipe_config->has_pch_encoder = true;
9085
9086                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9087                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9088                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9089
9090                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9091
9092                 if (HAS_PCH_IBX(dev_priv)) {
9093                         /*
9094                          * The pipe->pch transcoder and pch transcoder->pll
9095                          * mapping is fixed.
9096                          */
9097                         pll_id = (enum intel_dpll_id) crtc->pipe;
9098                 } else {
9099                         tmp = I915_READ(PCH_DPLL_SEL);
9100                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9101                                 pll_id = DPLL_ID_PCH_PLL_B;
9102                         else
9103                                 pll_id= DPLL_ID_PCH_PLL_A;
9104                 }
9105
9106                 pipe_config->shared_dpll =
9107                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9108                 pll = pipe_config->shared_dpll;
9109
9110                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9111                                                 &pipe_config->dpll_hw_state));
9112
9113                 tmp = pipe_config->dpll_hw_state.dpll;
9114                 pipe_config->pixel_multiplier =
9115                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9116                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9117
9118                 ironlake_pch_clock_get(crtc, pipe_config);
9119         } else {
9120                 pipe_config->pixel_multiplier = 1;
9121         }
9122
9123         intel_get_pipe_timings(crtc, pipe_config);
9124         intel_get_pipe_src_size(crtc, pipe_config);
9125
9126         ironlake_get_pfit_config(crtc, pipe_config);
9127
9128         ret = true;
9129
9130 out:
9131         intel_display_power_put(dev_priv, power_domain);
9132
9133         return ret;
9134 }
9135
9136 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9137 {
9138         struct drm_device *dev = &dev_priv->drm;
9139         struct intel_crtc *crtc;
9140
9141         for_each_intel_crtc(dev, crtc)
9142                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9143                      pipe_name(crtc->pipe));
9144
9145         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
9146                         "Display power well on\n");
9147         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9148         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9149         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9150         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9151         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9152              "CPU PWM1 enabled\n");
9153         if (IS_HASWELL(dev_priv))
9154                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9155                      "CPU PWM2 enabled\n");
9156         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9157              "PCH PWM1 enabled\n");
9158         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9159              "Utility pin enabled\n");
9160         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9161
9162         /*
9163          * In theory we can still leave IRQs enabled, as long as only the HPD
9164          * interrupts remain enabled. We used to check for that, but since it's
9165          * gen-specific and since we only disable LCPLL after we fully disable
9166          * the interrupts, the check below should be enough.
9167          */
9168         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9169 }
9170
9171 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9172 {
9173         if (IS_HASWELL(dev_priv))
9174                 return I915_READ(D_COMP_HSW);
9175         else
9176                 return I915_READ(D_COMP_BDW);
9177 }
9178
9179 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9180 {
9181         if (IS_HASWELL(dev_priv)) {
9182                 mutex_lock(&dev_priv->pcu_lock);
9183                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9184                                             val))
9185                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9186                 mutex_unlock(&dev_priv->pcu_lock);
9187         } else {
9188                 I915_WRITE(D_COMP_BDW, val);
9189                 POSTING_READ(D_COMP_BDW);
9190         }
9191 }
9192
9193 /*
9194  * This function implements pieces of two sequences from BSpec:
9195  * - Sequence for display software to disable LCPLL
9196  * - Sequence for display software to allow package C8+
9197  * The steps implemented here are just the steps that actually touch the LCPLL
9198  * register. Callers should take care of disabling all the display engine
9199  * functions, doing the mode unset, fixing interrupts, etc.
9200  */
9201 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9202                               bool switch_to_fclk, bool allow_power_down)
9203 {
9204         uint32_t val;
9205
9206         assert_can_disable_lcpll(dev_priv);
9207
9208         val = I915_READ(LCPLL_CTL);
9209
9210         if (switch_to_fclk) {
9211                 val |= LCPLL_CD_SOURCE_FCLK;
9212                 I915_WRITE(LCPLL_CTL, val);
9213
9214                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9215                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9216                         DRM_ERROR("Switching to FCLK failed\n");
9217
9218                 val = I915_READ(LCPLL_CTL);
9219         }
9220
9221         val |= LCPLL_PLL_DISABLE;
9222         I915_WRITE(LCPLL_CTL, val);
9223         POSTING_READ(LCPLL_CTL);
9224
9225         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9226                 DRM_ERROR("LCPLL still locked\n");
9227
9228         val = hsw_read_dcomp(dev_priv);
9229         val |= D_COMP_COMP_DISABLE;
9230         hsw_write_dcomp(dev_priv, val);
9231         ndelay(100);
9232
9233         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9234                      1))
9235                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9236
9237         if (allow_power_down) {
9238                 val = I915_READ(LCPLL_CTL);
9239                 val |= LCPLL_POWER_DOWN_ALLOW;
9240                 I915_WRITE(LCPLL_CTL, val);
9241                 POSTING_READ(LCPLL_CTL);
9242         }
9243 }
9244
9245 /*
9246  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9247  * source.
9248  */
9249 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9250 {
9251         uint32_t val;
9252
9253         val = I915_READ(LCPLL_CTL);
9254
9255         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9256                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9257                 return;
9258
9259         /*
9260          * Make sure we're not on PC8 state before disabling PC8, otherwise
9261          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9262          */
9263         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9264
9265         if (val & LCPLL_POWER_DOWN_ALLOW) {
9266                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9267                 I915_WRITE(LCPLL_CTL, val);
9268                 POSTING_READ(LCPLL_CTL);
9269         }
9270
9271         val = hsw_read_dcomp(dev_priv);
9272         val |= D_COMP_COMP_FORCE;
9273         val &= ~D_COMP_COMP_DISABLE;
9274         hsw_write_dcomp(dev_priv, val);
9275
9276         val = I915_READ(LCPLL_CTL);
9277         val &= ~LCPLL_PLL_DISABLE;
9278         I915_WRITE(LCPLL_CTL, val);
9279
9280         if (intel_wait_for_register(dev_priv,
9281                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9282                                     5))
9283                 DRM_ERROR("LCPLL not locked yet\n");
9284
9285         if (val & LCPLL_CD_SOURCE_FCLK) {
9286                 val = I915_READ(LCPLL_CTL);
9287                 val &= ~LCPLL_CD_SOURCE_FCLK;
9288                 I915_WRITE(LCPLL_CTL, val);
9289
9290                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9291                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9292                         DRM_ERROR("Switching back to LCPLL failed\n");
9293         }
9294
9295         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9296
9297         intel_update_cdclk(dev_priv);
9298         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9299 }
9300
9301 /*
9302  * Package states C8 and deeper are really deep PC states that can only be
9303  * reached when all the devices on the system allow it, so even if the graphics
9304  * device allows PC8+, it doesn't mean the system will actually get to these
9305  * states. Our driver only allows PC8+ when going into runtime PM.
9306  *
9307  * The requirements for PC8+ are that all the outputs are disabled, the power
9308  * well is disabled and most interrupts are disabled, and these are also
9309  * requirements for runtime PM. When these conditions are met, we manually do
9310  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9311  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9312  * hang the machine.
9313  *
9314  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9315  * the state of some registers, so when we come back from PC8+ we need to
9316  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9317  * need to take care of the registers kept by RC6. Notice that this happens even
9318  * if we don't put the device in PCI D3 state (which is what currently happens
9319  * because of the runtime PM support).
9320  *
9321  * For more, read "Display Sequences for Package C8" on the hardware
9322  * documentation.
9323  */
9324 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9325 {
9326         uint32_t val;
9327
9328         DRM_DEBUG_KMS("Enabling package C8+\n");
9329
9330         if (HAS_PCH_LPT_LP(dev_priv)) {
9331                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9332                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9333                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9334         }
9335
9336         lpt_disable_clkout_dp(dev_priv);
9337         hsw_disable_lcpll(dev_priv, true, true);
9338 }
9339
9340 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9341 {
9342         uint32_t val;
9343
9344         DRM_DEBUG_KMS("Disabling package C8+\n");
9345
9346         hsw_restore_lcpll(dev_priv);
9347         lpt_init_pch_refclk(dev_priv);
9348
9349         if (HAS_PCH_LPT_LP(dev_priv)) {
9350                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9351                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9352                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9353         }
9354 }
9355
9356 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9357                                       struct intel_crtc_state *crtc_state)
9358 {
9359         struct intel_atomic_state *state =
9360                 to_intel_atomic_state(crtc_state->base.state);
9361
9362         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9363                 struct intel_encoder *encoder =
9364                         intel_get_crtc_new_encoder(state, crtc_state);
9365
9366                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9367                         DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9368                                       pipe_name(crtc->pipe));
9369                         return -EINVAL;
9370                 }
9371         }
9372
9373         return 0;
9374 }
9375
9376 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9377                                    enum port port,
9378                                    struct intel_crtc_state *pipe_config)
9379 {
9380         enum intel_dpll_id id;
9381         u32 temp;
9382
9383         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9384         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9385
9386         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9387                 return;
9388
9389         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9390 }
9391
9392 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9393                                 enum port port,
9394                                 struct intel_crtc_state *pipe_config)
9395 {
9396         enum intel_dpll_id id;
9397         u32 temp;
9398
9399         /* TODO: TBT pll not implemented. */
9400         switch (port) {
9401         case PORT_A:
9402         case PORT_B:
9403                 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9404                        DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9405                 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9406
9407                 if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
9408                         return;
9409                 break;
9410         case PORT_C:
9411                 id = DPLL_ID_ICL_MGPLL1;
9412                 break;
9413         case PORT_D:
9414                 id = DPLL_ID_ICL_MGPLL2;
9415                 break;
9416         case PORT_E:
9417                 id = DPLL_ID_ICL_MGPLL3;
9418                 break;
9419         case PORT_F:
9420                 id = DPLL_ID_ICL_MGPLL4;
9421                 break;
9422         default:
9423                 MISSING_CASE(port);
9424                 return;
9425         }
9426
9427         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9428 }
9429
9430 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9431                                 enum port port,
9432                                 struct intel_crtc_state *pipe_config)
9433 {
9434         enum intel_dpll_id id;
9435
9436         switch (port) {
9437         case PORT_A:
9438                 id = DPLL_ID_SKL_DPLL0;
9439                 break;
9440         case PORT_B:
9441                 id = DPLL_ID_SKL_DPLL1;
9442                 break;
9443         case PORT_C:
9444                 id = DPLL_ID_SKL_DPLL2;
9445                 break;
9446         default:
9447                 DRM_ERROR("Incorrect port type\n");
9448                 return;
9449         }
9450
9451         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9452 }
9453
9454 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9455                                 enum port port,
9456                                 struct intel_crtc_state *pipe_config)
9457 {
9458         enum intel_dpll_id id;
9459         u32 temp;
9460
9461         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9462         id = temp >> (port * 3 + 1);
9463
9464         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9465                 return;
9466
9467         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9468 }
9469
9470 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9471                                 enum port port,
9472                                 struct intel_crtc_state *pipe_config)
9473 {
9474         enum intel_dpll_id id;
9475         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9476
9477         switch (ddi_pll_sel) {
9478         case PORT_CLK_SEL_WRPLL1:
9479                 id = DPLL_ID_WRPLL1;
9480                 break;
9481         case PORT_CLK_SEL_WRPLL2:
9482                 id = DPLL_ID_WRPLL2;
9483                 break;
9484         case PORT_CLK_SEL_SPLL:
9485                 id = DPLL_ID_SPLL;
9486                 break;
9487         case PORT_CLK_SEL_LCPLL_810:
9488                 id = DPLL_ID_LCPLL_810;
9489                 break;
9490         case PORT_CLK_SEL_LCPLL_1350:
9491                 id = DPLL_ID_LCPLL_1350;
9492                 break;
9493         case PORT_CLK_SEL_LCPLL_2700:
9494                 id = DPLL_ID_LCPLL_2700;
9495                 break;
9496         default:
9497                 MISSING_CASE(ddi_pll_sel);
9498                 /* fall through */
9499         case PORT_CLK_SEL_NONE:
9500                 return;
9501         }
9502
9503         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9504 }
9505
9506 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9507                                      struct intel_crtc_state *pipe_config,
9508                                      u64 *power_domain_mask)
9509 {
9510         struct drm_device *dev = crtc->base.dev;
9511         struct drm_i915_private *dev_priv = to_i915(dev);
9512         enum intel_display_power_domain power_domain;
9513         u32 tmp;
9514
9515         /*
9516          * The pipe->transcoder mapping is fixed with the exception of the eDP
9517          * transcoder handled below.
9518          */
9519         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9520
9521         /*
9522          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9523          * consistency and less surprising code; it's in always on power).
9524          */
9525         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9526         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9527                 enum pipe trans_edp_pipe;
9528                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9529                 default:
9530                         WARN(1, "unknown pipe linked to edp transcoder\n");
9531                         /* fall through */
9532                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9533                 case TRANS_DDI_EDP_INPUT_A_ON:
9534                         trans_edp_pipe = PIPE_A;
9535                         break;
9536                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9537                         trans_edp_pipe = PIPE_B;
9538                         break;
9539                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9540                         trans_edp_pipe = PIPE_C;
9541                         break;
9542                 }
9543
9544                 if (trans_edp_pipe == crtc->pipe)
9545                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9546         }
9547
9548         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9549         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9550                 return false;
9551         *power_domain_mask |= BIT_ULL(power_domain);
9552
9553         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9554
9555         return tmp & PIPECONF_ENABLE;
9556 }
9557
9558 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9559                                          struct intel_crtc_state *pipe_config,
9560                                          u64 *power_domain_mask)
9561 {
9562         struct drm_device *dev = crtc->base.dev;
9563         struct drm_i915_private *dev_priv = to_i915(dev);
9564         enum intel_display_power_domain power_domain;
9565         enum port port;
9566         enum transcoder cpu_transcoder;
9567         u32 tmp;
9568
9569         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9570                 if (port == PORT_A)
9571                         cpu_transcoder = TRANSCODER_DSI_A;
9572                 else
9573                         cpu_transcoder = TRANSCODER_DSI_C;
9574
9575                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9576                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9577                         continue;
9578                 *power_domain_mask |= BIT_ULL(power_domain);
9579
9580                 /*
9581                  * The PLL needs to be enabled with a valid divider
9582                  * configuration, otherwise accessing DSI registers will hang
9583                  * the machine. See BSpec North Display Engine
9584                  * registers/MIPI[BXT]. We can break out here early, since we
9585                  * need the same DSI PLL to be enabled for both DSI ports.
9586                  */
9587                 if (!bxt_dsi_pll_is_enabled(dev_priv))
9588                         break;
9589
9590                 /* XXX: this works for video mode only */
9591                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9592                 if (!(tmp & DPI_ENABLE))
9593                         continue;
9594
9595                 tmp = I915_READ(MIPI_CTRL(port));
9596                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9597                         continue;
9598
9599                 pipe_config->cpu_transcoder = cpu_transcoder;
9600                 break;
9601         }
9602
9603         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9604 }
9605
9606 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9607                                        struct intel_crtc_state *pipe_config)
9608 {
9609         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9610         struct intel_shared_dpll *pll;
9611         enum port port;
9612         uint32_t tmp;
9613
9614         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9615
9616         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9617
9618         if (IS_ICELAKE(dev_priv))
9619                 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9620         else if (IS_CANNONLAKE(dev_priv))
9621                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9622         else if (IS_GEN9_BC(dev_priv))
9623                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9624         else if (IS_GEN9_LP(dev_priv))
9625                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9626         else
9627                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9628
9629         pll = pipe_config->shared_dpll;
9630         if (pll) {
9631                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9632                                                 &pipe_config->dpll_hw_state));
9633         }
9634
9635         /*
9636          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9637          * DDI E. So just check whether this pipe is wired to DDI E and whether
9638          * the PCH transcoder is on.
9639          */
9640         if (INTEL_GEN(dev_priv) < 9 &&
9641             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9642                 pipe_config->has_pch_encoder = true;
9643
9644                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9645                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9646                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9647
9648                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9649         }
9650 }
9651
9652 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9653                                     struct intel_crtc_state *pipe_config)
9654 {
9655         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9656         enum intel_display_power_domain power_domain;
9657         u64 power_domain_mask;
9658         bool active;
9659
9660         intel_crtc_init_scalers(crtc, pipe_config);
9661
9662         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9663         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9664                 return false;
9665         power_domain_mask = BIT_ULL(power_domain);
9666
9667         pipe_config->shared_dpll = NULL;
9668
9669         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9670
9671         if (IS_GEN9_LP(dev_priv) &&
9672             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9673                 WARN_ON(active);
9674                 active = true;
9675         }
9676
9677         if (!active)
9678                 goto out;
9679
9680         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9681                 haswell_get_ddi_port_state(crtc, pipe_config);
9682                 intel_get_pipe_timings(crtc, pipe_config);
9683         }
9684
9685         intel_get_pipe_src_size(crtc, pipe_config);
9686
9687         pipe_config->gamma_mode =
9688                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9689
9690         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9691                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9692                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9693
9694                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9695                         bool blend_mode_420 = tmp &
9696                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9697
9698                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9699                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9700                             pipe_config->ycbcr420 != blend_mode_420)
9701                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9702                 } else if (clrspace_yuv) {
9703                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9704                 }
9705         }
9706
9707         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9708         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9709                 power_domain_mask |= BIT_ULL(power_domain);
9710                 if (INTEL_GEN(dev_priv) >= 9)
9711                         skylake_get_pfit_config(crtc, pipe_config);
9712                 else
9713                         ironlake_get_pfit_config(crtc, pipe_config);
9714         }
9715
9716         if (hsw_crtc_supports_ips(crtc)) {
9717                 if (IS_HASWELL(dev_priv))
9718                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9719                 else {
9720                         /*
9721                          * We cannot readout IPS state on broadwell, set to
9722                          * true so we can set it to a defined state on first
9723                          * commit.
9724                          */
9725                         pipe_config->ips_enabled = true;
9726                 }
9727         }
9728
9729         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9730             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9731                 pipe_config->pixel_multiplier =
9732                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9733         } else {
9734                 pipe_config->pixel_multiplier = 1;
9735         }
9736
9737 out:
9738         for_each_power_domain(power_domain, power_domain_mask)
9739                 intel_display_power_put(dev_priv, power_domain);
9740
9741         return active;
9742 }
9743
9744 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9745 {
9746         struct drm_i915_private *dev_priv =
9747                 to_i915(plane_state->base.plane->dev);
9748         const struct drm_framebuffer *fb = plane_state->base.fb;
9749         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9750         u32 base;
9751
9752         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9753                 base = obj->phys_handle->busaddr;
9754         else
9755                 base = intel_plane_ggtt_offset(plane_state);
9756
9757         base += plane_state->color_plane[0].offset;
9758
9759         /* ILK+ do this automagically */
9760         if (HAS_GMCH_DISPLAY(dev_priv) &&
9761             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9762                 base += (plane_state->base.crtc_h *
9763                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9764
9765         return base;
9766 }
9767
9768 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9769 {
9770         int x = plane_state->base.crtc_x;
9771         int y = plane_state->base.crtc_y;
9772         u32 pos = 0;
9773
9774         if (x < 0) {
9775                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9776                 x = -x;
9777         }
9778         pos |= x << CURSOR_X_SHIFT;
9779
9780         if (y < 0) {
9781                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9782                 y = -y;
9783         }
9784         pos |= y << CURSOR_Y_SHIFT;
9785
9786         return pos;
9787 }
9788
9789 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9790 {
9791         const struct drm_mode_config *config =
9792                 &plane_state->base.plane->dev->mode_config;
9793         int width = plane_state->base.crtc_w;
9794         int height = plane_state->base.crtc_h;
9795
9796         return width > 0 && width <= config->cursor_width &&
9797                 height > 0 && height <= config->cursor_height;
9798 }
9799
9800 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
9801 {
9802         const struct drm_framebuffer *fb = plane_state->base.fb;
9803         unsigned int rotation = plane_state->base.rotation;
9804         int src_x, src_y;
9805         u32 offset;
9806         int ret;
9807
9808         intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
9809         plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
9810
9811         ret = intel_plane_check_stride(plane_state);
9812         if (ret)
9813                 return ret;
9814
9815         src_x = plane_state->base.src_x >> 16;
9816         src_y = plane_state->base.src_y >> 16;
9817
9818         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9819         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
9820                                                     plane_state, 0);
9821
9822         if (src_x != 0 || src_y != 0) {
9823                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9824                 return -EINVAL;
9825         }
9826
9827         plane_state->color_plane[0].offset = offset;
9828
9829         return 0;
9830 }
9831
9832 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9833                               struct intel_plane_state *plane_state)
9834 {
9835         const struct drm_framebuffer *fb = plane_state->base.fb;
9836         int ret;
9837
9838         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9839                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9840                 return -EINVAL;
9841         }
9842
9843         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9844                                                   &crtc_state->base,
9845                                                   DRM_PLANE_HELPER_NO_SCALING,
9846                                                   DRM_PLANE_HELPER_NO_SCALING,
9847                                                   true, true);
9848         if (ret)
9849                 return ret;
9850
9851         if (!plane_state->base.visible)
9852                 return 0;
9853
9854         ret = intel_plane_check_src_coordinates(plane_state);
9855         if (ret)
9856                 return ret;
9857
9858         ret = intel_cursor_check_surface(plane_state);
9859         if (ret)
9860                 return ret;
9861
9862         return 0;
9863 }
9864
9865 static unsigned int
9866 i845_cursor_max_stride(struct intel_plane *plane,
9867                        u32 pixel_format, u64 modifier,
9868                        unsigned int rotation)
9869 {
9870         return 2048;
9871 }
9872
9873 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9874                            const struct intel_plane_state *plane_state)
9875 {
9876         return CURSOR_ENABLE |
9877                 CURSOR_GAMMA_ENABLE |
9878                 CURSOR_FORMAT_ARGB |
9879                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
9880 }
9881
9882 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9883 {
9884         int width = plane_state->base.crtc_w;
9885
9886         /*
9887          * 845g/865g are only limited by the width of their cursors,
9888          * the height is arbitrary up to the precision of the register.
9889          */
9890         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9891 }
9892
9893 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
9894                              struct intel_plane_state *plane_state)
9895 {
9896         const struct drm_framebuffer *fb = plane_state->base.fb;
9897         int ret;
9898
9899         ret = intel_check_cursor(crtc_state, plane_state);
9900         if (ret)
9901                 return ret;
9902
9903         /* if we want to turn off the cursor ignore width and height */
9904         if (!fb)
9905                 return 0;
9906
9907         /* Check for which cursor types we support */
9908         if (!i845_cursor_size_ok(plane_state)) {
9909                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9910                           plane_state->base.crtc_w,
9911                           plane_state->base.crtc_h);
9912                 return -EINVAL;
9913         }
9914
9915         WARN_ON(plane_state->base.visible &&
9916                 plane_state->color_plane[0].stride != fb->pitches[0]);
9917
9918         switch (fb->pitches[0]) {
9919         case 256:
9920         case 512:
9921         case 1024:
9922         case 2048:
9923                 break;
9924         default:
9925                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9926                               fb->pitches[0]);
9927                 return -EINVAL;
9928         }
9929
9930         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9931
9932         return 0;
9933 }
9934
9935 static void i845_update_cursor(struct intel_plane *plane,
9936                                const struct intel_crtc_state *crtc_state,
9937                                const struct intel_plane_state *plane_state)
9938 {
9939         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9940         u32 cntl = 0, base = 0, pos = 0, size = 0;
9941         unsigned long irqflags;
9942
9943         if (plane_state && plane_state->base.visible) {
9944                 unsigned int width = plane_state->base.crtc_w;
9945                 unsigned int height = plane_state->base.crtc_h;
9946
9947                 cntl = plane_state->ctl;
9948                 size = (height << 12) | width;
9949
9950                 base = intel_cursor_base(plane_state);
9951                 pos = intel_cursor_position(plane_state);
9952         }
9953
9954         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9955
9956         /* On these chipsets we can only modify the base/size/stride
9957          * whilst the cursor is disabled.
9958          */
9959         if (plane->cursor.base != base ||
9960             plane->cursor.size != size ||
9961             plane->cursor.cntl != cntl) {
9962                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9963                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9964                 I915_WRITE_FW(CURSIZE, size);
9965                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9966                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9967
9968                 plane->cursor.base = base;
9969                 plane->cursor.size = size;
9970                 plane->cursor.cntl = cntl;
9971         } else {
9972                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9973         }
9974
9975         POSTING_READ_FW(CURCNTR(PIPE_A));
9976
9977         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9978 }
9979
9980 static void i845_disable_cursor(struct intel_plane *plane,
9981                                 struct intel_crtc *crtc)
9982 {
9983         i845_update_cursor(plane, NULL, NULL);
9984 }
9985
9986 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
9987                                      enum pipe *pipe)
9988 {
9989         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9990         enum intel_display_power_domain power_domain;
9991         bool ret;
9992
9993         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9994         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9995                 return false;
9996
9997         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9998
9999         *pipe = PIPE_A;
10000
10001         intel_display_power_put(dev_priv, power_domain);
10002
10003         return ret;
10004 }
10005
10006 static unsigned int
10007 i9xx_cursor_max_stride(struct intel_plane *plane,
10008                        u32 pixel_format, u64 modifier,
10009                        unsigned int rotation)
10010 {
10011         return plane->base.dev->mode_config.cursor_width * 4;
10012 }
10013
10014 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
10015                            const struct intel_plane_state *plane_state)
10016 {
10017         struct drm_i915_private *dev_priv =
10018                 to_i915(plane_state->base.plane->dev);
10019         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10020         u32 cntl = 0;
10021
10022         if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
10023                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10024
10025         if (INTEL_GEN(dev_priv) <= 10) {
10026                 cntl |= MCURSOR_GAMMA_ENABLE;
10027
10028                 if (HAS_DDI(dev_priv))
10029                         cntl |= MCURSOR_PIPE_CSC_ENABLE;
10030         }
10031
10032         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10033                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
10034
10035         switch (plane_state->base.crtc_w) {
10036         case 64:
10037                 cntl |= MCURSOR_MODE_64_ARGB_AX;
10038                 break;
10039         case 128:
10040                 cntl |= MCURSOR_MODE_128_ARGB_AX;
10041                 break;
10042         case 256:
10043                 cntl |= MCURSOR_MODE_256_ARGB_AX;
10044                 break;
10045         default:
10046                 MISSING_CASE(plane_state->base.crtc_w);
10047                 return 0;
10048         }
10049
10050         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
10051                 cntl |= MCURSOR_ROTATE_180;
10052
10053         return cntl;
10054 }
10055
10056 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
10057 {
10058         struct drm_i915_private *dev_priv =
10059                 to_i915(plane_state->base.plane->dev);
10060         int width = plane_state->base.crtc_w;
10061         int height = plane_state->base.crtc_h;
10062
10063         if (!intel_cursor_size_ok(plane_state))
10064                 return false;
10065
10066         /* Cursor width is limited to a few power-of-two sizes */
10067         switch (width) {
10068         case 256:
10069         case 128:
10070         case 64:
10071                 break;
10072         default:
10073                 return false;
10074         }
10075
10076         /*
10077          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10078          * height from 8 lines up to the cursor width, when the
10079          * cursor is not rotated. Everything else requires square
10080          * cursors.
10081          */
10082         if (HAS_CUR_FBC(dev_priv) &&
10083             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
10084                 if (height < 8 || height > width)
10085                         return false;
10086         } else {
10087                 if (height != width)
10088                         return false;
10089         }
10090
10091         return true;
10092 }
10093
10094 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
10095                              struct intel_plane_state *plane_state)
10096 {
10097         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
10098         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10099         const struct drm_framebuffer *fb = plane_state->base.fb;
10100         enum pipe pipe = plane->pipe;
10101         int ret;
10102
10103         ret = intel_check_cursor(crtc_state, plane_state);
10104         if (ret)
10105                 return ret;
10106
10107         /* if we want to turn off the cursor ignore width and height */
10108         if (!fb)
10109                 return 0;
10110
10111         /* Check for which cursor types we support */
10112         if (!i9xx_cursor_size_ok(plane_state)) {
10113                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10114                           plane_state->base.crtc_w,
10115                           plane_state->base.crtc_h);
10116                 return -EINVAL;
10117         }
10118
10119         WARN_ON(plane_state->base.visible &&
10120                 plane_state->color_plane[0].stride != fb->pitches[0]);
10121
10122         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
10123                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10124                               fb->pitches[0], plane_state->base.crtc_w);
10125                 return -EINVAL;
10126         }
10127
10128         /*
10129          * There's something wrong with the cursor on CHV pipe C.
10130          * If it straddles the left edge of the screen then
10131          * moving it away from the edge or disabling it often
10132          * results in a pipe underrun, and often that can lead to
10133          * dead pipe (constant underrun reported, and it scans
10134          * out just a solid color). To recover from that, the
10135          * display power well must be turned off and on again.
10136          * Refuse the put the cursor into that compromised position.
10137          */
10138         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
10139             plane_state->base.visible && plane_state->base.crtc_x < 0) {
10140                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10141                 return -EINVAL;
10142         }
10143
10144         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
10145
10146         return 0;
10147 }
10148
10149 static void i9xx_update_cursor(struct intel_plane *plane,
10150                                const struct intel_crtc_state *crtc_state,
10151                                const struct intel_plane_state *plane_state)
10152 {
10153         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10154         enum pipe pipe = plane->pipe;
10155         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
10156         unsigned long irqflags;
10157
10158         if (plane_state && plane_state->base.visible) {
10159                 cntl = plane_state->ctl;
10160
10161                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
10162                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
10163
10164                 base = intel_cursor_base(plane_state);
10165                 pos = intel_cursor_position(plane_state);
10166         }
10167
10168         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10169
10170         /*
10171          * On some platforms writing CURCNTR first will also
10172          * cause CURPOS to be armed by the CURBASE write.
10173          * Without the CURCNTR write the CURPOS write would
10174          * arm itself. Thus we always start the full update
10175          * with a CURCNTR write.
10176          *
10177          * On other platforms CURPOS always requires the
10178          * CURBASE write to arm the update. Additonally
10179          * a write to any of the cursor register will cancel
10180          * an already armed cursor update. Thus leaving out
10181          * the CURBASE write after CURPOS could lead to a
10182          * cursor that doesn't appear to move, or even change
10183          * shape. Thus we always write CURBASE.
10184          *
10185          * CURCNTR and CUR_FBC_CTL are always
10186          * armed by the CURBASE write only.
10187          */
10188         if (plane->cursor.base != base ||
10189             plane->cursor.size != fbc_ctl ||
10190             plane->cursor.cntl != cntl) {
10191                 I915_WRITE_FW(CURCNTR(pipe), cntl);
10192                 if (HAS_CUR_FBC(dev_priv))
10193                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10194                 I915_WRITE_FW(CURPOS(pipe), pos);
10195                 I915_WRITE_FW(CURBASE(pipe), base);
10196
10197                 plane->cursor.base = base;
10198                 plane->cursor.size = fbc_ctl;
10199                 plane->cursor.cntl = cntl;
10200         } else {
10201                 I915_WRITE_FW(CURPOS(pipe), pos);
10202                 I915_WRITE_FW(CURBASE(pipe), base);
10203         }
10204
10205         POSTING_READ_FW(CURBASE(pipe));
10206
10207         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10208 }
10209
10210 static void i9xx_disable_cursor(struct intel_plane *plane,
10211                                 struct intel_crtc *crtc)
10212 {
10213         i9xx_update_cursor(plane, NULL, NULL);
10214 }
10215
10216 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10217                                      enum pipe *pipe)
10218 {
10219         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10220         enum intel_display_power_domain power_domain;
10221         bool ret;
10222         u32 val;
10223
10224         /*
10225          * Not 100% correct for planes that can move between pipes,
10226          * but that's only the case for gen2-3 which don't have any
10227          * display power wells.
10228          */
10229         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10230         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10231                 return false;
10232
10233         val = I915_READ(CURCNTR(plane->pipe));
10234
10235         ret = val & MCURSOR_MODE;
10236
10237         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10238                 *pipe = plane->pipe;
10239         else
10240                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10241                         MCURSOR_PIPE_SELECT_SHIFT;
10242
10243         intel_display_power_put(dev_priv, power_domain);
10244
10245         return ret;
10246 }
10247
10248 /* VESA 640x480x72Hz mode to set on the pipe */
10249 static const struct drm_display_mode load_detect_mode = {
10250         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10251                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10252 };
10253
10254 struct drm_framebuffer *
10255 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10256                          struct drm_mode_fb_cmd2 *mode_cmd)
10257 {
10258         struct intel_framebuffer *intel_fb;
10259         int ret;
10260
10261         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10262         if (!intel_fb)
10263                 return ERR_PTR(-ENOMEM);
10264
10265         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10266         if (ret)
10267                 goto err;
10268
10269         return &intel_fb->base;
10270
10271 err:
10272         kfree(intel_fb);
10273         return ERR_PTR(ret);
10274 }
10275
10276 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10277                                         struct drm_crtc *crtc)
10278 {
10279         struct drm_plane *plane;
10280         struct drm_plane_state *plane_state;
10281         int ret, i;
10282
10283         ret = drm_atomic_add_affected_planes(state, crtc);
10284         if (ret)
10285                 return ret;
10286
10287         for_each_new_plane_in_state(state, plane, plane_state, i) {
10288                 if (plane_state->crtc != crtc)
10289                         continue;
10290
10291                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10292                 if (ret)
10293                         return ret;
10294
10295                 drm_atomic_set_fb_for_plane(plane_state, NULL);
10296         }
10297
10298         return 0;
10299 }
10300
10301 int intel_get_load_detect_pipe(struct drm_connector *connector,
10302                                const struct drm_display_mode *mode,
10303                                struct intel_load_detect_pipe *old,
10304                                struct drm_modeset_acquire_ctx *ctx)
10305 {
10306         struct intel_crtc *intel_crtc;
10307         struct intel_encoder *intel_encoder =
10308                 intel_attached_encoder(connector);
10309         struct drm_crtc *possible_crtc;
10310         struct drm_encoder *encoder = &intel_encoder->base;
10311         struct drm_crtc *crtc = NULL;
10312         struct drm_device *dev = encoder->dev;
10313         struct drm_i915_private *dev_priv = to_i915(dev);
10314         struct drm_mode_config *config = &dev->mode_config;
10315         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10316         struct drm_connector_state *connector_state;
10317         struct intel_crtc_state *crtc_state;
10318         int ret, i = -1;
10319
10320         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10321                       connector->base.id, connector->name,
10322                       encoder->base.id, encoder->name);
10323
10324         old->restore_state = NULL;
10325
10326         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10327
10328         /*
10329          * Algorithm gets a little messy:
10330          *
10331          *   - if the connector already has an assigned crtc, use it (but make
10332          *     sure it's on first)
10333          *
10334          *   - try to find the first unused crtc that can drive this connector,
10335          *     and use that if we find one
10336          */
10337
10338         /* See if we already have a CRTC for this connector */
10339         if (connector->state->crtc) {
10340                 crtc = connector->state->crtc;
10341
10342                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10343                 if (ret)
10344                         goto fail;
10345
10346                 /* Make sure the crtc and connector are running */
10347                 goto found;
10348         }
10349
10350         /* Find an unused one (if possible) */
10351         for_each_crtc(dev, possible_crtc) {
10352                 i++;
10353                 if (!(encoder->possible_crtcs & (1 << i)))
10354                         continue;
10355
10356                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10357                 if (ret)
10358                         goto fail;
10359
10360                 if (possible_crtc->state->enable) {
10361                         drm_modeset_unlock(&possible_crtc->mutex);
10362                         continue;
10363                 }
10364
10365                 crtc = possible_crtc;
10366                 break;
10367         }
10368
10369         /*
10370          * If we didn't find an unused CRTC, don't use any.
10371          */
10372         if (!crtc) {
10373                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10374                 ret = -ENODEV;
10375                 goto fail;
10376         }
10377
10378 found:
10379         intel_crtc = to_intel_crtc(crtc);
10380
10381         state = drm_atomic_state_alloc(dev);
10382         restore_state = drm_atomic_state_alloc(dev);
10383         if (!state || !restore_state) {
10384                 ret = -ENOMEM;
10385                 goto fail;
10386         }
10387
10388         state->acquire_ctx = ctx;
10389         restore_state->acquire_ctx = ctx;
10390
10391         connector_state = drm_atomic_get_connector_state(state, connector);
10392         if (IS_ERR(connector_state)) {
10393                 ret = PTR_ERR(connector_state);
10394                 goto fail;
10395         }
10396
10397         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10398         if (ret)
10399                 goto fail;
10400
10401         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10402         if (IS_ERR(crtc_state)) {
10403                 ret = PTR_ERR(crtc_state);
10404                 goto fail;
10405         }
10406
10407         crtc_state->base.active = crtc_state->base.enable = true;
10408
10409         if (!mode)
10410                 mode = &load_detect_mode;
10411
10412         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10413         if (ret)
10414                 goto fail;
10415
10416         ret = intel_modeset_disable_planes(state, crtc);
10417         if (ret)
10418                 goto fail;
10419
10420         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10421         if (!ret)
10422                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10423         if (!ret)
10424                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10425         if (ret) {
10426                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10427                 goto fail;
10428         }
10429
10430         ret = drm_atomic_commit(state);
10431         if (ret) {
10432                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10433                 goto fail;
10434         }
10435
10436         old->restore_state = restore_state;
10437         drm_atomic_state_put(state);
10438
10439         /* let the connector get through one full cycle before testing */
10440         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10441         return true;
10442
10443 fail:
10444         if (state) {
10445                 drm_atomic_state_put(state);
10446                 state = NULL;
10447         }
10448         if (restore_state) {
10449                 drm_atomic_state_put(restore_state);
10450                 restore_state = NULL;
10451         }
10452
10453         if (ret == -EDEADLK)
10454                 return ret;
10455
10456         return false;
10457 }
10458
10459 void intel_release_load_detect_pipe(struct drm_connector *connector,
10460                                     struct intel_load_detect_pipe *old,
10461                                     struct drm_modeset_acquire_ctx *ctx)
10462 {
10463         struct intel_encoder *intel_encoder =
10464                 intel_attached_encoder(connector);
10465         struct drm_encoder *encoder = &intel_encoder->base;
10466         struct drm_atomic_state *state = old->restore_state;
10467         int ret;
10468
10469         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10470                       connector->base.id, connector->name,
10471                       encoder->base.id, encoder->name);
10472
10473         if (!state)
10474                 return;
10475
10476         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10477         if (ret)
10478                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10479         drm_atomic_state_put(state);
10480 }
10481
10482 static int i9xx_pll_refclk(struct drm_device *dev,
10483                            const struct intel_crtc_state *pipe_config)
10484 {
10485         struct drm_i915_private *dev_priv = to_i915(dev);
10486         u32 dpll = pipe_config->dpll_hw_state.dpll;
10487
10488         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10489                 return dev_priv->vbt.lvds_ssc_freq;
10490         else if (HAS_PCH_SPLIT(dev_priv))
10491                 return 120000;
10492         else if (!IS_GEN2(dev_priv))
10493                 return 96000;
10494         else
10495                 return 48000;
10496 }
10497
10498 /* Returns the clock of the currently programmed mode of the given pipe. */
10499 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10500                                 struct intel_crtc_state *pipe_config)
10501 {
10502         struct drm_device *dev = crtc->base.dev;
10503         struct drm_i915_private *dev_priv = to_i915(dev);
10504         int pipe = pipe_config->cpu_transcoder;
10505         u32 dpll = pipe_config->dpll_hw_state.dpll;
10506         u32 fp;
10507         struct dpll clock;
10508         int port_clock;
10509         int refclk = i9xx_pll_refclk(dev, pipe_config);
10510
10511         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10512                 fp = pipe_config->dpll_hw_state.fp0;
10513         else
10514                 fp = pipe_config->dpll_hw_state.fp1;
10515
10516         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10517         if (IS_PINEVIEW(dev_priv)) {
10518                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10519                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10520         } else {
10521                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10522                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10523         }
10524
10525         if (!IS_GEN2(dev_priv)) {
10526                 if (IS_PINEVIEW(dev_priv))
10527                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10528                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10529                 else
10530                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10531                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10532
10533                 switch (dpll & DPLL_MODE_MASK) {
10534                 case DPLLB_MODE_DAC_SERIAL:
10535                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10536                                 5 : 10;
10537                         break;
10538                 case DPLLB_MODE_LVDS:
10539                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10540                                 7 : 14;
10541                         break;
10542                 default:
10543                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10544                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10545                         return;
10546                 }
10547
10548                 if (IS_PINEVIEW(dev_priv))
10549                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10550                 else
10551                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10552         } else {
10553                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10554                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10555
10556                 if (is_lvds) {
10557                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10558                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10559
10560                         if (lvds & LVDS_CLKB_POWER_UP)
10561                                 clock.p2 = 7;
10562                         else
10563                                 clock.p2 = 14;
10564                 } else {
10565                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10566                                 clock.p1 = 2;
10567                         else {
10568                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10569                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10570                         }
10571                         if (dpll & PLL_P2_DIVIDE_BY_4)
10572                                 clock.p2 = 4;
10573                         else
10574                                 clock.p2 = 2;
10575                 }
10576
10577                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10578         }
10579
10580         /*
10581          * This value includes pixel_multiplier. We will use
10582          * port_clock to compute adjusted_mode.crtc_clock in the
10583          * encoder's get_config() function.
10584          */
10585         pipe_config->port_clock = port_clock;
10586 }
10587
10588 int intel_dotclock_calculate(int link_freq,
10589                              const struct intel_link_m_n *m_n)
10590 {
10591         /*
10592          * The calculation for the data clock is:
10593          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10594          * But we want to avoid losing precison if possible, so:
10595          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10596          *
10597          * and the link clock is simpler:
10598          * link_clock = (m * link_clock) / n
10599          */
10600
10601         if (!m_n->link_n)
10602                 return 0;
10603
10604         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10605 }
10606
10607 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10608                                    struct intel_crtc_state *pipe_config)
10609 {
10610         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10611
10612         /* read out port_clock from the DPLL */
10613         i9xx_crtc_clock_get(crtc, pipe_config);
10614
10615         /*
10616          * In case there is an active pipe without active ports,
10617          * we may need some idea for the dotclock anyway.
10618          * Calculate one based on the FDI configuration.
10619          */
10620         pipe_config->base.adjusted_mode.crtc_clock =
10621                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10622                                          &pipe_config->fdi_m_n);
10623 }
10624
10625 /* Returns the currently programmed mode of the given encoder. */
10626 struct drm_display_mode *
10627 intel_encoder_current_mode(struct intel_encoder *encoder)
10628 {
10629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10630         struct intel_crtc_state *crtc_state;
10631         struct drm_display_mode *mode;
10632         struct intel_crtc *crtc;
10633         enum pipe pipe;
10634
10635         if (!encoder->get_hw_state(encoder, &pipe))
10636                 return NULL;
10637
10638         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10639
10640         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10641         if (!mode)
10642                 return NULL;
10643
10644         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10645         if (!crtc_state) {
10646                 kfree(mode);
10647                 return NULL;
10648         }
10649
10650         crtc_state->base.crtc = &crtc->base;
10651
10652         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10653                 kfree(crtc_state);
10654                 kfree(mode);
10655                 return NULL;
10656         }
10657
10658         encoder->get_config(encoder, crtc_state);
10659
10660         intel_mode_from_pipe_config(mode, crtc_state);
10661
10662         kfree(crtc_state);
10663
10664         return mode;
10665 }
10666
10667 static void intel_crtc_destroy(struct drm_crtc *crtc)
10668 {
10669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10670
10671         drm_crtc_cleanup(crtc);
10672         kfree(intel_crtc);
10673 }
10674
10675 /**
10676  * intel_wm_need_update - Check whether watermarks need updating
10677  * @plane: drm plane
10678  * @state: new plane state
10679  *
10680  * Check current plane state versus the new one to determine whether
10681  * watermarks need to be recalculated.
10682  *
10683  * Returns true or false.
10684  */
10685 static bool intel_wm_need_update(struct drm_plane *plane,
10686                                  struct drm_plane_state *state)
10687 {
10688         struct intel_plane_state *new = to_intel_plane_state(state);
10689         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10690
10691         /* Update watermarks on tiling or size changes. */
10692         if (new->base.visible != cur->base.visible)
10693                 return true;
10694
10695         if (!cur->base.fb || !new->base.fb)
10696                 return false;
10697
10698         if (cur->base.fb->modifier != new->base.fb->modifier ||
10699             cur->base.rotation != new->base.rotation ||
10700             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10701             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10702             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10703             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10704                 return true;
10705
10706         return false;
10707 }
10708
10709 static bool needs_scaling(const struct intel_plane_state *state)
10710 {
10711         int src_w = drm_rect_width(&state->base.src) >> 16;
10712         int src_h = drm_rect_height(&state->base.src) >> 16;
10713         int dst_w = drm_rect_width(&state->base.dst);
10714         int dst_h = drm_rect_height(&state->base.dst);
10715
10716         return (src_w != dst_w || src_h != dst_h);
10717 }
10718
10719 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10720                                     struct drm_crtc_state *crtc_state,
10721                                     const struct intel_plane_state *old_plane_state,
10722                                     struct drm_plane_state *plane_state)
10723 {
10724         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10725         struct drm_crtc *crtc = crtc_state->crtc;
10726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10727         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10728         struct drm_device *dev = crtc->dev;
10729         struct drm_i915_private *dev_priv = to_i915(dev);
10730         bool mode_changed = needs_modeset(crtc_state);
10731         bool was_crtc_enabled = old_crtc_state->base.active;
10732         bool is_crtc_enabled = crtc_state->active;
10733         bool turn_off, turn_on, visible, was_visible;
10734         struct drm_framebuffer *fb = plane_state->fb;
10735         int ret;
10736
10737         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10738                 ret = skl_update_scaler_plane(
10739                         to_intel_crtc_state(crtc_state),
10740                         to_intel_plane_state(plane_state));
10741                 if (ret)
10742                         return ret;
10743         }
10744
10745         was_visible = old_plane_state->base.visible;
10746         visible = plane_state->visible;
10747
10748         if (!was_crtc_enabled && WARN_ON(was_visible))
10749                 was_visible = false;
10750
10751         /*
10752          * Visibility is calculated as if the crtc was on, but
10753          * after scaler setup everything depends on it being off
10754          * when the crtc isn't active.
10755          *
10756          * FIXME this is wrong for watermarks. Watermarks should also
10757          * be computed as if the pipe would be active. Perhaps move
10758          * per-plane wm computation to the .check_plane() hook, and
10759          * only combine the results from all planes in the current place?
10760          */
10761         if (!is_crtc_enabled) {
10762                 plane_state->visible = visible = false;
10763                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10764         }
10765
10766         if (!was_visible && !visible)
10767                 return 0;
10768
10769         if (fb != old_plane_state->base.fb)
10770                 pipe_config->fb_changed = true;
10771
10772         turn_off = was_visible && (!visible || mode_changed);
10773         turn_on = visible && (!was_visible || mode_changed);
10774
10775         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10776                          intel_crtc->base.base.id, intel_crtc->base.name,
10777                          plane->base.base.id, plane->base.name,
10778                          fb ? fb->base.id : -1);
10779
10780         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10781                          plane->base.base.id, plane->base.name,
10782                          was_visible, visible,
10783                          turn_off, turn_on, mode_changed);
10784
10785         if (turn_on) {
10786                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10787                         pipe_config->update_wm_pre = true;
10788
10789                 /* must disable cxsr around plane enable/disable */
10790                 if (plane->id != PLANE_CURSOR)
10791                         pipe_config->disable_cxsr = true;
10792         } else if (turn_off) {
10793                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10794                         pipe_config->update_wm_post = true;
10795
10796                 /* must disable cxsr around plane enable/disable */
10797                 if (plane->id != PLANE_CURSOR)
10798                         pipe_config->disable_cxsr = true;
10799         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10800                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10801                         /* FIXME bollocks */
10802                         pipe_config->update_wm_pre = true;
10803                         pipe_config->update_wm_post = true;
10804                 }
10805         }
10806
10807         if (visible || was_visible)
10808                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10809
10810         /*
10811          * WaCxSRDisabledForSpriteScaling:ivb
10812          *
10813          * cstate->update_wm was already set above, so this flag will
10814          * take effect when we commit and program watermarks.
10815          */
10816         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10817             needs_scaling(to_intel_plane_state(plane_state)) &&
10818             !needs_scaling(old_plane_state))
10819                 pipe_config->disable_lp_wm = true;
10820
10821         return 0;
10822 }
10823
10824 static bool encoders_cloneable(const struct intel_encoder *a,
10825                                const struct intel_encoder *b)
10826 {
10827         /* masks could be asymmetric, so check both ways */
10828         return a == b || (a->cloneable & (1 << b->type) &&
10829                           b->cloneable & (1 << a->type));
10830 }
10831
10832 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10833                                          struct intel_crtc *crtc,
10834                                          struct intel_encoder *encoder)
10835 {
10836         struct intel_encoder *source_encoder;
10837         struct drm_connector *connector;
10838         struct drm_connector_state *connector_state;
10839         int i;
10840
10841         for_each_new_connector_in_state(state, connector, connector_state, i) {
10842                 if (connector_state->crtc != &crtc->base)
10843                         continue;
10844
10845                 source_encoder =
10846                         to_intel_encoder(connector_state->best_encoder);
10847                 if (!encoders_cloneable(encoder, source_encoder))
10848                         return false;
10849         }
10850
10851         return true;
10852 }
10853
10854 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10855                                    struct drm_crtc_state *crtc_state)
10856 {
10857         struct drm_device *dev = crtc->dev;
10858         struct drm_i915_private *dev_priv = to_i915(dev);
10859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10860         struct intel_crtc_state *pipe_config =
10861                 to_intel_crtc_state(crtc_state);
10862         struct drm_atomic_state *state = crtc_state->state;
10863         int ret;
10864         bool mode_changed = needs_modeset(crtc_state);
10865
10866         if (mode_changed && !crtc_state->active)
10867                 pipe_config->update_wm_post = true;
10868
10869         if (mode_changed && crtc_state->enable &&
10870             dev_priv->display.crtc_compute_clock &&
10871             !WARN_ON(pipe_config->shared_dpll)) {
10872                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10873                                                            pipe_config);
10874                 if (ret)
10875                         return ret;
10876         }
10877
10878         if (crtc_state->color_mgmt_changed) {
10879                 ret = intel_color_check(crtc, crtc_state);
10880                 if (ret)
10881                         return ret;
10882
10883                 /*
10884                  * Changing color management on Intel hardware is
10885                  * handled as part of planes update.
10886                  */
10887                 crtc_state->planes_changed = true;
10888         }
10889
10890         ret = 0;
10891         if (dev_priv->display.compute_pipe_wm) {
10892                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10893                 if (ret) {
10894                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10895                         return ret;
10896                 }
10897         }
10898
10899         if (dev_priv->display.compute_intermediate_wm &&
10900             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10901                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10902                         return 0;
10903
10904                 /*
10905                  * Calculate 'intermediate' watermarks that satisfy both the
10906                  * old state and the new state.  We can program these
10907                  * immediately.
10908                  */
10909                 ret = dev_priv->display.compute_intermediate_wm(dev,
10910                                                                 intel_crtc,
10911                                                                 pipe_config);
10912                 if (ret) {
10913                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10914                         return ret;
10915                 }
10916         } else if (dev_priv->display.compute_intermediate_wm) {
10917                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10918                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10919         }
10920
10921         if (INTEL_GEN(dev_priv) >= 9) {
10922                 if (mode_changed)
10923                         ret = skl_update_scaler_crtc(pipe_config);
10924
10925                 if (!ret)
10926                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10927                                                             pipe_config);
10928                 if (!ret)
10929                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10930                                                          pipe_config);
10931         }
10932
10933         if (HAS_IPS(dev_priv))
10934                 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10935
10936         return ret;
10937 }
10938
10939 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10940         .atomic_begin = intel_begin_crtc_commit,
10941         .atomic_flush = intel_finish_crtc_commit,
10942         .atomic_check = intel_crtc_atomic_check,
10943 };
10944
10945 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10946 {
10947         struct intel_connector *connector;
10948         struct drm_connector_list_iter conn_iter;
10949
10950         drm_connector_list_iter_begin(dev, &conn_iter);
10951         for_each_intel_connector_iter(connector, &conn_iter) {
10952                 if (connector->base.state->crtc)
10953                         drm_connector_put(&connector->base);
10954
10955                 if (connector->base.encoder) {
10956                         connector->base.state->best_encoder =
10957                                 connector->base.encoder;
10958                         connector->base.state->crtc =
10959                                 connector->base.encoder->crtc;
10960
10961                         drm_connector_get(&connector->base);
10962                 } else {
10963                         connector->base.state->best_encoder = NULL;
10964                         connector->base.state->crtc = NULL;
10965                 }
10966         }
10967         drm_connector_list_iter_end(&conn_iter);
10968 }
10969
10970 static void
10971 connected_sink_compute_bpp(struct intel_connector *connector,
10972                            struct intel_crtc_state *pipe_config)
10973 {
10974         const struct drm_display_info *info = &connector->base.display_info;
10975         int bpp = pipe_config->pipe_bpp;
10976
10977         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10978                       connector->base.base.id,
10979                       connector->base.name);
10980
10981         /* Don't use an invalid EDID bpc value */
10982         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10983                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10984                               bpp, info->bpc * 3);
10985                 pipe_config->pipe_bpp = info->bpc * 3;
10986         }
10987
10988         /* Clamp bpp to 8 on screens without EDID 1.4 */
10989         if (info->bpc == 0 && bpp > 24) {
10990                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10991                               bpp);
10992                 pipe_config->pipe_bpp = 24;
10993         }
10994 }
10995
10996 static int
10997 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10998                           struct intel_crtc_state *pipe_config)
10999 {
11000         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11001         struct drm_atomic_state *state;
11002         struct drm_connector *connector;
11003         struct drm_connector_state *connector_state;
11004         int bpp, i;
11005
11006         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11007             IS_CHERRYVIEW(dev_priv)))
11008                 bpp = 10*3;
11009         else if (INTEL_GEN(dev_priv) >= 5)
11010                 bpp = 12*3;
11011         else
11012                 bpp = 8*3;
11013
11014
11015         pipe_config->pipe_bpp = bpp;
11016
11017         state = pipe_config->base.state;
11018
11019         /* Clamp display bpp to EDID value */
11020         for_each_new_connector_in_state(state, connector, connector_state, i) {
11021                 if (connector_state->crtc != &crtc->base)
11022                         continue;
11023
11024                 connected_sink_compute_bpp(to_intel_connector(connector),
11025                                            pipe_config);
11026         }
11027
11028         return bpp;
11029 }
11030
11031 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11032 {
11033         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11034                         "type: 0x%x flags: 0x%x\n",
11035                 mode->crtc_clock,
11036                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11037                 mode->crtc_hsync_end, mode->crtc_htotal,
11038                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11039                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11040 }
11041
11042 static inline void
11043 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11044                       unsigned int lane_count, struct intel_link_m_n *m_n)
11045 {
11046         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11047                       id, lane_count,
11048                       m_n->gmch_m, m_n->gmch_n,
11049                       m_n->link_m, m_n->link_n, m_n->tu);
11050 }
11051
11052 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11053
11054 static const char * const output_type_str[] = {
11055         OUTPUT_TYPE(UNUSED),
11056         OUTPUT_TYPE(ANALOG),
11057         OUTPUT_TYPE(DVO),
11058         OUTPUT_TYPE(SDVO),
11059         OUTPUT_TYPE(LVDS),
11060         OUTPUT_TYPE(TVOUT),
11061         OUTPUT_TYPE(HDMI),
11062         OUTPUT_TYPE(DP),
11063         OUTPUT_TYPE(EDP),
11064         OUTPUT_TYPE(DSI),
11065         OUTPUT_TYPE(DDI),
11066         OUTPUT_TYPE(DP_MST),
11067 };
11068
11069 #undef OUTPUT_TYPE
11070
11071 static void snprintf_output_types(char *buf, size_t len,
11072                                   unsigned int output_types)
11073 {
11074         char *str = buf;
11075         int i;
11076
11077         str[0] = '\0';
11078
11079         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
11080                 int r;
11081
11082                 if ((output_types & BIT(i)) == 0)
11083                         continue;
11084
11085                 r = snprintf(str, len, "%s%s",
11086                              str != buf ? "," : "", output_type_str[i]);
11087                 if (r >= len)
11088                         break;
11089                 str += r;
11090                 len -= r;
11091
11092                 output_types &= ~BIT(i);
11093         }
11094
11095         WARN_ON_ONCE(output_types != 0);
11096 }
11097
11098 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11099                                    struct intel_crtc_state *pipe_config,
11100                                    const char *context)
11101 {
11102         struct drm_device *dev = crtc->base.dev;
11103         struct drm_i915_private *dev_priv = to_i915(dev);
11104         struct drm_plane *plane;
11105         struct intel_plane *intel_plane;
11106         struct intel_plane_state *state;
11107         struct drm_framebuffer *fb;
11108         char buf[64];
11109
11110         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11111                       crtc->base.base.id, crtc->base.name, context);
11112
11113         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
11114         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
11115                       buf, pipe_config->output_types);
11116
11117         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11118                       transcoder_name(pipe_config->cpu_transcoder),
11119                       pipe_config->pipe_bpp, pipe_config->dither);
11120
11121         if (pipe_config->has_pch_encoder)
11122                 intel_dump_m_n_config(pipe_config, "fdi",
11123                                       pipe_config->fdi_lanes,
11124                                       &pipe_config->fdi_m_n);
11125
11126         if (pipe_config->ycbcr420)
11127                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
11128
11129         if (intel_crtc_has_dp_encoder(pipe_config)) {
11130                 intel_dump_m_n_config(pipe_config, "dp m_n",
11131                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11132                 if (pipe_config->has_drrs)
11133                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11134                                               pipe_config->lane_count,
11135                                               &pipe_config->dp_m2_n2);
11136         }
11137
11138         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11139                       pipe_config->has_audio, pipe_config->has_infoframe);
11140
11141         DRM_DEBUG_KMS("requested mode:\n");
11142         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11143         DRM_DEBUG_KMS("adjusted mode:\n");
11144         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11145         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11146         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11147                       pipe_config->port_clock,
11148                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11149                       pipe_config->pixel_rate);
11150
11151         if (INTEL_GEN(dev_priv) >= 9)
11152                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11153                               crtc->num_scalers,
11154                               pipe_config->scaler_state.scaler_users,
11155                               pipe_config->scaler_state.scaler_id);
11156
11157         if (HAS_GMCH_DISPLAY(dev_priv))
11158                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11159                               pipe_config->gmch_pfit.control,
11160                               pipe_config->gmch_pfit.pgm_ratios,
11161                               pipe_config->gmch_pfit.lvds_border_bits);
11162         else
11163                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11164                               pipe_config->pch_pfit.pos,
11165                               pipe_config->pch_pfit.size,
11166                               enableddisabled(pipe_config->pch_pfit.enabled));
11167
11168         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11169                       pipe_config->ips_enabled, pipe_config->double_wide);
11170
11171         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11172
11173         DRM_DEBUG_KMS("planes on this crtc\n");
11174         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11175                 struct drm_format_name_buf format_name;
11176                 intel_plane = to_intel_plane(plane);
11177                 if (intel_plane->pipe != crtc->pipe)
11178                         continue;
11179
11180                 state = to_intel_plane_state(plane->state);
11181                 fb = state->base.fb;
11182                 if (!fb) {
11183                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11184                                       plane->base.id, plane->name, state->scaler_id);
11185                         continue;
11186                 }
11187
11188                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11189                               plane->base.id, plane->name,
11190                               fb->base.id, fb->width, fb->height,
11191                               drm_get_format_name(fb->format->format, &format_name));
11192                 if (INTEL_GEN(dev_priv) >= 9)
11193                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11194                                       state->scaler_id,
11195                                       state->base.src.x1 >> 16,
11196                                       state->base.src.y1 >> 16,
11197                                       drm_rect_width(&state->base.src) >> 16,
11198                                       drm_rect_height(&state->base.src) >> 16,
11199                                       state->base.dst.x1, state->base.dst.y1,
11200                                       drm_rect_width(&state->base.dst),
11201                                       drm_rect_height(&state->base.dst));
11202         }
11203 }
11204
11205 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11206 {
11207         struct drm_device *dev = state->dev;
11208         struct drm_connector *connector;
11209         struct drm_connector_list_iter conn_iter;
11210         unsigned int used_ports = 0;
11211         unsigned int used_mst_ports = 0;
11212         bool ret = true;
11213
11214         /*
11215          * Walk the connector list instead of the encoder
11216          * list to detect the problem on ddi platforms
11217          * where there's just one encoder per digital port.
11218          */
11219         drm_connector_list_iter_begin(dev, &conn_iter);
11220         drm_for_each_connector_iter(connector, &conn_iter) {
11221                 struct drm_connector_state *connector_state;
11222                 struct intel_encoder *encoder;
11223
11224                 connector_state = drm_atomic_get_new_connector_state(state, connector);
11225                 if (!connector_state)
11226                         connector_state = connector->state;
11227
11228                 if (!connector_state->best_encoder)
11229                         continue;
11230
11231                 encoder = to_intel_encoder(connector_state->best_encoder);
11232
11233                 WARN_ON(!connector_state->crtc);
11234
11235                 switch (encoder->type) {
11236                         unsigned int port_mask;
11237                 case INTEL_OUTPUT_DDI:
11238                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11239                                 break;
11240                         /* else: fall through */
11241                 case INTEL_OUTPUT_DP:
11242                 case INTEL_OUTPUT_HDMI:
11243                 case INTEL_OUTPUT_EDP:
11244                         port_mask = 1 << encoder->port;
11245
11246                         /* the same port mustn't appear more than once */
11247                         if (used_ports & port_mask)
11248                                 ret = false;
11249
11250                         used_ports |= port_mask;
11251                         break;
11252                 case INTEL_OUTPUT_DP_MST:
11253                         used_mst_ports |=
11254                                 1 << encoder->port;
11255                         break;
11256                 default:
11257                         break;
11258                 }
11259         }
11260         drm_connector_list_iter_end(&conn_iter);
11261
11262         /* can't mix MST and SST/HDMI on the same port */
11263         if (used_ports & used_mst_ports)
11264                 return false;
11265
11266         return ret;
11267 }
11268
11269 static void
11270 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11271 {
11272         struct drm_i915_private *dev_priv =
11273                 to_i915(crtc_state->base.crtc->dev);
11274         struct intel_crtc_scaler_state scaler_state;
11275         struct intel_dpll_hw_state dpll_hw_state;
11276         struct intel_shared_dpll *shared_dpll;
11277         struct intel_crtc_wm_state wm_state;
11278         bool force_thru, ips_force_disable;
11279
11280         /* FIXME: before the switch to atomic started, a new pipe_config was
11281          * kzalloc'd. Code that depends on any field being zero should be
11282          * fixed, so that the crtc_state can be safely duplicated. For now,
11283          * only fields that are know to not cause problems are preserved. */
11284
11285         scaler_state = crtc_state->scaler_state;
11286         shared_dpll = crtc_state->shared_dpll;
11287         dpll_hw_state = crtc_state->dpll_hw_state;
11288         force_thru = crtc_state->pch_pfit.force_thru;
11289         ips_force_disable = crtc_state->ips_force_disable;
11290         if (IS_G4X(dev_priv) ||
11291             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11292                 wm_state = crtc_state->wm;
11293
11294         /* Keep base drm_crtc_state intact, only clear our extended struct */
11295         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11296         memset(&crtc_state->base + 1, 0,
11297                sizeof(*crtc_state) - sizeof(crtc_state->base));
11298
11299         crtc_state->scaler_state = scaler_state;
11300         crtc_state->shared_dpll = shared_dpll;
11301         crtc_state->dpll_hw_state = dpll_hw_state;
11302         crtc_state->pch_pfit.force_thru = force_thru;
11303         crtc_state->ips_force_disable = ips_force_disable;
11304         if (IS_G4X(dev_priv) ||
11305             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11306                 crtc_state->wm = wm_state;
11307 }
11308
11309 static int
11310 intel_modeset_pipe_config(struct drm_crtc *crtc,
11311                           struct intel_crtc_state *pipe_config)
11312 {
11313         struct drm_atomic_state *state = pipe_config->base.state;
11314         struct intel_encoder *encoder;
11315         struct drm_connector *connector;
11316         struct drm_connector_state *connector_state;
11317         int base_bpp, ret = -EINVAL;
11318         int i;
11319         bool retry = true;
11320
11321         clear_intel_crtc_state(pipe_config);
11322
11323         pipe_config->cpu_transcoder =
11324                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11325
11326         /*
11327          * Sanitize sync polarity flags based on requested ones. If neither
11328          * positive or negative polarity is requested, treat this as meaning
11329          * negative polarity.
11330          */
11331         if (!(pipe_config->base.adjusted_mode.flags &
11332               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11333                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11334
11335         if (!(pipe_config->base.adjusted_mode.flags &
11336               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11337                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11338
11339         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11340                                              pipe_config);
11341         if (base_bpp < 0)
11342                 goto fail;
11343
11344         /*
11345          * Determine the real pipe dimensions. Note that stereo modes can
11346          * increase the actual pipe size due to the frame doubling and
11347          * insertion of additional space for blanks between the frame. This
11348          * is stored in the crtc timings. We use the requested mode to do this
11349          * computation to clearly distinguish it from the adjusted mode, which
11350          * can be changed by the connectors in the below retry loop.
11351          */
11352         drm_mode_get_hv_timing(&pipe_config->base.mode,
11353                                &pipe_config->pipe_src_w,
11354                                &pipe_config->pipe_src_h);
11355
11356         for_each_new_connector_in_state(state, connector, connector_state, i) {
11357                 if (connector_state->crtc != crtc)
11358                         continue;
11359
11360                 encoder = to_intel_encoder(connector_state->best_encoder);
11361
11362                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11363                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11364                         goto fail;
11365                 }
11366
11367                 /*
11368                  * Determine output_types before calling the .compute_config()
11369                  * hooks so that the hooks can use this information safely.
11370                  */
11371                 if (encoder->compute_output_type)
11372                         pipe_config->output_types |=
11373                                 BIT(encoder->compute_output_type(encoder, pipe_config,
11374                                                                  connector_state));
11375                 else
11376                         pipe_config->output_types |= BIT(encoder->type);
11377         }
11378
11379 encoder_retry:
11380         /* Ensure the port clock defaults are reset when retrying. */
11381         pipe_config->port_clock = 0;
11382         pipe_config->pixel_multiplier = 1;
11383
11384         /* Fill in default crtc timings, allow encoders to overwrite them. */
11385         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11386                               CRTC_STEREO_DOUBLE);
11387
11388         /* Pass our mode to the connectors and the CRTC to give them a chance to
11389          * adjust it according to limitations or connector properties, and also
11390          * a chance to reject the mode entirely.
11391          */
11392         for_each_new_connector_in_state(state, connector, connector_state, i) {
11393                 if (connector_state->crtc != crtc)
11394                         continue;
11395
11396                 encoder = to_intel_encoder(connector_state->best_encoder);
11397
11398                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11399                         DRM_DEBUG_KMS("Encoder config failure\n");
11400                         goto fail;
11401                 }
11402         }
11403
11404         /* Set default port clock if not overwritten by the encoder. Needs to be
11405          * done afterwards in case the encoder adjusts the mode. */
11406         if (!pipe_config->port_clock)
11407                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11408                         * pipe_config->pixel_multiplier;
11409
11410         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11411         if (ret < 0) {
11412                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11413                 goto fail;
11414         }
11415
11416         if (ret == RETRY) {
11417                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11418                         ret = -EINVAL;
11419                         goto fail;
11420                 }
11421
11422                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11423                 retry = false;
11424                 goto encoder_retry;
11425         }
11426
11427         /* Dithering seems to not pass-through bits correctly when it should, so
11428          * only enable it on 6bpc panels and when its not a compliance
11429          * test requesting 6bpc video pattern.
11430          */
11431         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11432                 !pipe_config->dither_force_disable;
11433         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11434                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11435
11436 fail:
11437         return ret;
11438 }
11439
11440 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11441 {
11442         int diff;
11443
11444         if (clock1 == clock2)
11445                 return true;
11446
11447         if (!clock1 || !clock2)
11448                 return false;
11449
11450         diff = abs(clock1 - clock2);
11451
11452         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11453                 return true;
11454
11455         return false;
11456 }
11457
11458 static bool
11459 intel_compare_m_n(unsigned int m, unsigned int n,
11460                   unsigned int m2, unsigned int n2,
11461                   bool exact)
11462 {
11463         if (m == m2 && n == n2)
11464                 return true;
11465
11466         if (exact || !m || !n || !m2 || !n2)
11467                 return false;
11468
11469         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11470
11471         if (n > n2) {
11472                 while (n > n2) {
11473                         m2 <<= 1;
11474                         n2 <<= 1;
11475                 }
11476         } else if (n < n2) {
11477                 while (n < n2) {
11478                         m <<= 1;
11479                         n <<= 1;
11480                 }
11481         }
11482
11483         if (n != n2)
11484                 return false;
11485
11486         return intel_fuzzy_clock_check(m, m2);
11487 }
11488
11489 static bool
11490 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11491                        struct intel_link_m_n *m2_n2,
11492                        bool adjust)
11493 {
11494         if (m_n->tu == m2_n2->tu &&
11495             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11496                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11497             intel_compare_m_n(m_n->link_m, m_n->link_n,
11498                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11499                 if (adjust)
11500                         *m2_n2 = *m_n;
11501
11502                 return true;
11503         }
11504
11505         return false;
11506 }
11507
11508 static void __printf(3, 4)
11509 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11510 {
11511         struct va_format vaf;
11512         va_list args;
11513
11514         va_start(args, format);
11515         vaf.fmt = format;
11516         vaf.va = &args;
11517
11518         if (adjust)
11519                 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11520         else
11521                 drm_err("mismatch in %s %pV", name, &vaf);
11522
11523         va_end(args);
11524 }
11525
11526 static bool
11527 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11528                           struct intel_crtc_state *current_config,
11529                           struct intel_crtc_state *pipe_config,
11530                           bool adjust)
11531 {
11532         bool ret = true;
11533         bool fixup_inherited = adjust &&
11534                 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11535                 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11536
11537 #define PIPE_CONF_CHECK_X(name) do { \
11538         if (current_config->name != pipe_config->name) { \
11539                 pipe_config_err(adjust, __stringify(name), \
11540                           "(expected 0x%08x, found 0x%08x)\n", \
11541                           current_config->name, \
11542                           pipe_config->name); \
11543                 ret = false; \
11544         } \
11545 } while (0)
11546
11547 #define PIPE_CONF_CHECK_I(name) do { \
11548         if (current_config->name != pipe_config->name) { \
11549                 pipe_config_err(adjust, __stringify(name), \
11550                           "(expected %i, found %i)\n", \
11551                           current_config->name, \
11552                           pipe_config->name); \
11553                 ret = false; \
11554         } \
11555 } while (0)
11556
11557 #define PIPE_CONF_CHECK_BOOL(name) do { \
11558         if (current_config->name != pipe_config->name) { \
11559                 pipe_config_err(adjust, __stringify(name), \
11560                           "(expected %s, found %s)\n", \
11561                           yesno(current_config->name), \
11562                           yesno(pipe_config->name)); \
11563                 ret = false; \
11564         } \
11565 } while (0)
11566
11567 /*
11568  * Checks state where we only read out the enabling, but not the entire
11569  * state itself (like full infoframes or ELD for audio). These states
11570  * require a full modeset on bootup to fix up.
11571  */
11572 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11573         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11574                 PIPE_CONF_CHECK_BOOL(name); \
11575         } else { \
11576                 pipe_config_err(adjust, __stringify(name), \
11577                           "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11578                           yesno(current_config->name), \
11579                           yesno(pipe_config->name)); \
11580                 ret = false; \
11581         } \
11582 } while (0)
11583
11584 #define PIPE_CONF_CHECK_P(name) do { \
11585         if (current_config->name != pipe_config->name) { \
11586                 pipe_config_err(adjust, __stringify(name), \
11587                           "(expected %p, found %p)\n", \
11588                           current_config->name, \
11589                           pipe_config->name); \
11590                 ret = false; \
11591         } \
11592 } while (0)
11593
11594 #define PIPE_CONF_CHECK_M_N(name) do { \
11595         if (!intel_compare_link_m_n(&current_config->name, \
11596                                     &pipe_config->name,\
11597                                     adjust)) { \
11598                 pipe_config_err(adjust, __stringify(name), \
11599                           "(expected tu %i gmch %i/%i link %i/%i, " \
11600                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11601                           current_config->name.tu, \
11602                           current_config->name.gmch_m, \
11603                           current_config->name.gmch_n, \
11604                           current_config->name.link_m, \
11605                           current_config->name.link_n, \
11606                           pipe_config->name.tu, \
11607                           pipe_config->name.gmch_m, \
11608                           pipe_config->name.gmch_n, \
11609                           pipe_config->name.link_m, \
11610                           pipe_config->name.link_n); \
11611                 ret = false; \
11612         } \
11613 } while (0)
11614
11615 /* This is required for BDW+ where there is only one set of registers for
11616  * switching between high and low RR.
11617  * This macro can be used whenever a comparison has to be made between one
11618  * hw state and multiple sw state variables.
11619  */
11620 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11621         if (!intel_compare_link_m_n(&current_config->name, \
11622                                     &pipe_config->name, adjust) && \
11623             !intel_compare_link_m_n(&current_config->alt_name, \
11624                                     &pipe_config->name, adjust)) { \
11625                 pipe_config_err(adjust, __stringify(name), \
11626                           "(expected tu %i gmch %i/%i link %i/%i, " \
11627                           "or tu %i gmch %i/%i link %i/%i, " \
11628                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11629                           current_config->name.tu, \
11630                           current_config->name.gmch_m, \
11631                           current_config->name.gmch_n, \
11632                           current_config->name.link_m, \
11633                           current_config->name.link_n, \
11634                           current_config->alt_name.tu, \
11635                           current_config->alt_name.gmch_m, \
11636                           current_config->alt_name.gmch_n, \
11637                           current_config->alt_name.link_m, \
11638                           current_config->alt_name.link_n, \
11639                           pipe_config->name.tu, \
11640                           pipe_config->name.gmch_m, \
11641                           pipe_config->name.gmch_n, \
11642                           pipe_config->name.link_m, \
11643                           pipe_config->name.link_n); \
11644                 ret = false; \
11645         } \
11646 } while (0)
11647
11648 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11649         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11650                 pipe_config_err(adjust, __stringify(name), \
11651                           "(%x) (expected %i, found %i)\n", \
11652                           (mask), \
11653                           current_config->name & (mask), \
11654                           pipe_config->name & (mask)); \
11655                 ret = false; \
11656         } \
11657 } while (0)
11658
11659 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11660         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11661                 pipe_config_err(adjust, __stringify(name), \
11662                           "(expected %i, found %i)\n", \
11663                           current_config->name, \
11664                           pipe_config->name); \
11665                 ret = false; \
11666         } \
11667 } while (0)
11668
11669 #define PIPE_CONF_QUIRK(quirk)  \
11670         ((current_config->quirks | pipe_config->quirks) & (quirk))
11671
11672         PIPE_CONF_CHECK_I(cpu_transcoder);
11673
11674         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11675         PIPE_CONF_CHECK_I(fdi_lanes);
11676         PIPE_CONF_CHECK_M_N(fdi_m_n);
11677
11678         PIPE_CONF_CHECK_I(lane_count);
11679         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11680
11681         if (INTEL_GEN(dev_priv) < 8) {
11682                 PIPE_CONF_CHECK_M_N(dp_m_n);
11683
11684                 if (current_config->has_drrs)
11685                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11686         } else
11687                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11688
11689         PIPE_CONF_CHECK_X(output_types);
11690
11691         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11692         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11693         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11694         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11695         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11696         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11697
11698         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11699         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11700         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11701         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11702         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11703         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11704
11705         PIPE_CONF_CHECK_I(pixel_multiplier);
11706         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11707         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11708             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11709                 PIPE_CONF_CHECK_BOOL(limited_color_range);
11710
11711         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11712         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11713         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11714         PIPE_CONF_CHECK_BOOL(ycbcr420);
11715
11716         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11717
11718         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11719                               DRM_MODE_FLAG_INTERLACE);
11720
11721         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11722                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11723                                       DRM_MODE_FLAG_PHSYNC);
11724                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11725                                       DRM_MODE_FLAG_NHSYNC);
11726                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11727                                       DRM_MODE_FLAG_PVSYNC);
11728                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11729                                       DRM_MODE_FLAG_NVSYNC);
11730         }
11731
11732         PIPE_CONF_CHECK_X(gmch_pfit.control);
11733         /* pfit ratios are autocomputed by the hw on gen4+ */
11734         if (INTEL_GEN(dev_priv) < 4)
11735                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11736         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11737
11738         if (!adjust) {
11739                 PIPE_CONF_CHECK_I(pipe_src_w);
11740                 PIPE_CONF_CHECK_I(pipe_src_h);
11741
11742                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11743                 if (current_config->pch_pfit.enabled) {
11744                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11745                         PIPE_CONF_CHECK_X(pch_pfit.size);
11746                 }
11747
11748                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11749                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11750         }
11751
11752         PIPE_CONF_CHECK_BOOL(double_wide);
11753
11754         PIPE_CONF_CHECK_P(shared_dpll);
11755         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11756         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11757         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11758         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11759         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11760         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11761         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11762         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11763         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11764         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11765         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11766         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11767         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11768         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11769         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11770         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11771         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11772         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11773         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11774         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11775         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11776         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11777         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11778         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11779         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11780         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11781         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11782         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11783         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11784         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11785         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11786
11787         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11788         PIPE_CONF_CHECK_X(dsi_pll.div);
11789
11790         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11791                 PIPE_CONF_CHECK_I(pipe_bpp);
11792
11793         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11794         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11795
11796         PIPE_CONF_CHECK_I(min_voltage_level);
11797
11798 #undef PIPE_CONF_CHECK_X
11799 #undef PIPE_CONF_CHECK_I
11800 #undef PIPE_CONF_CHECK_BOOL
11801 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11802 #undef PIPE_CONF_CHECK_P
11803 #undef PIPE_CONF_CHECK_FLAGS
11804 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11805 #undef PIPE_CONF_QUIRK
11806
11807         return ret;
11808 }
11809
11810 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11811                                            const struct intel_crtc_state *pipe_config)
11812 {
11813         if (pipe_config->has_pch_encoder) {
11814                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11815                                                             &pipe_config->fdi_m_n);
11816                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11817
11818                 /*
11819                  * FDI already provided one idea for the dotclock.
11820                  * Yell if the encoder disagrees.
11821                  */
11822                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11823                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11824                      fdi_dotclock, dotclock);
11825         }
11826 }
11827
11828 static void verify_wm_state(struct drm_crtc *crtc,
11829                             struct drm_crtc_state *new_state)
11830 {
11831         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11832         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11833         struct skl_pipe_wm hw_wm, *sw_wm;
11834         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11835         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11837         const enum pipe pipe = intel_crtc->pipe;
11838         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11839
11840         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11841                 return;
11842
11843         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11844         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11845
11846         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11847         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11848
11849         if (INTEL_GEN(dev_priv) >= 11)
11850                 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11851                         DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11852                                   sw_ddb->enabled_slices,
11853                                   hw_ddb.enabled_slices);
11854         /* planes */
11855         for_each_universal_plane(dev_priv, pipe, plane) {
11856                 hw_plane_wm = &hw_wm.planes[plane];
11857                 sw_plane_wm = &sw_wm->planes[plane];
11858
11859                 /* Watermarks */
11860                 for (level = 0; level <= max_level; level++) {
11861                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11862                                                 &sw_plane_wm->wm[level]))
11863                                 continue;
11864
11865                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11866                                   pipe_name(pipe), plane + 1, level,
11867                                   sw_plane_wm->wm[level].plane_en,
11868                                   sw_plane_wm->wm[level].plane_res_b,
11869                                   sw_plane_wm->wm[level].plane_res_l,
11870                                   hw_plane_wm->wm[level].plane_en,
11871                                   hw_plane_wm->wm[level].plane_res_b,
11872                                   hw_plane_wm->wm[level].plane_res_l);
11873                 }
11874
11875                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11876                                          &sw_plane_wm->trans_wm)) {
11877                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11878                                   pipe_name(pipe), plane + 1,
11879                                   sw_plane_wm->trans_wm.plane_en,
11880                                   sw_plane_wm->trans_wm.plane_res_b,
11881                                   sw_plane_wm->trans_wm.plane_res_l,
11882                                   hw_plane_wm->trans_wm.plane_en,
11883                                   hw_plane_wm->trans_wm.plane_res_b,
11884                                   hw_plane_wm->trans_wm.plane_res_l);
11885                 }
11886
11887                 /* DDB */
11888                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11889                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11890
11891                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11892                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11893                                   pipe_name(pipe), plane + 1,
11894                                   sw_ddb_entry->start, sw_ddb_entry->end,
11895                                   hw_ddb_entry->start, hw_ddb_entry->end);
11896                 }
11897         }
11898
11899         /*
11900          * cursor
11901          * If the cursor plane isn't active, we may not have updated it's ddb
11902          * allocation. In that case since the ddb allocation will be updated
11903          * once the plane becomes visible, we can skip this check
11904          */
11905         if (1) {
11906                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11907                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11908
11909                 /* Watermarks */
11910                 for (level = 0; level <= max_level; level++) {
11911                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11912                                                 &sw_plane_wm->wm[level]))
11913                                 continue;
11914
11915                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11916                                   pipe_name(pipe), level,
11917                                   sw_plane_wm->wm[level].plane_en,
11918                                   sw_plane_wm->wm[level].plane_res_b,
11919                                   sw_plane_wm->wm[level].plane_res_l,
11920                                   hw_plane_wm->wm[level].plane_en,
11921                                   hw_plane_wm->wm[level].plane_res_b,
11922                                   hw_plane_wm->wm[level].plane_res_l);
11923                 }
11924
11925                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11926                                          &sw_plane_wm->trans_wm)) {
11927                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11928                                   pipe_name(pipe),
11929                                   sw_plane_wm->trans_wm.plane_en,
11930                                   sw_plane_wm->trans_wm.plane_res_b,
11931                                   sw_plane_wm->trans_wm.plane_res_l,
11932                                   hw_plane_wm->trans_wm.plane_en,
11933                                   hw_plane_wm->trans_wm.plane_res_b,
11934                                   hw_plane_wm->trans_wm.plane_res_l);
11935                 }
11936
11937                 /* DDB */
11938                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11939                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11940
11941                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11942                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11943                                   pipe_name(pipe),
11944                                   sw_ddb_entry->start, sw_ddb_entry->end,
11945                                   hw_ddb_entry->start, hw_ddb_entry->end);
11946                 }
11947         }
11948 }
11949
11950 static void
11951 verify_connector_state(struct drm_device *dev,
11952                        struct drm_atomic_state *state,
11953                        struct drm_crtc *crtc)
11954 {
11955         struct drm_connector *connector;
11956         struct drm_connector_state *new_conn_state;
11957         int i;
11958
11959         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11960                 struct drm_encoder *encoder = connector->encoder;
11961                 struct drm_crtc_state *crtc_state = NULL;
11962
11963                 if (new_conn_state->crtc != crtc)
11964                         continue;
11965
11966                 if (crtc)
11967                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11968
11969                 intel_connector_verify_state(crtc_state, new_conn_state);
11970
11971                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11972                      "connector's atomic encoder doesn't match legacy encoder\n");
11973         }
11974 }
11975
11976 static void
11977 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11978 {
11979         struct intel_encoder *encoder;
11980         struct drm_connector *connector;
11981         struct drm_connector_state *old_conn_state, *new_conn_state;
11982         int i;
11983
11984         for_each_intel_encoder(dev, encoder) {
11985                 bool enabled = false, found = false;
11986                 enum pipe pipe;
11987
11988                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11989                               encoder->base.base.id,
11990                               encoder->base.name);
11991
11992                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11993                                                    new_conn_state, i) {
11994                         if (old_conn_state->best_encoder == &encoder->base)
11995                                 found = true;
11996
11997                         if (new_conn_state->best_encoder != &encoder->base)
11998                                 continue;
11999                         found = enabled = true;
12000
12001                         I915_STATE_WARN(new_conn_state->crtc !=
12002                                         encoder->base.crtc,
12003                              "connector's crtc doesn't match encoder crtc\n");
12004                 }
12005
12006                 if (!found)
12007                         continue;
12008
12009                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12010                      "encoder's enabled state mismatch "
12011                      "(expected %i, found %i)\n",
12012                      !!encoder->base.crtc, enabled);
12013
12014                 if (!encoder->base.crtc) {
12015                         bool active;
12016
12017                         active = encoder->get_hw_state(encoder, &pipe);
12018                         I915_STATE_WARN(active,
12019                              "encoder detached but still enabled on pipe %c.\n",
12020                              pipe_name(pipe));
12021                 }
12022         }
12023 }
12024
12025 static void
12026 verify_crtc_state(struct drm_crtc *crtc,
12027                   struct drm_crtc_state *old_crtc_state,
12028                   struct drm_crtc_state *new_crtc_state)
12029 {
12030         struct drm_device *dev = crtc->dev;
12031         struct drm_i915_private *dev_priv = to_i915(dev);
12032         struct intel_encoder *encoder;
12033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12034         struct intel_crtc_state *pipe_config, *sw_config;
12035         struct drm_atomic_state *old_state;
12036         bool active;
12037
12038         old_state = old_crtc_state->state;
12039         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12040         pipe_config = to_intel_crtc_state(old_crtc_state);
12041         memset(pipe_config, 0, sizeof(*pipe_config));
12042         pipe_config->base.crtc = crtc;
12043         pipe_config->base.state = old_state;
12044
12045         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12046
12047         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12048
12049         /* we keep both pipes enabled on 830 */
12050         if (IS_I830(dev_priv))
12051                 active = new_crtc_state->active;
12052
12053         I915_STATE_WARN(new_crtc_state->active != active,
12054              "crtc active state doesn't match with hw state "
12055              "(expected %i, found %i)\n", new_crtc_state->active, active);
12056
12057         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12058              "transitional active state does not match atomic hw state "
12059              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12060
12061         for_each_encoder_on_crtc(dev, crtc, encoder) {
12062                 enum pipe pipe;
12063
12064                 active = encoder->get_hw_state(encoder, &pipe);
12065                 I915_STATE_WARN(active != new_crtc_state->active,
12066                         "[ENCODER:%i] active %i with crtc active %i\n",
12067                         encoder->base.base.id, active, new_crtc_state->active);
12068
12069                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12070                                 "Encoder connected to wrong pipe %c\n",
12071                                 pipe_name(pipe));
12072
12073                 if (active)
12074                         encoder->get_config(encoder, pipe_config);
12075         }
12076
12077         intel_crtc_compute_pixel_rate(pipe_config);
12078
12079         if (!new_crtc_state->active)
12080                 return;
12081
12082         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12083
12084         sw_config = to_intel_crtc_state(new_crtc_state);
12085         if (!intel_pipe_config_compare(dev_priv, sw_config,
12086                                        pipe_config, false)) {
12087                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12088                 intel_dump_pipe_config(intel_crtc, pipe_config,
12089                                        "[hw state]");
12090                 intel_dump_pipe_config(intel_crtc, sw_config,
12091                                        "[sw state]");
12092         }
12093 }
12094
12095 static void
12096 intel_verify_planes(struct intel_atomic_state *state)
12097 {
12098         struct intel_plane *plane;
12099         const struct intel_plane_state *plane_state;
12100         int i;
12101
12102         for_each_new_intel_plane_in_state(state, plane,
12103                                           plane_state, i)
12104                 assert_plane(plane, plane_state->base.visible);
12105 }
12106
12107 static void
12108 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12109                          struct intel_shared_dpll *pll,
12110                          struct drm_crtc *crtc,
12111                          struct drm_crtc_state *new_state)
12112 {
12113         struct intel_dpll_hw_state dpll_hw_state;
12114         unsigned int crtc_mask;
12115         bool active;
12116
12117         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12118
12119         DRM_DEBUG_KMS("%s\n", pll->info->name);
12120
12121         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
12122
12123         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
12124                 I915_STATE_WARN(!pll->on && pll->active_mask,
12125                      "pll in active use but not on in sw tracking\n");
12126                 I915_STATE_WARN(pll->on && !pll->active_mask,
12127                      "pll is on but not used by any active crtc\n");
12128                 I915_STATE_WARN(pll->on != active,
12129                      "pll on state mismatch (expected %i, found %i)\n",
12130                      pll->on, active);
12131         }
12132
12133         if (!crtc) {
12134                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12135                                 "more active pll users than references: %x vs %x\n",
12136                                 pll->active_mask, pll->state.crtc_mask);
12137
12138                 return;
12139         }
12140
12141         crtc_mask = drm_crtc_mask(crtc);
12142
12143         if (new_state->active)
12144                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12145                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12146                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12147         else
12148                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12149                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12150                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12151
12152         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12153                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12154                         crtc_mask, pll->state.crtc_mask);
12155
12156         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12157                                           &dpll_hw_state,
12158                                           sizeof(dpll_hw_state)),
12159                         "pll hw state mismatch\n");
12160 }
12161
12162 static void
12163 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12164                          struct drm_crtc_state *old_crtc_state,
12165                          struct drm_crtc_state *new_crtc_state)
12166 {
12167         struct drm_i915_private *dev_priv = to_i915(dev);
12168         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12169         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12170
12171         if (new_state->shared_dpll)
12172                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12173
12174         if (old_state->shared_dpll &&
12175             old_state->shared_dpll != new_state->shared_dpll) {
12176                 unsigned int crtc_mask = drm_crtc_mask(crtc);
12177                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12178
12179                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12180                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12181                                 pipe_name(drm_crtc_index(crtc)));
12182                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12183                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12184                                 pipe_name(drm_crtc_index(crtc)));
12185         }
12186 }
12187
12188 static void
12189 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12190                           struct drm_atomic_state *state,
12191                           struct drm_crtc_state *old_state,
12192                           struct drm_crtc_state *new_state)
12193 {
12194         if (!needs_modeset(new_state) &&
12195             !to_intel_crtc_state(new_state)->update_pipe)
12196                 return;
12197
12198         verify_wm_state(crtc, new_state);
12199         verify_connector_state(crtc->dev, state, crtc);
12200         verify_crtc_state(crtc, old_state, new_state);
12201         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12202 }
12203
12204 static void
12205 verify_disabled_dpll_state(struct drm_device *dev)
12206 {
12207         struct drm_i915_private *dev_priv = to_i915(dev);
12208         int i;
12209
12210         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12211                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12212 }
12213
12214 static void
12215 intel_modeset_verify_disabled(struct drm_device *dev,
12216                               struct drm_atomic_state *state)
12217 {
12218         verify_encoder_state(dev, state);
12219         verify_connector_state(dev, state, NULL);
12220         verify_disabled_dpll_state(dev);
12221 }
12222
12223 static void update_scanline_offset(struct intel_crtc *crtc)
12224 {
12225         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12226
12227         /*
12228          * The scanline counter increments at the leading edge of hsync.
12229          *
12230          * On most platforms it starts counting from vtotal-1 on the
12231          * first active line. That means the scanline counter value is
12232          * always one less than what we would expect. Ie. just after
12233          * start of vblank, which also occurs at start of hsync (on the
12234          * last active line), the scanline counter will read vblank_start-1.
12235          *
12236          * On gen2 the scanline counter starts counting from 1 instead
12237          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12238          * to keep the value positive), instead of adding one.
12239          *
12240          * On HSW+ the behaviour of the scanline counter depends on the output
12241          * type. For DP ports it behaves like most other platforms, but on HDMI
12242          * there's an extra 1 line difference. So we need to add two instead of
12243          * one to the value.
12244          *
12245          * On VLV/CHV DSI the scanline counter would appear to increment
12246          * approx. 1/3 of a scanline before start of vblank. Unfortunately
12247          * that means we can't tell whether we're in vblank or not while
12248          * we're on that particular line. We must still set scanline_offset
12249          * to 1 so that the vblank timestamps come out correct when we query
12250          * the scanline counter from within the vblank interrupt handler.
12251          * However if queried just before the start of vblank we'll get an
12252          * answer that's slightly in the future.
12253          */
12254         if (IS_GEN2(dev_priv)) {
12255                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12256                 int vtotal;
12257
12258                 vtotal = adjusted_mode->crtc_vtotal;
12259                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12260                         vtotal /= 2;
12261
12262                 crtc->scanline_offset = vtotal - 1;
12263         } else if (HAS_DDI(dev_priv) &&
12264                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12265                 crtc->scanline_offset = 2;
12266         } else
12267                 crtc->scanline_offset = 1;
12268 }
12269
12270 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12271 {
12272         struct drm_device *dev = state->dev;
12273         struct drm_i915_private *dev_priv = to_i915(dev);
12274         struct drm_crtc *crtc;
12275         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12276         int i;
12277
12278         if (!dev_priv->display.crtc_compute_clock)
12279                 return;
12280
12281         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12282                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12283                 struct intel_shared_dpll *old_dpll =
12284                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12285
12286                 if (!needs_modeset(new_crtc_state))
12287                         continue;
12288
12289                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12290
12291                 if (!old_dpll)
12292                         continue;
12293
12294                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12295         }
12296 }
12297
12298 /*
12299  * This implements the workaround described in the "notes" section of the mode
12300  * set sequence documentation. When going from no pipes or single pipe to
12301  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12302  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12303  */
12304 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12305 {
12306         struct drm_crtc_state *crtc_state;
12307         struct intel_crtc *intel_crtc;
12308         struct drm_crtc *crtc;
12309         struct intel_crtc_state *first_crtc_state = NULL;
12310         struct intel_crtc_state *other_crtc_state = NULL;
12311         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12312         int i;
12313
12314         /* look at all crtc's that are going to be enabled in during modeset */
12315         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12316                 intel_crtc = to_intel_crtc(crtc);
12317
12318                 if (!crtc_state->active || !needs_modeset(crtc_state))
12319                         continue;
12320
12321                 if (first_crtc_state) {
12322                         other_crtc_state = to_intel_crtc_state(crtc_state);
12323                         break;
12324                 } else {
12325                         first_crtc_state = to_intel_crtc_state(crtc_state);
12326                         first_pipe = intel_crtc->pipe;
12327                 }
12328         }
12329
12330         /* No workaround needed? */
12331         if (!first_crtc_state)
12332                 return 0;
12333
12334         /* w/a possibly needed, check how many crtc's are already enabled. */
12335         for_each_intel_crtc(state->dev, intel_crtc) {
12336                 struct intel_crtc_state *pipe_config;
12337
12338                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12339                 if (IS_ERR(pipe_config))
12340                         return PTR_ERR(pipe_config);
12341
12342                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12343
12344                 if (!pipe_config->base.active ||
12345                     needs_modeset(&pipe_config->base))
12346                         continue;
12347
12348                 /* 2 or more enabled crtcs means no need for w/a */
12349                 if (enabled_pipe != INVALID_PIPE)
12350                         return 0;
12351
12352                 enabled_pipe = intel_crtc->pipe;
12353         }
12354
12355         if (enabled_pipe != INVALID_PIPE)
12356                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12357         else if (other_crtc_state)
12358                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12359
12360         return 0;
12361 }
12362
12363 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12364 {
12365         struct drm_crtc *crtc;
12366
12367         /* Add all pipes to the state */
12368         for_each_crtc(state->dev, crtc) {
12369                 struct drm_crtc_state *crtc_state;
12370
12371                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12372                 if (IS_ERR(crtc_state))
12373                         return PTR_ERR(crtc_state);
12374         }
12375
12376         return 0;
12377 }
12378
12379 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12380 {
12381         struct drm_crtc *crtc;
12382
12383         /*
12384          * Add all pipes to the state, and force
12385          * a modeset on all the active ones.
12386          */
12387         for_each_crtc(state->dev, crtc) {
12388                 struct drm_crtc_state *crtc_state;
12389                 int ret;
12390
12391                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12392                 if (IS_ERR(crtc_state))
12393                         return PTR_ERR(crtc_state);
12394
12395                 if (!crtc_state->active || needs_modeset(crtc_state))
12396                         continue;
12397
12398                 crtc_state->mode_changed = true;
12399
12400                 ret = drm_atomic_add_affected_connectors(state, crtc);
12401                 if (ret)
12402                         return ret;
12403
12404                 ret = drm_atomic_add_affected_planes(state, crtc);
12405                 if (ret)
12406                         return ret;
12407         }
12408
12409         return 0;
12410 }
12411
12412 static int intel_modeset_checks(struct drm_atomic_state *state)
12413 {
12414         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12415         struct drm_i915_private *dev_priv = to_i915(state->dev);
12416         struct drm_crtc *crtc;
12417         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12418         int ret = 0, i;
12419
12420         if (!check_digital_port_conflicts(state)) {
12421                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12422                 return -EINVAL;
12423         }
12424
12425         intel_state->modeset = true;
12426         intel_state->active_crtcs = dev_priv->active_crtcs;
12427         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12428         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12429
12430         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12431                 if (new_crtc_state->active)
12432                         intel_state->active_crtcs |= 1 << i;
12433                 else
12434                         intel_state->active_crtcs &= ~(1 << i);
12435
12436                 if (old_crtc_state->active != new_crtc_state->active)
12437                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12438         }
12439
12440         /*
12441          * See if the config requires any additional preparation, e.g.
12442          * to adjust global state with pipes off.  We need to do this
12443          * here so we can get the modeset_pipe updated config for the new
12444          * mode set on this crtc.  For other crtcs we need to use the
12445          * adjusted_mode bits in the crtc directly.
12446          */
12447         if (dev_priv->display.modeset_calc_cdclk) {
12448                 ret = dev_priv->display.modeset_calc_cdclk(state);
12449                 if (ret < 0)
12450                         return ret;
12451
12452                 /*
12453                  * Writes to dev_priv->cdclk.logical must protected by
12454                  * holding all the crtc locks, even if we don't end up
12455                  * touching the hardware
12456                  */
12457                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12458                                         &intel_state->cdclk.logical)) {
12459                         ret = intel_lock_all_pipes(state);
12460                         if (ret < 0)
12461                                 return ret;
12462                 }
12463
12464                 /* All pipes must be switched off while we change the cdclk. */
12465                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12466                                               &intel_state->cdclk.actual)) {
12467                         ret = intel_modeset_all_pipes(state);
12468                         if (ret < 0)
12469                                 return ret;
12470                 }
12471
12472                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12473                               intel_state->cdclk.logical.cdclk,
12474                               intel_state->cdclk.actual.cdclk);
12475                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12476                               intel_state->cdclk.logical.voltage_level,
12477                               intel_state->cdclk.actual.voltage_level);
12478         } else {
12479                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12480         }
12481
12482         intel_modeset_clear_plls(state);
12483
12484         if (IS_HASWELL(dev_priv))
12485                 return haswell_mode_set_planes_workaround(state);
12486
12487         return 0;
12488 }
12489
12490 /*
12491  * Handle calculation of various watermark data at the end of the atomic check
12492  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12493  * handlers to ensure that all derived state has been updated.
12494  */
12495 static int calc_watermark_data(struct drm_atomic_state *state)
12496 {
12497         struct drm_device *dev = state->dev;
12498         struct drm_i915_private *dev_priv = to_i915(dev);
12499
12500         /* Is there platform-specific watermark information to calculate? */
12501         if (dev_priv->display.compute_global_watermarks)
12502                 return dev_priv->display.compute_global_watermarks(state);
12503
12504         return 0;
12505 }
12506
12507 /**
12508  * intel_atomic_check - validate state object
12509  * @dev: drm device
12510  * @state: state to validate
12511  */
12512 static int intel_atomic_check(struct drm_device *dev,
12513                               struct drm_atomic_state *state)
12514 {
12515         struct drm_i915_private *dev_priv = to_i915(dev);
12516         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12517         struct drm_crtc *crtc;
12518         struct drm_crtc_state *old_crtc_state, *crtc_state;
12519         int ret, i;
12520         bool any_ms = false;
12521
12522         /* Catch I915_MODE_FLAG_INHERITED */
12523         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12524                                       crtc_state, i) {
12525                 if (crtc_state->mode.private_flags !=
12526                     old_crtc_state->mode.private_flags)
12527                         crtc_state->mode_changed = true;
12528         }
12529
12530         ret = drm_atomic_helper_check_modeset(dev, state);
12531         if (ret)
12532                 return ret;
12533
12534         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12535                 struct intel_crtc_state *pipe_config =
12536                         to_intel_crtc_state(crtc_state);
12537
12538                 if (!needs_modeset(crtc_state))
12539                         continue;
12540
12541                 if (!crtc_state->enable) {
12542                         any_ms = true;
12543                         continue;
12544                 }
12545
12546                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12547                 if (ret) {
12548                         intel_dump_pipe_config(to_intel_crtc(crtc),
12549                                                pipe_config, "[failed]");
12550                         return ret;
12551                 }
12552
12553                 if (i915_modparams.fastboot &&
12554                     intel_pipe_config_compare(dev_priv,
12555                                         to_intel_crtc_state(old_crtc_state),
12556                                         pipe_config, true)) {
12557                         crtc_state->mode_changed = false;
12558                         pipe_config->update_pipe = true;
12559                 }
12560
12561                 if (needs_modeset(crtc_state))
12562                         any_ms = true;
12563
12564                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12565                                        needs_modeset(crtc_state) ?
12566                                        "[modeset]" : "[fastset]");
12567         }
12568
12569         if (any_ms) {
12570                 ret = intel_modeset_checks(state);
12571
12572                 if (ret)
12573                         return ret;
12574         } else {
12575                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12576         }
12577
12578         ret = drm_atomic_helper_check_planes(dev, state);
12579         if (ret)
12580                 return ret;
12581
12582         intel_fbc_choose_crtc(dev_priv, intel_state);
12583         return calc_watermark_data(state);
12584 }
12585
12586 static int intel_atomic_prepare_commit(struct drm_device *dev,
12587                                        struct drm_atomic_state *state)
12588 {
12589         return drm_atomic_helper_prepare_planes(dev, state);
12590 }
12591
12592 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12593 {
12594         struct drm_device *dev = crtc->base.dev;
12595
12596         if (!dev->max_vblank_count)
12597                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12598
12599         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12600 }
12601
12602 static void intel_update_crtc(struct drm_crtc *crtc,
12603                               struct drm_atomic_state *state,
12604                               struct drm_crtc_state *old_crtc_state,
12605                               struct drm_crtc_state *new_crtc_state)
12606 {
12607         struct drm_device *dev = crtc->dev;
12608         struct drm_i915_private *dev_priv = to_i915(dev);
12609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12610         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12611         bool modeset = needs_modeset(new_crtc_state);
12612         struct intel_plane_state *new_plane_state =
12613                 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12614                                                  to_intel_plane(crtc->primary));
12615
12616         if (modeset) {
12617                 update_scanline_offset(intel_crtc);
12618                 dev_priv->display.crtc_enable(pipe_config, state);
12619
12620                 /* vblanks work again, re-enable pipe CRC. */
12621                 intel_crtc_enable_pipe_crc(intel_crtc);
12622         } else {
12623                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12624                                        pipe_config);
12625         }
12626
12627         if (new_plane_state)
12628                 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12629
12630         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12631 }
12632
12633 static void intel_update_crtcs(struct drm_atomic_state *state)
12634 {
12635         struct drm_crtc *crtc;
12636         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12637         int i;
12638
12639         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12640                 if (!new_crtc_state->active)
12641                         continue;
12642
12643                 intel_update_crtc(crtc, state, old_crtc_state,
12644                                   new_crtc_state);
12645         }
12646 }
12647
12648 static void skl_update_crtcs(struct drm_atomic_state *state)
12649 {
12650         struct drm_i915_private *dev_priv = to_i915(state->dev);
12651         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12652         struct drm_crtc *crtc;
12653         struct intel_crtc *intel_crtc;
12654         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12655         struct intel_crtc_state *cstate;
12656         unsigned int updated = 0;
12657         bool progress;
12658         enum pipe pipe;
12659         int i;
12660         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12661         u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12662
12663         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12664
12665         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12666                 /* ignore allocations for crtc's that have been turned off. */
12667                 if (new_crtc_state->active)
12668                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12669
12670         /* If 2nd DBuf slice required, enable it here */
12671         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12672                 icl_dbuf_slices_update(dev_priv, required_slices);
12673
12674         /*
12675          * Whenever the number of active pipes changes, we need to make sure we
12676          * update the pipes in the right order so that their ddb allocations
12677          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12678          * cause pipe underruns and other bad stuff.
12679          */
12680         do {
12681                 progress = false;
12682
12683                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12684                         bool vbl_wait = false;
12685                         unsigned int cmask = drm_crtc_mask(crtc);
12686
12687                         intel_crtc = to_intel_crtc(crtc);
12688                         cstate = to_intel_crtc_state(new_crtc_state);
12689                         pipe = intel_crtc->pipe;
12690
12691                         if (updated & cmask || !cstate->base.active)
12692                                 continue;
12693
12694                         if (skl_ddb_allocation_overlaps(dev_priv,
12695                                                         entries,
12696                                                         &cstate->wm.skl.ddb,
12697                                                         i))
12698                                 continue;
12699
12700                         updated |= cmask;
12701                         entries[i] = &cstate->wm.skl.ddb;
12702
12703                         /*
12704                          * If this is an already active pipe, it's DDB changed,
12705                          * and this isn't the last pipe that needs updating
12706                          * then we need to wait for a vblank to pass for the
12707                          * new ddb allocation to take effect.
12708                          */
12709                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12710                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12711                             !new_crtc_state->active_changed &&
12712                             intel_state->wm_results.dirty_pipes != updated)
12713                                 vbl_wait = true;
12714
12715                         intel_update_crtc(crtc, state, old_crtc_state,
12716                                           new_crtc_state);
12717
12718                         if (vbl_wait)
12719                                 intel_wait_for_vblank(dev_priv, pipe);
12720
12721                         progress = true;
12722                 }
12723         } while (progress);
12724
12725         /* If 2nd DBuf slice is no more required disable it */
12726         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12727                 icl_dbuf_slices_update(dev_priv, required_slices);
12728 }
12729
12730 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12731 {
12732         struct intel_atomic_state *state, *next;
12733         struct llist_node *freed;
12734
12735         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12736         llist_for_each_entry_safe(state, next, freed, freed)
12737                 drm_atomic_state_put(&state->base);
12738 }
12739
12740 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12741 {
12742         struct drm_i915_private *dev_priv =
12743                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12744
12745         intel_atomic_helper_free_state(dev_priv);
12746 }
12747
12748 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12749 {
12750         struct wait_queue_entry wait_fence, wait_reset;
12751         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12752
12753         init_wait_entry(&wait_fence, 0);
12754         init_wait_entry(&wait_reset, 0);
12755         for (;;) {
12756                 prepare_to_wait(&intel_state->commit_ready.wait,
12757                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12758                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12759                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12760
12761
12762                 if (i915_sw_fence_done(&intel_state->commit_ready)
12763                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12764                         break;
12765
12766                 schedule();
12767         }
12768         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12769         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12770 }
12771
12772 static void intel_atomic_cleanup_work(struct work_struct *work)
12773 {
12774         struct drm_atomic_state *state =
12775                 container_of(work, struct drm_atomic_state, commit_work);
12776         struct drm_i915_private *i915 = to_i915(state->dev);
12777
12778         drm_atomic_helper_cleanup_planes(&i915->drm, state);
12779         drm_atomic_helper_commit_cleanup_done(state);
12780         drm_atomic_state_put(state);
12781
12782         intel_atomic_helper_free_state(i915);
12783 }
12784
12785 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12786 {
12787         struct drm_device *dev = state->dev;
12788         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12789         struct drm_i915_private *dev_priv = to_i915(dev);
12790         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12791         struct drm_crtc *crtc;
12792         struct intel_crtc_state *intel_cstate;
12793         u64 put_domains[I915_MAX_PIPES] = {};
12794         int i;
12795
12796         intel_atomic_commit_fence_wait(intel_state);
12797
12798         drm_atomic_helper_wait_for_dependencies(state);
12799
12800         if (intel_state->modeset)
12801                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12802
12803         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12804                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12805
12806                 if (needs_modeset(new_crtc_state) ||
12807                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12808
12809                         put_domains[to_intel_crtc(crtc)->pipe] =
12810                                 modeset_get_crtc_power_domains(crtc,
12811                                         to_intel_crtc_state(new_crtc_state));
12812                 }
12813
12814                 if (!needs_modeset(new_crtc_state))
12815                         continue;
12816
12817                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12818                                        to_intel_crtc_state(new_crtc_state));
12819
12820                 if (old_crtc_state->active) {
12821                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12822
12823                         /*
12824                          * We need to disable pipe CRC before disabling the pipe,
12825                          * or we race against vblank off.
12826                          */
12827                         intel_crtc_disable_pipe_crc(intel_crtc);
12828
12829                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12830                         intel_crtc->active = false;
12831                         intel_fbc_disable(intel_crtc);
12832                         intel_disable_shared_dpll(intel_crtc);
12833
12834                         /*
12835                          * Underruns don't always raise
12836                          * interrupts, so check manually.
12837                          */
12838                         intel_check_cpu_fifo_underruns(dev_priv);
12839                         intel_check_pch_fifo_underruns(dev_priv);
12840
12841                         /* FIXME unify this for all platforms */
12842                         if (!new_crtc_state->active &&
12843                             !HAS_GMCH_DISPLAY(dev_priv) &&
12844                             dev_priv->display.initial_watermarks)
12845                                 dev_priv->display.initial_watermarks(intel_state,
12846                                                                      to_intel_crtc_state(new_crtc_state));
12847                 }
12848         }
12849
12850         /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12851         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12852                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12853
12854         if (intel_state->modeset) {
12855                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12856
12857                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12858
12859                 /*
12860                  * SKL workaround: bspec recommends we disable the SAGV when we
12861                  * have more then one pipe enabled
12862                  */
12863                 if (!intel_can_enable_sagv(state))
12864                         intel_disable_sagv(dev_priv);
12865
12866                 intel_modeset_verify_disabled(dev, state);
12867         }
12868
12869         /* Complete the events for pipes that have now been disabled */
12870         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12871                 bool modeset = needs_modeset(new_crtc_state);
12872
12873                 /* Complete events for now disable pipes here. */
12874                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12875                         spin_lock_irq(&dev->event_lock);
12876                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12877                         spin_unlock_irq(&dev->event_lock);
12878
12879                         new_crtc_state->event = NULL;
12880                 }
12881         }
12882
12883         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12884         dev_priv->display.update_crtcs(state);
12885
12886         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12887          * already, but still need the state for the delayed optimization. To
12888          * fix this:
12889          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12890          * - schedule that vblank worker _before_ calling hw_done
12891          * - at the start of commit_tail, cancel it _synchrously
12892          * - switch over to the vblank wait helper in the core after that since
12893          *   we don't need out special handling any more.
12894          */
12895         drm_atomic_helper_wait_for_flip_done(dev, state);
12896
12897         /*
12898          * Now that the vblank has passed, we can go ahead and program the
12899          * optimal watermarks on platforms that need two-step watermark
12900          * programming.
12901          *
12902          * TODO: Move this (and other cleanup) to an async worker eventually.
12903          */
12904         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12905                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12906
12907                 if (dev_priv->display.optimize_watermarks)
12908                         dev_priv->display.optimize_watermarks(intel_state,
12909                                                               intel_cstate);
12910         }
12911
12912         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12913                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12914
12915                 if (put_domains[i])
12916                         modeset_put_power_domains(dev_priv, put_domains[i]);
12917
12918                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12919         }
12920
12921         if (intel_state->modeset)
12922                 intel_verify_planes(intel_state);
12923
12924         if (intel_state->modeset && intel_can_enable_sagv(state))
12925                 intel_enable_sagv(dev_priv);
12926
12927         drm_atomic_helper_commit_hw_done(state);
12928
12929         if (intel_state->modeset) {
12930                 /* As one of the primary mmio accessors, KMS has a high
12931                  * likelihood of triggering bugs in unclaimed access. After we
12932                  * finish modesetting, see if an error has been flagged, and if
12933                  * so enable debugging for the next modeset - and hope we catch
12934                  * the culprit.
12935                  */
12936                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12937                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12938         }
12939
12940         /*
12941          * Defer the cleanup of the old state to a separate worker to not
12942          * impede the current task (userspace for blocking modesets) that
12943          * are executed inline. For out-of-line asynchronous modesets/flips,
12944          * deferring to a new worker seems overkill, but we would place a
12945          * schedule point (cond_resched()) here anyway to keep latencies
12946          * down.
12947          */
12948         INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
12949         queue_work(system_highpri_wq, &state->commit_work);
12950 }
12951
12952 static void intel_atomic_commit_work(struct work_struct *work)
12953 {
12954         struct drm_atomic_state *state =
12955                 container_of(work, struct drm_atomic_state, commit_work);
12956
12957         intel_atomic_commit_tail(state);
12958 }
12959
12960 static int __i915_sw_fence_call
12961 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12962                           enum i915_sw_fence_notify notify)
12963 {
12964         struct intel_atomic_state *state =
12965                 container_of(fence, struct intel_atomic_state, commit_ready);
12966
12967         switch (notify) {
12968         case FENCE_COMPLETE:
12969                 /* we do blocking waits in the worker, nothing to do here */
12970                 break;
12971         case FENCE_FREE:
12972                 {
12973                         struct intel_atomic_helper *helper =
12974                                 &to_i915(state->base.dev)->atomic_helper;
12975
12976                         if (llist_add(&state->freed, &helper->free_list))
12977                                 schedule_work(&helper->free_work);
12978                         break;
12979                 }
12980         }
12981
12982         return NOTIFY_DONE;
12983 }
12984
12985 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12986 {
12987         struct drm_plane_state *old_plane_state, *new_plane_state;
12988         struct drm_plane *plane;
12989         int i;
12990
12991         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12992                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12993                                   intel_fb_obj(new_plane_state->fb),
12994                                   to_intel_plane(plane)->frontbuffer_bit);
12995 }
12996
12997 /**
12998  * intel_atomic_commit - commit validated state object
12999  * @dev: DRM device
13000  * @state: the top-level driver state object
13001  * @nonblock: nonblocking commit
13002  *
13003  * This function commits a top-level state object that has been validated
13004  * with drm_atomic_helper_check().
13005  *
13006  * RETURNS
13007  * Zero for success or -errno.
13008  */
13009 static int intel_atomic_commit(struct drm_device *dev,
13010                                struct drm_atomic_state *state,
13011                                bool nonblock)
13012 {
13013         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13014         struct drm_i915_private *dev_priv = to_i915(dev);
13015         int ret = 0;
13016
13017         drm_atomic_state_get(state);
13018         i915_sw_fence_init(&intel_state->commit_ready,
13019                            intel_atomic_commit_ready);
13020
13021         /*
13022          * The intel_legacy_cursor_update() fast path takes care
13023          * of avoiding the vblank waits for simple cursor
13024          * movement and flips. For cursor on/off and size changes,
13025          * we want to perform the vblank waits so that watermark
13026          * updates happen during the correct frames. Gen9+ have
13027          * double buffered watermarks and so shouldn't need this.
13028          *
13029          * Unset state->legacy_cursor_update before the call to
13030          * drm_atomic_helper_setup_commit() because otherwise
13031          * drm_atomic_helper_wait_for_flip_done() is a noop and
13032          * we get FIFO underruns because we didn't wait
13033          * for vblank.
13034          *
13035          * FIXME doing watermarks and fb cleanup from a vblank worker
13036          * (assuming we had any) would solve these problems.
13037          */
13038         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
13039                 struct intel_crtc_state *new_crtc_state;
13040                 struct intel_crtc *crtc;
13041                 int i;
13042
13043                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
13044                         if (new_crtc_state->wm.need_postvbl_update ||
13045                             new_crtc_state->update_wm_post)
13046                                 state->legacy_cursor_update = false;
13047         }
13048
13049         ret = intel_atomic_prepare_commit(dev, state);
13050         if (ret) {
13051                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13052                 i915_sw_fence_commit(&intel_state->commit_ready);
13053                 return ret;
13054         }
13055
13056         ret = drm_atomic_helper_setup_commit(state, nonblock);
13057         if (!ret)
13058                 ret = drm_atomic_helper_swap_state(state, true);
13059
13060         if (ret) {
13061                 i915_sw_fence_commit(&intel_state->commit_ready);
13062
13063                 drm_atomic_helper_cleanup_planes(dev, state);
13064                 return ret;
13065         }
13066         dev_priv->wm.distrust_bios_wm = false;
13067         intel_shared_dpll_swap_state(state);
13068         intel_atomic_track_fbs(state);
13069
13070         if (intel_state->modeset) {
13071                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
13072                        sizeof(intel_state->min_cdclk));
13073                 memcpy(dev_priv->min_voltage_level,
13074                        intel_state->min_voltage_level,
13075                        sizeof(intel_state->min_voltage_level));
13076                 dev_priv->active_crtcs = intel_state->active_crtcs;
13077                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13078                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13079         }
13080
13081         drm_atomic_state_get(state);
13082         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13083
13084         i915_sw_fence_commit(&intel_state->commit_ready);
13085         if (nonblock && intel_state->modeset) {
13086                 queue_work(dev_priv->modeset_wq, &state->commit_work);
13087         } else if (nonblock) {
13088                 queue_work(system_unbound_wq, &state->commit_work);
13089         } else {
13090                 if (intel_state->modeset)
13091                         flush_workqueue(dev_priv->modeset_wq);
13092                 intel_atomic_commit_tail(state);
13093         }
13094
13095         return 0;
13096 }
13097
13098 static const struct drm_crtc_funcs intel_crtc_funcs = {
13099         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13100         .set_config = drm_atomic_helper_set_config,
13101         .destroy = intel_crtc_destroy,
13102         .page_flip = drm_atomic_helper_page_flip,
13103         .atomic_duplicate_state = intel_crtc_duplicate_state,
13104         .atomic_destroy_state = intel_crtc_destroy_state,
13105         .set_crc_source = intel_crtc_set_crc_source,
13106         .verify_crc_source = intel_crtc_verify_crc_source,
13107         .get_crc_sources = intel_crtc_get_crc_sources,
13108 };
13109
13110 struct wait_rps_boost {
13111         struct wait_queue_entry wait;
13112
13113         struct drm_crtc *crtc;
13114         struct i915_request *request;
13115 };
13116
13117 static int do_rps_boost(struct wait_queue_entry *_wait,
13118                         unsigned mode, int sync, void *key)
13119 {
13120         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
13121         struct i915_request *rq = wait->request;
13122
13123         /*
13124          * If we missed the vblank, but the request is already running it
13125          * is reasonable to assume that it will complete before the next
13126          * vblank without our intervention, so leave RPS alone.
13127          */
13128         if (!i915_request_started(rq))
13129                 gen6_rps_boost(rq, NULL);
13130         i915_request_put(rq);
13131
13132         drm_crtc_vblank_put(wait->crtc);
13133
13134         list_del(&wait->wait.entry);
13135         kfree(wait);
13136         return 1;
13137 }
13138
13139 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
13140                                        struct dma_fence *fence)
13141 {
13142         struct wait_rps_boost *wait;
13143
13144         if (!dma_fence_is_i915(fence))
13145                 return;
13146
13147         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
13148                 return;
13149
13150         if (drm_crtc_vblank_get(crtc))
13151                 return;
13152
13153         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
13154         if (!wait) {
13155                 drm_crtc_vblank_put(crtc);
13156                 return;
13157         }
13158
13159         wait->request = to_request(dma_fence_get(fence));
13160         wait->crtc = crtc;
13161
13162         wait->wait.func = do_rps_boost;
13163         wait->wait.flags = 0;
13164
13165         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
13166 }
13167
13168 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
13169 {
13170         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
13171         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13172         struct drm_framebuffer *fb = plane_state->base.fb;
13173         struct i915_vma *vma;
13174
13175         if (plane->id == PLANE_CURSOR &&
13176             INTEL_INFO(dev_priv)->cursor_needs_physical) {
13177                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13178                 const int align = intel_cursor_alignment(dev_priv);
13179                 int err;
13180
13181                 err = i915_gem_object_attach_phys(obj, align);
13182                 if (err)
13183                         return err;
13184         }
13185
13186         vma = intel_pin_and_fence_fb_obj(fb,
13187                                          &plane_state->view,
13188                                          intel_plane_uses_fence(plane_state),
13189                                          &plane_state->flags);
13190         if (IS_ERR(vma))
13191                 return PTR_ERR(vma);
13192
13193         plane_state->vma = vma;
13194
13195         return 0;
13196 }
13197
13198 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
13199 {
13200         struct i915_vma *vma;
13201
13202         vma = fetch_and_zero(&old_plane_state->vma);
13203         if (vma)
13204                 intel_unpin_fb_vma(vma, old_plane_state->flags);
13205 }
13206
13207 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
13208 {
13209         struct i915_sched_attr attr = {
13210                 .priority = I915_PRIORITY_DISPLAY,
13211         };
13212
13213         i915_gem_object_wait_priority(obj, 0, &attr);
13214 }
13215
13216 /**
13217  * intel_prepare_plane_fb - Prepare fb for usage on plane
13218  * @plane: drm plane to prepare for
13219  * @new_state: the plane state being prepared
13220  *
13221  * Prepares a framebuffer for usage on a display plane.  Generally this
13222  * involves pinning the underlying object and updating the frontbuffer tracking
13223  * bits.  Some older platforms need special physical address handling for
13224  * cursor planes.
13225  *
13226  * Must be called with struct_mutex held.
13227  *
13228  * Returns 0 on success, negative error code on failure.
13229  */
13230 int
13231 intel_prepare_plane_fb(struct drm_plane *plane,
13232                        struct drm_plane_state *new_state)
13233 {
13234         struct intel_atomic_state *intel_state =
13235                 to_intel_atomic_state(new_state->state);
13236         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13237         struct drm_framebuffer *fb = new_state->fb;
13238         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13239         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13240         int ret;
13241
13242         if (old_obj) {
13243                 struct drm_crtc_state *crtc_state =
13244                         drm_atomic_get_new_crtc_state(new_state->state,
13245                                                       plane->state->crtc);
13246
13247                 /* Big Hammer, we also need to ensure that any pending
13248                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13249                  * current scanout is retired before unpinning the old
13250                  * framebuffer. Note that we rely on userspace rendering
13251                  * into the buffer attached to the pipe they are waiting
13252                  * on. If not, userspace generates a GPU hang with IPEHR
13253                  * point to the MI_WAIT_FOR_EVENT.
13254                  *
13255                  * This should only fail upon a hung GPU, in which case we
13256                  * can safely continue.
13257                  */
13258                 if (needs_modeset(crtc_state)) {
13259                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13260                                                               old_obj->resv, NULL,
13261                                                               false, 0,
13262                                                               GFP_KERNEL);
13263                         if (ret < 0)
13264                                 return ret;
13265                 }
13266         }
13267
13268         if (new_state->fence) { /* explicit fencing */
13269                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13270                                                     new_state->fence,
13271                                                     I915_FENCE_TIMEOUT,
13272                                                     GFP_KERNEL);
13273                 if (ret < 0)
13274                         return ret;
13275         }
13276
13277         if (!obj)
13278                 return 0;
13279
13280         ret = i915_gem_object_pin_pages(obj);
13281         if (ret)
13282                 return ret;
13283
13284         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13285         if (ret) {
13286                 i915_gem_object_unpin_pages(obj);
13287                 return ret;
13288         }
13289
13290         ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13291
13292         fb_obj_bump_render_priority(obj);
13293
13294         mutex_unlock(&dev_priv->drm.struct_mutex);
13295         i915_gem_object_unpin_pages(obj);
13296         if (ret)
13297                 return ret;
13298
13299         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13300
13301         if (!new_state->fence) { /* implicit fencing */
13302                 struct dma_fence *fence;
13303
13304                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13305                                                       obj->resv, NULL,
13306                                                       false, I915_FENCE_TIMEOUT,
13307                                                       GFP_KERNEL);
13308                 if (ret < 0)
13309                         return ret;
13310
13311                 fence = reservation_object_get_excl_rcu(obj->resv);
13312                 if (fence) {
13313                         add_rps_boost_after_vblank(new_state->crtc, fence);
13314                         dma_fence_put(fence);
13315                 }
13316         } else {
13317                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13318         }
13319
13320         /*
13321          * We declare pageflips to be interactive and so merit a small bias
13322          * towards upclocking to deliver the frame on time. By only changing
13323          * the RPS thresholds to sample more regularly and aim for higher
13324          * clocks we can hopefully deliver low power workloads (like kodi)
13325          * that are not quite steady state without resorting to forcing
13326          * maximum clocks following a vblank miss (see do_rps_boost()).
13327          */
13328         if (!intel_state->rps_interactive) {
13329                 intel_rps_mark_interactive(dev_priv, true);
13330                 intel_state->rps_interactive = true;
13331         }
13332
13333         return 0;
13334 }
13335
13336 /**
13337  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13338  * @plane: drm plane to clean up for
13339  * @old_state: the state from the previous modeset
13340  *
13341  * Cleans up a framebuffer that has just been removed from a plane.
13342  *
13343  * Must be called with struct_mutex held.
13344  */
13345 void
13346 intel_cleanup_plane_fb(struct drm_plane *plane,
13347                        struct drm_plane_state *old_state)
13348 {
13349         struct intel_atomic_state *intel_state =
13350                 to_intel_atomic_state(old_state->state);
13351         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13352
13353         if (intel_state->rps_interactive) {
13354                 intel_rps_mark_interactive(dev_priv, false);
13355                 intel_state->rps_interactive = false;
13356         }
13357
13358         /* Should only be called after a successful intel_prepare_plane_fb()! */
13359         mutex_lock(&dev_priv->drm.struct_mutex);
13360         intel_plane_unpin_fb(to_intel_plane_state(old_state));
13361         mutex_unlock(&dev_priv->drm.struct_mutex);
13362 }
13363
13364 int
13365 skl_max_scale(const struct intel_crtc_state *crtc_state,
13366               u32 pixel_format)
13367 {
13368         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
13369         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13370         int max_scale, mult;
13371         int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13372
13373         if (!crtc_state->base.enable)
13374                 return DRM_PLANE_HELPER_NO_SCALING;
13375
13376         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13377         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13378
13379         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13380                 max_dotclk *= 2;
13381
13382         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13383                 return DRM_PLANE_HELPER_NO_SCALING;
13384
13385         /*
13386          * skl max scale is lower of:
13387          *    close to 3 but not 3, -1 is for that purpose
13388          *            or
13389          *    cdclk/crtc_clock
13390          */
13391         mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
13392         tmpclk1 = (1 << 16) * mult - 1;
13393         tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13394         max_scale = min(tmpclk1, tmpclk2);
13395
13396         return max_scale;
13397 }
13398
13399 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13400                                     struct drm_crtc_state *old_crtc_state)
13401 {
13402         struct drm_device *dev = crtc->dev;
13403         struct drm_i915_private *dev_priv = to_i915(dev);
13404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13405         struct intel_crtc_state *old_intel_cstate =
13406                 to_intel_crtc_state(old_crtc_state);
13407         struct intel_atomic_state *old_intel_state =
13408                 to_intel_atomic_state(old_crtc_state->state);
13409         struct intel_crtc_state *intel_cstate =
13410                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13411         bool modeset = needs_modeset(&intel_cstate->base);
13412
13413         if (!modeset &&
13414             (intel_cstate->base.color_mgmt_changed ||
13415              intel_cstate->update_pipe)) {
13416                 intel_color_set_csc(&intel_cstate->base);
13417                 intel_color_load_luts(&intel_cstate->base);
13418         }
13419
13420         /* Perform vblank evasion around commit operation */
13421         intel_pipe_update_start(intel_cstate);
13422
13423         if (modeset)
13424                 goto out;
13425
13426         if (intel_cstate->update_pipe)
13427                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13428         else if (INTEL_GEN(dev_priv) >= 9)
13429                 skl_detach_scalers(intel_crtc);
13430
13431 out:
13432         if (dev_priv->display.atomic_update_watermarks)
13433                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13434                                                            intel_cstate);
13435 }
13436
13437 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13438                                   struct intel_crtc_state *crtc_state)
13439 {
13440         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13441
13442         if (!IS_GEN2(dev_priv))
13443                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13444
13445         if (crtc_state->has_pch_encoder) {
13446                 enum pipe pch_transcoder =
13447                         intel_crtc_pch_transcoder(crtc);
13448
13449                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13450         }
13451 }
13452
13453 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13454                                      struct drm_crtc_state *old_crtc_state)
13455 {
13456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13457         struct intel_atomic_state *old_intel_state =
13458                 to_intel_atomic_state(old_crtc_state->state);
13459         struct intel_crtc_state *new_crtc_state =
13460                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13461
13462         intel_pipe_update_end(new_crtc_state);
13463
13464         if (new_crtc_state->update_pipe &&
13465             !needs_modeset(&new_crtc_state->base) &&
13466             old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13467                 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13468 }
13469
13470 /**
13471  * intel_plane_destroy - destroy a plane
13472  * @plane: plane to destroy
13473  *
13474  * Common destruction function for all types of planes (primary, cursor,
13475  * sprite).
13476  */
13477 void intel_plane_destroy(struct drm_plane *plane)
13478 {
13479         drm_plane_cleanup(plane);
13480         kfree(to_intel_plane(plane));
13481 }
13482
13483 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
13484                                             u32 format, u64 modifier)
13485 {
13486         switch (modifier) {
13487         case DRM_FORMAT_MOD_LINEAR:
13488         case I915_FORMAT_MOD_X_TILED:
13489                 break;
13490         default:
13491                 return false;
13492         }
13493
13494         switch (format) {
13495         case DRM_FORMAT_C8:
13496         case DRM_FORMAT_RGB565:
13497         case DRM_FORMAT_XRGB1555:
13498         case DRM_FORMAT_XRGB8888:
13499                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13500                         modifier == I915_FORMAT_MOD_X_TILED;
13501         default:
13502                 return false;
13503         }
13504 }
13505
13506 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
13507                                             u32 format, u64 modifier)
13508 {
13509         switch (modifier) {
13510         case DRM_FORMAT_MOD_LINEAR:
13511         case I915_FORMAT_MOD_X_TILED:
13512                 break;
13513         default:
13514                 return false;
13515         }
13516
13517         switch (format) {
13518         case DRM_FORMAT_C8:
13519         case DRM_FORMAT_RGB565:
13520         case DRM_FORMAT_XRGB8888:
13521         case DRM_FORMAT_XBGR8888:
13522         case DRM_FORMAT_XRGB2101010:
13523         case DRM_FORMAT_XBGR2101010:
13524                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13525                         modifier == I915_FORMAT_MOD_X_TILED;
13526         default:
13527                 return false;
13528         }
13529 }
13530
13531 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
13532                                            u32 format, u64 modifier)
13533 {
13534         struct intel_plane *plane = to_intel_plane(_plane);
13535
13536         switch (modifier) {
13537         case DRM_FORMAT_MOD_LINEAR:
13538         case I915_FORMAT_MOD_X_TILED:
13539         case I915_FORMAT_MOD_Y_TILED:
13540         case I915_FORMAT_MOD_Yf_TILED:
13541                 break;
13542         case I915_FORMAT_MOD_Y_TILED_CCS:
13543         case I915_FORMAT_MOD_Yf_TILED_CCS:
13544                 if (!plane->has_ccs)
13545                         return false;
13546                 break;
13547         default:
13548                 return false;
13549         }
13550
13551         switch (format) {
13552         case DRM_FORMAT_XRGB8888:
13553         case DRM_FORMAT_XBGR8888:
13554         case DRM_FORMAT_ARGB8888:
13555         case DRM_FORMAT_ABGR8888:
13556                 if (is_ccs_modifier(modifier))
13557                         return true;
13558                 /* fall through */
13559         case DRM_FORMAT_RGB565:
13560         case DRM_FORMAT_XRGB2101010:
13561         case DRM_FORMAT_XBGR2101010:
13562         case DRM_FORMAT_YUYV:
13563         case DRM_FORMAT_YVYU:
13564         case DRM_FORMAT_UYVY:
13565         case DRM_FORMAT_VYUY:
13566         case DRM_FORMAT_NV12:
13567                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13568                         return true;
13569                 /* fall through */
13570         case DRM_FORMAT_C8:
13571                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13572                     modifier == I915_FORMAT_MOD_X_TILED ||
13573                     modifier == I915_FORMAT_MOD_Y_TILED)
13574                         return true;
13575                 /* fall through */
13576         default:
13577                 return false;
13578         }
13579 }
13580
13581 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13582                                               u32 format, u64 modifier)
13583 {
13584         return modifier == DRM_FORMAT_MOD_LINEAR &&
13585                 format == DRM_FORMAT_ARGB8888;
13586 }
13587
13588 static struct drm_plane_funcs skl_plane_funcs = {
13589         .update_plane = drm_atomic_helper_update_plane,
13590         .disable_plane = drm_atomic_helper_disable_plane,
13591         .destroy = intel_plane_destroy,
13592         .atomic_get_property = intel_plane_atomic_get_property,
13593         .atomic_set_property = intel_plane_atomic_set_property,
13594         .atomic_duplicate_state = intel_plane_duplicate_state,
13595         .atomic_destroy_state = intel_plane_destroy_state,
13596         .format_mod_supported = skl_plane_format_mod_supported,
13597 };
13598
13599 static struct drm_plane_funcs i965_plane_funcs = {
13600         .update_plane = drm_atomic_helper_update_plane,
13601         .disable_plane = drm_atomic_helper_disable_plane,
13602         .destroy = intel_plane_destroy,
13603         .atomic_get_property = intel_plane_atomic_get_property,
13604         .atomic_set_property = intel_plane_atomic_set_property,
13605         .atomic_duplicate_state = intel_plane_duplicate_state,
13606         .atomic_destroy_state = intel_plane_destroy_state,
13607         .format_mod_supported = i965_plane_format_mod_supported,
13608 };
13609
13610 static struct drm_plane_funcs i8xx_plane_funcs = {
13611         .update_plane = drm_atomic_helper_update_plane,
13612         .disable_plane = drm_atomic_helper_disable_plane,
13613         .destroy = intel_plane_destroy,
13614         .atomic_get_property = intel_plane_atomic_get_property,
13615         .atomic_set_property = intel_plane_atomic_set_property,
13616         .atomic_duplicate_state = intel_plane_duplicate_state,
13617         .atomic_destroy_state = intel_plane_destroy_state,
13618         .format_mod_supported = i8xx_plane_format_mod_supported,
13619 };
13620
13621 static int
13622 intel_legacy_cursor_update(struct drm_plane *plane,
13623                            struct drm_crtc *crtc,
13624                            struct drm_framebuffer *fb,
13625                            int crtc_x, int crtc_y,
13626                            unsigned int crtc_w, unsigned int crtc_h,
13627                            uint32_t src_x, uint32_t src_y,
13628                            uint32_t src_w, uint32_t src_h,
13629                            struct drm_modeset_acquire_ctx *ctx)
13630 {
13631         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13632         int ret;
13633         struct drm_plane_state *old_plane_state, *new_plane_state;
13634         struct intel_plane *intel_plane = to_intel_plane(plane);
13635         struct drm_framebuffer *old_fb;
13636         struct drm_crtc_state *crtc_state = crtc->state;
13637
13638         /*
13639          * When crtc is inactive or there is a modeset pending,
13640          * wait for it to complete in the slowpath
13641          */
13642         if (!crtc_state->active || needs_modeset(crtc_state) ||
13643             to_intel_crtc_state(crtc_state)->update_pipe)
13644                 goto slow;
13645
13646         old_plane_state = plane->state;
13647         /*
13648          * Don't do an async update if there is an outstanding commit modifying
13649          * the plane.  This prevents our async update's changes from getting
13650          * overridden by a previous synchronous update's state.
13651          */
13652         if (old_plane_state->commit &&
13653             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13654                 goto slow;
13655
13656         /*
13657          * If any parameters change that may affect watermarks,
13658          * take the slowpath. Only changing fb or position should be
13659          * in the fastpath.
13660          */
13661         if (old_plane_state->crtc != crtc ||
13662             old_plane_state->src_w != src_w ||
13663             old_plane_state->src_h != src_h ||
13664             old_plane_state->crtc_w != crtc_w ||
13665             old_plane_state->crtc_h != crtc_h ||
13666             !old_plane_state->fb != !fb)
13667                 goto slow;
13668
13669         new_plane_state = intel_plane_duplicate_state(plane);
13670         if (!new_plane_state)
13671                 return -ENOMEM;
13672
13673         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13674
13675         new_plane_state->src_x = src_x;
13676         new_plane_state->src_y = src_y;
13677         new_plane_state->src_w = src_w;
13678         new_plane_state->src_h = src_h;
13679         new_plane_state->crtc_x = crtc_x;
13680         new_plane_state->crtc_y = crtc_y;
13681         new_plane_state->crtc_w = crtc_w;
13682         new_plane_state->crtc_h = crtc_h;
13683
13684         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13685                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13686                                                   to_intel_plane_state(plane->state),
13687                                                   to_intel_plane_state(new_plane_state));
13688         if (ret)
13689                 goto out_free;
13690
13691         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13692         if (ret)
13693                 goto out_free;
13694
13695         ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13696         if (ret)
13697                 goto out_unlock;
13698
13699         intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13700
13701         old_fb = old_plane_state->fb;
13702         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13703                           intel_plane->frontbuffer_bit);
13704
13705         /* Swap plane state */
13706         plane->state = new_plane_state;
13707
13708         if (plane->state->visible) {
13709                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13710                 intel_plane->update_plane(intel_plane,
13711                                           to_intel_crtc_state(crtc->state),
13712                                           to_intel_plane_state(plane->state));
13713         } else {
13714                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13715                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13716         }
13717
13718         intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13719
13720 out_unlock:
13721         mutex_unlock(&dev_priv->drm.struct_mutex);
13722 out_free:
13723         if (ret)
13724                 intel_plane_destroy_state(plane, new_plane_state);
13725         else
13726                 intel_plane_destroy_state(plane, old_plane_state);
13727         return ret;
13728
13729 slow:
13730         return drm_atomic_helper_update_plane(plane, crtc, fb,
13731                                               crtc_x, crtc_y, crtc_w, crtc_h,
13732                                               src_x, src_y, src_w, src_h, ctx);
13733 }
13734
13735 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13736         .update_plane = intel_legacy_cursor_update,
13737         .disable_plane = drm_atomic_helper_disable_plane,
13738         .destroy = intel_plane_destroy,
13739         .atomic_get_property = intel_plane_atomic_get_property,
13740         .atomic_set_property = intel_plane_atomic_set_property,
13741         .atomic_duplicate_state = intel_plane_duplicate_state,
13742         .atomic_destroy_state = intel_plane_destroy_state,
13743         .format_mod_supported = intel_cursor_format_mod_supported,
13744 };
13745
13746 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13747                                enum i9xx_plane_id i9xx_plane)
13748 {
13749         if (!HAS_FBC(dev_priv))
13750                 return false;
13751
13752         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13753                 return i9xx_plane == PLANE_A; /* tied to pipe A */
13754         else if (IS_IVYBRIDGE(dev_priv))
13755                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13756                         i9xx_plane == PLANE_C;
13757         else if (INTEL_GEN(dev_priv) >= 4)
13758                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13759         else
13760                 return i9xx_plane == PLANE_A;
13761 }
13762
13763 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13764                               enum pipe pipe, enum plane_id plane_id)
13765 {
13766         if (!HAS_FBC(dev_priv))
13767                 return false;
13768
13769         return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13770 }
13771
13772 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13773                           enum pipe pipe, enum plane_id plane_id)
13774 {
13775         /*
13776          * FIXME: ICL requires two hardware planes for scanning out NV12
13777          * framebuffers. Do not advertize support until this is implemented.
13778          */
13779         if (INTEL_GEN(dev_priv) >= 11)
13780                 return false;
13781
13782         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13783                 return false;
13784
13785         if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
13786                 return false;
13787
13788         if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
13789                 return false;
13790
13791         return true;
13792 }
13793
13794 static struct intel_plane *
13795 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13796 {
13797         struct intel_plane *primary = NULL;
13798         struct intel_plane_state *state = NULL;
13799         const struct drm_plane_funcs *plane_funcs;
13800         const uint32_t *intel_primary_formats;
13801         unsigned int supported_rotations;
13802         unsigned int num_formats;
13803         const uint64_t *modifiers;
13804         int ret;
13805
13806         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13807         if (!primary) {
13808                 ret = -ENOMEM;
13809                 goto fail;
13810         }
13811
13812         state = intel_create_plane_state(&primary->base);
13813         if (!state) {
13814                 ret = -ENOMEM;
13815                 goto fail;
13816         }
13817
13818         primary->base.state = &state->base;
13819
13820         if (INTEL_GEN(dev_priv) >= 9)
13821                 state->scaler_id = -1;
13822         primary->pipe = pipe;
13823         /*
13824          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13825          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13826          */
13827         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13828                 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13829         else
13830                 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13831         primary->id = PLANE_PRIMARY;
13832         primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13833
13834         if (INTEL_GEN(dev_priv) >= 9)
13835                 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13836                                                      primary->pipe,
13837                                                      primary->id);
13838         else
13839                 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13840                                                       primary->i9xx_plane);
13841
13842         if (primary->has_fbc) {
13843                 struct intel_fbc *fbc = &dev_priv->fbc;
13844
13845                 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13846         }
13847
13848         if (INTEL_GEN(dev_priv) >= 9) {
13849                 primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
13850                                                      PLANE_PRIMARY);
13851
13852                 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13853                         intel_primary_formats = skl_pri_planar_formats;
13854                         num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13855                 } else {
13856                         intel_primary_formats = skl_primary_formats;
13857                         num_formats = ARRAY_SIZE(skl_primary_formats);
13858                 }
13859
13860                 if (primary->has_ccs)
13861                         modifiers = skl_format_modifiers_ccs;
13862                 else
13863                         modifiers = skl_format_modifiers_noccs;
13864
13865                 primary->max_stride = skl_plane_max_stride;
13866                 primary->update_plane = skl_update_plane;
13867                 primary->disable_plane = skl_disable_plane;
13868                 primary->get_hw_state = skl_plane_get_hw_state;
13869                 primary->check_plane = skl_plane_check;
13870
13871                 plane_funcs = &skl_plane_funcs;
13872         } else if (INTEL_GEN(dev_priv) >= 4) {
13873                 intel_primary_formats = i965_primary_formats;
13874                 num_formats = ARRAY_SIZE(i965_primary_formats);
13875                 modifiers = i9xx_format_modifiers;
13876
13877                 primary->max_stride = i9xx_plane_max_stride;
13878                 primary->update_plane = i9xx_update_plane;
13879                 primary->disable_plane = i9xx_disable_plane;
13880                 primary->get_hw_state = i9xx_plane_get_hw_state;
13881                 primary->check_plane = i9xx_plane_check;
13882
13883                 plane_funcs = &i965_plane_funcs;
13884         } else {
13885                 intel_primary_formats = i8xx_primary_formats;
13886                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13887                 modifiers = i9xx_format_modifiers;
13888
13889                 primary->max_stride = i9xx_plane_max_stride;
13890                 primary->update_plane = i9xx_update_plane;
13891                 primary->disable_plane = i9xx_disable_plane;
13892                 primary->get_hw_state = i9xx_plane_get_hw_state;
13893                 primary->check_plane = i9xx_plane_check;
13894
13895                 plane_funcs = &i8xx_plane_funcs;
13896         }
13897
13898         if (INTEL_GEN(dev_priv) >= 9)
13899                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13900                                                0, plane_funcs,
13901                                                intel_primary_formats, num_formats,
13902                                                modifiers,
13903                                                DRM_PLANE_TYPE_PRIMARY,
13904                                                "plane 1%c", pipe_name(pipe));
13905         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13906                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13907                                                0, plane_funcs,
13908                                                intel_primary_formats, num_formats,
13909                                                modifiers,
13910                                                DRM_PLANE_TYPE_PRIMARY,
13911                                                "primary %c", pipe_name(pipe));
13912         else
13913                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13914                                                0, plane_funcs,
13915                                                intel_primary_formats, num_formats,
13916                                                modifiers,
13917                                                DRM_PLANE_TYPE_PRIMARY,
13918                                                "plane %c",
13919                                                plane_name(primary->i9xx_plane));
13920         if (ret)
13921                 goto fail;
13922
13923         if (INTEL_GEN(dev_priv) >= 10) {
13924                 supported_rotations =
13925                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13926                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13927                         DRM_MODE_REFLECT_X;
13928         } else if (INTEL_GEN(dev_priv) >= 9) {
13929                 supported_rotations =
13930                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13931                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13932         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13933                 supported_rotations =
13934                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13935                         DRM_MODE_REFLECT_X;
13936         } else if (INTEL_GEN(dev_priv) >= 4) {
13937                 supported_rotations =
13938                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13939         } else {
13940                 supported_rotations = DRM_MODE_ROTATE_0;
13941         }
13942
13943         if (INTEL_GEN(dev_priv) >= 4)
13944                 drm_plane_create_rotation_property(&primary->base,
13945                                                    DRM_MODE_ROTATE_0,
13946                                                    supported_rotations);
13947
13948         if (INTEL_GEN(dev_priv) >= 9)
13949                 drm_plane_create_color_properties(&primary->base,
13950                                                   BIT(DRM_COLOR_YCBCR_BT601) |
13951                                                   BIT(DRM_COLOR_YCBCR_BT709),
13952                                                   BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13953                                                   BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13954                                                   DRM_COLOR_YCBCR_BT709,
13955                                                   DRM_COLOR_YCBCR_LIMITED_RANGE);
13956
13957         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13958
13959         return primary;
13960
13961 fail:
13962         kfree(state);
13963         kfree(primary);
13964
13965         return ERR_PTR(ret);
13966 }
13967
13968 static struct intel_plane *
13969 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13970                           enum pipe pipe)
13971 {
13972         struct intel_plane *cursor = NULL;
13973         struct intel_plane_state *state = NULL;
13974         int ret;
13975
13976         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13977         if (!cursor) {
13978                 ret = -ENOMEM;
13979                 goto fail;
13980         }
13981
13982         state = intel_create_plane_state(&cursor->base);
13983         if (!state) {
13984                 ret = -ENOMEM;
13985                 goto fail;
13986         }
13987
13988         cursor->base.state = &state->base;
13989
13990         cursor->pipe = pipe;
13991         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13992         cursor->id = PLANE_CURSOR;
13993         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13994
13995         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13996                 cursor->max_stride = i845_cursor_max_stride;
13997                 cursor->update_plane = i845_update_cursor;
13998                 cursor->disable_plane = i845_disable_cursor;
13999                 cursor->get_hw_state = i845_cursor_get_hw_state;
14000                 cursor->check_plane = i845_check_cursor;
14001         } else {
14002                 cursor->max_stride = i9xx_cursor_max_stride;
14003                 cursor->update_plane = i9xx_update_cursor;
14004                 cursor->disable_plane = i9xx_disable_cursor;
14005                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
14006                 cursor->check_plane = i9xx_check_cursor;
14007         }
14008
14009         cursor->cursor.base = ~0;
14010         cursor->cursor.cntl = ~0;
14011
14012         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
14013                 cursor->cursor.size = ~0;
14014
14015         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
14016                                        0, &intel_cursor_plane_funcs,
14017                                        intel_cursor_formats,
14018                                        ARRAY_SIZE(intel_cursor_formats),
14019                                        cursor_format_modifiers,
14020                                        DRM_PLANE_TYPE_CURSOR,
14021                                        "cursor %c", pipe_name(pipe));
14022         if (ret)
14023                 goto fail;
14024
14025         if (INTEL_GEN(dev_priv) >= 4)
14026                 drm_plane_create_rotation_property(&cursor->base,
14027                                                    DRM_MODE_ROTATE_0,
14028                                                    DRM_MODE_ROTATE_0 |
14029                                                    DRM_MODE_ROTATE_180);
14030
14031         if (INTEL_GEN(dev_priv) >= 9)
14032                 state->scaler_id = -1;
14033
14034         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14035
14036         return cursor;
14037
14038 fail:
14039         kfree(state);
14040         kfree(cursor);
14041
14042         return ERR_PTR(ret);
14043 }
14044
14045 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
14046                                     struct intel_crtc_state *crtc_state)
14047 {
14048         struct intel_crtc_scaler_state *scaler_state =
14049                 &crtc_state->scaler_state;
14050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14051         int i;
14052
14053         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
14054         if (!crtc->num_scalers)
14055                 return;
14056
14057         for (i = 0; i < crtc->num_scalers; i++) {
14058                 struct intel_scaler *scaler = &scaler_state->scalers[i];
14059
14060                 scaler->in_use = 0;
14061                 scaler->mode = PS_SCALER_MODE_DYN;
14062         }
14063
14064         scaler_state->scaler_id = -1;
14065 }
14066
14067 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
14068 {
14069         struct intel_crtc *intel_crtc;
14070         struct intel_crtc_state *crtc_state = NULL;
14071         struct intel_plane *primary = NULL;
14072         struct intel_plane *cursor = NULL;
14073         int sprite, ret;
14074
14075         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14076         if (!intel_crtc)
14077                 return -ENOMEM;
14078
14079         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14080         if (!crtc_state) {
14081                 ret = -ENOMEM;
14082                 goto fail;
14083         }
14084         intel_crtc->config = crtc_state;
14085         intel_crtc->base.state = &crtc_state->base;
14086         crtc_state->base.crtc = &intel_crtc->base;
14087
14088         primary = intel_primary_plane_create(dev_priv, pipe);
14089         if (IS_ERR(primary)) {
14090                 ret = PTR_ERR(primary);
14091                 goto fail;
14092         }
14093         intel_crtc->plane_ids_mask |= BIT(primary->id);
14094
14095         for_each_sprite(dev_priv, pipe, sprite) {
14096                 struct intel_plane *plane;
14097
14098                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
14099                 if (IS_ERR(plane)) {
14100                         ret = PTR_ERR(plane);
14101                         goto fail;
14102                 }
14103                 intel_crtc->plane_ids_mask |= BIT(plane->id);
14104         }
14105
14106         cursor = intel_cursor_plane_create(dev_priv, pipe);
14107         if (IS_ERR(cursor)) {
14108                 ret = PTR_ERR(cursor);
14109                 goto fail;
14110         }
14111         intel_crtc->plane_ids_mask |= BIT(cursor->id);
14112
14113         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14114                                         &primary->base, &cursor->base,
14115                                         &intel_crtc_funcs,
14116                                         "pipe %c", pipe_name(pipe));
14117         if (ret)
14118                 goto fail;
14119
14120         intel_crtc->pipe = pipe;
14121
14122         /* initialize shared scalers */
14123         intel_crtc_init_scalers(intel_crtc, crtc_state);
14124
14125         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
14126                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
14127         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
14128
14129         if (INTEL_GEN(dev_priv) < 9) {
14130                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
14131
14132                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14133                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
14134                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
14135         }
14136
14137         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14138
14139         intel_color_init(&intel_crtc->base);
14140
14141         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14142
14143         return 0;
14144
14145 fail:
14146         /*
14147          * drm_mode_config_cleanup() will free up any
14148          * crtcs/planes already initialized.
14149          */
14150         kfree(crtc_state);
14151         kfree(intel_crtc);
14152
14153         return ret;
14154 }
14155
14156 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14157 {
14158         struct drm_device *dev = connector->base.dev;
14159
14160         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14161
14162         if (!connector->base.state->crtc)
14163                 return INVALID_PIPE;
14164
14165         return to_intel_crtc(connector->base.state->crtc)->pipe;
14166 }
14167
14168 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14169                                       struct drm_file *file)
14170 {
14171         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14172         struct drm_crtc *drmmode_crtc;
14173         struct intel_crtc *crtc;
14174
14175         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14176         if (!drmmode_crtc)
14177                 return -ENOENT;
14178
14179         crtc = to_intel_crtc(drmmode_crtc);
14180         pipe_from_crtc_id->pipe = crtc->pipe;
14181
14182         return 0;
14183 }
14184
14185 static int intel_encoder_clones(struct intel_encoder *encoder)
14186 {
14187         struct drm_device *dev = encoder->base.dev;
14188         struct intel_encoder *source_encoder;
14189         int index_mask = 0;
14190         int entry = 0;
14191
14192         for_each_intel_encoder(dev, source_encoder) {
14193                 if (encoders_cloneable(encoder, source_encoder))
14194                         index_mask |= (1 << entry);
14195
14196                 entry++;
14197         }
14198
14199         return index_mask;
14200 }
14201
14202 static bool has_edp_a(struct drm_i915_private *dev_priv)
14203 {
14204         if (!IS_MOBILE(dev_priv))
14205                 return false;
14206
14207         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14208                 return false;
14209
14210         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14211                 return false;
14212
14213         return true;
14214 }
14215
14216 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14217 {
14218         if (INTEL_GEN(dev_priv) >= 9)
14219                 return false;
14220
14221         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14222                 return false;
14223
14224         if (IS_CHERRYVIEW(dev_priv))
14225                 return false;
14226
14227         if (HAS_PCH_LPT_H(dev_priv) &&
14228             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14229                 return false;
14230
14231         /* DDI E can't be used if DDI A requires 4 lanes */
14232         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14233                 return false;
14234
14235         if (!dev_priv->vbt.int_crt_support)
14236                 return false;
14237
14238         return true;
14239 }
14240
14241 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14242 {
14243         int pps_num;
14244         int pps_idx;
14245
14246         if (HAS_DDI(dev_priv))
14247                 return;
14248         /*
14249          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14250          * everywhere where registers can be write protected.
14251          */
14252         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14253                 pps_num = 2;
14254         else
14255                 pps_num = 1;
14256
14257         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14258                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14259
14260                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14261                 I915_WRITE(PP_CONTROL(pps_idx), val);
14262         }
14263 }
14264
14265 static void intel_pps_init(struct drm_i915_private *dev_priv)
14266 {
14267         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14268                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14269         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14270                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14271         else
14272                 dev_priv->pps_mmio_base = PPS_BASE;
14273
14274         intel_pps_unlock_regs_wa(dev_priv);
14275 }
14276
14277 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14278 {
14279         struct intel_encoder *encoder;
14280         bool dpd_is_edp = false;
14281
14282         intel_pps_init(dev_priv);
14283
14284         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14285                 return;
14286
14287         /*
14288          * intel_edp_init_connector() depends on this completing first, to
14289          * prevent the registeration of both eDP and LVDS and the incorrect
14290          * sharing of the PPS.
14291          */
14292         intel_lvds_init(dev_priv);
14293
14294         if (intel_crt_present(dev_priv))
14295                 intel_crt_init(dev_priv);
14296
14297         if (IS_ICELAKE(dev_priv)) {
14298                 intel_ddi_init(dev_priv, PORT_A);
14299                 intel_ddi_init(dev_priv, PORT_B);
14300                 intel_ddi_init(dev_priv, PORT_C);
14301                 intel_ddi_init(dev_priv, PORT_D);
14302                 intel_ddi_init(dev_priv, PORT_E);
14303                 intel_ddi_init(dev_priv, PORT_F);
14304         } else if (IS_GEN9_LP(dev_priv)) {
14305                 /*
14306                  * FIXME: Broxton doesn't support port detection via the
14307                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14308                  * detect the ports.
14309                  */
14310                 intel_ddi_init(dev_priv, PORT_A);
14311                 intel_ddi_init(dev_priv, PORT_B);
14312                 intel_ddi_init(dev_priv, PORT_C);
14313
14314                 vlv_dsi_init(dev_priv);
14315         } else if (HAS_DDI(dev_priv)) {
14316                 int found;
14317
14318                 /*
14319                  * Haswell uses DDI functions to detect digital outputs.
14320                  * On SKL pre-D0 the strap isn't connected, so we assume
14321                  * it's there.
14322                  */
14323                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14324                 /* WaIgnoreDDIAStrap: skl */
14325                 if (found || IS_GEN9_BC(dev_priv))
14326                         intel_ddi_init(dev_priv, PORT_A);
14327
14328                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14329                  * register */
14330                 found = I915_READ(SFUSE_STRAP);
14331
14332                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14333                         intel_ddi_init(dev_priv, PORT_B);
14334                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14335                         intel_ddi_init(dev_priv, PORT_C);
14336                 if (found & SFUSE_STRAP_DDID_DETECTED)
14337                         intel_ddi_init(dev_priv, PORT_D);
14338                 if (found & SFUSE_STRAP_DDIF_DETECTED)
14339                         intel_ddi_init(dev_priv, PORT_F);
14340                 /*
14341                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14342                  */
14343                 if (IS_GEN9_BC(dev_priv) &&
14344                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14345                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14346                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14347                         intel_ddi_init(dev_priv, PORT_E);
14348
14349         } else if (HAS_PCH_SPLIT(dev_priv)) {
14350                 int found;
14351                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14352
14353                 if (has_edp_a(dev_priv))
14354                         intel_dp_init(dev_priv, DP_A, PORT_A);
14355
14356                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14357                         /* PCH SDVOB multiplex with HDMIB */
14358                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14359                         if (!found)
14360                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14361                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14362                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14363                 }
14364
14365                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14366                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14367
14368                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14369                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14370
14371                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14372                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14373
14374                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14375                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14376         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14377                 bool has_edp, has_port;
14378
14379                 /*
14380                  * The DP_DETECTED bit is the latched state of the DDC
14381                  * SDA pin at boot. However since eDP doesn't require DDC
14382                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14383                  * eDP ports may have been muxed to an alternate function.
14384                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14385                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14386                  * detect eDP ports.
14387                  *
14388                  * Sadly the straps seem to be missing sometimes even for HDMI
14389                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14390                  * and VBT for the presence of the port. Additionally we can't
14391                  * trust the port type the VBT declares as we've seen at least
14392                  * HDMI ports that the VBT claim are DP or eDP.
14393                  */
14394                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14395                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14396                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14397                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14398                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14399                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14400
14401                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14402                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14403                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14404                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14405                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14406                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14407
14408                 if (IS_CHERRYVIEW(dev_priv)) {
14409                         /*
14410                          * eDP not supported on port D,
14411                          * so no need to worry about it
14412                          */
14413                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14414                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14415                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14416                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14417                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14418                 }
14419
14420                 vlv_dsi_init(dev_priv);
14421         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14422                 bool found = false;
14423
14424                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14425                         DRM_DEBUG_KMS("probing SDVOB\n");
14426                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14427                         if (!found && IS_G4X(dev_priv)) {
14428                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14429                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14430                         }
14431
14432                         if (!found && IS_G4X(dev_priv))
14433                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14434                 }
14435
14436                 /* Before G4X SDVOC doesn't have its own detect register */
14437
14438                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14439                         DRM_DEBUG_KMS("probing SDVOC\n");
14440                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14441                 }
14442
14443                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14444
14445                         if (IS_G4X(dev_priv)) {
14446                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14447                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14448                         }
14449                         if (IS_G4X(dev_priv))
14450                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14451                 }
14452
14453                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14454                         intel_dp_init(dev_priv, DP_D, PORT_D);
14455         } else if (IS_GEN2(dev_priv))
14456                 intel_dvo_init(dev_priv);
14457
14458         if (SUPPORTS_TV(dev_priv))
14459                 intel_tv_init(dev_priv);
14460
14461         intel_psr_init(dev_priv);
14462
14463         for_each_intel_encoder(&dev_priv->drm, encoder) {
14464                 encoder->base.possible_crtcs = encoder->crtc_mask;
14465                 encoder->base.possible_clones =
14466                         intel_encoder_clones(encoder);
14467         }
14468
14469         intel_init_pch_refclk(dev_priv);
14470
14471         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14472 }
14473
14474 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14475 {
14476         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14477         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14478
14479         drm_framebuffer_cleanup(fb);
14480
14481         i915_gem_object_lock(obj);
14482         WARN_ON(!obj->framebuffer_references--);
14483         i915_gem_object_unlock(obj);
14484
14485         i915_gem_object_put(obj);
14486
14487         kfree(intel_fb);
14488 }
14489
14490 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14491                                                 struct drm_file *file,
14492                                                 unsigned int *handle)
14493 {
14494         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14495
14496         if (obj->userptr.mm) {
14497                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14498                 return -EINVAL;
14499         }
14500
14501         return drm_gem_handle_create(file, &obj->base, handle);
14502 }
14503
14504 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14505                                         struct drm_file *file,
14506                                         unsigned flags, unsigned color,
14507                                         struct drm_clip_rect *clips,
14508                                         unsigned num_clips)
14509 {
14510         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14511
14512         i915_gem_object_flush_if_display(obj);
14513         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14514
14515         return 0;
14516 }
14517
14518 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14519         .destroy = intel_user_framebuffer_destroy,
14520         .create_handle = intel_user_framebuffer_create_handle,
14521         .dirty = intel_user_framebuffer_dirty,
14522 };
14523
14524 static
14525 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14526                          uint64_t fb_modifier, uint32_t pixel_format)
14527 {
14528         struct intel_crtc *crtc;
14529         struct intel_plane *plane;
14530
14531         /*
14532          * We assume the primary plane for pipe A has
14533          * the highest stride limits of them all.
14534          */
14535         crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
14536         plane = to_intel_plane(crtc->base.primary);
14537
14538         return plane->max_stride(plane, pixel_format, fb_modifier,
14539                                  DRM_MODE_ROTATE_0);
14540 }
14541
14542 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14543                                   struct drm_i915_gem_object *obj,
14544                                   struct drm_mode_fb_cmd2 *mode_cmd)
14545 {
14546         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14547         struct drm_framebuffer *fb = &intel_fb->base;
14548         struct drm_format_name_buf format_name;
14549         u32 pitch_limit;
14550         unsigned int tiling, stride;
14551         int ret = -EINVAL;
14552         int i;
14553
14554         i915_gem_object_lock(obj);
14555         obj->framebuffer_references++;
14556         tiling = i915_gem_object_get_tiling(obj);
14557         stride = i915_gem_object_get_stride(obj);
14558         i915_gem_object_unlock(obj);
14559
14560         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14561                 /*
14562                  * If there's a fence, enforce that
14563                  * the fb modifier and tiling mode match.
14564                  */
14565                 if (tiling != I915_TILING_NONE &&
14566                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14567                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14568                         goto err;
14569                 }
14570         } else {
14571                 if (tiling == I915_TILING_X) {
14572                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14573                 } else if (tiling == I915_TILING_Y) {
14574                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14575                         goto err;
14576                 }
14577         }
14578
14579         /* Passed in modifier sanity checking. */
14580         switch (mode_cmd->modifier[0]) {
14581         case I915_FORMAT_MOD_Y_TILED_CCS:
14582         case I915_FORMAT_MOD_Yf_TILED_CCS:
14583                 switch (mode_cmd->pixel_format) {
14584                 case DRM_FORMAT_XBGR8888:
14585                 case DRM_FORMAT_ABGR8888:
14586                 case DRM_FORMAT_XRGB8888:
14587                 case DRM_FORMAT_ARGB8888:
14588                         break;
14589                 default:
14590                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14591                         goto err;
14592                 }
14593                 /* fall through */
14594         case I915_FORMAT_MOD_Y_TILED:
14595         case I915_FORMAT_MOD_Yf_TILED:
14596                 if (INTEL_GEN(dev_priv) < 9) {
14597                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14598                                       mode_cmd->modifier[0]);
14599                         goto err;
14600                 }
14601         case DRM_FORMAT_MOD_LINEAR:
14602         case I915_FORMAT_MOD_X_TILED:
14603                 break;
14604         default:
14605                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14606                               mode_cmd->modifier[0]);
14607                 goto err;
14608         }
14609
14610         /*
14611          * gen2/3 display engine uses the fence if present,
14612          * so the tiling mode must match the fb modifier exactly.
14613          */
14614         if (INTEL_GEN(dev_priv) < 4 &&
14615             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14616                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14617                 goto err;
14618         }
14619
14620         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14621                                            mode_cmd->pixel_format);
14622         if (mode_cmd->pitches[0] > pitch_limit) {
14623                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14624                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14625                               "tiled" : "linear",
14626                               mode_cmd->pitches[0], pitch_limit);
14627                 goto err;
14628         }
14629
14630         /*
14631          * If there's a fence, enforce that
14632          * the fb pitch and fence stride match.
14633          */
14634         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14635                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14636                               mode_cmd->pitches[0], stride);
14637                 goto err;
14638         }
14639
14640         /* Reject formats not supported by any plane early. */
14641         switch (mode_cmd->pixel_format) {
14642         case DRM_FORMAT_C8:
14643         case DRM_FORMAT_RGB565:
14644         case DRM_FORMAT_XRGB8888:
14645         case DRM_FORMAT_ARGB8888:
14646                 break;
14647         case DRM_FORMAT_XRGB1555:
14648                 if (INTEL_GEN(dev_priv) > 3) {
14649                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14650                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14651                         goto err;
14652                 }
14653                 break;
14654         case DRM_FORMAT_ABGR8888:
14655                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14656                     INTEL_GEN(dev_priv) < 9) {
14657                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14658                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14659                         goto err;
14660                 }
14661                 break;
14662         case DRM_FORMAT_XBGR8888:
14663         case DRM_FORMAT_XRGB2101010:
14664         case DRM_FORMAT_XBGR2101010:
14665                 if (INTEL_GEN(dev_priv) < 4) {
14666                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14667                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14668                         goto err;
14669                 }
14670                 break;
14671         case DRM_FORMAT_ABGR2101010:
14672                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14673                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14674                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14675                         goto err;
14676                 }
14677                 break;
14678         case DRM_FORMAT_YUYV:
14679         case DRM_FORMAT_UYVY:
14680         case DRM_FORMAT_YVYU:
14681         case DRM_FORMAT_VYUY:
14682                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14683                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14684                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14685                         goto err;
14686                 }
14687                 break;
14688         case DRM_FORMAT_NV12:
14689                 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14690                     IS_BROXTON(dev_priv) || INTEL_GEN(dev_priv) >= 11) {
14691                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14692                                       drm_get_format_name(mode_cmd->pixel_format,
14693                                                           &format_name));
14694                         goto err;
14695                 }
14696                 break;
14697         default:
14698                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14699                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14700                 goto err;
14701         }
14702
14703         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14704         if (mode_cmd->offsets[0] != 0)
14705                 goto err;
14706
14707         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14708
14709         if (fb->format->format == DRM_FORMAT_NV12 &&
14710             (fb->width < SKL_MIN_YUV_420_SRC_W ||
14711              fb->height < SKL_MIN_YUV_420_SRC_H ||
14712              (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14713                 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14714                 goto err;
14715         }
14716
14717         for (i = 0; i < fb->format->num_planes; i++) {
14718                 u32 stride_alignment;
14719
14720                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14721                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14722                         goto err;
14723                 }
14724
14725                 stride_alignment = intel_fb_stride_alignment(fb, i);
14726
14727                 /*
14728                  * Display WA #0531: skl,bxt,kbl,glk
14729                  *
14730                  * Render decompression and plane width > 3840
14731                  * combined with horizontal panning requires the
14732                  * plane stride to be a multiple of 4. We'll just
14733                  * require the entire fb to accommodate that to avoid
14734                  * potential runtime errors at plane configuration time.
14735                  */
14736                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14737                     is_ccs_modifier(fb->modifier))
14738                         stride_alignment *= 4;
14739
14740                 if (fb->pitches[i] & (stride_alignment - 1)) {
14741                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14742                                       i, fb->pitches[i], stride_alignment);
14743                         goto err;
14744                 }
14745
14746                 fb->obj[i] = &obj->base;
14747         }
14748
14749         ret = intel_fill_fb_info(dev_priv, fb);
14750         if (ret)
14751                 goto err;
14752
14753         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14754         if (ret) {
14755                 DRM_ERROR("framebuffer init failed %d\n", ret);
14756                 goto err;
14757         }
14758
14759         return 0;
14760
14761 err:
14762         i915_gem_object_lock(obj);
14763         obj->framebuffer_references--;
14764         i915_gem_object_unlock(obj);
14765         return ret;
14766 }
14767
14768 static struct drm_framebuffer *
14769 intel_user_framebuffer_create(struct drm_device *dev,
14770                               struct drm_file *filp,
14771                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14772 {
14773         struct drm_framebuffer *fb;
14774         struct drm_i915_gem_object *obj;
14775         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14776
14777         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14778         if (!obj)
14779                 return ERR_PTR(-ENOENT);
14780
14781         fb = intel_framebuffer_create(obj, &mode_cmd);
14782         if (IS_ERR(fb))
14783                 i915_gem_object_put(obj);
14784
14785         return fb;
14786 }
14787
14788 static void intel_atomic_state_free(struct drm_atomic_state *state)
14789 {
14790         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14791
14792         drm_atomic_state_default_release(state);
14793
14794         i915_sw_fence_fini(&intel_state->commit_ready);
14795
14796         kfree(state);
14797 }
14798
14799 static enum drm_mode_status
14800 intel_mode_valid(struct drm_device *dev,
14801                  const struct drm_display_mode *mode)
14802 {
14803         struct drm_i915_private *dev_priv = to_i915(dev);
14804         int hdisplay_max, htotal_max;
14805         int vdisplay_max, vtotal_max;
14806
14807         /*
14808          * Can't reject DBLSCAN here because Xorg ddxen can add piles
14809          * of DBLSCAN modes to the output's mode list when they detect
14810          * the scaling mode property on the connector. And they don't
14811          * ask the kernel to validate those modes in any way until
14812          * modeset time at which point the client gets a protocol error.
14813          * So in order to not upset those clients we silently ignore the
14814          * DBLSCAN flag on such connectors. For other connectors we will
14815          * reject modes with the DBLSCAN flag in encoder->compute_config().
14816          * And we always reject DBLSCAN modes in connector->mode_valid()
14817          * as we never want such modes on the connector's mode list.
14818          */
14819
14820         if (mode->vscan > 1)
14821                 return MODE_NO_VSCAN;
14822
14823         if (mode->flags & DRM_MODE_FLAG_HSKEW)
14824                 return MODE_H_ILLEGAL;
14825
14826         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14827                            DRM_MODE_FLAG_NCSYNC |
14828                            DRM_MODE_FLAG_PCSYNC))
14829                 return MODE_HSYNC;
14830
14831         if (mode->flags & (DRM_MODE_FLAG_BCAST |
14832                            DRM_MODE_FLAG_PIXMUX |
14833                            DRM_MODE_FLAG_CLKDIV2))
14834                 return MODE_BAD;
14835
14836         if (INTEL_GEN(dev_priv) >= 9 ||
14837             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
14838                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
14839                 vdisplay_max = 4096;
14840                 htotal_max = 8192;
14841                 vtotal_max = 8192;
14842         } else if (INTEL_GEN(dev_priv) >= 3) {
14843                 hdisplay_max = 4096;
14844                 vdisplay_max = 4096;
14845                 htotal_max = 8192;
14846                 vtotal_max = 8192;
14847         } else {
14848                 hdisplay_max = 2048;
14849                 vdisplay_max = 2048;
14850                 htotal_max = 4096;
14851                 vtotal_max = 4096;
14852         }
14853
14854         if (mode->hdisplay > hdisplay_max ||
14855             mode->hsync_start > htotal_max ||
14856             mode->hsync_end > htotal_max ||
14857             mode->htotal > htotal_max)
14858                 return MODE_H_ILLEGAL;
14859
14860         if (mode->vdisplay > vdisplay_max ||
14861             mode->vsync_start > vtotal_max ||
14862             mode->vsync_end > vtotal_max ||
14863             mode->vtotal > vtotal_max)
14864                 return MODE_V_ILLEGAL;
14865
14866         return MODE_OK;
14867 }
14868
14869 static const struct drm_mode_config_funcs intel_mode_funcs = {
14870         .fb_create = intel_user_framebuffer_create,
14871         .get_format_info = intel_get_format_info,
14872         .output_poll_changed = intel_fbdev_output_poll_changed,
14873         .mode_valid = intel_mode_valid,
14874         .atomic_check = intel_atomic_check,
14875         .atomic_commit = intel_atomic_commit,
14876         .atomic_state_alloc = intel_atomic_state_alloc,
14877         .atomic_state_clear = intel_atomic_state_clear,
14878         .atomic_state_free = intel_atomic_state_free,
14879 };
14880
14881 /**
14882  * intel_init_display_hooks - initialize the display modesetting hooks
14883  * @dev_priv: device private
14884  */
14885 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14886 {
14887         intel_init_cdclk_hooks(dev_priv);
14888
14889         if (INTEL_GEN(dev_priv) >= 9) {
14890                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14891                 dev_priv->display.get_initial_plane_config =
14892                         skylake_get_initial_plane_config;
14893                 dev_priv->display.crtc_compute_clock =
14894                         haswell_crtc_compute_clock;
14895                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14896                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14897         } else if (HAS_DDI(dev_priv)) {
14898                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14899                 dev_priv->display.get_initial_plane_config =
14900                         i9xx_get_initial_plane_config;
14901                 dev_priv->display.crtc_compute_clock =
14902                         haswell_crtc_compute_clock;
14903                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14904                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14905         } else if (HAS_PCH_SPLIT(dev_priv)) {
14906                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14907                 dev_priv->display.get_initial_plane_config =
14908                         i9xx_get_initial_plane_config;
14909                 dev_priv->display.crtc_compute_clock =
14910                         ironlake_crtc_compute_clock;
14911                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14912                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14913         } else if (IS_CHERRYVIEW(dev_priv)) {
14914                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14915                 dev_priv->display.get_initial_plane_config =
14916                         i9xx_get_initial_plane_config;
14917                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14918                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14919                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14920         } else if (IS_VALLEYVIEW(dev_priv)) {
14921                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14922                 dev_priv->display.get_initial_plane_config =
14923                         i9xx_get_initial_plane_config;
14924                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14925                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14926                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14927         } else if (IS_G4X(dev_priv)) {
14928                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14929                 dev_priv->display.get_initial_plane_config =
14930                         i9xx_get_initial_plane_config;
14931                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14932                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14933                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14934         } else if (IS_PINEVIEW(dev_priv)) {
14935                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14936                 dev_priv->display.get_initial_plane_config =
14937                         i9xx_get_initial_plane_config;
14938                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14939                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14940                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14941         } else if (!IS_GEN2(dev_priv)) {
14942                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14943                 dev_priv->display.get_initial_plane_config =
14944                         i9xx_get_initial_plane_config;
14945                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14946                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14947                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14948         } else {
14949                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14950                 dev_priv->display.get_initial_plane_config =
14951                         i9xx_get_initial_plane_config;
14952                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14953                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14954                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14955         }
14956
14957         if (IS_GEN5(dev_priv)) {
14958                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14959         } else if (IS_GEN6(dev_priv)) {
14960                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14961         } else if (IS_IVYBRIDGE(dev_priv)) {
14962                 /* FIXME: detect B0+ stepping and use auto training */
14963                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14964         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14965                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14966         }
14967
14968         if (INTEL_GEN(dev_priv) >= 9)
14969                 dev_priv->display.update_crtcs = skl_update_crtcs;
14970         else
14971                 dev_priv->display.update_crtcs = intel_update_crtcs;
14972 }
14973
14974 /*
14975  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14976  */
14977 static void quirk_ssc_force_disable(struct drm_device *dev)
14978 {
14979         struct drm_i915_private *dev_priv = to_i915(dev);
14980         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14981         DRM_INFO("applying lvds SSC disable quirk\n");
14982 }
14983
14984 /*
14985  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14986  * brightness value
14987  */
14988 static void quirk_invert_brightness(struct drm_device *dev)
14989 {
14990         struct drm_i915_private *dev_priv = to_i915(dev);
14991         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14992         DRM_INFO("applying inverted panel brightness quirk\n");
14993 }
14994
14995 /* Some VBT's incorrectly indicate no backlight is present */
14996 static void quirk_backlight_present(struct drm_device *dev)
14997 {
14998         struct drm_i915_private *dev_priv = to_i915(dev);
14999         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15000         DRM_INFO("applying backlight present quirk\n");
15001 }
15002
15003 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
15004  * which is 300 ms greater than eDP spec T12 min.
15005  */
15006 static void quirk_increase_t12_delay(struct drm_device *dev)
15007 {
15008         struct drm_i915_private *dev_priv = to_i915(dev);
15009
15010         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
15011         DRM_INFO("Applying T12 delay quirk\n");
15012 }
15013
15014 /*
15015  * GeminiLake NUC HDMI outputs require additional off time
15016  * this allows the onboard retimer to correctly sync to signal
15017  */
15018 static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
15019 {
15020         struct drm_i915_private *dev_priv = to_i915(dev);
15021
15022         dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
15023         DRM_INFO("Applying Increase DDI Disabled quirk\n");
15024 }
15025
15026 struct intel_quirk {
15027         int device;
15028         int subsystem_vendor;
15029         int subsystem_device;
15030         void (*hook)(struct drm_device *dev);
15031 };
15032
15033 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15034 struct intel_dmi_quirk {
15035         void (*hook)(struct drm_device *dev);
15036         const struct dmi_system_id (*dmi_id_list)[];
15037 };
15038
15039 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15040 {
15041         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15042         return 1;
15043 }
15044
15045 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15046         {
15047                 .dmi_id_list = &(const struct dmi_system_id[]) {
15048                         {
15049                                 .callback = intel_dmi_reverse_brightness,
15050                                 .ident = "NCR Corporation",
15051                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15052                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15053                                 },
15054                         },
15055                         { }  /* terminating entry */
15056                 },
15057                 .hook = quirk_invert_brightness,
15058         },
15059 };
15060
15061 static struct intel_quirk intel_quirks[] = {
15062         /* Lenovo U160 cannot use SSC on LVDS */
15063         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15064
15065         /* Sony Vaio Y cannot use SSC on LVDS */
15066         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15067
15068         /* Acer Aspire 5734Z must invert backlight brightness */
15069         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15070
15071         /* Acer/eMachines G725 */
15072         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15073
15074         /* Acer/eMachines e725 */
15075         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15076
15077         /* Acer/Packard Bell NCL20 */
15078         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15079
15080         /* Acer Aspire 4736Z */
15081         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15082
15083         /* Acer Aspire 5336 */
15084         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15085
15086         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15087         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15088
15089         /* Acer C720 Chromebook (Core i3 4005U) */
15090         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15091
15092         /* Apple Macbook 2,1 (Core 2 T7400) */
15093         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15094
15095         /* Apple Macbook 4,1 */
15096         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15097
15098         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15099         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15100
15101         /* HP Chromebook 14 (Celeron 2955U) */
15102         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15103
15104         /* Dell Chromebook 11 */
15105         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15106
15107         /* Dell Chromebook 11 (2015 version) */
15108         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15109
15110         /* Toshiba Satellite P50-C-18C */
15111         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
15112
15113         /* GeminiLake NUC */
15114         { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
15115         { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
15116         /* ASRock ITX*/
15117         { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
15118         { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
15119 };
15120
15121 static void intel_init_quirks(struct drm_device *dev)
15122 {
15123         struct pci_dev *d = dev->pdev;
15124         int i;
15125
15126         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15127                 struct intel_quirk *q = &intel_quirks[i];
15128
15129                 if (d->device == q->device &&
15130                     (d->subsystem_vendor == q->subsystem_vendor ||
15131                      q->subsystem_vendor == PCI_ANY_ID) &&
15132                     (d->subsystem_device == q->subsystem_device ||
15133                      q->subsystem_device == PCI_ANY_ID))
15134                         q->hook(dev);
15135         }
15136         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15137                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15138                         intel_dmi_quirks[i].hook(dev);
15139         }
15140 }
15141
15142 /* Disable the VGA plane that we never use */
15143 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15144 {
15145         struct pci_dev *pdev = dev_priv->drm.pdev;
15146         u8 sr1;
15147         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15148
15149         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15150         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15151         outb(SR01, VGA_SR_INDEX);
15152         sr1 = inb(VGA_SR_DATA);
15153         outb(sr1 | 1<<5, VGA_SR_DATA);
15154         vga_put(pdev, VGA_RSRC_LEGACY_IO);
15155         udelay(300);
15156
15157         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15158         POSTING_READ(vga_reg);
15159 }
15160
15161 void intel_modeset_init_hw(struct drm_device *dev)
15162 {
15163         struct drm_i915_private *dev_priv = to_i915(dev);
15164
15165         intel_update_cdclk(dev_priv);
15166         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15167         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15168 }
15169
15170 /*
15171  * Calculate what we think the watermarks should be for the state we've read
15172  * out of the hardware and then immediately program those watermarks so that
15173  * we ensure the hardware settings match our internal state.
15174  *
15175  * We can calculate what we think WM's should be by creating a duplicate of the
15176  * current state (which was constructed during hardware readout) and running it
15177  * through the atomic check code to calculate new watermark values in the
15178  * state object.
15179  */
15180 static void sanitize_watermarks(struct drm_device *dev)
15181 {
15182         struct drm_i915_private *dev_priv = to_i915(dev);
15183         struct drm_atomic_state *state;
15184         struct intel_atomic_state *intel_state;
15185         struct drm_crtc *crtc;
15186         struct drm_crtc_state *cstate;
15187         struct drm_modeset_acquire_ctx ctx;
15188         int ret;
15189         int i;
15190
15191         /* Only supported on platforms that use atomic watermark design */
15192         if (!dev_priv->display.optimize_watermarks)
15193                 return;
15194
15195         /*
15196          * We need to hold connection_mutex before calling duplicate_state so
15197          * that the connector loop is protected.
15198          */
15199         drm_modeset_acquire_init(&ctx, 0);
15200 retry:
15201         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15202         if (ret == -EDEADLK) {
15203                 drm_modeset_backoff(&ctx);
15204                 goto retry;
15205         } else if (WARN_ON(ret)) {
15206                 goto fail;
15207         }
15208
15209         state = drm_atomic_helper_duplicate_state(dev, &ctx);
15210         if (WARN_ON(IS_ERR(state)))
15211                 goto fail;
15212
15213         intel_state = to_intel_atomic_state(state);
15214
15215         /*
15216          * Hardware readout is the only time we don't want to calculate
15217          * intermediate watermarks (since we don't trust the current
15218          * watermarks).
15219          */
15220         if (!HAS_GMCH_DISPLAY(dev_priv))
15221                 intel_state->skip_intermediate_wm = true;
15222
15223         ret = intel_atomic_check(dev, state);
15224         if (ret) {
15225                 /*
15226                  * If we fail here, it means that the hardware appears to be
15227                  * programmed in a way that shouldn't be possible, given our
15228                  * understanding of watermark requirements.  This might mean a
15229                  * mistake in the hardware readout code or a mistake in the
15230                  * watermark calculations for a given platform.  Raise a WARN
15231                  * so that this is noticeable.
15232                  *
15233                  * If this actually happens, we'll have to just leave the
15234                  * BIOS-programmed watermarks untouched and hope for the best.
15235                  */
15236                 WARN(true, "Could not determine valid watermarks for inherited state\n");
15237                 goto put_state;
15238         }
15239
15240         /* Write calculated watermark values back */
15241         for_each_new_crtc_in_state(state, crtc, cstate, i) {
15242                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15243
15244                 cs->wm.need_postvbl_update = true;
15245                 dev_priv->display.optimize_watermarks(intel_state, cs);
15246
15247                 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15248         }
15249
15250 put_state:
15251         drm_atomic_state_put(state);
15252 fail:
15253         drm_modeset_drop_locks(&ctx);
15254         drm_modeset_acquire_fini(&ctx);
15255 }
15256
15257 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15258 {
15259         if (IS_GEN5(dev_priv)) {
15260                 u32 fdi_pll_clk =
15261                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15262
15263                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15264         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
15265                 dev_priv->fdi_pll_freq = 270000;
15266         } else {
15267                 return;
15268         }
15269
15270         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15271 }
15272
15273 static int intel_initial_commit(struct drm_device *dev)
15274 {
15275         struct drm_atomic_state *state = NULL;
15276         struct drm_modeset_acquire_ctx ctx;
15277         struct drm_crtc *crtc;
15278         struct drm_crtc_state *crtc_state;
15279         int ret = 0;
15280
15281         state = drm_atomic_state_alloc(dev);
15282         if (!state)
15283                 return -ENOMEM;
15284
15285         drm_modeset_acquire_init(&ctx, 0);
15286
15287 retry:
15288         state->acquire_ctx = &ctx;
15289
15290         drm_for_each_crtc(crtc, dev) {
15291                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
15292                 if (IS_ERR(crtc_state)) {
15293                         ret = PTR_ERR(crtc_state);
15294                         goto out;
15295                 }
15296
15297                 if (crtc_state->active) {
15298                         ret = drm_atomic_add_affected_planes(state, crtc);
15299                         if (ret)
15300                                 goto out;
15301
15302                         /*
15303                          * FIXME hack to force a LUT update to avoid the
15304                          * plane update forcing the pipe gamma on without
15305                          * having a proper LUT loaded. Remove once we
15306                          * have readout for pipe gamma enable.
15307                          */
15308                         crtc_state->color_mgmt_changed = true;
15309                 }
15310         }
15311
15312         ret = drm_atomic_commit(state);
15313
15314 out:
15315         if (ret == -EDEADLK) {
15316                 drm_atomic_state_clear(state);
15317                 drm_modeset_backoff(&ctx);
15318                 goto retry;
15319         }
15320
15321         drm_atomic_state_put(state);
15322
15323         drm_modeset_drop_locks(&ctx);
15324         drm_modeset_acquire_fini(&ctx);
15325
15326         return ret;
15327 }
15328
15329 int intel_modeset_init(struct drm_device *dev)
15330 {
15331         struct drm_i915_private *dev_priv = to_i915(dev);
15332         struct i915_ggtt *ggtt = &dev_priv->ggtt;
15333         enum pipe pipe;
15334         struct intel_crtc *crtc;
15335         int ret;
15336
15337         dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15338
15339         drm_mode_config_init(dev);
15340
15341         dev->mode_config.min_width = 0;
15342         dev->mode_config.min_height = 0;
15343
15344         dev->mode_config.preferred_depth = 24;
15345         dev->mode_config.prefer_shadow = 1;
15346
15347         dev->mode_config.allow_fb_modifiers = true;
15348
15349         dev->mode_config.funcs = &intel_mode_funcs;
15350
15351         init_llist_head(&dev_priv->atomic_helper.free_list);
15352         INIT_WORK(&dev_priv->atomic_helper.free_work,
15353                   intel_atomic_helper_free_state_worker);
15354
15355         intel_init_quirks(dev);
15356
15357         intel_init_pm(dev_priv);
15358
15359         /*
15360          * There may be no VBT; and if the BIOS enabled SSC we can
15361          * just keep using it to avoid unnecessary flicker.  Whereas if the
15362          * BIOS isn't using it, don't assume it will work even if the VBT
15363          * indicates as much.
15364          */
15365         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15366                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15367                                             DREF_SSC1_ENABLE);
15368
15369                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15370                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15371                                      bios_lvds_use_ssc ? "en" : "dis",
15372                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15373                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15374                 }
15375         }
15376
15377         /* maximum framebuffer dimensions */
15378         if (IS_GEN2(dev_priv)) {
15379                 dev->mode_config.max_width = 2048;
15380                 dev->mode_config.max_height = 2048;
15381         } else if (IS_GEN3(dev_priv)) {
15382                 dev->mode_config.max_width = 4096;
15383                 dev->mode_config.max_height = 4096;
15384         } else {
15385                 dev->mode_config.max_width = 8192;
15386                 dev->mode_config.max_height = 8192;
15387         }
15388
15389         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15390                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15391                 dev->mode_config.cursor_height = 1023;
15392         } else if (IS_GEN2(dev_priv)) {
15393                 dev->mode_config.cursor_width = 64;
15394                 dev->mode_config.cursor_height = 64;
15395         } else {
15396                 dev->mode_config.cursor_width = 256;
15397                 dev->mode_config.cursor_height = 256;
15398         }
15399
15400         dev->mode_config.fb_base = ggtt->gmadr.start;
15401
15402         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15403                       INTEL_INFO(dev_priv)->num_pipes,
15404                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15405
15406         for_each_pipe(dev_priv, pipe) {
15407                 ret = intel_crtc_init(dev_priv, pipe);
15408                 if (ret) {
15409                         drm_mode_config_cleanup(dev);
15410                         return ret;
15411                 }
15412         }
15413
15414         intel_shared_dpll_init(dev);
15415         intel_update_fdi_pll_freq(dev_priv);
15416
15417         intel_update_czclk(dev_priv);
15418         intel_modeset_init_hw(dev);
15419
15420         if (dev_priv->max_cdclk_freq == 0)
15421                 intel_update_max_cdclk(dev_priv);
15422
15423         /* Just disable it once at startup */
15424         i915_disable_vga(dev_priv);
15425         intel_setup_outputs(dev_priv);
15426
15427         drm_modeset_lock_all(dev);
15428         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15429         drm_modeset_unlock_all(dev);
15430
15431         for_each_intel_crtc(dev, crtc) {
15432                 struct intel_initial_plane_config plane_config = {};
15433
15434                 if (!crtc->active)
15435                         continue;
15436
15437                 /*
15438                  * Note that reserving the BIOS fb up front prevents us
15439                  * from stuffing other stolen allocations like the ring
15440                  * on top.  This prevents some ugliness at boot time, and
15441                  * can even allow for smooth boot transitions if the BIOS
15442                  * fb is large enough for the active pipe configuration.
15443                  */
15444                 dev_priv->display.get_initial_plane_config(crtc,
15445                                                            &plane_config);
15446
15447                 /*
15448                  * If the fb is shared between multiple heads, we'll
15449                  * just get the first one.
15450                  */
15451                 intel_find_initial_plane_obj(crtc, &plane_config);
15452         }
15453
15454         /*
15455          * Make sure hardware watermarks really match the state we read out.
15456          * Note that we need to do this after reconstructing the BIOS fb's
15457          * since the watermark calculation done here will use pstate->fb.
15458          */
15459         if (!HAS_GMCH_DISPLAY(dev_priv))
15460                 sanitize_watermarks(dev);
15461
15462         /*
15463          * Force all active planes to recompute their states. So that on
15464          * mode_setcrtc after probe, all the intel_plane_state variables
15465          * are already calculated and there is no assert_plane warnings
15466          * during bootup.
15467          */
15468         ret = intel_initial_commit(dev);
15469         if (ret)
15470                 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
15471
15472         return 0;
15473 }
15474
15475 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15476 {
15477         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15478         /* 640x480@60Hz, ~25175 kHz */
15479         struct dpll clock = {
15480                 .m1 = 18,
15481                 .m2 = 7,
15482                 .p1 = 13,
15483                 .p2 = 4,
15484                 .n = 2,
15485         };
15486         u32 dpll, fp;
15487         int i;
15488
15489         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15490
15491         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15492                       pipe_name(pipe), clock.vco, clock.dot);
15493
15494         fp = i9xx_dpll_compute_fp(&clock);
15495         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15496                 DPLL_VGA_MODE_DIS |
15497                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15498                 PLL_P2_DIVIDE_BY_4 |
15499                 PLL_REF_INPUT_DREFCLK |
15500                 DPLL_VCO_ENABLE;
15501
15502         I915_WRITE(FP0(pipe), fp);
15503         I915_WRITE(FP1(pipe), fp);
15504
15505         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15506         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15507         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15508         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15509         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15510         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15511         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15512
15513         /*
15514          * Apparently we need to have VGA mode enabled prior to changing
15515          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15516          * dividers, even though the register value does change.
15517          */
15518         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15519         I915_WRITE(DPLL(pipe), dpll);
15520
15521         /* Wait for the clocks to stabilize. */
15522         POSTING_READ(DPLL(pipe));
15523         udelay(150);
15524
15525         /* The pixel multiplier can only be updated once the
15526          * DPLL is enabled and the clocks are stable.
15527          *
15528          * So write it again.
15529          */
15530         I915_WRITE(DPLL(pipe), dpll);
15531
15532         /* We do this three times for luck */
15533         for (i = 0; i < 3 ; i++) {
15534                 I915_WRITE(DPLL(pipe), dpll);
15535                 POSTING_READ(DPLL(pipe));
15536                 udelay(150); /* wait for warmup */
15537         }
15538
15539         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15540         POSTING_READ(PIPECONF(pipe));
15541
15542         intel_wait_for_pipe_scanline_moving(crtc);
15543 }
15544
15545 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15546 {
15547         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15548
15549         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15550                       pipe_name(pipe));
15551
15552         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15553         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15554         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15555         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15556         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15557
15558         I915_WRITE(PIPECONF(pipe), 0);
15559         POSTING_READ(PIPECONF(pipe));
15560
15561         intel_wait_for_pipe_scanline_stopped(crtc);
15562
15563         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15564         POSTING_READ(DPLL(pipe));
15565 }
15566
15567 static void
15568 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15569 {
15570         struct intel_crtc *crtc;
15571
15572         if (INTEL_GEN(dev_priv) >= 4)
15573                 return;
15574
15575         for_each_intel_crtc(&dev_priv->drm, crtc) {
15576                 struct intel_plane *plane =
15577                         to_intel_plane(crtc->base.primary);
15578                 struct intel_crtc *plane_crtc;
15579                 enum pipe pipe;
15580
15581                 if (!plane->get_hw_state(plane, &pipe))
15582                         continue;
15583
15584                 if (pipe == crtc->pipe)
15585                         continue;
15586
15587                 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15588                               plane->base.name);
15589
15590                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15591                 intel_plane_disable_noatomic(plane_crtc, plane);
15592         }
15593 }
15594
15595 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15596 {
15597         struct drm_device *dev = crtc->base.dev;
15598         struct intel_encoder *encoder;
15599
15600         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15601                 return true;
15602
15603         return false;
15604 }
15605
15606 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15607 {
15608         struct drm_device *dev = encoder->base.dev;
15609         struct intel_connector *connector;
15610
15611         for_each_connector_on_encoder(dev, &encoder->base, connector)
15612                 return connector;
15613
15614         return NULL;
15615 }
15616
15617 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15618                               enum pipe pch_transcoder)
15619 {
15620         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15621                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15622 }
15623
15624 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15625                                 struct drm_modeset_acquire_ctx *ctx)
15626 {
15627         struct drm_device *dev = crtc->base.dev;
15628         struct drm_i915_private *dev_priv = to_i915(dev);
15629         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15630
15631         /* Clear any frame start delays used for debugging left by the BIOS */
15632         if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15633                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15634
15635                 I915_WRITE(reg,
15636                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15637         }
15638
15639         if (crtc->active) {
15640                 struct intel_plane *plane;
15641
15642                 /* Disable everything but the primary plane */
15643                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15644                         const struct intel_plane_state *plane_state =
15645                                 to_intel_plane_state(plane->base.state);
15646
15647                         if (plane_state->base.visible &&
15648                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15649                                 intel_plane_disable_noatomic(crtc, plane);
15650                 }
15651         }
15652
15653         /* Adjust the state of the output pipe according to whether we
15654          * have active connectors/encoders. */
15655         if (crtc->active && !intel_crtc_has_encoders(crtc))
15656                 intel_crtc_disable_noatomic(&crtc->base, ctx);
15657
15658         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15659                 /*
15660                  * We start out with underrun reporting disabled to avoid races.
15661                  * For correct bookkeeping mark this on active crtcs.
15662                  *
15663                  * Also on gmch platforms we dont have any hardware bits to
15664                  * disable the underrun reporting. Which means we need to start
15665                  * out with underrun reporting disabled also on inactive pipes,
15666                  * since otherwise we'll complain about the garbage we read when
15667                  * e.g. coming up after runtime pm.
15668                  *
15669                  * No protection against concurrent access is required - at
15670                  * worst a fifo underrun happens which also sets this to false.
15671                  */
15672                 crtc->cpu_fifo_underrun_disabled = true;
15673                 /*
15674                  * We track the PCH trancoder underrun reporting state
15675                  * within the crtc. With crtc for pipe A housing the underrun
15676                  * reporting state for PCH transcoder A, crtc for pipe B housing
15677                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15678                  * and marking underrun reporting as disabled for the non-existing
15679                  * PCH transcoders B and C would prevent enabling the south
15680                  * error interrupt (see cpt_can_enable_serr_int()).
15681                  */
15682                 if (has_pch_trancoder(dev_priv, crtc->pipe))
15683                         crtc->pch_fifo_underrun_disabled = true;
15684         }
15685 }
15686
15687 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15688 {
15689         struct intel_connector *connector;
15690
15691         /* We need to check both for a crtc link (meaning that the
15692          * encoder is active and trying to read from a pipe) and the
15693          * pipe itself being active. */
15694         bool has_active_crtc = encoder->base.crtc &&
15695                 to_intel_crtc(encoder->base.crtc)->active;
15696
15697         connector = intel_encoder_find_connector(encoder);
15698         if (connector && !has_active_crtc) {
15699                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15700                               encoder->base.base.id,
15701                               encoder->base.name);
15702
15703                 /* Connector is active, but has no active pipe. This is
15704                  * fallout from our resume register restoring. Disable
15705                  * the encoder manually again. */
15706                 if (encoder->base.crtc) {
15707                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15708
15709                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15710                                       encoder->base.base.id,
15711                                       encoder->base.name);
15712                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15713                         if (encoder->post_disable)
15714                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15715                 }
15716                 encoder->base.crtc = NULL;
15717
15718                 /* Inconsistent output/port/pipe state happens presumably due to
15719                  * a bug in one of the get_hw_state functions. Or someplace else
15720                  * in our code, like the register restore mess on resume. Clamp
15721                  * things to off as a safer default. */
15722
15723                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15724                 connector->base.encoder = NULL;
15725         }
15726
15727         /* notify opregion of the sanitized encoder state */
15728         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15729 }
15730
15731 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15732 {
15733         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15734
15735         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15736                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15737                 i915_disable_vga(dev_priv);
15738         }
15739 }
15740
15741 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15742 {
15743         /* This function can be called both from intel_modeset_setup_hw_state or
15744          * at a very early point in our resume sequence, where the power well
15745          * structures are not yet restored. Since this function is at a very
15746          * paranoid "someone might have enabled VGA while we were not looking"
15747          * level, just check if the power well is enabled instead of trying to
15748          * follow the "don't touch the power well if we don't need it" policy
15749          * the rest of the driver uses. */
15750         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15751                 return;
15752
15753         i915_redisable_vga_power_on(dev_priv);
15754
15755         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15756 }
15757
15758 /* FIXME read out full plane state for all planes */
15759 static void readout_plane_state(struct drm_i915_private *dev_priv)
15760 {
15761         struct intel_plane *plane;
15762         struct intel_crtc *crtc;
15763
15764         for_each_intel_plane(&dev_priv->drm, plane) {
15765                 struct intel_plane_state *plane_state =
15766                         to_intel_plane_state(plane->base.state);
15767                 struct intel_crtc_state *crtc_state;
15768                 enum pipe pipe = PIPE_A;
15769                 bool visible;
15770
15771                 visible = plane->get_hw_state(plane, &pipe);
15772
15773                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15774                 crtc_state = to_intel_crtc_state(crtc->base.state);
15775
15776                 intel_set_plane_visible(crtc_state, plane_state, visible);
15777         }
15778
15779         for_each_intel_crtc(&dev_priv->drm, crtc) {
15780                 struct intel_crtc_state *crtc_state =
15781                         to_intel_crtc_state(crtc->base.state);
15782
15783                 fixup_active_planes(crtc_state);
15784         }
15785 }
15786
15787 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15788 {
15789         struct drm_i915_private *dev_priv = to_i915(dev);
15790         enum pipe pipe;
15791         struct intel_crtc *crtc;
15792         struct intel_encoder *encoder;
15793         struct intel_connector *connector;
15794         struct drm_connector_list_iter conn_iter;
15795         int i;
15796
15797         dev_priv->active_crtcs = 0;
15798
15799         for_each_intel_crtc(dev, crtc) {
15800                 struct intel_crtc_state *crtc_state =
15801                         to_intel_crtc_state(crtc->base.state);
15802
15803                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15804                 memset(crtc_state, 0, sizeof(*crtc_state));
15805                 crtc_state->base.crtc = &crtc->base;
15806
15807                 crtc_state->base.active = crtc_state->base.enable =
15808                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15809
15810                 crtc->base.enabled = crtc_state->base.enable;
15811                 crtc->active = crtc_state->base.active;
15812
15813                 if (crtc_state->base.active)
15814                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15815
15816                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15817                               crtc->base.base.id, crtc->base.name,
15818                               enableddisabled(crtc_state->base.active));
15819         }
15820
15821         readout_plane_state(dev_priv);
15822
15823         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15824                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15825
15826                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15827                                                         &pll->state.hw_state);
15828                 pll->state.crtc_mask = 0;
15829                 for_each_intel_crtc(dev, crtc) {
15830                         struct intel_crtc_state *crtc_state =
15831                                 to_intel_crtc_state(crtc->base.state);
15832
15833                         if (crtc_state->base.active &&
15834                             crtc_state->shared_dpll == pll)
15835                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15836                 }
15837                 pll->active_mask = pll->state.crtc_mask;
15838
15839                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15840                               pll->info->name, pll->state.crtc_mask, pll->on);
15841         }
15842
15843         for_each_intel_encoder(dev, encoder) {
15844                 pipe = 0;
15845
15846                 if (encoder->get_hw_state(encoder, &pipe)) {
15847                         struct intel_crtc_state *crtc_state;
15848
15849                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15850                         crtc_state = to_intel_crtc_state(crtc->base.state);
15851
15852                         encoder->base.crtc = &crtc->base;
15853                         encoder->get_config(encoder, crtc_state);
15854                 } else {
15855                         encoder->base.crtc = NULL;
15856                 }
15857
15858                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15859                               encoder->base.base.id, encoder->base.name,
15860                               enableddisabled(encoder->base.crtc),
15861                               pipe_name(pipe));
15862         }
15863
15864         drm_connector_list_iter_begin(dev, &conn_iter);
15865         for_each_intel_connector_iter(connector, &conn_iter) {
15866                 if (connector->get_hw_state(connector)) {
15867                         connector->base.dpms = DRM_MODE_DPMS_ON;
15868
15869                         encoder = connector->encoder;
15870                         connector->base.encoder = &encoder->base;
15871
15872                         if (encoder->base.crtc &&
15873                             encoder->base.crtc->state->active) {
15874                                 /*
15875                                  * This has to be done during hardware readout
15876                                  * because anything calling .crtc_disable may
15877                                  * rely on the connector_mask being accurate.
15878                                  */
15879                                 encoder->base.crtc->state->connector_mask |=
15880                                         drm_connector_mask(&connector->base);
15881                                 encoder->base.crtc->state->encoder_mask |=
15882                                         drm_encoder_mask(&encoder->base);
15883                         }
15884
15885                 } else {
15886                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15887                         connector->base.encoder = NULL;
15888                 }
15889                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15890                               connector->base.base.id, connector->base.name,
15891                               enableddisabled(connector->base.encoder));
15892         }
15893         drm_connector_list_iter_end(&conn_iter);
15894
15895         for_each_intel_crtc(dev, crtc) {
15896                 struct intel_crtc_state *crtc_state =
15897                         to_intel_crtc_state(crtc->base.state);
15898                 int min_cdclk = 0;
15899
15900                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15901                 if (crtc_state->base.active) {
15902                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15903                         crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15904                         crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15905                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15906                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15907
15908                         /*
15909                          * The initial mode needs to be set in order to keep
15910                          * the atomic core happy. It wants a valid mode if the
15911                          * crtc's enabled, so we do the above call.
15912                          *
15913                          * But we don't set all the derived state fully, hence
15914                          * set a flag to indicate that a full recalculation is
15915                          * needed on the next commit.
15916                          */
15917                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15918
15919                         intel_crtc_compute_pixel_rate(crtc_state);
15920
15921                         if (dev_priv->display.modeset_calc_cdclk) {
15922                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15923                                 if (WARN_ON(min_cdclk < 0))
15924                                         min_cdclk = 0;
15925                         }
15926
15927                         drm_calc_timestamping_constants(&crtc->base,
15928                                                         &crtc_state->base.adjusted_mode);
15929                         update_scanline_offset(crtc);
15930                 }
15931
15932                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15933                 dev_priv->min_voltage_level[crtc->pipe] =
15934                         crtc_state->min_voltage_level;
15935
15936                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15937         }
15938 }
15939
15940 static void
15941 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15942 {
15943         struct intel_encoder *encoder;
15944
15945         for_each_intel_encoder(&dev_priv->drm, encoder) {
15946                 u64 get_domains;
15947                 enum intel_display_power_domain domain;
15948                 struct intel_crtc_state *crtc_state;
15949
15950                 if (!encoder->get_power_domains)
15951                         continue;
15952
15953                 /*
15954                  * MST-primary and inactive encoders don't have a crtc state
15955                  * and neither of these require any power domain references.
15956                  */
15957                 if (!encoder->base.crtc)
15958                         continue;
15959
15960                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
15961                 get_domains = encoder->get_power_domains(encoder, crtc_state);
15962                 for_each_power_domain(domain, get_domains)
15963                         intel_display_power_get(dev_priv, domain);
15964         }
15965 }
15966
15967 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15968 {
15969         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15970         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15971                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15972                            DARBF_GATING_DIS);
15973
15974         if (IS_HASWELL(dev_priv)) {
15975                 /*
15976                  * WaRsPkgCStateDisplayPMReq:hsw
15977                  * System hang if this isn't done before disabling all planes!
15978                  */
15979                 I915_WRITE(CHICKEN_PAR1_1,
15980                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15981         }
15982 }
15983
15984 /* Scan out the current hw modeset state,
15985  * and sanitizes it to the current state
15986  */
15987 static void
15988 intel_modeset_setup_hw_state(struct drm_device *dev,
15989                              struct drm_modeset_acquire_ctx *ctx)
15990 {
15991         struct drm_i915_private *dev_priv = to_i915(dev);
15992         struct intel_crtc *crtc;
15993         struct intel_encoder *encoder;
15994         int i;
15995
15996         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
15997
15998         intel_early_display_was(dev_priv);
15999         intel_modeset_readout_hw_state(dev);
16000
16001         /* HW state is read out, now we need to sanitize this mess. */
16002         get_encoder_power_domains(dev_priv);
16003
16004         /*
16005          * intel_sanitize_plane_mapping() may need to do vblank
16006          * waits, so we need vblank interrupts restored beforehand.
16007          */
16008         for_each_intel_crtc(&dev_priv->drm, crtc) {
16009                 drm_crtc_vblank_reset(&crtc->base);
16010
16011                 if (crtc->active)
16012                         drm_crtc_vblank_on(&crtc->base);
16013         }
16014
16015         intel_sanitize_plane_mapping(dev_priv);
16016
16017         for_each_intel_encoder(dev, encoder)
16018                 intel_sanitize_encoder(encoder);
16019
16020         for_each_intel_crtc(&dev_priv->drm, crtc) {
16021                 intel_sanitize_crtc(crtc, ctx);
16022                 intel_dump_pipe_config(crtc, crtc->config,
16023                                        "[setup_hw_state]");
16024         }
16025
16026         intel_modeset_update_connector_atomic_state(dev);
16027
16028         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16029                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16030
16031                 if (!pll->on || pll->active_mask)
16032                         continue;
16033
16034                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
16035                               pll->info->name);
16036
16037                 pll->info->funcs->disable(dev_priv, pll);
16038                 pll->on = false;
16039         }
16040
16041         if (IS_G4X(dev_priv)) {
16042                 g4x_wm_get_hw_state(dev);
16043                 g4x_wm_sanitize(dev_priv);
16044         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16045                 vlv_wm_get_hw_state(dev);
16046                 vlv_wm_sanitize(dev_priv);
16047         } else if (INTEL_GEN(dev_priv) >= 9) {
16048                 skl_wm_get_hw_state(dev);
16049         } else if (HAS_PCH_SPLIT(dev_priv)) {
16050                 ilk_wm_get_hw_state(dev);
16051         }
16052
16053         for_each_intel_crtc(dev, crtc) {
16054                 u64 put_domains;
16055
16056                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16057                 if (WARN_ON(put_domains))
16058                         modeset_put_power_domains(dev_priv, put_domains);
16059         }
16060
16061         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
16062
16063         intel_fbc_init_pipe_state(dev_priv);
16064 }
16065
16066 void intel_display_resume(struct drm_device *dev)
16067 {
16068         struct drm_i915_private *dev_priv = to_i915(dev);
16069         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16070         struct drm_modeset_acquire_ctx ctx;
16071         int ret;
16072
16073         dev_priv->modeset_restore_state = NULL;
16074         if (state)
16075                 state->acquire_ctx = &ctx;
16076
16077         drm_modeset_acquire_init(&ctx, 0);
16078
16079         while (1) {
16080                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16081                 if (ret != -EDEADLK)
16082                         break;
16083
16084                 drm_modeset_backoff(&ctx);
16085         }
16086
16087         if (!ret)
16088                 ret = __intel_display_resume(dev, state, &ctx);
16089
16090         intel_enable_ipc(dev_priv);
16091         drm_modeset_drop_locks(&ctx);
16092         drm_modeset_acquire_fini(&ctx);
16093
16094         if (ret)
16095                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16096         if (state)
16097                 drm_atomic_state_put(state);
16098 }
16099
16100 int intel_connector_register(struct drm_connector *connector)
16101 {
16102         struct intel_connector *intel_connector = to_intel_connector(connector);
16103         int ret;
16104
16105         ret = intel_backlight_device_register(intel_connector);
16106         if (ret)
16107                 goto err;
16108
16109         return 0;
16110
16111 err:
16112         return ret;
16113 }
16114
16115 void intel_connector_unregister(struct drm_connector *connector)
16116 {
16117         struct intel_connector *intel_connector = to_intel_connector(connector);
16118
16119         intel_backlight_device_unregister(intel_connector);
16120         intel_panel_destroy_backlight(connector);
16121 }
16122
16123 static void intel_hpd_poll_fini(struct drm_device *dev)
16124 {
16125         struct intel_connector *connector;
16126         struct drm_connector_list_iter conn_iter;
16127
16128         /* Kill all the work that may have been queued by hpd. */
16129         drm_connector_list_iter_begin(dev, &conn_iter);
16130         for_each_intel_connector_iter(connector, &conn_iter) {
16131                 if (connector->modeset_retry_work.func)
16132                         cancel_work_sync(&connector->modeset_retry_work);
16133                 if (connector->hdcp_shim) {
16134                         cancel_delayed_work_sync(&connector->hdcp_check_work);
16135                         cancel_work_sync(&connector->hdcp_prop_work);
16136                 }
16137         }
16138         drm_connector_list_iter_end(&conn_iter);
16139 }
16140
16141 void intel_modeset_cleanup(struct drm_device *dev)
16142 {
16143         struct drm_i915_private *dev_priv = to_i915(dev);
16144
16145         flush_workqueue(dev_priv->modeset_wq);
16146
16147         flush_work(&dev_priv->atomic_helper.free_work);
16148         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
16149
16150         /*
16151          * Interrupts and polling as the first thing to avoid creating havoc.
16152          * Too much stuff here (turning of connectors, ...) would
16153          * experience fancy races otherwise.
16154          */
16155         intel_irq_uninstall(dev_priv);
16156
16157         /*
16158          * Due to the hpd irq storm handling the hotplug work can re-arm the
16159          * poll handlers. Hence disable polling after hpd handling is shut down.
16160          */
16161         intel_hpd_poll_fini(dev);
16162
16163         /* poll work can call into fbdev, hence clean that up afterwards */
16164         intel_fbdev_fini(dev_priv);
16165
16166         intel_unregister_dsm_handler();
16167
16168         intel_fbc_global_disable(dev_priv);
16169
16170         /* flush any delayed tasks or pending work */
16171         flush_scheduled_work();
16172
16173         drm_mode_config_cleanup(dev);
16174
16175         intel_cleanup_overlay(dev_priv);
16176
16177         intel_teardown_gmbus(dev_priv);
16178
16179         destroy_workqueue(dev_priv->modeset_wq);
16180 }
16181
16182 void intel_connector_attach_encoder(struct intel_connector *connector,
16183                                     struct intel_encoder *encoder)
16184 {
16185         connector->encoder = encoder;
16186         drm_connector_attach_encoder(&connector->base, &encoder->base);
16187 }
16188
16189 /*
16190  * set vga decode state - true == enable VGA decode
16191  */
16192 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
16193 {
16194         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16195         u16 gmch_ctrl;
16196
16197         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16198                 DRM_ERROR("failed to read control word\n");
16199                 return -EIO;
16200         }
16201
16202         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16203                 return 0;
16204
16205         if (state)
16206                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16207         else
16208                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16209
16210         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16211                 DRM_ERROR("failed to write control word\n");
16212                 return -EIO;
16213         }
16214
16215         return 0;
16216 }
16217
16218 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16219
16220 struct intel_display_error_state {
16221
16222         u32 power_well_driver;
16223
16224         int num_transcoders;
16225
16226         struct intel_cursor_error_state {
16227                 u32 control;
16228                 u32 position;
16229                 u32 base;
16230                 u32 size;
16231         } cursor[I915_MAX_PIPES];
16232
16233         struct intel_pipe_error_state {
16234                 bool power_domain_on;
16235                 u32 source;
16236                 u32 stat;
16237         } pipe[I915_MAX_PIPES];
16238
16239         struct intel_plane_error_state {
16240                 u32 control;
16241                 u32 stride;
16242                 u32 size;
16243                 u32 pos;
16244                 u32 addr;
16245                 u32 surface;
16246                 u32 tile_offset;
16247         } plane[I915_MAX_PIPES];
16248
16249         struct intel_transcoder_error_state {
16250                 bool power_domain_on;
16251                 enum transcoder cpu_transcoder;
16252
16253                 u32 conf;
16254
16255                 u32 htotal;
16256                 u32 hblank;
16257                 u32 hsync;
16258                 u32 vtotal;
16259                 u32 vblank;
16260                 u32 vsync;
16261         } transcoder[4];
16262 };
16263
16264 struct intel_display_error_state *
16265 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16266 {
16267         struct intel_display_error_state *error;
16268         int transcoders[] = {
16269                 TRANSCODER_A,
16270                 TRANSCODER_B,
16271                 TRANSCODER_C,
16272                 TRANSCODER_EDP,
16273         };
16274         int i;
16275
16276         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16277                 return NULL;
16278
16279         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16280         if (error == NULL)
16281                 return NULL;
16282
16283         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16284                 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
16285
16286         for_each_pipe(dev_priv, i) {
16287                 error->pipe[i].power_domain_on =
16288                         __intel_display_power_is_enabled(dev_priv,
16289                                                          POWER_DOMAIN_PIPE(i));
16290                 if (!error->pipe[i].power_domain_on)
16291                         continue;
16292
16293                 error->cursor[i].control = I915_READ(CURCNTR(i));
16294                 error->cursor[i].position = I915_READ(CURPOS(i));
16295                 error->cursor[i].base = I915_READ(CURBASE(i));
16296
16297                 error->plane[i].control = I915_READ(DSPCNTR(i));
16298                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16299                 if (INTEL_GEN(dev_priv) <= 3) {
16300                         error->plane[i].size = I915_READ(DSPSIZE(i));
16301                         error->plane[i].pos = I915_READ(DSPPOS(i));
16302                 }
16303                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16304                         error->plane[i].addr = I915_READ(DSPADDR(i));
16305                 if (INTEL_GEN(dev_priv) >= 4) {
16306                         error->plane[i].surface = I915_READ(DSPSURF(i));
16307                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16308                 }
16309
16310                 error->pipe[i].source = I915_READ(PIPESRC(i));
16311
16312                 if (HAS_GMCH_DISPLAY(dev_priv))
16313                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16314         }
16315
16316         /* Note: this does not include DSI transcoders. */
16317         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16318         if (HAS_DDI(dev_priv))
16319                 error->num_transcoders++; /* Account for eDP. */
16320
16321         for (i = 0; i < error->num_transcoders; i++) {
16322                 enum transcoder cpu_transcoder = transcoders[i];
16323
16324                 error->transcoder[i].power_domain_on =
16325                         __intel_display_power_is_enabled(dev_priv,
16326                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16327                 if (!error->transcoder[i].power_domain_on)
16328                         continue;
16329
16330                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16331
16332                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16333                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16334                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16335                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16336                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16337                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16338                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16339         }
16340
16341         return error;
16342 }
16343
16344 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16345
16346 void
16347 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16348                                 struct intel_display_error_state *error)
16349 {
16350         struct drm_i915_private *dev_priv = m->i915;
16351         int i;
16352
16353         if (!error)
16354                 return;
16355
16356         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16357         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16358                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16359                            error->power_well_driver);
16360         for_each_pipe(dev_priv, i) {
16361                 err_printf(m, "Pipe [%d]:\n", i);
16362                 err_printf(m, "  Power: %s\n",
16363                            onoff(error->pipe[i].power_domain_on));
16364                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16365                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16366
16367                 err_printf(m, "Plane [%d]:\n", i);
16368                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16369                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16370                 if (INTEL_GEN(dev_priv) <= 3) {
16371                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16372                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16373                 }
16374                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16375                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16376                 if (INTEL_GEN(dev_priv) >= 4) {
16377                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16378                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16379                 }
16380
16381                 err_printf(m, "Cursor [%d]:\n", i);
16382                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16383                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16384                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16385         }
16386
16387         for (i = 0; i < error->num_transcoders; i++) {
16388                 err_printf(m, "CPU transcoder: %s\n",
16389                            transcoder_name(error->transcoder[i].cpu_transcoder));
16390                 err_printf(m, "  Power: %s\n",
16391                            onoff(error->transcoder[i].power_domain_on));
16392                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16393                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16394                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16395                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16396                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16397                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16398                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16399         }
16400 }
16401
16402 #endif