arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <[email protected]>
  12  *   Gregory Haskins <[email protected]>
  13  *   Yaozu (Eddie) Dong <[email protected]>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...) do {} while (0)
  59
  60 /* 14 is the version for Xeon and Pentium 8.4.8*/
  61 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  62 #define LAPIC_MMIO_LENGTH               (1 << 12)
  63 /* followed define is not in apicdef.h */
  64 #define APIC_SHORT_MASK                 0xc0000
  65 #define APIC_DEST_NOSHORT               0x0
  66 #define APIC_DEST_MASK                  0x800
  67 #define MAX_APIC_VECTOR                 256
  68 #define APIC_VECTORS_PER_REG            32
  69
  70 #define APIC_BROADCAST                  0xFF
  71 #define X2APIC_BROADCAST                0xFFFFFFFFul
  72
  73 static bool lapic_timer_advance_adjust_done = false;
  74 #define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100
  75 /* step-by-step approximation to mitigate fluctuation */
  76 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
  77
  78 static inline int apic_test_vector(int vec, void *bitmap)
  79 {
  80         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  81 }
  82
  83 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  84 {
  85         struct kvm_lapic *apic = vcpu->arch.apic;
  86
  87         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  88                 apic_test_vector(vector, apic->regs + APIC_IRR);
  89 }
  90
  91 static inline void apic_clear_vector(int vec, void *bitmap)
  92 {
  93         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  97 {
  98         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 102 {
 103         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 struct static_key_deferred apic_hw_disabled __read_mostly;
 107 struct static_key_deferred apic_sw_disabled __read_mostly;
 108
 109 static inline int apic_enabled(struct kvm_lapic *apic)
 110 {
 111         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 112 }
 113
 114 #define LVT_MASK        \
 115         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 116
 117 #define LINT_MASK       \
 118         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 119          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 120
 121 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 122 {
 123         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 124 }
 125
 126 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 127 {
 128         return apic->vcpu->vcpu_id;
 129 }
 130
 131 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 132                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 133         switch (map->mode) {
 134         case KVM_APIC_MODE_X2APIC: {
 135                 u32 offset = (dest_id >> 16) * 16;
 136                 u32 max_apic_id = map->max_apic_id;
 137
 138                 if (offset <= max_apic_id) {
 139                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 140
 141                         *cluster = &map->phys_map[offset];
 142                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 143                 } else {
 144                         *mask = 0;
 145                 }
 146
 147                 return true;
 148                 }
 149         case KVM_APIC_MODE_XAPIC_FLAT:
 150                 *cluster = map->xapic_flat_map;
 151                 *mask = dest_id & 0xff;
 152                 return true;
 153         case KVM_APIC_MODE_XAPIC_CLUSTER:
 154                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 155                 *mask = dest_id & 0xf;
 156                 return true;
 157         default:
 158                 /* Not optimized. */
 159                 return false;
 160         }
 161 }
 162
 163 static void kvm_apic_map_free(struct rcu_head *rcu)
 164 {
 165         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 166
 167         kvfree(map);
 168 }
 169
 170 static void recalculate_apic_map(struct kvm *kvm)
 171 {
 172         struct kvm_apic_map *new, *old = NULL;
 173         struct kvm_vcpu *vcpu;
 174         int i;
 175         u32 max_id = 255; /* enough space for any xAPIC ID */
 176
 177         mutex_lock(&kvm->arch.apic_map_lock);
 178
 179         kvm_for_each_vcpu(i, vcpu, kvm)
 180                 if (kvm_apic_present(vcpu))
 181                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 182
 183         new = kvzalloc(sizeof(struct kvm_apic_map) +
 184                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
 185
 186         if (!new)
 187                 goto out;
 188
 189         new->max_apic_id = max_id;
 190
 191         kvm_for_each_vcpu(i, vcpu, kvm) {
 192                 struct kvm_lapic *apic = vcpu->arch.apic;
 193                 struct kvm_lapic **cluster;
 194                 u16 mask;
 195                 u32 ldr;
 196                 u8 xapic_id;
 197                 u32 x2apic_id;
 198
 199                 if (!kvm_apic_present(vcpu))
 200                         continue;
 201
 202                 xapic_id = kvm_xapic_id(apic);
 203                 x2apic_id = kvm_x2apic_id(apic);
 204
 205                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 206                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 207                                 x2apic_id <= new->max_apic_id)
 208                         new->phys_map[x2apic_id] = apic;
 209                 /*
 210                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 211                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 212                  */
 213                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 214                         new->phys_map[xapic_id] = apic;
 215
 216                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 217
 218                 if (apic_x2apic_mode(apic)) {
 219                         new->mode |= KVM_APIC_MODE_X2APIC;
 220                 } else if (ldr) {
 221                         ldr = GET_APIC_LOGICAL_ID(ldr);
 222                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 223                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 224                         else
 225                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 226                 }
 227
 228                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 229                         continue;
 230
 231                 if (mask)
 232                         cluster[ffs(mask) - 1] = apic;
 233         }
 234 out:
 235         old = rcu_dereference_protected(kvm->arch.apic_map,
 236                         lockdep_is_held(&kvm->arch.apic_map_lock));
 237         rcu_assign_pointer(kvm->arch.apic_map, new);
 238         mutex_unlock(&kvm->arch.apic_map_lock);
 239
 240         if (old)
 241                 call_rcu(&old->rcu, kvm_apic_map_free);
 242
 243         kvm_make_scan_ioapic_request(kvm);
 244 }
 245
 246 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 247 {
 248         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 249
 250         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 251
 252         if (enabled != apic->sw_enabled) {
 253                 apic->sw_enabled = enabled;
 254                 if (enabled) {
 255                         static_key_slow_dec_deferred(&apic_sw_disabled);
 256                         recalculate_apic_map(apic->vcpu->kvm);
 257                 } else
 258                         static_key_slow_inc(&apic_sw_disabled.key);
 259         }
 260 }
 261
 262 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 263 {
 264         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 265         recalculate_apic_map(apic->vcpu->kvm);
 266 }
 267
 268 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 269 {
 270         kvm_lapic_set_reg(apic, APIC_LDR, id);
 271         recalculate_apic_map(apic->vcpu->kvm);
 272 }
 273
 274 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
 275 {
 276         return ((id >> 4) << 16) | (1 << (id & 0xf));
 277 }
 278
 279 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 280 {
 281         u32 ldr = kvm_apic_calc_x2apic_ldr(id);
 282
 283         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 284
 285         kvm_lapic_set_reg(apic, APIC_ID, id);
 286         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 287         recalculate_apic_map(apic->vcpu->kvm);
 288 }
 289
 290 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 291 {
 292         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 293 }
 294
 295 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 296 {
 297         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 298 }
 299
 300 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 301 {
 302         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 303 }
 304
 305 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 306 {
 307         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 308 }
 309
 310 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 311 {
 312         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 313 }
 314
 315 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 316 {
 317         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 318 }
 319
 320 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 321 {
 322         struct kvm_lapic *apic = vcpu->arch.apic;
 323         struct kvm_cpuid_entry2 *feat;
 324         u32 v = APIC_VERSION;
 325
 326         if (!lapic_in_kernel(vcpu))
 327                 return;
 328
 329         /*
 330          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 331          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 332          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 333          * version first and level-triggered interrupts never get EOIed in
 334          * IOAPIC.
 335          */
 336         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 337         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
 338             !ioapic_in_kernel(vcpu->kvm))
 339                 v |= APIC_LVR_DIRECTED_EOI;
 340         kvm_lapic_set_reg(apic, APIC_LVR, v);
 341 }
 342
 343 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 344         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 345         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 346         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 347         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 348         LVT_MASK                /* LVTERR */
 349 };
 350
 351 static int find_highest_vector(void *bitmap)
 352 {
 353         int vec;
 354         u32 *reg;
 355
 356         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 357              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 358                 reg = bitmap + REG_POS(vec);
 359                 if (*reg)
 360                         return __fls(*reg) + vec;
 361         }
 362
 363         return -1;
 364 }
 365
 366 static u8 count_vectors(void *bitmap)
 367 {
 368         int vec;
 369         u32 *reg;
 370         u8 count = 0;
 371
 372         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 373                 reg = bitmap + REG_POS(vec);
 374                 count += hweight32(*reg);
 375         }
 376
 377         return count;
 378 }
 379
 380 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 381 {
 382         u32 i, vec;
 383         u32 pir_val, irr_val, prev_irr_val;
 384         int max_updated_irr;
 385
 386         max_updated_irr = -1;
 387         *max_irr = -1;
 388
 389         for (i = vec = 0; i <= 7; i++, vec += 32) {
 390                 pir_val = READ_ONCE(pir[i]);
 391                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 392                 if (pir_val) {
 393                         prev_irr_val = irr_val;
 394                         irr_val |= xchg(&pir[i], 0);
 395                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 396                         if (prev_irr_val != irr_val) {
 397                                 max_updated_irr =
 398                                         __fls(irr_val ^ prev_irr_val) + vec;
 399                         }
 400                 }
 401                 if (irr_val)
 402                         *max_irr = __fls(irr_val) + vec;
 403         }
 404
 405         return ((max_updated_irr != -1) &&
 406                 (max_updated_irr == *max_irr));
 407 }
 408 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 409
 410 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 411 {
 412         struct kvm_lapic *apic = vcpu->arch.apic;
 413
 414         return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 415 }
 416 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 417
 418 static inline int apic_search_irr(struct kvm_lapic *apic)
 419 {
 420         return find_highest_vector(apic->regs + APIC_IRR);
 421 }
 422
 423 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 424 {
 425         int result;
 426
 427         /*
 428          * Note that irr_pending is just a hint. It will be always
 429          * true with virtual interrupt delivery enabled.
 430          */
 431         if (!apic->irr_pending)
 432                 return -1;
 433
 434         result = apic_search_irr(apic);
 435         ASSERT(result == -1 || result >= 16);
 436
 437         return result;
 438 }
 439
 440 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 441 {
 442         struct kvm_vcpu *vcpu;
 443
 444         vcpu = apic->vcpu;
 445
 446         if (unlikely(vcpu->arch.apicv_active)) {
 447                 /* need to update RVI */
 448                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 449                 kvm_x86_ops->hwapic_irr_update(vcpu,
 450                                 apic_find_highest_irr(apic));
 451         } else {
 452                 apic->irr_pending = false;
 453                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 454                 if (apic_search_irr(apic) != -1)
 455                         apic->irr_pending = true;
 456         }
 457 }
 458
 459 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 460 {
 461         struct kvm_vcpu *vcpu;
 462
 463         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 464                 return;
 465
 466         vcpu = apic->vcpu;
 467
 468         /*
 469          * With APIC virtualization enabled, all caching is disabled
 470          * because the processor can modify ISR under the hood.  Instead
 471          * just set SVI.
 472          */
 473         if (unlikely(vcpu->arch.apicv_active))
 474                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 475         else {
 476                 ++apic->isr_count;
 477                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 478                 /*
 479                  * ISR (in service register) bit is set when injecting an interrupt.
 480                  * The highest vector is injected. Thus the latest bit set matches
 481                  * the highest bit in ISR.
 482                  */
 483                 apic->highest_isr_cache = vec;
 484         }
 485 }
 486
 487 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 488 {
 489         int result;
 490
 491         /*
 492          * Note that isr_count is always 1, and highest_isr_cache
 493          * is always -1, with APIC virtualization enabled.
 494          */
 495         if (!apic->isr_count)
 496                 return -1;
 497         if (likely(apic->highest_isr_cache != -1))
 498                 return apic->highest_isr_cache;
 499
 500         result = find_highest_vector(apic->regs + APIC_ISR);
 501         ASSERT(result == -1 || result >= 16);
 502
 503         return result;
 504 }
 505
 506 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 507 {
 508         struct kvm_vcpu *vcpu;
 509         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 510                 return;
 511
 512         vcpu = apic->vcpu;
 513
 514         /*
 515          * We do get here for APIC virtualization enabled if the guest
 516          * uses the Hyper-V APIC enlightenment.  In this case we may need
 517          * to trigger a new interrupt delivery by writing the SVI field;
 518          * on the other hand isr_count and highest_isr_cache are unused
 519          * and must be left alone.
 520          */
 521         if (unlikely(vcpu->arch.apicv_active))
 522                 kvm_x86_ops->hwapic_isr_update(vcpu,
 523                                                apic_find_highest_isr(apic));
 524         else {
 525                 --apic->isr_count;
 526                 BUG_ON(apic->isr_count < 0);
 527                 apic->highest_isr_cache = -1;
 528         }
 529 }
 530
 531 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 532 {
 533         /* This may race with setting of irr in __apic_accept_irq() and
 534          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 535          * will cause vmexit immediately and the value will be recalculated
 536          * on the next vmentry.
 537          */
 538         return apic_find_highest_irr(vcpu->arch.apic);
 539 }
 540 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 541
 542 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 543                              int vector, int level, int trig_mode,
 544                              struct dest_map *dest_map);
 545
 546 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 547                      struct dest_map *dest_map)
 548 {
 549         struct kvm_lapic *apic = vcpu->arch.apic;
 550
 551         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 552                         irq->level, irq->trig_mode, dest_map);
 553 }
 554
 555 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
 556                     unsigned long ipi_bitmap_high, u32 min,
 557                     unsigned long icr, int op_64_bit)
 558 {
 559         int i;
 560         struct kvm_apic_map *map;
 561         struct kvm_vcpu *vcpu;
 562         struct kvm_lapic_irq irq = {0};
 563         int cluster_size = op_64_bit ? 64 : 32;
 564         int count = 0;
 565
 566         irq.vector = icr & APIC_VECTOR_MASK;
 567         irq.delivery_mode = icr & APIC_MODE_MASK;
 568         irq.level = (icr & APIC_INT_ASSERT) != 0;
 569         irq.trig_mode = icr & APIC_INT_LEVELTRIG;
 570
 571         if (icr & APIC_DEST_MASK)
 572                 return -KVM_EINVAL;
 573         if (icr & APIC_SHORT_MASK)
 574                 return -KVM_EINVAL;
 575
 576         rcu_read_lock();
 577         map = rcu_dereference(kvm->arch.apic_map);
 578
 579         if (unlikely(!map)) {
 580                 count = -EOPNOTSUPP;
 581                 goto out;
 582         }
 583
 584         if (min > map->max_apic_id)
 585                 goto out;
 586         /* Bits above cluster_size are masked in the caller.  */
 587         for_each_set_bit(i, &ipi_bitmap_low,
 588                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 589                 if (map->phys_map[min + i]) {
 590                         vcpu = map->phys_map[min + i]->vcpu;
 591                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 592                 }
 593         }
 594
 595         min += cluster_size;
 596
 597         if (min > map->max_apic_id)
 598                 goto out;
 599
 600         for_each_set_bit(i, &ipi_bitmap_high,
 601                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 602                 if (map->phys_map[min + i]) {
 603                         vcpu = map->phys_map[min + i]->vcpu;
 604                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 605                 }
 606         }
 607
 608 out:
 609         rcu_read_unlock();
 610         return count;
 611 }
 612
 613 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 614 {
 615
 616         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 617                                       sizeof(val));
 618 }
 619
 620 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 621 {
 622
 623         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 624                                       sizeof(*val));
 625 }
 626
 627 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 628 {
 629         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 630 }
 631
 632 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 633 {
 634         u8 val;
 635         if (pv_eoi_get_user(vcpu, &val) < 0)
 636                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 637                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 638         return val & 0x1;
 639 }
 640
 641 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 642 {
 643         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 644                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 645                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 646                 return;
 647         }
 648         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 649 }
 650
 651 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 652 {
 653         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 654                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 655                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 656                 return;
 657         }
 658         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 659 }
 660
 661 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 662 {
 663         int highest_irr;
 664         if (apic->vcpu->arch.apicv_active)
 665                 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 666         else
 667                 highest_irr = apic_find_highest_irr(apic);
 668         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 669                 return -1;
 670         return highest_irr;
 671 }
 672
 673 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 674 {
 675         u32 tpr, isrv, ppr, old_ppr;
 676         int isr;
 677
 678         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 679         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 680         isr = apic_find_highest_isr(apic);
 681         isrv = (isr != -1) ? isr : 0;
 682
 683         if ((tpr & 0xf0) >= (isrv & 0xf0))
 684                 ppr = tpr & 0xff;
 685         else
 686                 ppr = isrv & 0xf0;
 687
 688         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 689                    apic, ppr, isr, isrv);
 690
 691         *new_ppr = ppr;
 692         if (old_ppr != ppr)
 693                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 694
 695         return ppr < old_ppr;
 696 }
 697
 698 static void apic_update_ppr(struct kvm_lapic *apic)
 699 {
 700         u32 ppr;
 701
 702         if (__apic_update_ppr(apic, &ppr) &&
 703             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 704                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 705 }
 706
 707 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 708 {
 709         apic_update_ppr(vcpu->arch.apic);
 710 }
 711 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 712
 713 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 714 {
 715         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 716         apic_update_ppr(apic);
 717 }
 718
 719 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 720 {
 721         return mda == (apic_x2apic_mode(apic) ?
 722                         X2APIC_BROADCAST : APIC_BROADCAST);
 723 }
 724
 725 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 726 {
 727         if (kvm_apic_broadcast(apic, mda))
 728                 return true;
 729
 730         if (apic_x2apic_mode(apic))
 731                 return mda == kvm_x2apic_id(apic);
 732
 733         /*
 734          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 735          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 736          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 737          * The 0xff condition is needed because writeable xAPIC ID.
 738          */
 739         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 740                 return true;
 741
 742         return mda == kvm_xapic_id(apic);
 743 }
 744
 745 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 746 {
 747         u32 logical_id;
 748
 749         if (kvm_apic_broadcast(apic, mda))
 750                 return true;
 751
 752         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 753
 754         if (apic_x2apic_mode(apic))
 755                 return ((logical_id >> 16) == (mda >> 16))
 756                        && (logical_id & mda & 0xffff) != 0;
 757
 758         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 759
 760         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 761         case APIC_DFR_FLAT:
 762                 return (logical_id & mda) != 0;
 763         case APIC_DFR_CLUSTER:
 764                 return ((logical_id >> 4) == (mda >> 4))
 765                        && (logical_id & mda & 0xf) != 0;
 766         default:
 767                 apic_debug("Bad DFR vcpu %d: %08x\n",
 768                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 769                 return false;
 770         }
 771 }
 772
 773 /* The KVM local APIC implementation has two quirks:
 774  *
 775  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 776  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 777  *    KVM doesn't do that aliasing.
 778  *
 779  *  - in-kernel IOAPIC messages have to be delivered directly to
 780  *    x2APIC, because the kernel does not support interrupt remapping.
 781  *    In order to support broadcast without interrupt remapping, x2APIC
 782  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 783  *    to X2APIC_BROADCAST.
 784  *
 785  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 786  * important when userspace wants to use x2APIC-format MSIs, because
 787  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 788  */
 789 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 790                 struct kvm_lapic *source, struct kvm_lapic *target)
 791 {
 792         bool ipi = source != NULL;
 793
 794         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 795             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 796                 return X2APIC_BROADCAST;
 797
 798         return dest_id;
 799 }
 800
 801 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 802                            int short_hand, unsigned int dest, int dest_mode)
 803 {
 804         struct kvm_lapic *target = vcpu->arch.apic;
 805         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 806
 807         apic_debug("target %p, source %p, dest 0x%x, "
 808                    "dest_mode 0x%x, short_hand 0x%x\n",
 809                    target, source, dest, dest_mode, short_hand);
 810
 811         ASSERT(target);
 812         switch (short_hand) {
 813         case APIC_DEST_NOSHORT:
 814                 if (dest_mode == APIC_DEST_PHYSICAL)
 815                         return kvm_apic_match_physical_addr(target, mda);
 816                 else
 817                         return kvm_apic_match_logical_addr(target, mda);
 818         case APIC_DEST_SELF:
 819                 return target == source;
 820         case APIC_DEST_ALLINC:
 821                 return true;
 822         case APIC_DEST_ALLBUT:
 823                 return target != source;
 824         default:
 825                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 826                            short_hand);
 827                 return false;
 828         }
 829 }
 830 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 831
 832 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 833                        const unsigned long *bitmap, u32 bitmap_size)
 834 {
 835         u32 mod;
 836         int i, idx = -1;
 837
 838         mod = vector % dest_vcpus;
 839
 840         for (i = 0; i <= mod; i++) {
 841                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 842                 BUG_ON(idx == bitmap_size);
 843         }
 844
 845         return idx;
 846 }
 847
 848 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 849 {
 850         if (!kvm->arch.disabled_lapic_found) {
 851                 kvm->arch.disabled_lapic_found = true;
 852                 printk(KERN_INFO
 853                        "Disabled LAPIC found during irq injection\n");
 854         }
 855 }
 856
 857 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 858                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 859 {
 860         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 861                 if ((irq->dest_id == APIC_BROADCAST &&
 862                                 map->mode != KVM_APIC_MODE_X2APIC))
 863                         return true;
 864                 if (irq->dest_id == X2APIC_BROADCAST)
 865                         return true;
 866         } else {
 867                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 868                 if (irq->dest_id == (x2apic_ipi ?
 869                                      X2APIC_BROADCAST : APIC_BROADCAST))
 870                         return true;
 871         }
 872
 873         return false;
 874 }
 875
 876 /* Return true if the interrupt can be handled by using *bitmap as index mask
 877  * for valid destinations in *dst array.
 878  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 879  * Note: we may have zero kvm_lapic destinations when we return true, which
 880  * means that the interrupt should be dropped.  In this case, *bitmap would be
 881  * zero and *dst undefined.
 882  */
 883 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 884                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 885                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 886                 unsigned long *bitmap)
 887 {
 888         int i, lowest;
 889
 890         if (irq->shorthand == APIC_DEST_SELF && src) {
 891                 *dst = src;
 892                 *bitmap = 1;
 893                 return true;
 894         } else if (irq->shorthand)
 895                 return false;
 896
 897         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 898                 return false;
 899
 900         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 901                 if (irq->dest_id > map->max_apic_id) {
 902                         *bitmap = 0;
 903                 } else {
 904                         *dst = &map->phys_map[irq->dest_id];
 905                         *bitmap = 1;
 906                 }
 907                 return true;
 908         }
 909
 910         *bitmap = 0;
 911         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 912                                 (u16 *)bitmap))
 913                 return false;
 914
 915         if (!kvm_lowest_prio_delivery(irq))
 916                 return true;
 917
 918         if (!kvm_vector_hashing_enabled()) {
 919                 lowest = -1;
 920                 for_each_set_bit(i, bitmap, 16) {
 921                         if (!(*dst)[i])
 922                                 continue;
 923                         if (lowest < 0)
 924                                 lowest = i;
 925                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 926                                                 (*dst)[lowest]->vcpu) < 0)
 927                                 lowest = i;
 928                 }
 929         } else {
 930                 if (!*bitmap)
 931                         return true;
 932
 933                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 934                                 bitmap, 16);
 935
 936                 if (!(*dst)[lowest]) {
 937                         kvm_apic_disabled_lapic_found(kvm);
 938                         *bitmap = 0;
 939                         return true;
 940                 }
 941         }
 942
 943         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 944
 945         return true;
 946 }
 947
 948 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 949                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 950 {
 951         struct kvm_apic_map *map;
 952         unsigned long bitmap;
 953         struct kvm_lapic **dst = NULL;
 954         int i;
 955         bool ret;
 956
 957         *r = -1;
 958
 959         if (irq->shorthand == APIC_DEST_SELF) {
 960                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 961                 return true;
 962         }
 963
 964         rcu_read_lock();
 965         map = rcu_dereference(kvm->arch.apic_map);
 966
 967         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 968         if (ret) {
 969                 *r = 0;
 970                 for_each_set_bit(i, &bitmap, 16) {
 971                         if (!dst[i])
 972                                 continue;
 973                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 974                 }
 975         }
 976
 977         rcu_read_unlock();
 978         return ret;
 979 }
 980
 981 /*
 982  * This routine tries to handler interrupts in posted mode, here is how
 983  * it deals with different cases:
 984  * - For single-destination interrupts, handle it in posted mode
 985  * - Else if vector hashing is enabled and it is a lowest-priority
 986  *   interrupt, handle it in posted mode and use the following mechanism
 987  *   to find the destinaiton vCPU.
 988  *      1. For lowest-priority interrupts, store all the possible
 989  *         destination vCPUs in an array.
 990  *      2. Use "guest vector % max number of destination vCPUs" to find
 991  *         the right destination vCPU in the array for the lowest-priority
 992  *         interrupt.
 993  * - Otherwise, use remapped mode to inject the interrupt.
 994  */
 995 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 996                         struct kvm_vcpu **dest_vcpu)
 997 {
 998         struct kvm_apic_map *map;
 999         unsigned long bitmap;
1000         struct kvm_lapic **dst = NULL;
1001         bool ret = false;
1002
1003         if (irq->shorthand)
1004                 return false;
1005
1006         rcu_read_lock();
1007         map = rcu_dereference(kvm->arch.apic_map);
1008
1009         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1010                         hweight16(bitmap) == 1) {
1011                 unsigned long i = find_first_bit(&bitmap, 16);
1012
1013                 if (dst[i]) {
1014                         *dest_vcpu = dst[i]->vcpu;
1015                         ret = true;
1016                 }
1017         }
1018
1019         rcu_read_unlock();
1020         return ret;
1021 }
1022
1023 /*
1024  * Add a pending IRQ into lapic.
1025  * Return 1 if successfully added and 0 if discarded.
1026  */
1027 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1028                              int vector, int level, int trig_mode,
1029                              struct dest_map *dest_map)
1030 {
1031         int result = 0;
1032         struct kvm_vcpu *vcpu = apic->vcpu;
1033
1034         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1035                                   trig_mode, vector);
1036         switch (delivery_mode) {
1037         case APIC_DM_LOWEST:
1038                 vcpu->arch.apic_arb_prio++;
1039         case APIC_DM_FIXED:
1040                 if (unlikely(trig_mode && !level))
1041                         break;
1042
1043                 /* FIXME add logic for vcpu on reset */
1044                 if (unlikely(!apic_enabled(apic)))
1045                         break;
1046
1047                 result = 1;
1048
1049                 if (dest_map) {
1050                         __set_bit(vcpu->vcpu_id, dest_map->map);
1051                         dest_map->vectors[vcpu->vcpu_id] = vector;
1052                 }
1053
1054                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1055                         if (trig_mode)
1056                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
1057                         else
1058                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
1059                 }
1060
1061                 if (vcpu->arch.apicv_active)
1062                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1063                 else {
1064                         kvm_lapic_set_irr(vector, apic);
1065
1066                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1067                         kvm_vcpu_kick(vcpu);
1068                 }
1069                 break;
1070
1071         case APIC_DM_REMRD:
1072                 result = 1;
1073                 vcpu->arch.pv.pv_unhalted = 1;
1074                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1075                 kvm_vcpu_kick(vcpu);
1076                 break;
1077
1078         case APIC_DM_SMI:
1079                 result = 1;
1080                 kvm_make_request(KVM_REQ_SMI, vcpu);
1081                 kvm_vcpu_kick(vcpu);
1082                 break;
1083
1084         case APIC_DM_NMI:
1085                 result = 1;
1086                 kvm_inject_nmi(vcpu);
1087                 kvm_vcpu_kick(vcpu);
1088                 break;
1089
1090         case APIC_DM_INIT:
1091                 if (!trig_mode || level) {
1092                         result = 1;
1093                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1094                         apic->pending_events = (1UL << KVM_APIC_INIT);
1095                         /* make sure pending_events is visible before sending
1096                          * the request */
1097                         smp_wmb();
1098                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1099                         kvm_vcpu_kick(vcpu);
1100                 } else {
1101                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1102                                    vcpu->vcpu_id);
1103                 }
1104                 break;
1105
1106         case APIC_DM_STARTUP:
1107                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1108                            vcpu->vcpu_id, vector);
1109                 result = 1;
1110                 apic->sipi_vector = vector;
1111                 /* make sure sipi_vector is visible for the receiver */
1112                 smp_wmb();
1113                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1114                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1115                 kvm_vcpu_kick(vcpu);
1116                 break;
1117
1118         case APIC_DM_EXTINT:
1119                 /*
1120                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1121                  * before NMI watchdog was enabled. Already handled by
1122                  * kvm_apic_accept_pic_intr().
1123                  */
1124                 break;
1125
1126         default:
1127                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1128                        delivery_mode);
1129                 break;
1130         }
1131         return result;
1132 }
1133
1134 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1135 {
1136         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1137 }
1138
1139 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1140 {
1141         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1142 }
1143
1144 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1145 {
1146         int trigger_mode;
1147
1148         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1149         if (!kvm_ioapic_handles_vector(apic, vector))
1150                 return;
1151
1152         /* Request a KVM exit to inform the userspace IOAPIC. */
1153         if (irqchip_split(apic->vcpu->kvm)) {
1154                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1155                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1156                 return;
1157         }
1158
1159         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1160                 trigger_mode = IOAPIC_LEVEL_TRIG;
1161         else
1162                 trigger_mode = IOAPIC_EDGE_TRIG;
1163
1164         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1165 }
1166
1167 static int apic_set_eoi(struct kvm_lapic *apic)
1168 {
1169         int vector = apic_find_highest_isr(apic);
1170
1171         trace_kvm_eoi(apic, vector);
1172
1173         /*
1174          * Not every write EOI will has corresponding ISR,
1175          * one example is when Kernel check timer on setup_IO_APIC
1176          */
1177         if (vector == -1)
1178                 return vector;
1179
1180         apic_clear_isr(vector, apic);
1181         apic_update_ppr(apic);
1182
1183         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1184                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1185
1186         kvm_ioapic_send_eoi(apic, vector);
1187         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1188         return vector;
1189 }
1190
1191 /*
1192  * this interface assumes a trap-like exit, which has already finished
1193  * desired side effect including vISR and vPPR update.
1194  */
1195 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1196 {
1197         struct kvm_lapic *apic = vcpu->arch.apic;
1198
1199         trace_kvm_eoi(apic, vector);
1200
1201         kvm_ioapic_send_eoi(apic, vector);
1202         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1203 }
1204 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1205
1206 static void apic_send_ipi(struct kvm_lapic *apic)
1207 {
1208         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1209         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1210         struct kvm_lapic_irq irq;
1211
1212         irq.vector = icr_low & APIC_VECTOR_MASK;
1213         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1214         irq.dest_mode = icr_low & APIC_DEST_MASK;
1215         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1216         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1217         irq.shorthand = icr_low & APIC_SHORT_MASK;
1218         irq.msi_redir_hint = false;
1219         if (apic_x2apic_mode(apic))
1220                 irq.dest_id = icr_high;
1221         else
1222                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1223
1224         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1225
1226         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1227                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1228                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1229                    "msi_redir_hint 0x%x\n",
1230                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1231                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1232                    irq.vector, irq.msi_redir_hint);
1233
1234         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1235 }
1236
1237 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1238 {
1239         ktime_t remaining, now;
1240         s64 ns;
1241         u32 tmcct;
1242
1243         ASSERT(apic != NULL);
1244
1245         /* if initial count is 0, current count should also be 0 */
1246         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1247                 apic->lapic_timer.period == 0)
1248                 return 0;
1249
1250         now = ktime_get();
1251         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1252         if (ktime_to_ns(remaining) < 0)
1253                 remaining = 0;
1254
1255         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1256         tmcct = div64_u64(ns,
1257                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1258
1259         return tmcct;
1260 }
1261
1262 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1263 {
1264         struct kvm_vcpu *vcpu = apic->vcpu;
1265         struct kvm_run *run = vcpu->run;
1266
1267         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1268         run->tpr_access.rip = kvm_rip_read(vcpu);
1269         run->tpr_access.is_write = write;
1270 }
1271
1272 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1273 {
1274         if (apic->vcpu->arch.tpr_access_reporting)
1275                 __report_tpr_access(apic, write);
1276 }
1277
1278 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1279 {
1280         u32 val = 0;
1281
1282         if (offset >= LAPIC_MMIO_LENGTH)
1283                 return 0;
1284
1285         switch (offset) {
1286         case APIC_ARBPRI:
1287                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1288                 break;
1289
1290         case APIC_TMCCT:        /* Timer CCR */
1291                 if (apic_lvtt_tscdeadline(apic))
1292                         return 0;
1293
1294                 val = apic_get_tmcct(apic);
1295                 break;
1296         case APIC_PROCPRI:
1297                 apic_update_ppr(apic);
1298                 val = kvm_lapic_get_reg(apic, offset);
1299                 break;
1300         case APIC_TASKPRI:
1301                 report_tpr_access(apic, false);
1302                 /* fall thru */
1303         default:
1304                 val = kvm_lapic_get_reg(apic, offset);
1305                 break;
1306         }
1307
1308         return val;
1309 }
1310
1311 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1312 {
1313         return container_of(dev, struct kvm_lapic, dev);
1314 }
1315
1316 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1317                 void *data)
1318 {
1319         unsigned char alignment = offset & 0xf;
1320         u32 result;
1321         /* this bitmask has a bit cleared for each reserved register */
1322         static const u64 rmask = 0x43ff01ffffffe70cULL;
1323
1324         if ((alignment + len) > 4) {
1325                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1326                            offset, len);
1327                 return 1;
1328         }
1329
1330         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1331                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1332                            offset);
1333                 return 1;
1334         }
1335
1336         result = __apic_read(apic, offset & ~0xf);
1337
1338         trace_kvm_apic_read(offset, result);
1339
1340         switch (len) {
1341         case 1:
1342         case 2:
1343         case 4:
1344                 memcpy(data, (char *)&result + alignment, len);
1345                 break;
1346         default:
1347                 printk(KERN_ERR "Local APIC read with len = %x, "
1348                        "should be 1,2, or 4 instead\n", len);
1349                 break;
1350         }
1351         return 0;
1352 }
1353 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1354
1355 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1356 {
1357         return addr >= apic->base_address &&
1358                 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1359 }
1360
1361 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1362                            gpa_t address, int len, void *data)
1363 {
1364         struct kvm_lapic *apic = to_lapic(this);
1365         u32 offset = address - apic->base_address;
1366
1367         if (!apic_mmio_in_range(apic, address))
1368                 return -EOPNOTSUPP;
1369
1370         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1371                 if (!kvm_check_has_quirk(vcpu->kvm,
1372                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1373                         return -EOPNOTSUPP;
1374
1375                 memset(data, 0xff, len);
1376                 return 0;
1377         }
1378
1379         kvm_lapic_reg_read(apic, offset, len, data);
1380
1381         return 0;
1382 }
1383
1384 static void update_divide_count(struct kvm_lapic *apic)
1385 {
1386         u32 tmp1, tmp2, tdcr;
1387
1388         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1389         tmp1 = tdcr & 0xf;
1390         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1391         apic->divide_count = 0x1 << (tmp2 & 0x7);
1392
1393         apic_debug("timer divide count is 0x%x\n",
1394                                    apic->divide_count);
1395 }
1396
1397 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1398 {
1399         /*
1400          * Do not allow the guest to program periodic timers with small
1401          * interval, since the hrtimers are not throttled by the host
1402          * scheduler.
1403          */
1404         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1405                 s64 min_period = min_timer_period_us * 1000LL;
1406
1407                 if (apic->lapic_timer.period < min_period) {
1408                         pr_info_ratelimited(
1409                             "kvm: vcpu %i: requested %lld ns "
1410                             "lapic timer period limited to %lld ns\n",
1411                             apic->vcpu->vcpu_id,
1412                             apic->lapic_timer.period, min_period);
1413                         apic->lapic_timer.period = min_period;
1414                 }
1415         }
1416 }
1417
1418 static void apic_update_lvtt(struct kvm_lapic *apic)
1419 {
1420         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1421                         apic->lapic_timer.timer_mode_mask;
1422
1423         if (apic->lapic_timer.timer_mode != timer_mode) {
1424                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1425                                 APIC_LVT_TIMER_TSCDEADLINE)) {
1426                         hrtimer_cancel(&apic->lapic_timer.timer);
1427                         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1428                         apic->lapic_timer.period = 0;
1429                         apic->lapic_timer.tscdeadline = 0;
1430                 }
1431                 apic->lapic_timer.timer_mode = timer_mode;
1432                 limit_periodic_timer_frequency(apic);
1433         }
1434 }
1435
1436 static void apic_timer_expired(struct kvm_lapic *apic)
1437 {
1438         struct kvm_vcpu *vcpu = apic->vcpu;
1439         struct swait_queue_head *q = &vcpu->wq;
1440         struct kvm_timer *ktimer = &apic->lapic_timer;
1441
1442         if (atomic_read(&apic->lapic_timer.pending))
1443                 return;
1444
1445         atomic_inc(&apic->lapic_timer.pending);
1446         kvm_set_pending_timer(vcpu);
1447
1448         /*
1449          * For x86, the atomic_inc() is serialized, thus
1450          * using swait_active() is safe.
1451          */
1452         if (swait_active(q))
1453                 swake_up_one(q);
1454
1455         if (apic_lvtt_tscdeadline(apic))
1456                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1457 }
1458
1459 /*
1460  * On APICv, this test will cause a busy wait
1461  * during a higher-priority task.
1462  */
1463
1464 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1465 {
1466         struct kvm_lapic *apic = vcpu->arch.apic;
1467         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1468
1469         if (kvm_apic_hw_enabled(apic)) {
1470                 int vec = reg & APIC_VECTOR_MASK;
1471                 void *bitmap = apic->regs + APIC_ISR;
1472
1473                 if (vcpu->arch.apicv_active)
1474                         bitmap = apic->regs + APIC_IRR;
1475
1476                 if (apic_test_vector(vec, bitmap))
1477                         return true;
1478         }
1479         return false;
1480 }
1481
1482 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1483 {
1484         struct kvm_lapic *apic = vcpu->arch.apic;
1485         u64 guest_tsc, tsc_deadline, ns;
1486
1487         if (!lapic_in_kernel(vcpu))
1488                 return;
1489
1490         if (apic->lapic_timer.expired_tscdeadline == 0)
1491                 return;
1492
1493         if (!lapic_timer_int_injected(vcpu))
1494                 return;
1495
1496         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1497         apic->lapic_timer.expired_tscdeadline = 0;
1498         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1499         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1500
1501         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1502         if (guest_tsc < tsc_deadline)
1503                 __delay(min(tsc_deadline - guest_tsc,
1504                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1505
1506         if (!lapic_timer_advance_adjust_done) {
1507                 /* too early */
1508                 if (guest_tsc < tsc_deadline) {
1509                         ns = (tsc_deadline - guest_tsc) * 1000000ULL;
1510                         do_div(ns, vcpu->arch.virtual_tsc_khz);
1511                         lapic_timer_advance_ns -= min((unsigned int)ns,
1512                                 lapic_timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1513                 } else {
1514                 /* too late */
1515                         ns = (guest_tsc - tsc_deadline) * 1000000ULL;
1516                         do_div(ns, vcpu->arch.virtual_tsc_khz);
1517                         lapic_timer_advance_ns += min((unsigned int)ns,
1518                                 lapic_timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1519                 }
1520                 if (abs(guest_tsc - tsc_deadline) < LAPIC_TIMER_ADVANCE_ADJUST_DONE)
1521                         lapic_timer_advance_adjust_done = true;
1522         }
1523 }
1524
1525 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1526 {
1527         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1528         u64 ns = 0;
1529         ktime_t expire;
1530         struct kvm_vcpu *vcpu = apic->vcpu;
1531         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1532         unsigned long flags;
1533         ktime_t now;
1534
1535         if (unlikely(!tscdeadline || !this_tsc_khz))
1536                 return;
1537
1538         local_irq_save(flags);
1539
1540         now = ktime_get();
1541         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1542         if (likely(tscdeadline > guest_tsc)) {
1543                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1544                 do_div(ns, this_tsc_khz);
1545                 expire = ktime_add_ns(now, ns);
1546                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1547                 hrtimer_start(&apic->lapic_timer.timer,
1548                                 expire, HRTIMER_MODE_ABS_PINNED);
1549         } else
1550                 apic_timer_expired(apic);
1551
1552         local_irq_restore(flags);
1553 }
1554
1555 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1556 {
1557         ktime_t now, remaining;
1558         u64 ns_remaining_old, ns_remaining_new;
1559
1560         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1561                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1562         limit_periodic_timer_frequency(apic);
1563
1564         now = ktime_get();
1565         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1566         if (ktime_to_ns(remaining) < 0)
1567                 remaining = 0;
1568
1569         ns_remaining_old = ktime_to_ns(remaining);
1570         ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1571                                            apic->divide_count, old_divisor);
1572
1573         apic->lapic_timer.tscdeadline +=
1574                 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1575                 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1576         apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1577 }
1578
1579 static bool set_target_expiration(struct kvm_lapic *apic)
1580 {
1581         ktime_t now;
1582         u64 tscl = rdtsc();
1583
1584         now = ktime_get();
1585         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1586                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1587
1588         if (!apic->lapic_timer.period) {
1589                 apic->lapic_timer.tscdeadline = 0;
1590                 return false;
1591         }
1592
1593         limit_periodic_timer_frequency(apic);
1594
1595         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1596                    PRIx64 ", "
1597                    "timer initial count 0x%x, period %lldns, "
1598                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1599                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1600                    kvm_lapic_get_reg(apic, APIC_TMICT),
1601                    apic->lapic_timer.period,
1602                    ktime_to_ns(ktime_add_ns(now,
1603                                 apic->lapic_timer.period)));
1604
1605         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1606                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1607         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1608
1609         return true;
1610 }
1611
1612 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1613 {
1614         ktime_t now = ktime_get();
1615         u64 tscl = rdtsc();
1616         ktime_t delta;
1617
1618         /*
1619          * Synchronize both deadlines to the same time source or
1620          * differences in the periods (caused by differences in the
1621          * underlying clocks or numerical approximation errors) will
1622          * cause the two to drift apart over time as the errors
1623          * accumulate.
1624          */
1625         apic->lapic_timer.target_expiration =
1626                 ktime_add_ns(apic->lapic_timer.target_expiration,
1627                                 apic->lapic_timer.period);
1628         delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1629         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1630                 nsec_to_cycles(apic->vcpu, delta);
1631 }
1632
1633 static void start_sw_period(struct kvm_lapic *apic)
1634 {
1635         if (!apic->lapic_timer.period)
1636                 return;
1637
1638         if (ktime_after(ktime_get(),
1639                         apic->lapic_timer.target_expiration)) {
1640                 apic_timer_expired(apic);
1641
1642                 if (apic_lvtt_oneshot(apic))
1643                         return;
1644
1645                 advance_periodic_target_expiration(apic);
1646         }
1647
1648         hrtimer_start(&apic->lapic_timer.timer,
1649                 apic->lapic_timer.target_expiration,
1650                 HRTIMER_MODE_ABS_PINNED);
1651 }
1652
1653 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1654 {
1655         if (!lapic_in_kernel(vcpu))
1656                 return false;
1657
1658         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1659 }
1660 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1661
1662 static void cancel_hv_timer(struct kvm_lapic *apic)
1663 {
1664         WARN_ON(preemptible());
1665         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1666         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1667         apic->lapic_timer.hv_timer_in_use = false;
1668 }
1669
1670 static bool start_hv_timer(struct kvm_lapic *apic)
1671 {
1672         struct kvm_timer *ktimer = &apic->lapic_timer;
1673         int r;
1674
1675         WARN_ON(preemptible());
1676         if (!kvm_x86_ops->set_hv_timer)
1677                 return false;
1678
1679         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1680                 return false;
1681
1682         if (!ktimer->tscdeadline)
1683                 return false;
1684
1685         r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1686         if (r < 0)
1687                 return false;
1688
1689         ktimer->hv_timer_in_use = true;
1690         hrtimer_cancel(&ktimer->timer);
1691
1692         /*
1693          * Also recheck ktimer->pending, in case the sw timer triggered in
1694          * the window.  For periodic timer, leave the hv timer running for
1695          * simplicity, and the deadline will be recomputed on the next vmexit.
1696          */
1697         if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1698                 if (r)
1699                         apic_timer_expired(apic);
1700                 return false;
1701         }
1702
1703         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1704         return true;
1705 }
1706
1707 static void start_sw_timer(struct kvm_lapic *apic)
1708 {
1709         struct kvm_timer *ktimer = &apic->lapic_timer;
1710
1711         WARN_ON(preemptible());
1712         if (apic->lapic_timer.hv_timer_in_use)
1713                 cancel_hv_timer(apic);
1714         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1715                 return;
1716
1717         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1718                 start_sw_period(apic);
1719         else if (apic_lvtt_tscdeadline(apic))
1720                 start_sw_tscdeadline(apic);
1721         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1722 }
1723
1724 static void restart_apic_timer(struct kvm_lapic *apic)
1725 {
1726         preempt_disable();
1727         if (!start_hv_timer(apic))
1728                 start_sw_timer(apic);
1729         preempt_enable();
1730 }
1731
1732 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1733 {
1734         struct kvm_lapic *apic = vcpu->arch.apic;
1735
1736         preempt_disable();
1737         /* If the preempt notifier has already run, it also called apic_timer_expired */
1738         if (!apic->lapic_timer.hv_timer_in_use)
1739                 goto out;
1740         WARN_ON(swait_active(&vcpu->wq));
1741         cancel_hv_timer(apic);
1742         apic_timer_expired(apic);
1743
1744         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1745                 advance_periodic_target_expiration(apic);
1746                 restart_apic_timer(apic);
1747         }
1748 out:
1749         preempt_enable();
1750 }
1751 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1752
1753 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1754 {
1755         restart_apic_timer(vcpu->arch.apic);
1756 }
1757 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1758
1759 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1760 {
1761         struct kvm_lapic *apic = vcpu->arch.apic;
1762
1763         preempt_disable();
1764         /* Possibly the TSC deadline timer is not enabled yet */
1765         if (apic->lapic_timer.hv_timer_in_use)
1766                 start_sw_timer(apic);
1767         preempt_enable();
1768 }
1769 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1770
1771 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1772 {
1773         struct kvm_lapic *apic = vcpu->arch.apic;
1774
1775         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1776         restart_apic_timer(apic);
1777 }
1778
1779 static void start_apic_timer(struct kvm_lapic *apic)
1780 {
1781         atomic_set(&apic->lapic_timer.pending, 0);
1782
1783         if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1784             && !set_target_expiration(apic))
1785                 return;
1786
1787         restart_apic_timer(apic);
1788 }
1789
1790 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1791 {
1792         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1793
1794         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1795                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1796                 if (lvt0_in_nmi_mode) {
1797                         apic_debug("Receive NMI setting on APIC_LVT0 "
1798                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1799                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1800                 } else
1801                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1802         }
1803 }
1804
1805 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1806 {
1807         int ret = 0;
1808
1809         trace_kvm_apic_write(reg, val);
1810
1811         switch (reg) {
1812         case APIC_ID:           /* Local APIC ID */
1813                 if (!apic_x2apic_mode(apic))
1814                         kvm_apic_set_xapic_id(apic, val >> 24);
1815                 else
1816                         ret = 1;
1817                 break;
1818
1819         case APIC_TASKPRI:
1820                 report_tpr_access(apic, true);
1821                 apic_set_tpr(apic, val & 0xff);
1822                 break;
1823
1824         case APIC_EOI:
1825                 apic_set_eoi(apic);
1826                 break;
1827
1828         case APIC_LDR:
1829                 if (!apic_x2apic_mode(apic))
1830                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1831                 else
1832                         ret = 1;
1833                 break;
1834
1835         case APIC_DFR:
1836                 if (!apic_x2apic_mode(apic)) {
1837                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1838                         recalculate_apic_map(apic->vcpu->kvm);
1839                 } else
1840                         ret = 1;
1841                 break;
1842
1843         case APIC_SPIV: {
1844                 u32 mask = 0x3ff;
1845                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1846                         mask |= APIC_SPIV_DIRECTED_EOI;
1847                 apic_set_spiv(apic, val & mask);
1848                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1849                         int i;
1850                         u32 lvt_val;
1851
1852                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1853                                 lvt_val = kvm_lapic_get_reg(apic,
1854                                                        APIC_LVTT + 0x10 * i);
1855                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1856                                              lvt_val | APIC_LVT_MASKED);
1857                         }
1858                         apic_update_lvtt(apic);
1859                         atomic_set(&apic->lapic_timer.pending, 0);
1860
1861                 }
1862                 break;
1863         }
1864         case APIC_ICR:
1865                 /* No delay here, so we always clear the pending bit */
1866                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1867                 apic_send_ipi(apic);
1868                 break;
1869
1870         case APIC_ICR2:
1871                 if (!apic_x2apic_mode(apic))
1872                         val &= 0xff000000;
1873                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1874                 break;
1875
1876         case APIC_LVT0:
1877                 apic_manage_nmi_watchdog(apic, val);
1878         case APIC_LVTTHMR:
1879         case APIC_LVTPC:
1880         case APIC_LVT1:
1881         case APIC_LVTERR:
1882                 /* TODO: Check vector */
1883                 if (!kvm_apic_sw_enabled(apic))
1884                         val |= APIC_LVT_MASKED;
1885
1886                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1887                 kvm_lapic_set_reg(apic, reg, val);
1888
1889                 break;
1890
1891         case APIC_LVTT:
1892                 if (!kvm_apic_sw_enabled(apic))
1893                         val |= APIC_LVT_MASKED;
1894                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1895                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1896                 apic_update_lvtt(apic);
1897                 break;
1898
1899         case APIC_TMICT:
1900                 if (apic_lvtt_tscdeadline(apic))
1901                         break;
1902
1903                 hrtimer_cancel(&apic->lapic_timer.timer);
1904                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1905                 start_apic_timer(apic);
1906                 break;
1907
1908         case APIC_TDCR: {
1909                 uint32_t old_divisor = apic->divide_count;
1910
1911                 if (val & 4)
1912                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1913                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1914                 update_divide_count(apic);
1915                 if (apic->divide_count != old_divisor &&
1916                                 apic->lapic_timer.period) {
1917                         hrtimer_cancel(&apic->lapic_timer.timer);
1918                         update_target_expiration(apic, old_divisor);
1919                         restart_apic_timer(apic);
1920                 }
1921                 break;
1922         }
1923         case APIC_ESR:
1924                 if (apic_x2apic_mode(apic) && val != 0) {
1925                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1926                         ret = 1;
1927                 }
1928                 break;
1929
1930         case APIC_SELF_IPI:
1931                 if (apic_x2apic_mode(apic)) {
1932                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1933                 } else
1934                         ret = 1;
1935                 break;
1936         default:
1937                 ret = 1;
1938                 break;
1939         }
1940         if (ret)
1941                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1942         return ret;
1943 }
1944 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1945
1946 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1947                             gpa_t address, int len, const void *data)
1948 {
1949         struct kvm_lapic *apic = to_lapic(this);
1950         unsigned int offset = address - apic->base_address;
1951         u32 val;
1952
1953         if (!apic_mmio_in_range(apic, address))
1954                 return -EOPNOTSUPP;
1955
1956         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1957                 if (!kvm_check_has_quirk(vcpu->kvm,
1958                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1959                         return -EOPNOTSUPP;
1960
1961                 return 0;
1962         }
1963
1964         /*
1965          * APIC register must be aligned on 128-bits boundary.
1966          * 32/64/128 bits registers must be accessed thru 32 bits.
1967          * Refer SDM 8.4.1
1968          */
1969         if (len != 4 || (offset & 0xf)) {
1970                 /* Don't shout loud, $infamous_os would cause only noise. */
1971                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1972                 return 0;
1973         }
1974
1975         val = *(u32*)data;
1976
1977         /* too common printing */
1978         if (offset != APIC_EOI)
1979                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1980                            "0x%x\n", __func__, offset, len, val);
1981
1982         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1983
1984         return 0;
1985 }
1986
1987 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1988 {
1989         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1990 }
1991 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1992
1993 /* emulate APIC access in a trap manner */
1994 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1995 {
1996         u32 val = 0;
1997
1998         /* hw has done the conditional check and inst decode */
1999         offset &= 0xff0;
2000
2001         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2002
2003         /* TODO: optimize to just emulate side effect w/o one more write */
2004         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2005 }
2006 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2007
2008 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2009 {
2010         struct kvm_lapic *apic = vcpu->arch.apic;
2011
2012         if (!vcpu->arch.apic)
2013                 return;
2014
2015         hrtimer_cancel(&apic->lapic_timer.timer);
2016
2017         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2018                 static_key_slow_dec_deferred(&apic_hw_disabled);
2019
2020         if (!apic->sw_enabled)
2021                 static_key_slow_dec_deferred(&apic_sw_disabled);
2022
2023         if (apic->regs)
2024                 free_page((unsigned long)apic->regs);
2025
2026         kfree(apic);
2027 }
2028
2029 /*
2030  *----------------------------------------------------------------------
2031  * LAPIC interface
2032  *----------------------------------------------------------------------
2033  */
2034 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2035 {
2036         struct kvm_lapic *apic = vcpu->arch.apic;
2037
2038         if (!lapic_in_kernel(vcpu) ||
2039                 !apic_lvtt_tscdeadline(apic))
2040                 return 0;
2041
2042         return apic->lapic_timer.tscdeadline;
2043 }
2044
2045 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2046 {
2047         struct kvm_lapic *apic = vcpu->arch.apic;
2048
2049         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2050                         apic_lvtt_period(apic))
2051                 return;
2052
2053         hrtimer_cancel(&apic->lapic_timer.timer);
2054         apic->lapic_timer.tscdeadline = data;
2055         start_apic_timer(apic);
2056 }
2057
2058 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2059 {
2060         struct kvm_lapic *apic = vcpu->arch.apic;
2061
2062         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2063                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2064 }
2065
2066 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2067 {
2068         u64 tpr;
2069
2070         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2071
2072         return (tpr & 0xf0) >> 4;
2073 }
2074
2075 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2076 {
2077         u64 old_value = vcpu->arch.apic_base;
2078         struct kvm_lapic *apic = vcpu->arch.apic;
2079
2080         if (!apic)
2081                 value |= MSR_IA32_APICBASE_BSP;
2082
2083         vcpu->arch.apic_base = value;
2084
2085         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2086                 kvm_update_cpuid(vcpu);
2087
2088         if (!apic)
2089                 return;
2090
2091         /* update jump label if enable bit changes */
2092         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2093                 if (value & MSR_IA32_APICBASE_ENABLE) {
2094                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2095                         static_key_slow_dec_deferred(&apic_hw_disabled);
2096                 } else {
2097                         static_key_slow_inc(&apic_hw_disabled.key);
2098                         recalculate_apic_map(vcpu->kvm);
2099                 }
2100         }
2101
2102         if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2103                 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2104
2105         if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2106                 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2107
2108         apic->base_address = apic->vcpu->arch.apic_base &
2109                              MSR_IA32_APICBASE_BASE;
2110
2111         if ((value & MSR_IA32_APICBASE_ENABLE) &&
2112              apic->base_address != APIC_DEFAULT_PHYS_BASE)
2113                 pr_warn_once("APIC base relocation is unsupported by KVM");
2114
2115         /* with FSB delivery interrupt, we can restart APIC functionality */
2116         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2117                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2118
2119 }
2120
2121 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2122 {
2123         struct kvm_lapic *apic = vcpu->arch.apic;
2124         int i;
2125
2126         if (!apic)
2127                 return;
2128
2129         apic_debug("%s\n", __func__);
2130
2131         /* Stop the timer in case it's a reset to an active apic */
2132         hrtimer_cancel(&apic->lapic_timer.timer);
2133
2134         if (!init_event) {
2135                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2136                                          MSR_IA32_APICBASE_ENABLE);
2137                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2138         }
2139         kvm_apic_set_version(apic->vcpu);
2140
2141         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2142                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2143         apic_update_lvtt(apic);
2144         if (kvm_vcpu_is_reset_bsp(vcpu) &&
2145             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2146                 kvm_lapic_set_reg(apic, APIC_LVT0,
2147                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2148         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2149
2150         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2151         apic_set_spiv(apic, 0xff);
2152         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2153         if (!apic_x2apic_mode(apic))
2154                 kvm_apic_set_ldr(apic, 0);
2155         kvm_lapic_set_reg(apic, APIC_ESR, 0);
2156         kvm_lapic_set_reg(apic, APIC_ICR, 0);
2157         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2158         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2159         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2160         for (i = 0; i < 8; i++) {
2161                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2162                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2163                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2164         }
2165         apic->irr_pending = vcpu->arch.apicv_active;
2166         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2167         apic->highest_isr_cache = -1;
2168         update_divide_count(apic);
2169         atomic_set(&apic->lapic_timer.pending, 0);
2170         if (kvm_vcpu_is_bsp(vcpu))
2171                 kvm_lapic_set_base(vcpu,
2172                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2173         vcpu->arch.pv_eoi.msr_val = 0;
2174         apic_update_ppr(apic);
2175         if (vcpu->arch.apicv_active) {
2176                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2177                 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2178                 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2179         }
2180
2181         vcpu->arch.apic_arb_prio = 0;
2182         vcpu->arch.apic_attention = 0;
2183
2184         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2185                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2186                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2187                    vcpu->arch.apic_base, apic->base_address);
2188 }
2189
2190 /*
2191  *----------------------------------------------------------------------
2192  * timer interface
2193  *----------------------------------------------------------------------
2194  */
2195
2196 static bool lapic_is_periodic(struct kvm_lapic *apic)
2197 {
2198         return apic_lvtt_period(apic);
2199 }
2200
2201 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2202 {
2203         struct kvm_lapic *apic = vcpu->arch.apic;
2204
2205         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2206                 return atomic_read(&apic->lapic_timer.pending);
2207
2208         return 0;
2209 }
2210
2211 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2212 {
2213         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2214         int vector, mode, trig_mode;
2215
2216         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2217                 vector = reg & APIC_VECTOR_MASK;
2218                 mode = reg & APIC_MODE_MASK;
2219                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2220                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2221                                         NULL);
2222         }
2223         return 0;
2224 }
2225
2226 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2227 {
2228         struct kvm_lapic *apic = vcpu->arch.apic;
2229
2230         if (apic)
2231                 kvm_apic_local_deliver(apic, APIC_LVT0);
2232 }
2233
2234 static const struct kvm_io_device_ops apic_mmio_ops = {
2235         .read     = apic_mmio_read,
2236         .write    = apic_mmio_write,
2237 };
2238
2239 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2240 {
2241         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2242         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2243
2244         apic_timer_expired(apic);
2245
2246         if (lapic_is_periodic(apic)) {
2247                 advance_periodic_target_expiration(apic);
2248                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2249                 return HRTIMER_RESTART;
2250         } else
2251                 return HRTIMER_NORESTART;
2252 }
2253
2254 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2255 {
2256         struct kvm_lapic *apic;
2257
2258         ASSERT(vcpu != NULL);
2259         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2260
2261         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2262         if (!apic)
2263                 goto nomem;
2264
2265         vcpu->arch.apic = apic;
2266
2267         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2268         if (!apic->regs) {
2269                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2270                        vcpu->vcpu_id);
2271                 goto nomem_free_apic;
2272         }
2273         apic->vcpu = vcpu;
2274
2275         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2276                      HRTIMER_MODE_ABS_PINNED);
2277         apic->lapic_timer.timer.function = apic_timer_fn;
2278
2279         /*
2280          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2281          * thinking that APIC satet has changed.
2282          */
2283         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2284         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2285         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2286
2287         return 0;
2288 nomem_free_apic:
2289         kfree(apic);
2290 nomem:
2291         return -ENOMEM;
2292 }
2293
2294 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2295 {
2296         struct kvm_lapic *apic = vcpu->arch.apic;
2297         u32 ppr;
2298
2299         if (!apic_enabled(apic))
2300                 return -1;
2301
2302         __apic_update_ppr(apic, &ppr);
2303         return apic_has_interrupt_for_ppr(apic, ppr);
2304 }
2305
2306 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2307 {
2308         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2309         int r = 0;
2310
2311         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2312                 r = 1;
2313         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2314             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2315                 r = 1;
2316         return r;
2317 }
2318
2319 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2320 {
2321         struct kvm_lapic *apic = vcpu->arch.apic;
2322
2323         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2324                 kvm_apic_local_deliver(apic, APIC_LVTT);
2325                 if (apic_lvtt_tscdeadline(apic))
2326                         apic->lapic_timer.tscdeadline = 0;
2327                 if (apic_lvtt_oneshot(apic)) {
2328                         apic->lapic_timer.tscdeadline = 0;
2329                         apic->lapic_timer.target_expiration = 0;
2330                 }
2331                 atomic_set(&apic->lapic_timer.pending, 0);
2332         }
2333 }
2334
2335 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2336 {
2337         int vector = kvm_apic_has_interrupt(vcpu);
2338         struct kvm_lapic *apic = vcpu->arch.apic;
2339         u32 ppr;
2340
2341         if (vector == -1)
2342                 return -1;
2343
2344         /*
2345          * We get here even with APIC virtualization enabled, if doing
2346          * nested virtualization and L1 runs with the "acknowledge interrupt
2347          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2348          * because the process would deliver it through the IDT.
2349          */
2350
2351         apic_clear_irr(vector, apic);
2352         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2353                 /*
2354                  * For auto-EOI interrupts, there might be another pending
2355                  * interrupt above PPR, so check whether to raise another
2356                  * KVM_REQ_EVENT.
2357                  */
2358                 apic_update_ppr(apic);
2359         } else {
2360                 /*
2361                  * For normal interrupts, PPR has been raised and there cannot
2362                  * be a higher-priority pending interrupt---except if there was
2363                  * a concurrent interrupt injection, but that would have
2364                  * triggered KVM_REQ_EVENT already.
2365                  */
2366                 apic_set_isr(vector, apic);
2367                 __apic_update_ppr(apic, &ppr);
2368         }
2369
2370         return vector;
2371 }
2372
2373 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2374                 struct kvm_lapic_state *s, bool set)
2375 {
2376         if (apic_x2apic_mode(vcpu->arch.apic)) {
2377                 u32 *id = (u32 *)(s->regs + APIC_ID);
2378                 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2379
2380                 if (vcpu->kvm->arch.x2apic_format) {
2381                         if (*id != vcpu->vcpu_id)
2382                                 return -EINVAL;
2383                 } else {
2384                         if (set)
2385                                 *id >>= 24;
2386                         else
2387                                 *id <<= 24;
2388                 }
2389
2390                 /* In x2APIC mode, the LDR is fixed and based on the id */
2391                 if (set)
2392                         *ldr = kvm_apic_calc_x2apic_ldr(*id);
2393         }
2394
2395         return 0;
2396 }
2397
2398 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2399 {
2400         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2401         return kvm_apic_state_fixup(vcpu, s, false);
2402 }
2403
2404 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2405 {
2406         struct kvm_lapic *apic = vcpu->arch.apic;
2407         int r;
2408
2409
2410         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2411         /* set SPIV separately to get count of SW disabled APICs right */
2412         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2413
2414         r = kvm_apic_state_fixup(vcpu, s, true);
2415         if (r)
2416                 return r;
2417         memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2418
2419         recalculate_apic_map(vcpu->kvm);
2420         kvm_apic_set_version(vcpu);
2421
2422         apic_update_ppr(apic);
2423         hrtimer_cancel(&apic->lapic_timer.timer);
2424         apic_update_lvtt(apic);
2425         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2426         update_divide_count(apic);
2427         start_apic_timer(apic);
2428         apic->irr_pending = true;
2429         apic->isr_count = vcpu->arch.apicv_active ?
2430                                 1 : count_vectors(apic->regs + APIC_ISR);
2431         apic->highest_isr_cache = -1;
2432         if (vcpu->arch.apicv_active) {
2433                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2434                 kvm_x86_ops->hwapic_irr_update(vcpu,
2435                                 apic_find_highest_irr(apic));
2436                 kvm_x86_ops->hwapic_isr_update(vcpu,
2437                                 apic_find_highest_isr(apic));
2438         }
2439         kvm_make_request(KVM_REQ_EVENT, vcpu);
2440         if (ioapic_in_kernel(vcpu->kvm))
2441                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2442
2443         vcpu->arch.apic_arb_prio = 0;
2444
2445         return 0;
2446 }
2447
2448 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2449 {
2450         struct hrtimer *timer;
2451
2452         if (!lapic_in_kernel(vcpu))
2453                 return;
2454
2455         timer = &vcpu->arch.apic->lapic_timer.timer;
2456         if (hrtimer_cancel(timer))
2457                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2458 }
2459
2460 /*
2461  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2462  *
2463  * Detect whether guest triggered PV EOI since the
2464  * last entry. If yes, set EOI on guests's behalf.
2465  * Clear PV EOI in guest memory in any case.
2466  */
2467 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2468                                         struct kvm_lapic *apic)
2469 {
2470         bool pending;
2471         int vector;
2472         /*
2473          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2474          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2475          *
2476          * KVM_APIC_PV_EOI_PENDING is unset:
2477          *      -> host disabled PV EOI.
2478          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2479          *      -> host enabled PV EOI, guest did not execute EOI yet.
2480          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2481          *      -> host enabled PV EOI, guest executed EOI.
2482          */
2483         BUG_ON(!pv_eoi_enabled(vcpu));
2484         pending = pv_eoi_get_pending(vcpu);
2485         /*
2486          * Clear pending bit in any case: it will be set again on vmentry.
2487          * While this might not be ideal from performance point of view,
2488          * this makes sure pv eoi is only enabled when we know it's safe.
2489          */
2490         pv_eoi_clr_pending(vcpu);
2491         if (pending)
2492                 return;
2493         vector = apic_set_eoi(apic);
2494         trace_kvm_pv_eoi(apic, vector);
2495 }
2496
2497 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2498 {
2499         u32 data;
2500
2501         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2502                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2503
2504         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2505                 return;
2506
2507         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2508                                   sizeof(u32)))
2509                 return;
2510
2511         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2512 }
2513
2514 /*
2515  * apic_sync_pv_eoi_to_guest - called before vmentry
2516  *
2517  * Detect whether it's safe to enable PV EOI and
2518  * if yes do so.
2519  */
2520 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2521                                         struct kvm_lapic *apic)
2522 {
2523         if (!pv_eoi_enabled(vcpu) ||
2524             /* IRR set or many bits in ISR: could be nested. */
2525             apic->irr_pending ||
2526             /* Cache not set: could be safe but we don't bother. */
2527             apic->highest_isr_cache == -1 ||
2528             /* Need EOI to update ioapic. */
2529             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2530                 /*
2531                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2532                  * so we need not do anything here.
2533                  */
2534                 return;
2535         }
2536
2537         pv_eoi_set_pending(apic->vcpu);
2538 }
2539
2540 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2541 {
2542         u32 data, tpr;
2543         int max_irr, max_isr;
2544         struct kvm_lapic *apic = vcpu->arch.apic;
2545
2546         apic_sync_pv_eoi_to_guest(vcpu, apic);
2547
2548         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2549                 return;
2550
2551         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2552         max_irr = apic_find_highest_irr(apic);
2553         if (max_irr < 0)
2554                 max_irr = 0;
2555         max_isr = apic_find_highest_isr(apic);
2556         if (max_isr < 0)
2557                 max_isr = 0;
2558         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2559
2560         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2561                                 sizeof(u32));
2562 }
2563
2564 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2565 {
2566         if (vapic_addr) {
2567                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2568                                         &vcpu->arch.apic->vapic_cache,
2569                                         vapic_addr, sizeof(u32)))
2570                         return -EINVAL;
2571                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2572         } else {
2573                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2574         }
2575
2576         vcpu->arch.apic->vapic_addr = vapic_addr;
2577         return 0;
2578 }
2579
2580 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2581 {
2582         struct kvm_lapic *apic = vcpu->arch.apic;
2583         u32 reg = (msr - APIC_BASE_MSR) << 4;
2584
2585         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2586                 return 1;
2587
2588         if (reg == APIC_ICR2)
2589                 return 1;
2590
2591         /* if this is ICR write vector before command */
2592         if (reg == APIC_ICR)
2593                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2594         return kvm_lapic_reg_write(apic, reg, (u32)data);
2595 }
2596
2597 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2598 {
2599         struct kvm_lapic *apic = vcpu->arch.apic;
2600         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2601
2602         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2603                 return 1;
2604
2605         if (reg == APIC_DFR || reg == APIC_ICR2) {
2606                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2607                            reg);
2608                 return 1;
2609         }
2610
2611         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2612                 return 1;
2613         if (reg == APIC_ICR)
2614                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2615
2616         *data = (((u64)high) << 32) | low;
2617
2618         return 0;
2619 }
2620
2621 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2622 {
2623         struct kvm_lapic *apic = vcpu->arch.apic;
2624
2625         if (!lapic_in_kernel(vcpu))
2626                 return 1;
2627
2628         /* if this is ICR write vector before command */
2629         if (reg == APIC_ICR)
2630                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2631         return kvm_lapic_reg_write(apic, reg, (u32)data);
2632 }
2633
2634 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2635 {
2636         struct kvm_lapic *apic = vcpu->arch.apic;
2637         u32 low, high = 0;
2638
2639         if (!lapic_in_kernel(vcpu))
2640                 return 1;
2641
2642         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2643                 return 1;
2644         if (reg == APIC_ICR)
2645                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2646
2647         *data = (((u64)high) << 32) | low;
2648
2649         return 0;
2650 }
2651
2652 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2653 {
2654         u64 addr = data & ~KVM_MSR_ENABLED;
2655         struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2656         unsigned long new_len;
2657
2658         if (!IS_ALIGNED(addr, 4))
2659                 return 1;
2660
2661         vcpu->arch.pv_eoi.msr_val = data;
2662         if (!pv_eoi_enabled(vcpu))
2663                 return 0;
2664
2665         if (addr == ghc->gpa && len <= ghc->len)
2666                 new_len = ghc->len;
2667         else
2668                 new_len = len;
2669
2670         return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2671 }
2672
2673 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2674 {
2675         struct kvm_lapic *apic = vcpu->arch.apic;
2676         u8 sipi_vector;
2677         unsigned long pe;
2678
2679         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2680                 return;
2681
2682         /*
2683          * INITs are latched while in SMM.  Because an SMM CPU cannot
2684          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2685          * and delay processing of INIT until the next RSM.
2686          */
2687         if (is_smm(vcpu)) {
2688                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2689                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2690                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2691                 return;
2692         }
2693
2694         pe = xchg(&apic->pending_events, 0);
2695         if (test_bit(KVM_APIC_INIT, &pe)) {
2696                 kvm_vcpu_reset(vcpu, true);
2697                 if (kvm_vcpu_is_bsp(apic->vcpu))
2698                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2699                 else
2700                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2701         }
2702         if (test_bit(KVM_APIC_SIPI, &pe) &&
2703             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2704                 /* evaluate pending_events before reading the vector */
2705                 smp_rmb();
2706                 sipi_vector = apic->sipi_vector;
2707                 apic_debug("vcpu %d received sipi with vector # %x\n",
2708                          vcpu->vcpu_id, sipi_vector);
2709                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2710                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2711         }
2712 }
2713
2714 void kvm_lapic_init(void)
2715 {
2716         /* do not patch jump label more than once per second */
2717         jump_label_rate_limit(&apic_hw_disabled, HZ);
2718         jump_label_rate_limit(&apic_sw_disabled, HZ);
2719 }
2720
2721 void kvm_lapic_exit(void)
2722 {
2723         static_key_deferred_flush(&apic_hw_disabled);
2724         static_key_deferred_flush(&apic_sw_disabled);
2725 }