drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_drv.h"
  26
  27 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  28
  29 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
  30 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
  31
  32 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
  33 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
  34
  35 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
  36 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
  37
  38 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
  39 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
  40
  41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  42
  43 static void
  44 assert_device_not_suspended(struct drm_i915_private *dev_priv)
  45 {
  46         WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
  47              "Device suspended\n");
  48 }
  49
  50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  51 {
  52         u32 gt_thread_status_mask;
  53
  54         if (IS_HASWELL(dev_priv->dev))
  55                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
  56         else
  57                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
  58
  59         /* w/a for a sporadic read returning 0 by waiting for the GT
  60          * thread to wake up.
  61          */
  62         if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
  63                 DRM_ERROR("GT thread status wait timed out\n");
  64 }
  65
  66 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
  67 {
  68         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
  69         /* something from same cacheline, but !FORCEWAKE */
  70         __raw_posting_read(dev_priv, ECOBUS);
  71 }
  72
  73 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
  74                                                         int fw_engine)
  75 {
  76         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
  77                             FORCEWAKE_ACK_TIMEOUT_MS))
  78                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  79
  80         __raw_i915_write32(dev_priv, FORCEWAKE, 1);
  81         /* something from same cacheline, but !FORCEWAKE */
  82         __raw_posting_read(dev_priv, ECOBUS);
  83
  84         if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
  85                             FORCEWAKE_ACK_TIMEOUT_MS))
  86                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  87
  88         /* WaRsForcewakeWaitTC0:snb */
  89         __gen6_gt_wait_for_thread_c0(dev_priv);
  90 }
  91
  92 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
  93 {
  94         __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
  95         /* something from same cacheline, but !FORCEWAKE_MT */
  96         __raw_posting_read(dev_priv, ECOBUS);
  97 }
  98
  99 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
 100                                                         int fw_engine)
 101 {
 102         u32 forcewake_ack;
 103
 104         if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
 105                 forcewake_ack = FORCEWAKE_ACK_HSW;
 106         else
 107                 forcewake_ack = FORCEWAKE_MT_ACK;
 108
 109         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
 110                             FORCEWAKE_ACK_TIMEOUT_MS))
 111                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 112
 113         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 114                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 115         /* something from same cacheline, but !FORCEWAKE_MT */
 116         __raw_posting_read(dev_priv, ECOBUS);
 117
 118         if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
 119                             FORCEWAKE_ACK_TIMEOUT_MS))
 120                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
 121
 122         /* WaRsForcewakeWaitTC0:ivb,hsw */
 123         if (INTEL_INFO(dev_priv->dev)->gen < 8)
 124                 __gen6_gt_wait_for_thread_c0(dev_priv);
 125 }
 126
 127 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 128 {
 129         u32 gtfifodbg;
 130
 131         gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
 132         if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
 133                 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
 134 }
 135
 136 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
 137                                                         int fw_engine)
 138 {
 139         __raw_i915_write32(dev_priv, FORCEWAKE, 0);
 140         /* something from same cacheline, but !FORCEWAKE */
 141         __raw_posting_read(dev_priv, ECOBUS);
 142         gen6_gt_check_fifodbg(dev_priv);
 143 }
 144
 145 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
 146                                                         int fw_engine)
 147 {
 148         __raw_i915_write32(dev_priv, FORCEWAKE_MT,
 149                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 150         /* something from same cacheline, but !FORCEWAKE_MT */
 151         __raw_posting_read(dev_priv, ECOBUS);
 152
 153         if (IS_GEN7(dev_priv->dev))
 154                 gen6_gt_check_fifodbg(dev_priv);
 155 }
 156
 157 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 158 {
 159         int ret = 0;
 160
 161         /* On VLV, FIFO will be shared by both SW and HW.
 162          * So, we need to read the FREE_ENTRIES everytime */
 163         if (IS_VALLEYVIEW(dev_priv->dev))
 164                 dev_priv->uncore.fifo_count =
 165                         __raw_i915_read32(dev_priv, GTFIFOCTL) &
 166                                                 GT_FIFO_FREE_ENTRIES_MASK;
 167
 168         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 169                 int loop = 500;
 170                 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 171                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 172                         udelay(10);
 173                         fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
 174                 }
 175                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 176                         ++ret;
 177                 dev_priv->uncore.fifo_count = fifo;
 178         }
 179         dev_priv->uncore.fifo_count--;
 180
 181         return ret;
 182 }
 183
 184 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
 185 {
 186         __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 187                            _MASKED_BIT_DISABLE(0xffff));
 188         /* something from same cacheline, but !FORCEWAKE_VLV */
 189         __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 190 }
 191
 192 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
 193                                                 int fw_engine)
 194 {
 195         /* Check for Render Engine */
 196         if (FORCEWAKE_RENDER & fw_engine) {
 197                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 198                                                 FORCEWAKE_ACK_VLV) &
 199                                                 FORCEWAKE_KERNEL) == 0,
 200                                         FORCEWAKE_ACK_TIMEOUT_MS))
 201                         DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
 202
 203                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 204                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 205
 206                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 207                                                 FORCEWAKE_ACK_VLV) &
 208                                                 FORCEWAKE_KERNEL),
 209                                         FORCEWAKE_ACK_TIMEOUT_MS))
 210                         DRM_ERROR("Timed out: waiting for Render to ack.\n");
 211         }
 212
 213         /* Check for Media Engine */
 214         if (FORCEWAKE_MEDIA & fw_engine) {
 215                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 216                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 217                                                 FORCEWAKE_KERNEL) == 0,
 218                                         FORCEWAKE_ACK_TIMEOUT_MS))
 219                         DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
 220
 221                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 222                                    _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 223
 224                 if (wait_for_atomic((__raw_i915_read32(dev_priv,
 225                                                 FORCEWAKE_ACK_MEDIA_VLV) &
 226                                                 FORCEWAKE_KERNEL),
 227                                         FORCEWAKE_ACK_TIMEOUT_MS))
 228                         DRM_ERROR("Timed out: waiting for media to ack.\n");
 229         }
 230
 231         /* WaRsForcewakeWaitTC0:vlv */
 232         __gen6_gt_wait_for_thread_c0(dev_priv);
 233
 234 }
 235
 236 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
 237                                         int fw_engine)
 238 {
 239
 240         /* Check for Render Engine */
 241         if (FORCEWAKE_RENDER & fw_engine)
 242                 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 243                                         _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 244
 245
 246         /* Check for Media Engine */
 247         if (FORCEWAKE_MEDIA & fw_engine)
 248                 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
 249                                 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 250
 251         /* The below doubles as a POSTING_READ */
 252         gen6_gt_check_fifodbg(dev_priv);
 253
 254 }
 255
 256 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 257 {
 258         unsigned long irqflags;
 259
 260         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 261
 262         if (fw_engine & FORCEWAKE_RENDER &&
 263             dev_priv->uncore.fw_rendercount++ != 0)
 264                 fw_engine &= ~FORCEWAKE_RENDER;
 265         if (fw_engine & FORCEWAKE_MEDIA &&
 266             dev_priv->uncore.fw_mediacount++ != 0)
 267                 fw_engine &= ~FORCEWAKE_MEDIA;
 268
 269         if (fw_engine)
 270                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
 271
 272         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 273 }
 274
 275 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 276 {
 277         unsigned long irqflags;
 278
 279         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 280
 281         if (fw_engine & FORCEWAKE_RENDER) {
 282                 WARN_ON(!dev_priv->uncore.fw_rendercount);
 283                 if (--dev_priv->uncore.fw_rendercount != 0)
 284                         fw_engine &= ~FORCEWAKE_RENDER;
 285         }
 286
 287         if (fw_engine & FORCEWAKE_MEDIA) {
 288                 WARN_ON(!dev_priv->uncore.fw_mediacount);
 289                 if (--dev_priv->uncore.fw_mediacount != 0)
 290                         fw_engine &= ~FORCEWAKE_MEDIA;
 291         }
 292
 293         if (fw_engine)
 294                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
 295
 296         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 297 }
 298
 299 static void gen6_force_wake_timer(unsigned long arg)
 300 {
 301         struct drm_i915_private *dev_priv = (void *)arg;
 302         unsigned long irqflags;
 303
 304         assert_device_not_suspended(dev_priv);
 305
 306         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 307         WARN_ON(!dev_priv->uncore.forcewake_count);
 308
 309         if (--dev_priv->uncore.forcewake_count == 0)
 310                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
 311         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 312
 313         intel_runtime_pm_put(dev_priv);
 314 }
 315
 316 static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319         unsigned long irqflags;
 320
 321         del_timer_sync(&dev_priv->uncore.force_wake_timer);
 322
 323         /* Hold uncore.lock across reset to prevent any register access
 324          * with forcewake not set correctly
 325          */
 326         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 327
 328         if (IS_VALLEYVIEW(dev))
 329                 vlv_force_wake_reset(dev_priv);
 330         else if (IS_GEN6(dev) || IS_GEN7(dev))
 331                 __gen6_gt_force_wake_reset(dev_priv);
 332
 333         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
 334                 __gen7_gt_force_wake_mt_reset(dev_priv);
 335
 336         if (restore) { /* If reset with a user forcewake, try to restore */
 337                 unsigned fw = 0;
 338
 339                 if (IS_VALLEYVIEW(dev)) {
 340                         if (dev_priv->uncore.fw_rendercount)
 341                                 fw |= FORCEWAKE_RENDER;
 342
 343                         if (dev_priv->uncore.fw_mediacount)
 344                                 fw |= FORCEWAKE_MEDIA;
 345                 } else {
 346                         if (dev_priv->uncore.forcewake_count)
 347                                 fw = FORCEWAKE_ALL;
 348                 }
 349
 350                 if (fw)
 351                         dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
 352
 353                 if (IS_GEN6(dev) || IS_GEN7(dev))
 354                         dev_priv->uncore.fifo_count =
 355                                 __raw_i915_read32(dev_priv, GTFIFOCTL) &
 356                                 GT_FIFO_FREE_ENTRIES_MASK;
 357         } else {
 358                 dev_priv->uncore.forcewake_count = 0;
 359                 dev_priv->uncore.fw_rendercount = 0;
 360                 dev_priv->uncore.fw_mediacount = 0;
 361         }
 362
 363         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 364 }
 365
 366 void intel_uncore_early_sanitize(struct drm_device *dev)
 367 {
 368         struct drm_i915_private *dev_priv = dev->dev_private;
 369
 370         if (HAS_FPGA_DBG_UNCLAIMED(dev))
 371                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 372
 373         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 374             (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 375                 /* The docs do not explain exactly how the calculation can be
 376                  * made. It is somewhat guessable, but for now, it's always
 377                  * 128MB.
 378                  * NB: We can't write IDICR yet because we do not have gt funcs
 379                  * set up */
 380                 dev_priv->ellc_size = 128;
 381                 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
 382         }
 383
 384         /* clear out old GT FIFO errors */
 385         if (IS_GEN6(dev) || IS_GEN7(dev))
 386                 __raw_i915_write32(dev_priv, GTFIFODBG,
 387                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 388
 389         intel_uncore_forcewake_reset(dev, false);
 390 }
 391
 392 void intel_uncore_sanitize(struct drm_device *dev)
 393 {
 394         /* BIOS often leaves RC6 enabled, but disable it for hw init */
 395         intel_disable_gt_powersave(dev);
 396 }
 397
 398 /*
 399  * Generally this is called implicitly by the register read function. However,
 400  * if some sequence requires the GT to not power down then this function should
 401  * be called at the beginning of the sequence followed by a call to
 402  * gen6_gt_force_wake_put() at the end of the sequence.
 403  */
 404 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
 405 {
 406         unsigned long irqflags;
 407
 408         if (!dev_priv->uncore.funcs.force_wake_get)
 409                 return;
 410
 411         intel_runtime_pm_get(dev_priv);
 412
 413         /* Redirect to VLV specific routine */
 414         if (IS_VALLEYVIEW(dev_priv->dev))
 415                 return vlv_force_wake_get(dev_priv, fw_engine);
 416
 417         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 418         if (dev_priv->uncore.forcewake_count++ == 0)
 419                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
 420         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 421 }
 422
 423 /*
 424  * see gen6_gt_force_wake_get()
 425  */
 426 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
 427 {
 428         unsigned long irqflags;
 429         bool delayed = false;
 430
 431         if (!dev_priv->uncore.funcs.force_wake_put)
 432                 return;
 433
 434         /* Redirect to VLV specific routine */
 435         if (IS_VALLEYVIEW(dev_priv->dev)) {
 436                 vlv_force_wake_put(dev_priv, fw_engine);
 437                 goto out;
 438         }
 439
 440
 441         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 442         WARN_ON(!dev_priv->uncore.forcewake_count);
 443
 444         if (--dev_priv->uncore.forcewake_count == 0) {
 445                 dev_priv->uncore.forcewake_count++;
 446                 delayed = true;
 447                 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
 448                                  jiffies + 1);
 449         }
 450         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 451
 452 out:
 453         if (!delayed)
 454                 intel_runtime_pm_put(dev_priv);
 455 }
 456
 457 void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 458 {
 459         if (!dev_priv->uncore.funcs.force_wake_get)
 460                 return;
 461
 462         WARN_ON(dev_priv->uncore.forcewake_count > 0);
 463 }
 464
 465 /* We give fast paths for the really cool registers */
 466 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 467          ((reg) < 0x40000 && (reg) != FORCEWAKE)
 468
 469 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
 470         (((reg) >= 0x2000 && (reg) < 0x4000) ||\
 471         ((reg) >= 0x5000 && (reg) < 0x8000) ||\
 472         ((reg) >= 0xB000 && (reg) < 0x12000) ||\
 473         ((reg) >= 0x2E000 && (reg) < 0x30000))
 474
 475 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
 476         (((reg) >= 0x12000 && (reg) < 0x14000) ||\
 477         ((reg) >= 0x22000 && (reg) < 0x24000) ||\
 478         ((reg) >= 0x30000 && (reg) < 0x40000))
 479
 480 static void
 481 ilk_dummy_write(struct drm_i915_private *dev_priv)
 482 {
 483         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
 484          * the chip from rc6 before touching it for real. MI_MODE is masked,
 485          * hence harmless to write 0 into. */
 486         __raw_i915_write32(dev_priv, MI_MODE, 0);
 487 }
 488
 489 static void
 490 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
 491 {
 492         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 493                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
 494                           reg);
 495                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 496         }
 497 }
 498
 499 static void
 500 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
 501 {
 502         if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
 503                 DRM_ERROR("Unclaimed write to %x\n", reg);
 504                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 505         }
 506 }
 507
 508 #define REG_READ_HEADER(x) \
 509         unsigned long irqflags; \
 510         u##x val = 0; \
 511         assert_device_not_suspended(dev_priv); \
 512         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 513
 514 #define REG_READ_FOOTER \
 515         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
 516         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
 517         return val
 518
 519 #define __gen4_read(x) \
 520 static u##x \
 521 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 522         REG_READ_HEADER(x); \
 523         val = __raw_i915_read##x(dev_priv, reg); \
 524         REG_READ_FOOTER; \
 525 }
 526
 527 #define __gen5_read(x) \
 528 static u##x \
 529 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 530         REG_READ_HEADER(x); \
 531         ilk_dummy_write(dev_priv); \
 532         val = __raw_i915_read##x(dev_priv, reg); \
 533         REG_READ_FOOTER; \
 534 }
 535
 536 #define __gen6_read(x) \
 537 static u##x \
 538 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 539         REG_READ_HEADER(x); \
 540         if (dev_priv->uncore.forcewake_count == 0 && \
 541             NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 542                 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 543                                                       FORCEWAKE_ALL); \
 544                 val = __raw_i915_read##x(dev_priv, reg); \
 545                 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
 546                                                       FORCEWAKE_ALL); \
 547         } else { \
 548                 val = __raw_i915_read##x(dev_priv, reg); \
 549         } \
 550         REG_READ_FOOTER; \
 551 }
 552
 553 #define __vlv_read(x) \
 554 static u##x \
 555 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 556         unsigned fwengine = 0; \
 557         REG_READ_HEADER(x); \
 558         if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
 559                 if (dev_priv->uncore.fw_rendercount == 0) \
 560                         fwengine = FORCEWAKE_RENDER; \
 561         } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
 562                 if (dev_priv->uncore.fw_mediacount == 0) \
 563                         fwengine = FORCEWAKE_MEDIA; \
 564         }  \
 565         if (fwengine) \
 566                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
 567         val = __raw_i915_read##x(dev_priv, reg); \
 568         if (fwengine) \
 569                 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
 570         REG_READ_FOOTER; \
 571 }
 572
 573
 574 __vlv_read(8)
 575 __vlv_read(16)
 576 __vlv_read(32)
 577 __vlv_read(64)
 578 __gen6_read(8)
 579 __gen6_read(16)
 580 __gen6_read(32)
 581 __gen6_read(64)
 582 __gen5_read(8)
 583 __gen5_read(16)
 584 __gen5_read(32)
 585 __gen5_read(64)
 586 __gen4_read(8)
 587 __gen4_read(16)
 588 __gen4_read(32)
 589 __gen4_read(64)
 590
 591 #undef __vlv_read
 592 #undef __gen6_read
 593 #undef __gen5_read
 594 #undef __gen4_read
 595 #undef REG_READ_FOOTER
 596 #undef REG_READ_HEADER
 597
 598 #define REG_WRITE_HEADER \
 599         unsigned long irqflags; \
 600         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
 601         assert_device_not_suspended(dev_priv); \
 602         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
 603
 604 #define REG_WRITE_FOOTER \
 605         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
 606
 607 #define __gen4_write(x) \
 608 static void \
 609 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 610         REG_WRITE_HEADER; \
 611         __raw_i915_write##x(dev_priv, reg, val); \
 612         REG_WRITE_FOOTER; \
 613 }
 614
 615 #define __gen5_write(x) \
 616 static void \
 617 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 618         REG_WRITE_HEADER; \
 619         ilk_dummy_write(dev_priv); \
 620         __raw_i915_write##x(dev_priv, reg, val); \
 621         REG_WRITE_FOOTER; \
 622 }
 623
 624 #define __gen6_write(x) \
 625 static void \
 626 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 627         u32 __fifo_ret = 0; \
 628         REG_WRITE_HEADER; \
 629         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 630                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 631         } \
 632         __raw_i915_write##x(dev_priv, reg, val); \
 633         if (unlikely(__fifo_ret)) { \
 634                 gen6_gt_check_fifodbg(dev_priv); \
 635         } \
 636         REG_WRITE_FOOTER; \
 637 }
 638
 639 #define __hsw_write(x) \
 640 static void \
 641 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 642         u32 __fifo_ret = 0; \
 643         REG_WRITE_HEADER; \
 644         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 645                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 646         } \
 647         hsw_unclaimed_reg_clear(dev_priv, reg); \
 648         __raw_i915_write##x(dev_priv, reg, val); \
 649         if (unlikely(__fifo_ret)) { \
 650                 gen6_gt_check_fifodbg(dev_priv); \
 651         } \
 652         hsw_unclaimed_reg_check(dev_priv, reg); \
 653         REG_WRITE_FOOTER; \
 654 }
 655
 656 static const u32 gen8_shadowed_regs[] = {
 657         FORCEWAKE_MT,
 658         GEN6_RPNSWREQ,
 659         GEN6_RC_VIDEO_FREQ,
 660         RING_TAIL(RENDER_RING_BASE),
 661         RING_TAIL(GEN6_BSD_RING_BASE),
 662         RING_TAIL(VEBOX_RING_BASE),
 663         RING_TAIL(BLT_RING_BASE),
 664         /* TODO: Other registers are not yet used */
 665 };
 666
 667 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
 668 {
 669         int i;
 670         for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
 671                 if (reg == gen8_shadowed_regs[i])
 672                         return true;
 673
 674         return false;
 675 }
 676
 677 #define __gen8_write(x) \
 678 static void \
 679 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
 680         REG_WRITE_HEADER; \
 681         if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
 682                 if (dev_priv->uncore.forcewake_count == 0) \
 683                         dev_priv->uncore.funcs.force_wake_get(dev_priv, \
 684                                                               FORCEWAKE_ALL); \
 685                 __raw_i915_write##x(dev_priv, reg, val); \
 686                 if (dev_priv->uncore.forcewake_count == 0) \
 687                         dev_priv->uncore.funcs.force_wake_put(dev_priv, \
 688                                                               FORCEWAKE_ALL); \
 689         } else { \
 690                 __raw_i915_write##x(dev_priv, reg, val); \
 691         } \
 692         REG_WRITE_FOOTER; \
 693 }
 694
 695 __gen8_write(8)
 696 __gen8_write(16)
 697 __gen8_write(32)
 698 __gen8_write(64)
 699 __hsw_write(8)
 700 __hsw_write(16)
 701 __hsw_write(32)
 702 __hsw_write(64)
 703 __gen6_write(8)
 704 __gen6_write(16)
 705 __gen6_write(32)
 706 __gen6_write(64)
 707 __gen5_write(8)
 708 __gen5_write(16)
 709 __gen5_write(32)
 710 __gen5_write(64)
 711 __gen4_write(8)
 712 __gen4_write(16)
 713 __gen4_write(32)
 714 __gen4_write(64)
 715
 716 #undef __gen8_write
 717 #undef __hsw_write
 718 #undef __gen6_write
 719 #undef __gen5_write
 720 #undef __gen4_write
 721 #undef REG_WRITE_FOOTER
 722 #undef REG_WRITE_HEADER
 723
 724 void intel_uncore_init(struct drm_device *dev)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727
 728         setup_timer(&dev_priv->uncore.force_wake_timer,
 729                     gen6_force_wake_timer, (unsigned long)dev_priv);
 730
 731         intel_uncore_early_sanitize(dev);
 732
 733         if (IS_VALLEYVIEW(dev)) {
 734                 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
 735                 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
 736         } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
 737                 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
 738                 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
 739         } else if (IS_IVYBRIDGE(dev)) {
 740                 u32 ecobus;
 741
 742                 /* IVB configs may use multi-threaded forcewake */
 743
 744                 /* A small trick here - if the bios hasn't configured
 745                  * MT forcewake, and if the device is in RC6, then
 746                  * force_wake_mt_get will not wake the device and the
 747                  * ECOBUS read will return zero. Which will be
 748                  * (correctly) interpreted by the test below as MT
 749                  * forcewake being disabled.
 750                  */
 751                 mutex_lock(&dev->struct_mutex);
 752                 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
 753                 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
 754                 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
 755                 mutex_unlock(&dev->struct_mutex);
 756
 757                 if (ecobus & FORCEWAKE_MT_ENABLE) {
 758                         dev_priv->uncore.funcs.force_wake_get =
 759                                 __gen7_gt_force_wake_mt_get;
 760                         dev_priv->uncore.funcs.force_wake_put =
 761                                 __gen7_gt_force_wake_mt_put;
 762                 } else {
 763                         DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
 764                         DRM_INFO("when using vblank-synced partial screen updates.\n");
 765                         dev_priv->uncore.funcs.force_wake_get =
 766                                 __gen6_gt_force_wake_get;
 767                         dev_priv->uncore.funcs.force_wake_put =
 768                                 __gen6_gt_force_wake_put;
 769                 }
 770         } else if (IS_GEN6(dev)) {
 771                 dev_priv->uncore.funcs.force_wake_get =
 772                         __gen6_gt_force_wake_get;
 773                 dev_priv->uncore.funcs.force_wake_put =
 774                         __gen6_gt_force_wake_put;
 775         }
 776
 777         switch (INTEL_INFO(dev)->gen) {
 778         default:
 779                 dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
 780                 dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
 781                 dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
 782                 dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
 783                 dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
 784                 dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
 785                 dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
 786                 dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
 787                 break;
 788         case 7:
 789         case 6:
 790                 if (IS_HASWELL(dev)) {
 791                         dev_priv->uncore.funcs.mmio_writeb  = hsw_write8;
 792                         dev_priv->uncore.funcs.mmio_writew  = hsw_write16;
 793                         dev_priv->uncore.funcs.mmio_writel  = hsw_write32;
 794                         dev_priv->uncore.funcs.mmio_writeq  = hsw_write64;
 795                 } else {
 796                         dev_priv->uncore.funcs.mmio_writeb  = gen6_write8;
 797                         dev_priv->uncore.funcs.mmio_writew  = gen6_write16;
 798                         dev_priv->uncore.funcs.mmio_writel  = gen6_write32;
 799                         dev_priv->uncore.funcs.mmio_writeq  = gen6_write64;
 800                 }
 801
 802                 if (IS_VALLEYVIEW(dev)) {
 803                         dev_priv->uncore.funcs.mmio_readb  = vlv_read8;
 804                         dev_priv->uncore.funcs.mmio_readw  = vlv_read16;
 805                         dev_priv->uncore.funcs.mmio_readl  = vlv_read32;
 806                         dev_priv->uncore.funcs.mmio_readq  = vlv_read64;
 807                 } else {
 808                         dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
 809                         dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
 810                         dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
 811                         dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
 812                 }
 813                 break;
 814         case 5:
 815                 dev_priv->uncore.funcs.mmio_writeb  = gen5_write8;
 816                 dev_priv->uncore.funcs.mmio_writew  = gen5_write16;
 817                 dev_priv->uncore.funcs.mmio_writel  = gen5_write32;
 818                 dev_priv->uncore.funcs.mmio_writeq  = gen5_write64;
 819                 dev_priv->uncore.funcs.mmio_readb  = gen5_read8;
 820                 dev_priv->uncore.funcs.mmio_readw  = gen5_read16;
 821                 dev_priv->uncore.funcs.mmio_readl  = gen5_read32;
 822                 dev_priv->uncore.funcs.mmio_readq  = gen5_read64;
 823                 break;
 824         case 4:
 825         case 3:
 826         case 2:
 827                 dev_priv->uncore.funcs.mmio_writeb  = gen4_write8;
 828                 dev_priv->uncore.funcs.mmio_writew  = gen4_write16;
 829                 dev_priv->uncore.funcs.mmio_writel  = gen4_write32;
 830                 dev_priv->uncore.funcs.mmio_writeq  = gen4_write64;
 831                 dev_priv->uncore.funcs.mmio_readb  = gen4_read8;
 832                 dev_priv->uncore.funcs.mmio_readw  = gen4_read16;
 833                 dev_priv->uncore.funcs.mmio_readl  = gen4_read32;
 834                 dev_priv->uncore.funcs.mmio_readq  = gen4_read64;
 835                 break;
 836         }
 837 }
 838
 839 void intel_uncore_fini(struct drm_device *dev)
 840 {
 841         /* Paranoia: make sure we have disabled everything before we exit. */
 842         intel_uncore_sanitize(dev);
 843         intel_uncore_forcewake_reset(dev, false);
 844 }
 845
 846 #define GEN_RANGE(l, h) GENMASK(h, l)
 847
 848 static const struct register_whitelist {
 849         uint64_t offset;
 850         uint32_t size;
 851         /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
 852         uint32_t gen_bitmask;
 853 } whitelist[] = {
 854         { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
 855 };
 856
 857 int i915_reg_read_ioctl(struct drm_device *dev,
 858                         void *data, struct drm_file *file)
 859 {
 860         struct drm_i915_private *dev_priv = dev->dev_private;
 861         struct drm_i915_reg_read *reg = data;
 862         struct register_whitelist const *entry = whitelist;
 863         int i, ret = 0;
 864
 865         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
 866                 if (entry->offset == reg->offset &&
 867                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
 868                         break;
 869         }
 870
 871         if (i == ARRAY_SIZE(whitelist))
 872                 return -EINVAL;
 873
 874         intel_runtime_pm_get(dev_priv);
 875
 876         switch (entry->size) {
 877         case 8:
 878                 reg->val = I915_READ64(reg->offset);
 879                 break;
 880         case 4:
 881                 reg->val = I915_READ(reg->offset);
 882                 break;
 883         case 2:
 884                 reg->val = I915_READ16(reg->offset);
 885                 break;
 886         case 1:
 887                 reg->val = I915_READ8(reg->offset);
 888                 break;
 889         default:
 890                 WARN_ON(1);
 891                 ret = -EINVAL;
 892                 goto out;
 893         }
 894
 895 out:
 896         intel_runtime_pm_put(dev_priv);
 897         return ret;
 898 }
 899
 900 int i915_get_reset_stats_ioctl(struct drm_device *dev,
 901                                void *data, struct drm_file *file)
 902 {
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904         struct drm_i915_reset_stats *args = data;
 905         struct i915_ctx_hang_stats *hs;
 906         struct intel_context *ctx;
 907         int ret;
 908
 909         if (args->flags || args->pad)
 910                 return -EINVAL;
 911
 912         if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
 913                 return -EPERM;
 914
 915         ret = mutex_lock_interruptible(&dev->struct_mutex);
 916         if (ret)
 917                 return ret;
 918
 919         ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
 920         if (IS_ERR(ctx)) {
 921                 mutex_unlock(&dev->struct_mutex);
 922                 return PTR_ERR(ctx);
 923         }
 924         hs = &ctx->hang_stats;
 925
 926         if (capable(CAP_SYS_ADMIN))
 927                 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
 928         else
 929                 args->reset_count = 0;
 930
 931         args->batch_active = hs->batch_active;
 932         args->batch_pending = hs->batch_pending;
 933
 934         mutex_unlock(&dev->struct_mutex);
 935
 936         return 0;
 937 }
 938
 939 static int i965_reset_complete(struct drm_device *dev)
 940 {
 941         u8 gdrst;
 942         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 943         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 944 }
 945
 946 static int i965_do_reset(struct drm_device *dev)
 947 {
 948         int ret;
 949
 950         /* FIXME: i965g/gm need a display save/restore for gpu reset. */
 951         return -ENODEV;
 952
 953         /*
 954          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 955          * well as the reset bit (GR/bit 0).  Setting the GR bit
 956          * triggers the reset; when done, the hardware will clear it.
 957          */
 958         pci_write_config_byte(dev->pdev, I965_GDRST,
 959                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 960         ret =  wait_for(i965_reset_complete(dev), 500);
 961         if (ret)
 962                 return ret;
 963
 964         pci_write_config_byte(dev->pdev, I965_GDRST,
 965                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 966
 967         ret =  wait_for(i965_reset_complete(dev), 500);
 968         if (ret)
 969                 return ret;
 970
 971         pci_write_config_byte(dev->pdev, I965_GDRST, 0);
 972
 973         return 0;
 974 }
 975
 976 static int g4x_do_reset(struct drm_device *dev)
 977 {
 978         struct drm_i915_private *dev_priv = dev->dev_private;
 979         int ret;
 980
 981         pci_write_config_byte(dev->pdev, I965_GDRST,
 982                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 983         ret =  wait_for(i965_reset_complete(dev), 500);
 984         if (ret)
 985                 return ret;
 986
 987         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 988         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
 989         POSTING_READ(VDECCLK_GATE_D);
 990
 991         pci_write_config_byte(dev->pdev, I965_GDRST,
 992                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 993         ret =  wait_for(i965_reset_complete(dev), 500);
 994         if (ret)
 995                 return ret;
 996
 997         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 998         I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
 999         POSTING_READ(VDECCLK_GATE_D);
1000
1001         pci_write_config_byte(dev->pdev, I965_GDRST, 0);
1002
1003         return 0;
1004 }
1005
1006 static int ironlake_do_reset(struct drm_device *dev)
1007 {
1008         struct drm_i915_private *dev_priv = dev->dev_private;
1009         int ret;
1010
1011         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1012                    ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1013         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1014                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1015         if (ret)
1016                 return ret;
1017
1018         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1019                    ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1020         ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1021                         ILK_GRDOM_RESET_ENABLE) == 0, 500);
1022         if (ret)
1023                 return ret;
1024
1025         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1026
1027         return 0;
1028 }
1029
1030 static int gen6_do_reset(struct drm_device *dev)
1031 {
1032         struct drm_i915_private *dev_priv = dev->dev_private;
1033         int     ret;
1034
1035         /* Reset the chip */
1036
1037         /* GEN6_GDRST is not in the gt power well, no need to check
1038          * for fifo space for the write or forcewake the chip for
1039          * the read
1040          */
1041         __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1042
1043         /* Spin waiting for the device to ack the reset request */
1044         ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1045
1046         intel_uncore_forcewake_reset(dev, true);
1047
1048         return ret;
1049 }
1050
1051 int intel_gpu_reset(struct drm_device *dev)
1052 {
1053         switch (INTEL_INFO(dev)->gen) {
1054         case 8:
1055         case 7:
1056         case 6: return gen6_do_reset(dev);
1057         case 5: return ironlake_do_reset(dev);
1058         case 4:
1059                 if (IS_G4X(dev))
1060                         return g4x_do_reset(dev);
1061                 else
1062                         return i965_do_reset(dev);
1063         default: return -ENODEV;
1064         }
1065 }
1066
1067 void intel_uncore_check_errors(struct drm_device *dev)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070
1071         if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1072             (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1073                 DRM_ERROR("Unclaimed register before interrupt\n");
1074                 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1075         }
1076 }