drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28
  29 #include "dcn201/dcn201_init.h"
  30 #include "dml/dcn20/dcn20_fpu.h"
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dcn201_resource.h"
  34
  35 #include "dcn20/dcn20_resource.h"
  36
  37 #include "dcn10/dcn10_hubp.h"
  38 #include "dcn10/dcn10_ipp.h"
  39 #include "dcn201/dcn201_mpc.h"
  40 #include "dcn201/dcn201_hubp.h"
  41 #include "irq/dcn201/irq_service_dcn201.h"
  42 #include "dcn201/dcn201_dpp.h"
  43 #include "dcn201/dcn201_hubbub.h"
  44 #include "dcn201/dcn201_dccg.h"
  45 #include "dcn201/dcn201_optc.h"
  46 #include "dcn201/dcn201_hwseq.h"
  47 #include "dce110/dce110_hwseq.h"
  48 #include "dcn201/dcn201_opp.h"
  49 #include "dcn201/dcn201_link_encoder.h"
  50 #include "dcn20/dcn20_stream_encoder.h"
  51 #include "dce/dce_clock_source.h"
  52 #include "dce/dce_audio.h"
  53 #include "dce/dce_hwseq.h"
  54 #include "virtual/virtual_stream_encoder.h"
  55 #include "dce110/dce110_resource.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_i2c.h"
  58 #include "dcn10/dcn10_resource.h"
  59
  60 #include "cyan_skillfish_ip_offset.h"
  61
  62 #include "dcn/dcn_2_0_3_offset.h"
  63 #include "dcn/dcn_2_0_3_sh_mask.h"
  64 #include "dpcs/dpcs_2_0_3_offset.h"
  65 #include "dpcs/dpcs_2_0_3_sh_mask.h"
  66
  67 #include "mmhub/mmhub_2_0_0_offset.h"
  68 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  69 #include "nbio/nbio_7_4_offset.h"
  70
  71 #include "reg_helper.h"
  72
  73 #define MIN_DISP_CLK_KHZ 100000
  74 #define MIN_DPP_CLK_KHZ 100000
  75
  76 static struct _vcs_dpi_ip_params_st dcn201_ip = {
  77         .gpuvm_enable = 0,
  78         .hostvm_enable = 0,
  79         .gpuvm_max_page_table_levels = 4,
  80         .hostvm_max_page_table_levels = 4,
  81         .hostvm_cached_page_table_levels = 0,
  82         .pte_group_size_bytes = 2048,
  83         .rob_buffer_size_kbytes = 168,
  84         .det_buffer_size_kbytes = 164,
  85         .dpte_buffer_size_in_pte_reqs_luma = 84,
  86         .pde_proc_buffer_size_64k_reqs = 48,
  87         .dpp_output_buffer_pixels = 2560,
  88         .opp_output_buffer_lines = 1,
  89         .pixel_chunk_size_kbytes = 8,
  90         .pte_chunk_size_kbytes = 2,
  91         .meta_chunk_size_kbytes = 2,
  92         .writeback_chunk_size_kbytes = 2,
  93         .line_buffer_size_bits = 789504,
  94         .is_line_buffer_bpp_fixed = 0,
  95         .line_buffer_fixed_bpp = 0,
  96         .dcc_supported = true,
  97         .max_line_buffer_lines = 12,
  98         .writeback_luma_buffer_size_kbytes = 12,
  99         .writeback_chroma_buffer_size_kbytes = 8,
 100         .writeback_chroma_line_buffer_width_pixels = 4,
 101         .writeback_max_hscl_ratio = 1,
 102         .writeback_max_vscl_ratio = 1,
 103         .writeback_min_hscl_ratio = 1,
 104         .writeback_min_vscl_ratio = 1,
 105         .writeback_max_hscl_taps = 12,
 106         .writeback_max_vscl_taps = 12,
 107         .writeback_line_buffer_luma_buffer_size = 0,
 108         .writeback_line_buffer_chroma_buffer_size = 9600,
 109         .cursor_buffer_size = 8,
 110         .cursor_chunk_size = 2,
 111         .max_num_otg = 2,
 112         .max_num_dpp = 4,
 113         .max_num_wb = 0,
 114         .max_dchub_pscl_bw_pix_per_clk = 4,
 115         .max_pscl_lb_bw_pix_per_clk = 2,
 116         .max_lb_vscl_bw_pix_per_clk = 4,
 117         .max_vscl_hscl_bw_pix_per_clk = 4,
 118         .max_hscl_ratio = 8,
 119         .max_vscl_ratio = 8,
 120         .hscl_mults = 4,
 121         .vscl_mults = 4,
 122         .max_hscl_taps = 8,
 123         .max_vscl_taps = 8,
 124         .dispclk_ramp_margin_percent = 1,
 125         .underscan_factor = 1.10,
 126         .min_vblank_lines = 30,
 127         .dppclk_delay_subtotal = 77,
 128         .dppclk_delay_scl_lb_only = 16,
 129         .dppclk_delay_scl = 50,
 130         .dppclk_delay_cnvc_formatter = 8,
 131         .dppclk_delay_cnvc_cursor = 6,
 132         .dispclk_delay_subtotal = 87,
 133         .dcfclk_cstate_latency = 10,
 134         .max_inter_dcn_tile_repeaters = 8,
 135         .number_of_cursors = 1,
 136 };
 137
 138 static struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {
 139         .clock_limits = {
 140                         {
 141                                 .state = 0,
 142                                 .dscclk_mhz = 400.0,
 143                                 .dcfclk_mhz = 1000.0,
 144                                 .fabricclk_mhz = 200.0,
 145                                 .dispclk_mhz = 300.0,
 146                                 .dppclk_mhz = 300.0,
 147                                 .phyclk_mhz = 810.0,
 148                                 .socclk_mhz = 1254.0,
 149                                 .dram_speed_mts = 2000.0,
 150                         },
 151                         {
 152                                 .state = 1,
 153                                 .dscclk_mhz = 400.0,
 154                                 .dcfclk_mhz = 1000.0,
 155                                 .fabricclk_mhz = 250.0,
 156                                 .dispclk_mhz = 1200.0,
 157                                 .dppclk_mhz = 1200.0,
 158                                 .phyclk_mhz = 810.0,
 159                                 .socclk_mhz = 1254.0,
 160                                 .dram_speed_mts = 3600.0,
 161                         },
 162                         {
 163                                 .state = 2,
 164                                 .dscclk_mhz = 400.0,
 165                                 .dcfclk_mhz = 1000.0,
 166                                 .fabricclk_mhz = 750.0,
 167                                 .dispclk_mhz = 1200.0,
 168                                 .dppclk_mhz = 1200.0,
 169                                 .phyclk_mhz = 810.0,
 170                                 .socclk_mhz = 1254.0,
 171                                 .dram_speed_mts = 6800.0,
 172                         },
 173                         {
 174                                 .state = 3,
 175                                 .dscclk_mhz = 400.0,
 176                                 .dcfclk_mhz = 1000.0,
 177                                 .fabricclk_mhz = 250.0,
 178                                 .dispclk_mhz = 1200.0,
 179                                 .dppclk_mhz = 1200.0,
 180                                 .phyclk_mhz = 810.0,
 181                                 .socclk_mhz = 1254.0,
 182                                 .dram_speed_mts = 14000.0,
 183                         },
 184                         /* state4 is not an actual state, just defines unsupported for dml*/
 185                         {
 186                                 .state = 4,
 187                                 .dscclk_mhz = 400.0,
 188                                 .dcfclk_mhz = 1000.0,
 189                                 .fabricclk_mhz = 750.0,
 190                                 .dispclk_mhz = 1200.0,
 191                                 .dppclk_mhz = 1200.0,
 192                                 .phyclk_mhz = 810.0,
 193                                 .socclk_mhz = 1254.0,
 194                                 .dram_speed_mts = 14000.0,
 195                         }
 196                 },
 197         .num_states = 4,
 198         .sr_exit_time_us = 9.0,
 199         .sr_enter_plus_exit_time_us = 11.0,
 200         .urgent_latency_us = 4.0,
 201         .urgent_latency_pixel_data_only_us = 4.0,
 202         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 203         .urgent_latency_vm_data_only_us = 4.0,
 204         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 256,
 205         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 256,
 206         .urgent_out_of_order_return_per_channel_vm_only_bytes = 256,
 207         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 208         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 80.0,
 209         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 80.0,
 210         .max_avg_sdp_bw_use_normal_percent = 80.0,
 211         .max_avg_dram_bw_use_normal_percent = 69.0,
 212         .writeback_latency_us = 12.0,
 213         .ideal_dram_bw_after_urgent_percent = 80.0,
 214         .max_request_size_bytes = 256,
 215         .dram_channel_width_bytes = 2,
 216         .fabric_datapath_to_dcn_data_return_bytes = 64,
 217         .dcn_downspread_percent = 0.3,
 218         .downspread_percent = 0.3,
 219         .dram_page_open_time_ns = 50.0,
 220         .dram_rw_turnaround_time_ns = 17.5,
 221         .dram_return_buffer_per_channel_bytes = 8192,
 222         .round_trip_ping_latency_dcfclk_cycles = 128,
 223         .urgent_out_of_order_return_per_channel_bytes = 256,
 224         .channel_interleave_bytes = 256,
 225         .num_banks = 8,
 226         .num_chans = 16,
 227         .vmm_page_size_bytes = 4096,
 228         .dram_clock_change_latency_us = 250.0,
 229         .writeback_dram_clock_change_latency_us = 23.0,
 230         .return_bus_width_bytes = 64,
 231         .dispclk_dppclk_vco_speed_mhz = 3000,
 232         .use_urgent_burst_bw = 0,
 233 };
 234
 235 enum dcn20_clk_src_array_id {
 236         DCN20_CLK_SRC_PLL0,
 237         DCN20_CLK_SRC_PLL1,
 238         DCN20_CLK_SRC_TOTAL_DCN201
 239 };
 240
 241 /* begin *********************
 242  * macros to expend register list macro defined in HW object header file */
 243
 244 /* DCN */
 245
 246 #undef BASE_INNER
 247 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 248
 249 #define BASE(seg) BASE_INNER(seg)
 250
 251 #define SR(reg_name)\
 252                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 253                                         mm ## reg_name
 254
 255 #define SRI(reg_name, block, id)\
 256         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 257                                         mm ## block ## id ## _ ## reg_name
 258
 259 #define SRIR(var_name, reg_name, block, id)\
 260         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 261                                         mm ## block ## id ## _ ## reg_name
 262
 263 #define SRII(reg_name, block, id)\
 264         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 265                                         mm ## block ## id ## _ ## reg_name
 266
 267 #define SRI_IX(reg_name, block, id)\
 268         .reg_name = ix ## block ## id ## _ ## reg_name
 269
 270 #define DCCG_SRII(reg_name, block, id)\
 271         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 272                                         mm ## block ## id ## _ ## reg_name
 273
 274 #define VUPDATE_SRII(reg_name, block, id)\
 275         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 276                                         mm ## reg_name ## _ ## block ## id
 277
 278 /* NBIO */
 279 #define NBIO_BASE_INNER(seg) \
 280         NBIO_BASE__INST0_SEG ## seg
 281
 282 #define NBIO_BASE(seg) \
 283         NBIO_BASE_INNER(seg)
 284
 285 #define NBIO_SR(reg_name)\
 286                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 287                                         mm ## reg_name
 288
 289 /* MMHUB */
 290 #define MMHUB_BASE_INNER(seg) \
 291         MMHUB_BASE__INST0_SEG ## seg
 292
 293 #define MMHUB_BASE(seg) \
 294         MMHUB_BASE_INNER(seg)
 295
 296 #define MMHUB_SR(reg_name)\
 297                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 298                                         mmMM ## reg_name
 299
 300 static const struct bios_registers bios_regs = {
 301                 NBIO_SR(BIOS_SCRATCH_3),
 302                 NBIO_SR(BIOS_SCRATCH_6)
 303 };
 304
 305 #define clk_src_regs(index, pllid)\
 306 [index] = {\
 307         CS_COMMON_REG_LIST_DCN201(index, pllid),\
 308 }
 309
 310 static const struct dce110_clk_src_regs clk_src_regs[] = {
 311         clk_src_regs(0, A),
 312         clk_src_regs(1, B)
 313 };
 314
 315 static const struct dce110_clk_src_shift cs_shift = {
 316                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 317 };
 318
 319 static const struct dce110_clk_src_mask cs_mask = {
 320                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 321 };
 322
 323 #define audio_regs(id)\
 324 [id] = {\
 325                 AUD_COMMON_REG_LIST(id)\
 326 }
 327
 328 static const struct dce_audio_registers audio_regs[] = {
 329         audio_regs(0),
 330         audio_regs(1),
 331 };
 332
 333 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 334                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 335                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 336                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 337
 338 static const struct dce_audio_shift audio_shift = {
 339                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 340 };
 341
 342 static const struct dce_audio_mask audio_mask = {
 343                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 344 };
 345
 346 #define stream_enc_regs(id)\
 347 [id] = {\
 348         SE_DCN2_REG_LIST(id)\
 349 }
 350
 351 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 352         stream_enc_regs(0),
 353         stream_enc_regs(1)
 354 };
 355
 356 static const struct dcn10_stream_encoder_shift se_shift = {
 357                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 358 };
 359
 360 static const struct dcn10_stream_encoder_mask se_mask = {
 361                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 362 };
 363
 364 static const struct dce110_aux_registers_shift aux_shift = {
 365         DCN_AUX_MASK_SH_LIST(__SHIFT)
 366 };
 367
 368 static const struct dce110_aux_registers_mask aux_mask = {
 369         DCN_AUX_MASK_SH_LIST(_MASK)
 370 };
 371
 372 #define aux_regs(id)\
 373 [id] = {\
 374         DCN2_AUX_REG_LIST(id)\
 375 }
 376
 377 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 378                 aux_regs(0),
 379                 aux_regs(1),
 380 };
 381
 382 #define hpd_regs(id)\
 383 [id] = {\
 384         HPD_REG_LIST(id)\
 385 }
 386
 387 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 388                 hpd_regs(0),
 389                 hpd_regs(1),
 390 };
 391
 392 #define link_regs(id, phyid)\
 393 [id] = {\
 394         LE_DCN_COMMON_REG_LIST(id), \
 395         UNIPHY_DCN2_REG_LIST(phyid) \
 396 }
 397
 398 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 399         link_regs(0, A),
 400         link_regs(1, B),
 401 };
 402
 403 #define LINK_ENCODER_MASK_SH_LIST_DCN201(mask_sh)\
 404         LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
 405
 406 static const struct dcn10_link_enc_shift le_shift = {
 407                 LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
 408 };
 409
 410 static const struct dcn10_link_enc_mask le_mask = {
 411                 LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
 412 };
 413
 414 #define ipp_regs(id)\
 415 [id] = {\
 416                 IPP_REG_LIST_DCN201(id),\
 417 }
 418
 419 static const struct dcn10_ipp_registers ipp_regs[] = {
 420         ipp_regs(0),
 421         ipp_regs(1),
 422         ipp_regs(2),
 423         ipp_regs(3),
 424 };
 425
 426 static const struct dcn10_ipp_shift ipp_shift = {
 427                 IPP_MASK_SH_LIST_DCN201(__SHIFT)
 428 };
 429
 430 static const struct dcn10_ipp_mask ipp_mask = {
 431                 IPP_MASK_SH_LIST_DCN201(_MASK)
 432 };
 433
 434 #define opp_regs(id)\
 435 [id] = {\
 436         OPP_REG_LIST_DCN201(id),\
 437 }
 438
 439 static const struct dcn201_opp_registers opp_regs[] = {
 440         opp_regs(0),
 441         opp_regs(1),
 442 };
 443
 444 static const struct dcn201_opp_shift opp_shift = {
 445                 OPP_MASK_SH_LIST_DCN201(__SHIFT)
 446 };
 447
 448 static const struct dcn201_opp_mask opp_mask = {
 449                 OPP_MASK_SH_LIST_DCN201(_MASK)
 450 };
 451
 452 #define aux_engine_regs(id)\
 453 [id] = {\
 454         AUX_COMMON_REG_LIST0(id), \
 455         .AUX_RESET_MASK = 0 \
 456 }
 457
 458 static const struct dce110_aux_registers aux_engine_regs[] = {
 459                 aux_engine_regs(0),
 460                 aux_engine_regs(1)
 461 };
 462
 463 #define tf_regs(id)\
 464 [id] = {\
 465         TF_REG_LIST_DCN201(id),\
 466 }
 467
 468 static const struct dcn201_dpp_registers tf_regs[] = {
 469         tf_regs(0),
 470         tf_regs(1),
 471         tf_regs(2),
 472         tf_regs(3),
 473 };
 474
 475 static const struct dcn201_dpp_shift tf_shift = {
 476                 TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
 477 };
 478
 479 static const struct dcn201_dpp_mask tf_mask = {
 480                 TF_REG_LIST_SH_MASK_DCN201(_MASK)
 481 };
 482
 483 static const struct dcn201_mpc_registers mpc_regs = {
 484                 MPC_REG_LIST_DCN201(0),
 485                 MPC_REG_LIST_DCN201(1),
 486                 MPC_REG_LIST_DCN201(2),
 487                 MPC_REG_LIST_DCN201(3),
 488                 MPC_REG_LIST_DCN201(4),
 489                 MPC_OUT_MUX_REG_LIST_DCN201(0),
 490                 MPC_OUT_MUX_REG_LIST_DCN201(1),
 491 };
 492
 493 static const struct dcn201_mpc_shift mpc_shift = {
 494         MPC_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
 495 };
 496
 497 static const struct dcn201_mpc_mask mpc_mask = {
 498         MPC_COMMON_MASK_SH_LIST_DCN201(_MASK)
 499 };
 500
 501 #define tg_regs_dcn201(id)\
 502 [id] = {TG_COMMON_REG_LIST_DCN201(id)}
 503
 504 static const struct dcn_optc_registers tg_regs[] = {
 505         tg_regs_dcn201(0),
 506         tg_regs_dcn201(1)
 507 };
 508
 509 static const struct dcn_optc_shift tg_shift = {
 510         TG_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
 511 };
 512
 513 static const struct dcn_optc_mask tg_mask = {
 514         TG_COMMON_MASK_SH_LIST_DCN201(_MASK)
 515 };
 516
 517 #define hubp_regsDCN201(id)\
 518 [id] = {\
 519         HUBP_REG_LIST_DCN201(id)\
 520 }
 521
 522 static const struct dcn201_hubp_registers hubp_regs[] = {
 523                 hubp_regsDCN201(0),
 524                 hubp_regsDCN201(1),
 525                 hubp_regsDCN201(2),
 526                 hubp_regsDCN201(3)
 527 };
 528
 529 static const struct dcn201_hubp_shift hubp_shift = {
 530                 HUBP_MASK_SH_LIST_DCN201(__SHIFT)
 531 };
 532
 533 static const struct dcn201_hubp_mask hubp_mask = {
 534                 HUBP_MASK_SH_LIST_DCN201(_MASK)
 535 };
 536
 537 static const struct dcn_hubbub_registers hubbub_reg = {
 538                 HUBBUB_REG_LIST_DCN201(0)
 539 };
 540
 541 static const struct dcn_hubbub_shift hubbub_shift = {
 542                 HUBBUB_MASK_SH_LIST_DCN201(__SHIFT)
 543 };
 544
 545 static const struct dcn_hubbub_mask hubbub_mask = {
 546                 HUBBUB_MASK_SH_LIST_DCN201(_MASK)
 547 };
 548
 549
 550 static const struct dccg_registers dccg_regs = {
 551                 DCCG_COMMON_REG_LIST_DCN_BASE()
 552 };
 553
 554 static const struct dccg_shift dccg_shift = {
 555                 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(__SHIFT)
 556 };
 557
 558 static const struct dccg_mask dccg_mask = {
 559                 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK)
 560 };
 561
 562 static const struct resource_caps res_cap_dnc201 = {
 563                 .num_timing_generator = 2,
 564                 .num_opp = 2,
 565                 .num_video_plane = 4,
 566                 .num_audio = 2,
 567                 .num_stream_encoder = 2,
 568                 .num_pll = 2,
 569                 .num_dwb = 0,
 570                 .num_dsc = 0,
 571                 .num_ddc = 2,
 572 };
 573
 574 static const struct dc_plane_cap plane_cap = {
 575         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 576         .per_pixel_alpha = true,
 577
 578         .pixel_format_support = {
 579                         .argb8888 = true,
 580                         .nv12 = false,
 581                         .fp16 = true,
 582                         .p010 = false,
 583         },
 584
 585         .max_upscale_factor = {
 586                         .argb8888 = 16000,
 587                         .nv12 = 16000,
 588                         .fp16 = 1
 589         },
 590
 591         .max_downscale_factor = {
 592                         .argb8888 = 250,
 593                         .nv12 = 250,
 594                         .fp16 = 250
 595         },
 596         64,
 597         64
 598 };
 599
 600 static const struct dc_debug_options debug_defaults_drv = {
 601                 .disable_dmcu = true,
 602                 .force_abm_enable = false,
 603                 .timing_trace = false,
 604                 .clock_trace = true,
 605                 .disable_pplib_clock_request = true,
 606                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 607                 .force_single_disp_pipe_split = false,
 608                 .disable_dcc = DCC_ENABLE,
 609                 .vsr_support = true,
 610                 .performance_trace = false,
 611                 .az_endpoint_mute_only = true,
 612                 .max_downscale_src_width = 3840,
 613                 .disable_pplib_wm_range = true,
 614                 .scl_reset_length10 = true,
 615                 .sanity_checks = false,
 616                 .underflow_assert_delay_us = 0xFFFFFFFF,
 617                 .enable_tri_buf = true,
 618                 .enable_legacy_fast_update = true,
 619                 .using_dml2 = false,
 620 };
 621
 622 static void dcn201_dpp_destroy(struct dpp **dpp)
 623 {
 624         kfree(TO_DCN201_DPP(*dpp));
 625         *dpp = NULL;
 626 }
 627
 628 static struct dpp *dcn201_dpp_create(
 629         struct dc_context *ctx,
 630         uint32_t inst)
 631 {
 632         struct dcn201_dpp *dpp =
 633                 kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC);
 634
 635         if (!dpp)
 636                 return NULL;
 637
 638         if (dpp201_construct(dpp, ctx, inst,
 639                         &tf_regs[inst], &tf_shift, &tf_mask))
 640                 return &dpp->base;
 641
 642         kfree(dpp);
 643         return NULL;
 644 }
 645
 646 static struct input_pixel_processor *dcn201_ipp_create(
 647         struct dc_context *ctx, uint32_t inst)
 648 {
 649         struct dcn10_ipp *ipp =
 650                 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
 651
 652         if (!ipp) {
 653                 return NULL;
 654         }
 655
 656         dcn20_ipp_construct(ipp, ctx, inst,
 657                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 658         return &ipp->base;
 659 }
 660
 661
 662 static struct output_pixel_processor *dcn201_opp_create(
 663         struct dc_context *ctx, uint32_t inst)
 664 {
 665         struct dcn201_opp *opp =
 666                 kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC);
 667
 668         if (!opp) {
 669                 return NULL;
 670         }
 671
 672         dcn201_opp_construct(opp, ctx, inst,
 673                         &opp_regs[inst], &opp_shift, &opp_mask);
 674         return &opp->base;
 675 }
 676
 677 static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
 678                                                 uint32_t inst)
 679 {
 680         struct aux_engine_dce110 *aux_engine =
 681                 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
 682
 683         if (!aux_engine)
 684                 return NULL;
 685
 686         dce110_aux_engine_construct(aux_engine, ctx, inst,
 687                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 688                                     &aux_engine_regs[inst],
 689                                         &aux_mask,
 690                                         &aux_shift,
 691                                         ctx->dc->caps.extended_aux_timeout_support);
 692
 693         return &aux_engine->base;
 694 }
 695 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 696
 697 static const struct dce_i2c_registers i2c_hw_regs[] = {
 698                 i2c_inst_regs(1),
 699                 i2c_inst_regs(2),
 700 };
 701
 702 static const struct dce_i2c_shift i2c_shifts = {
 703                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 704 };
 705
 706 static const struct dce_i2c_mask i2c_masks = {
 707                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 708 };
 709
 710 static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
 711                                                uint32_t inst)
 712 {
 713         struct dce_i2c_hw *dce_i2c_hw =
 714                 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
 715
 716         if (!dce_i2c_hw)
 717                 return NULL;
 718
 719         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 720                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 721
 722         return dce_i2c_hw;
 723 }
 724
 725 static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)
 726 {
 727         struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc),
 728                                             GFP_ATOMIC);
 729
 730         if (!mpc201)
 731                 return NULL;
 732
 733         dcn201_mpc_construct(mpc201, ctx,
 734                         &mpc_regs,
 735                         &mpc_shift,
 736                         &mpc_mask,
 737                         num_mpcc);
 738
 739         return &mpc201->base;
 740 }
 741
 742 static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)
 743 {
 744         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
 745                                           GFP_ATOMIC);
 746
 747         if (!hubbub)
 748                 return NULL;
 749
 750         hubbub201_construct(hubbub, ctx,
 751                         &hubbub_reg,
 752                         &hubbub_shift,
 753                         &hubbub_mask);
 754
 755         return &hubbub->base;
 756 }
 757
 758 static struct timing_generator *dcn201_timing_generator_create(
 759                 struct dc_context *ctx,
 760                 uint32_t instance)
 761 {
 762         struct optc *tgn10 =
 763                 kzalloc(sizeof(struct optc), GFP_ATOMIC);
 764
 765         if (!tgn10)
 766                 return NULL;
 767
 768         tgn10->base.inst = instance;
 769         tgn10->base.ctx = ctx;
 770
 771         tgn10->tg_regs = &tg_regs[instance];
 772         tgn10->tg_shift = &tg_shift;
 773         tgn10->tg_mask = &tg_mask;
 774
 775         dcn201_timing_generator_init(tgn10);
 776
 777         return &tgn10->base;
 778 }
 779
 780 static const struct encoder_feature_support link_enc_feature = {
 781                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 782                 .max_hdmi_pixel_clock = 600000,
 783                 .hdmi_ycbcr420_supported = true,
 784                 .dp_ycbcr420_supported = true,
 785                 .fec_supported = true,
 786                 .flags.bits.IS_HBR2_CAPABLE = true,
 787                 .flags.bits.IS_HBR3_CAPABLE = true,
 788                 .flags.bits.IS_TPS3_CAPABLE = true,
 789                 .flags.bits.IS_TPS4_CAPABLE = true
 790 };
 791
 792 static struct link_encoder *dcn201_link_encoder_create(
 793         struct dc_context *ctx,
 794         const struct encoder_init_data *enc_init_data)
 795 {
 796         struct dcn20_link_encoder *enc20 =
 797                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);
 798         struct dcn10_link_encoder *enc10;
 799
 800         if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
 801                 return NULL;
 802
 803         enc10 = &enc20->enc10;
 804
 805         dcn201_link_encoder_construct(enc20,
 806                         enc_init_data,
 807                         &link_enc_feature,
 808                         &link_enc_regs[enc_init_data->transmitter],
 809                         &link_enc_aux_regs[enc_init_data->channel - 1],
 810                         &link_enc_hpd_regs[enc_init_data->hpd_source],
 811                         &le_shift,
 812                         &le_mask);
 813
 814         return &enc10->base;
 815 }
 816
 817 static struct clock_source *dcn201_clock_source_create(
 818         struct dc_context *ctx,
 819         struct dc_bios *bios,
 820         enum clock_source_id id,
 821         const struct dce110_clk_src_regs *regs,
 822         bool dp_clk_src)
 823 {
 824         struct dce110_clk_src *clk_src =
 825                 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
 826
 827         if (!clk_src)
 828                 return NULL;
 829
 830         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 831                         regs, &cs_shift, &cs_mask)) {
 832                 clk_src->base.dp_clk_src = dp_clk_src;
 833                 return &clk_src->base;
 834         }
 835         kfree(clk_src);
 836         return NULL;
 837 }
 838
 839 static void read_dce_straps(
 840         struct dc_context *ctx,
 841         struct resource_straps *straps)
 842 {
 843         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 844
 845                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 846 }
 847
 848 static struct audio *dcn201_create_audio(
 849                 struct dc_context *ctx, unsigned int inst)
 850 {
 851         return dce_audio_create(ctx, inst,
 852                         &audio_regs[inst], &audio_shift, &audio_mask);
 853 }
 854
 855 static struct stream_encoder *dcn201_stream_encoder_create(
 856         enum engine_id eng_id,
 857         struct dc_context *ctx)
 858 {
 859         struct dcn10_stream_encoder *enc1 =
 860                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC);
 861
 862         if (!enc1)
 863                 return NULL;
 864
 865         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 866                                         &stream_enc_regs[eng_id],
 867                                         &se_shift, &se_mask);
 868
 869         return &enc1->base;
 870 }
 871
 872 static const struct dce_hwseq_registers hwseq_reg = {
 873                 HWSEQ_DCN201_REG_LIST()
 874 };
 875
 876 static const struct dce_hwseq_shift hwseq_shift = {
 877                 HWSEQ_DCN201_MASK_SH_LIST(__SHIFT)
 878 };
 879
 880 static const struct dce_hwseq_mask hwseq_mask = {
 881                 HWSEQ_DCN201_MASK_SH_LIST(_MASK)
 882 };
 883
 884 static struct dce_hwseq *dcn201_hwseq_create(
 885         struct dc_context *ctx)
 886 {
 887         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC);
 888
 889         if (hws) {
 890                 hws->ctx = ctx;
 891                 hws->regs = &hwseq_reg;
 892                 hws->shifts = &hwseq_shift;
 893                 hws->masks = &hwseq_mask;
 894         }
 895         return hws;
 896 }
 897
 898 static const struct resource_create_funcs res_create_funcs = {
 899         .read_dce_straps = read_dce_straps,
 900         .create_audio = dcn201_create_audio,
 901         .create_stream_encoder = dcn201_stream_encoder_create,
 902         .create_hwseq = dcn201_hwseq_create,
 903 };
 904
 905 static void dcn201_clock_source_destroy(struct clock_source **clk_src)
 906 {
 907         kfree(TO_DCE110_CLK_SRC(*clk_src));
 908         *clk_src = NULL;
 909 }
 910
 911 static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)
 912 {
 913         unsigned int i;
 914
 915         for (i = 0; i < pool->base.stream_enc_count; i++) {
 916                 if (pool->base.stream_enc[i] != NULL) {
 917                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 918                         pool->base.stream_enc[i] = NULL;
 919                 }
 920         }
 921
 922
 923         if (pool->base.mpc != NULL) {
 924                 kfree(TO_DCN201_MPC(pool->base.mpc));
 925                 pool->base.mpc = NULL;
 926         }
 927
 928         if (pool->base.hubbub != NULL) {
 929                 kfree(pool->base.hubbub);
 930                 pool->base.hubbub = NULL;
 931         }
 932
 933         for (i = 0; i < pool->base.pipe_count; i++) {
 934                 if (pool->base.dpps[i] != NULL)
 935                         dcn201_dpp_destroy(&pool->base.dpps[i]);
 936
 937                 if (pool->base.ipps[i] != NULL)
 938                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 939
 940                 if (pool->base.hubps[i] != NULL) {
 941                         kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 942                         pool->base.hubps[i] = NULL;
 943                 }
 944
 945                 if (pool->base.irqs != NULL) {
 946                         dal_irq_service_destroy(&pool->base.irqs);
 947                 }
 948         }
 949
 950         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 951                 if (pool->base.opps[i] != NULL)
 952                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 953         }
 954
 955         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 956                 if (pool->base.timing_generators[i] != NULL)    {
 957                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 958                         pool->base.timing_generators[i] = NULL;
 959                 }
 960         }
 961         for (i = 0; i < pool->base.audio_count; i++) {
 962                 if (pool->base.audios[i])
 963                         dce_aud_destroy(&pool->base.audios[i]);
 964         }
 965
 966         for (i = 0; i < pool->base.clk_src_count; i++) {
 967                 if (pool->base.clock_sources[i] != NULL) {
 968                         dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
 969                         pool->base.clock_sources[i] = NULL;
 970                 }
 971         }
 972
 973         if (pool->base.dp_clock_source != NULL) {
 974                 dcn201_clock_source_destroy(&pool->base.dp_clock_source);
 975                 pool->base.dp_clock_source = NULL;
 976         }
 977
 978         if (pool->base.dccg != NULL)
 979                 dcn_dccg_destroy(&pool->base.dccg);
 980 }
 981
 982 static struct hubp *dcn201_hubp_create(
 983         struct dc_context *ctx,
 984         uint32_t inst)
 985 {
 986         struct dcn201_hubp *hubp201 =
 987                 kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC);
 988
 989         if (!hubp201)
 990                 return NULL;
 991
 992         if (dcn201_hubp_construct(hubp201, ctx, inst,
 993                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
 994                 return &hubp201->base;
 995
 996         kfree(hubp201);
 997         return NULL;
 998 }
 999
1000 static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(
1001                 const struct dc_state *cur_ctx,
1002                 struct dc_state *new_ctx,
1003                 const struct resource_pool *pool,
1004                 const struct pipe_ctx *opp_head_pipe)
1005 {
1006         struct resource_context *res_ctx = &new_ctx->res_ctx;
1007         struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1008         struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1009
1010         if (!head_pipe) {
1011                 ASSERT(0);
1012                 return NULL;
1013         }
1014
1015         if (!idle_pipe)
1016                 return NULL;
1017
1018         idle_pipe->stream = head_pipe->stream;
1019         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1020         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1021
1022         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1023         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1024         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1025         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1026
1027         return idle_pipe;
1028 }
1029
1030 static bool dcn201_get_dcc_compression_cap(const struct dc *dc,
1031                 const struct dc_dcc_surface_param *input,
1032                 struct dc_surface_dcc_cap *output)
1033 {
1034         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1035                         dc->res_pool->hubbub,
1036                         input,
1037                         output);
1038 }
1039
1040 static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
1041                                                        struct resource_context *res_ctx,
1042                                                        display_e2e_pipe_params_st *pipes)
1043 {
1044         DC_FP_START();
1045         dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1046         DC_FP_END();
1047 }
1048
1049 static void dcn201_destroy_resource_pool(struct resource_pool **pool)
1050 {
1051         struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool);
1052
1053         dcn201_resource_destruct(dcn201_pool);
1054         kfree(dcn201_pool);
1055         *pool = NULL;
1056 }
1057
1058 static void dcn201_link_init(struct dc_link *link)
1059 {
1060         if (link->ctx->dc_bios->integrated_info)
1061                 link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;
1062 }
1063
1064 static struct dc_cap_funcs cap_funcs = {
1065         .get_dcc_compression_cap = dcn201_get_dcc_compression_cap,
1066 };
1067
1068 static struct resource_funcs dcn201_res_pool_funcs = {
1069         .link_init = dcn201_link_init,
1070         .destroy = dcn201_destroy_resource_pool,
1071         .link_enc_create = dcn201_link_encoder_create,
1072         .panel_cntl_create = NULL,
1073         .validate_bandwidth = dcn20_validate_bandwidth,
1074         .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
1075         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1076         .add_dsc_to_stream_resource = NULL,
1077         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1078         .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer,
1079         .release_pipe = dcn20_release_pipe,
1080         .populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
1081         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1082         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1083         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1084 };
1085
1086 static bool dcn201_resource_construct(
1087         uint8_t num_virtual_links,
1088         struct dc *dc,
1089         struct dcn201_resource_pool *pool)
1090 {
1091         int i;
1092         struct dc_context *ctx = dc->ctx;
1093
1094         ctx->dc_bios->regs = &bios_regs;
1095
1096         pool->base.res_cap = &res_cap_dnc201;
1097         pool->base.funcs = &dcn201_res_pool_funcs;
1098
1099         /*************************************************
1100          *  Resource + asic cap harcoding                *
1101          *************************************************/
1102         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1103
1104         pool->base.pipe_count = 4;
1105         pool->base.mpcc_count = 5;
1106         dc->caps.max_downscale_ratio = 200;
1107         dc->caps.i2c_speed_in_khz = 100;
1108         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1109         dc->caps.max_cursor_size = 256;
1110         dc->caps.min_horizontal_blanking_period = 80;
1111         dc->caps.dmdata_alloc_size = 2048;
1112
1113         dc->caps.max_slave_planes = 1;
1114         dc->caps.max_slave_yuv_planes = 1;
1115         dc->caps.max_slave_rgb_planes = 1;
1116         dc->caps.post_blend_color_processing = true;
1117         dc->caps.force_dp_tps4_for_cp2520 = true;
1118         dc->caps.extended_aux_timeout_support = true;
1119
1120         /* Color pipeline capabilities */
1121         dc->caps.color.dpp.dcn_arch = 1;
1122         dc->caps.color.dpp.input_lut_shared = 0;
1123         dc->caps.color.dpp.icsc = 1;
1124         dc->caps.color.dpp.dgam_ram = 1;
1125         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1126         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1127         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1128         dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1129         dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1130         dc->caps.color.dpp.post_csc = 0;
1131         dc->caps.color.dpp.gamma_corr = 0;
1132         dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1133
1134         dc->caps.color.dpp.hw_3d_lut = 1;
1135         dc->caps.color.dpp.ogam_ram = 1;
1136         // no OGAM ROM on DCN2
1137         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1138         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1139         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1140         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1141         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1142         dc->caps.color.dpp.ocsc = 0;
1143
1144         dc->caps.color.mpc.gamut_remap = 0;
1145         dc->caps.color.mpc.num_3dluts = 0;
1146         dc->caps.color.mpc.shared_3d_lut = 0;
1147         dc->caps.color.mpc.ogam_ram = 1;
1148         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1149         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1150         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1151         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1152         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1153         dc->caps.color.mpc.ocsc = 1;
1154
1155         dc->debug = debug_defaults_drv;
1156
1157         /*a0 only, remove later*/
1158         dc->work_arounds.no_connect_phy_config  = true;
1159         dc->work_arounds.dedcn20_305_wa = true;
1160         /*************************************************
1161          *  Create resources                             *
1162          *************************************************/
1163
1164         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1165                         dcn201_clock_source_create(ctx, ctx->dc_bios,
1166                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1167                                 &clk_src_regs[0], false);
1168         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1169                         dcn201_clock_source_create(ctx, ctx->dc_bios,
1170                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1171                                 &clk_src_regs[1], false);
1172
1173         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;
1174
1175         /* todo: not reuse phy_pll registers */
1176         pool->base.dp_clock_source =
1177                         dcn201_clock_source_create(ctx, ctx->dc_bios,
1178                                 CLOCK_SOURCE_ID_DP_DTO,
1179                                 &clk_src_regs[0], true);
1180
1181         for (i = 0; i < pool->base.clk_src_count; i++) {
1182                 if (pool->base.clock_sources[i] == NULL) {
1183                         dm_error("DC: failed to create clock sources!\n");
1184                         goto create_fail;
1185                 }
1186         }
1187
1188         pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1189         if (pool->base.dccg == NULL) {
1190                 dm_error("DC: failed to create dccg!\n");
1191                 goto create_fail;
1192         }
1193
1194         dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1195         dcn201_ip.max_num_dpp = pool->base.pipe_count;
1196         dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);
1197         {
1198                 struct irq_service_init_data init_data;
1199                 init_data.ctx = dc->ctx;
1200                 pool->base.irqs = dal_irq_service_dcn201_create(&init_data);
1201                 if (!pool->base.irqs)
1202                         goto create_fail;
1203         }
1204
1205         /* mem input -> ipp -> dpp -> opp -> TG */
1206         for (i = 0; i < pool->base.pipe_count; i++) {
1207                 pool->base.hubps[i] = dcn201_hubp_create(ctx, i);
1208                 if (pool->base.hubps[i] == NULL) {
1209                         dm_error(
1210                                 "DC: failed to create memory input!\n");
1211                         goto create_fail;
1212                 }
1213
1214                 pool->base.ipps[i] = dcn201_ipp_create(ctx, i);
1215                 if (pool->base.ipps[i] == NULL) {
1216                         dm_error(
1217                                 "DC: failed to create input pixel processor!\n");
1218                         goto create_fail;
1219                 }
1220
1221                 pool->base.dpps[i] = dcn201_dpp_create(ctx, i);
1222                 if (pool->base.dpps[i] == NULL) {
1223                         dm_error(
1224                                 "DC: failed to create dpps!\n");
1225                         goto create_fail;
1226                 }
1227         }
1228
1229         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1230                 pool->base.opps[i] = dcn201_opp_create(ctx, i);
1231                 if (pool->base.opps[i] == NULL) {
1232                         dm_error(
1233                                 "DC: failed to create output pixel processor!\n");
1234                         goto create_fail;
1235                 }
1236         }
1237
1238         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1239                 pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);
1240                 if (pool->base.engines[i] == NULL) {
1241                         dm_error(
1242                                 "DC:failed to create aux engine!!\n");
1243                         goto create_fail;
1244                 }
1245                 pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);
1246                 if (pool->base.hw_i2cs[i] == NULL) {
1247                         dm_error(
1248                                 "DC:failed to create hw i2c!!\n");
1249                         goto create_fail;
1250                 }
1251                 pool->base.sw_i2cs[i] = NULL;
1252         }
1253
1254         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1255                 pool->base.timing_generators[i] = dcn201_timing_generator_create(
1256                                 ctx, i);
1257                 if (pool->base.timing_generators[i] == NULL) {
1258                         dm_error("DC: failed to create tg!\n");
1259                         goto create_fail;
1260                 }
1261         }
1262
1263         pool->base.timing_generator_count = i;
1264
1265         pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);
1266         if (pool->base.mpc == NULL) {
1267                 dm_error("DC: failed to create mpc!\n");
1268                 goto create_fail;
1269         }
1270
1271         pool->base.hubbub = dcn201_hubbub_create(ctx);
1272         if (pool->base.hubbub == NULL) {
1273                 dm_error("DC: failed to create hubbub!\n");
1274                 goto create_fail;
1275         }
1276
1277         if (!resource_construct(num_virtual_links, dc, &pool->base,
1278                         &res_create_funcs))
1279                 goto create_fail;
1280
1281         dcn201_hw_sequencer_construct(dc);
1282
1283         dc->caps.max_planes =  pool->base.pipe_count;
1284
1285         for (i = 0; i < dc->caps.max_planes; ++i)
1286                 dc->caps.planes[i] = plane_cap;
1287
1288         dc->cap_funcs = cap_funcs;
1289
1290         return true;
1291
1292 create_fail:
1293
1294         dcn201_resource_destruct(pool);
1295
1296         return false;
1297 }
1298
1299 struct resource_pool *dcn201_create_resource_pool(
1300                 const struct dc_init_data *init_data,
1301                 struct dc *dc)
1302 {
1303         struct dcn201_resource_pool *pool =
1304                 kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC);
1305
1306         if (!pool)
1307                 return NULL;
1308
1309         if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))
1310                 return &pool->base;
1311
1312         kfree(pool);
1313         return NULL;
1314 }