[linux.git] / drivers / pwm / pwm-tegra.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010-2020, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]>
 *
 * Overview of Tegra Pulse Width Modulator Register:
 * 1. 13-bit: Frequency division (SCALE)
 * 2. 8-bit : Pulse division (DUTY)
 * 3. 1-bit : Enable bit
 *
 * The PWM clock frequency is divided by 256 before subdividing it based
 * on the programmable frequency division value to generate the required
 * frequency for PWM output. The maximum output frequency that can be
 * achieved is (max rate of source clock) / 256.
 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
 * 408 MHz/256 = 1.6 MHz.
 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
 *
 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
 * To achieve 100% duty cycle, program Bit [24] of this register to
 * 1’b1. In which case the other bits [23:16] are set to don't care.
 *
 * Limitations:
 * -	When PWM is disabled, the output is driven to inactive.
 * -	It does not allow the current PWM period to complete and
 *	stops abruptly.
 *
 * -	If the register is reconfigured while PWM is running,
 *	it does not complete the currently running period.
 *
 * -	If the user input duty is beyond acceptible limits,
 *	-EINVAL is returned.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/reset.h>

#include <soc/tegra/common.h>

#define PWM_ENABLE	(1 << 31)
#define PWM_DUTY_WIDTH	8
#define PWM_DUTY_SHIFT	16
#define PWM_SCALE_WIDTH	13
#define PWM_SCALE_SHIFT	0

struct tegra_pwm_soc {
	unsigned int num_channels;

	/* Maximum IP frequency for given SoCs */
	unsigned long max_frequency;
};

struct tegra_pwm_chip {
	struct pwm_chip chip;
	struct device *dev;

	struct clk *clk;
	struct reset_control*rst;

	unsigned long clk_rate;
	unsigned long min_period_ns;

	void __iomem *regs;

	const struct tegra_pwm_soc *soc;
};

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct tegra_pwm_chip, chip);
}

static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
{
	return readl(pc->regs + (offset << 4));
}

static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
{
	writel(value, pc->regs + (offset << 4));
}

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	unsigned long long c = duty_ns;
	unsigned long rate, required_clk_rate;
	u32 val = 0;
	int err;

	/*
	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	 * nearest integer during division.
	 */
	c *= (1 << PWM_DUTY_WIDTH);
	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);

	val = (u32)c << PWM_DUTY_SHIFT;

	/*
	 *  min period = max clock limit >> PWM_DUTY_WIDTH
	 */
	if (period_ns < pc->min_period_ns)
		return -EINVAL;

	/*
	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	 * cycles at the PWM clock rate will take period_ns nanoseconds.
	 *
	 * num_channels: If single instance of PWM controller has multiple
	 * channels (e.g. Tegra210 or older) then it is not possible to
	 * configure separate clock rates to each of the channels, in such
	 * case the value stored during probe will be referred.
	 *
	 * If every PWM controller instance has one channel respectively, i.e.
	 * nums_channels == 1 then only the clock rate can be modified
	 * dynamically (e.g. Tegra186 or Tegra194).
	 */
	if (pc->soc->num_channels == 1) {
		/*
		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
		 * with the maximum possible rate that the controller can
		 * provide. Any further lower value can be derived by setting
		 * PFM bits[0:12].
		 *
		 * required_clk_rate is a reference rate for source clock and
		 * it is derived based on user requested period. By setting the
		 * source clock rate as required_clk_rate, PWM controller will
		 * be able to configure the requested period.
		 */
		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
						     period_ns);

		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
			/*
			 * required_clk_rate is a lower bound for the input
			 * rate; for lower rates there is no value for PWM_SCALE
			 * that yields a period less than or equal to the
			 * requested period. Hence, for lower rates, double the
			 * required_clk_rate to get a clock rate that can meet
			 * the requested period.
			 */
			required_clk_rate *= 2;

		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
		if (err < 0)
			return -EINVAL;

		/* Store the new rate for further references */
		pc->clk_rate = clk_get_rate(pc->clk);
	}

	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
				   (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);

	/*
	 * Since the actual PWM divider is the register's frequency divider
	 * field plus 1, we need to decrement to get the correct value to
	 * write to the register.
	 */
	if (rate > 0)
		rate--;
	else
		return -EINVAL;

	/*
	 * Make sure that the rate will fit in the register's frequency
	 * divider field.
	 */
	if (rate >> PWM_SCALE_WIDTH)
		return -EINVAL;

	val |= rate << PWM_SCALE_SHIFT;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		err = pm_runtime_resume_and_get(pc->dev);
		if (err)
			return err;
	} else
		val |= PWM_ENABLE;

	pwm_writel(pc, pwm->hwpwm, val);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		pm_runtime_put(pc->dev);

	return 0;
}

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int rc = 0;
	u32 val;

	rc = pm_runtime_resume_and_get(pc->dev);
	if (rc)
		return rc;

	val = pwm_readl(pc, pwm->hwpwm);
	val |= PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	return 0;
}

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	u32 val;

	val = pwm_readl(pc, pwm->hwpwm);
	val &= ~PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	pm_runtime_put_sync(pc->dev);
}

static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	int err;
	bool enabled = pwm->state.enabled;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (enabled)
			tegra_pwm_disable(chip, pwm);

		return 0;
	}

	err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!enabled)
		err = tegra_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops tegra_pwm_ops = {
	.apply = tegra_pwm_apply,
};

static int tegra_pwm_probe(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	pc->soc = of_device_get_match_data(&pdev->dev);
	pc->dev = &pdev->dev;

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	platform_set_drvdata(pdev, pc);

	pc->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pc->clk))
		return PTR_ERR(pc->clk);

	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
	if (ret)
		return ret;

	pm_runtime_enable(&pdev->dev);
	ret = pm_runtime_resume_and_get(&pdev->dev);
	if (ret)
		return ret;

	/* Set maximum frequency of the IP */
	ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
		goto put_pm;
	}

	/*
	 * The requested and configured frequency may differ due to
	 * clock register resolutions. Get the configured frequency
	 * so that PWM period can be calculated more accurately.
	 */
	pc->clk_rate = clk_get_rate(pc->clk);

	/* Set minimum limit of PWM period for the IP */
	pc->min_period_ns =
	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;

	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	if (IS_ERR(pc->rst)) {
		ret = PTR_ERR(pc->rst);
		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
		goto put_pm;
	}

	reset_control_deassert(pc->rst);

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &tegra_pwm_ops;
	pc->chip.npwm = pc->soc->num_channels;

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		reset_control_assert(pc->rst);
		goto put_pm;
	}

	pm_runtime_put(&pdev->dev);

	return 0;
put_pm:
	pm_runtime_put_sync_suspend(&pdev->dev);
	pm_runtime_force_suspend(&pdev->dev);
	return ret;
}

static void tegra_pwm_remove(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);

	pwmchip_remove(&pc->chip);

	reset_control_assert(pc->rst);

	pm_runtime_force_suspend(&pdev->dev);
}

static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
{
	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	int err;

	clk_disable_unprepare(pc->clk);

	err = pinctrl_pm_select_sleep_state(dev);
	if (err) {
		clk_prepare_enable(pc->clk);
		return err;
	}

	return 0;
}

static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
{
	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	int err;

	err = pinctrl_pm_select_default_state(dev);
	if (err)
		return err;

	err = clk_prepare_enable(pc->clk);
	if (err) {
		pinctrl_pm_select_sleep_state(dev);
		return err;
	}

	return 0;
}

static const struct tegra_pwm_soc tegra20_pwm_soc = {
	.num_channels = 4,
	.max_frequency = 48000000UL,
};

static const struct tegra_pwm_soc tegra186_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 102000000UL,
};

static const struct tegra_pwm_soc tegra194_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 408000000UL,
};

static const struct of_device_id tegra_pwm_of_match[] = {
	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static const struct dev_pm_ops tegra_pwm_pm_ops = {
	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
			   NULL)
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
};

static struct platform_driver tegra_pwm_driver = {
	.driver = {
		.name = "tegra-pwm",
		.of_match_table = tegra_pwm_of_match,
		.pm = &tegra_pwm_pm_ops,
	},
	.probe = tegra_pwm_probe,
	.remove_new = tegra_pwm_remove,
};

module_platform_driver(tegra_pwm_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sandipan Patra <[email protected]>");
MODULE_DESCRIPTION("Tegra PWM controller driver");
MODULE_ALIAS("platform:tegra-pwm");
Commit	Line	Data
16216333	1	// SPDX-License-Identifier: GPL-2.0-or-later
0134b932 TR	2	/*
	3	* drivers/pwm/pwm-tegra.c
	4	*
	5	* Tegra pulse-width-modulation controller driver
	6	*
1d7796bd	7	* Copyright (c) 2010-2020, NVIDIA Corporation.
0134b932	8	* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]>
1d7796bd SP	9	*
	10	* Overview of Tegra Pulse Width Modulator Register:
	11	* 1. 13-bit: Frequency division (SCALE)
	12	* 2. 8-bit : Pulse division (DUTY)
	13	* 3. 1-bit : Enable bit
	14	*
	15	* The PWM clock frequency is divided by 256 before subdividing it based
	16	* on the programmable frequency division value to generate the required
	17	* frequency for PWM output. The maximum output frequency that can be
	18	* achieved is (max rate of source clock) / 256.
	19	* e.g. if source clock rate is 408 MHz, maximum output frequency can be:
	20	* 408 MHz/256 = 1.6 MHz.
	21	* This 1.6 MHz frequency can further be divided using SCALE value in PWM.
	22	*
	23	* PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
	24	* To achieve 100% duty cycle, program Bit [24] of this register to
	25	* 1’b1. In which case the other bits [23:16] are set to don't care.
	26	*
	27	* Limitations:
	28	* - When PWM is disabled, the output is driven to inactive.
	29	* - It does not allow the current PWM period to complete and
	30	* stops abruptly.
	31	*
	32	* - If the register is reconfigured while PWM is running,
	33	* it does not complete the currently running period.
	34	*
	35	* - If the user input duty is beyond acceptible limits,
	36	* -EINVAL is returned.
0134b932 TR	37	*/
	38
	39	#include <linux/clk.h>
	40	#include <linux/err.h>
	41	#include <linux/io.h>
	42	#include <linux/module.h>
	43	#include <linux/of.h>
3da9b0fe	44	#include <linux/pm_opp.h>
0134b932 TR	45	#include <linux/pwm.h>
0134b932 TR	46	#include <linux/platform_device.h>
4a813b26	47	#include <linux/pinctrl/consumer.h>
3da9b0fe	48	#include <linux/pm_runtime.h>
0134b932	49	#include <linux/slab.h>
5dfbd2bd	50	#include <linux/reset.h>
0134b932	51
3da9b0fe DO	52	#include <soc/tegra/common.h>
3da9b0fe DO	53
0134b932 TR	54	#define PWM_ENABLE (1 << 31)
	55	#define PWM_DUTY_WIDTH 8
	56	#define PWM_DUTY_SHIFT 16
	57	#define PWM_SCALE_WIDTH 13
	58	#define PWM_SCALE_SHIFT 0
	59
e9be88a2 LD	60	struct tegra_pwm_soc {
e9be88a2 LD	61	unsigned int num_channels;
0527eb37 LD	62
	63	/* Maximum IP frequency for given SoCs */
	64	unsigned long max_frequency;
e9be88a2 LD	65	};
e9be88a2 LD	66
0134b932	67	struct tegra_pwm_chip {
e17c0b22 TR	68	struct pwm_chip chip;
e17c0b22 TR	69	struct device *dev;
0134b932	70
e17c0b22	71	struct clk *clk;
5dfbd2bd	72	struct reset_control*rst;
0134b932	73
46fa8bc0	74	unsigned long clk_rate;
1d7796bd	75	unsigned long min_period_ns;
46fa8bc0	76
4f57f5a0	77	void __iomem *regs;
e9be88a2 LD	78
e9be88a2 LD	79	const struct tegra_pwm_soc *soc;
0134b932 TR	80	};
	81
	82	static inline struct tegra_pwm_chip to_tegra_pwm_chip(struct pwm_chip chip)
	83	{
	84	return container_of(chip, struct tegra_pwm_chip, chip);
	85	}
	86
f19460c1	87	static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
0134b932	88	{
f19460c1	89	return readl(pc->regs + (offset << 4));
0134b932 TR	90	}
0134b932 TR	91
f19460c1	92	static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
0134b932	93	{
f19460c1	94	writel(value, pc->regs + (offset << 4));
0134b932 TR	95	}
	96
	97	static int tegra_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	98	int duty_ns, int period_ns)
	99	{
	100	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
8c193f47	101	unsigned long long c = duty_ns;
1d7796bd	102	unsigned long rate, required_clk_rate;
0134b932 TR	103	u32 val = 0;
	104	int err;
	105
	106	/*
	107	* Convert from duty_ns / period_ns to a fixed number of duty ticks
	108	* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	109	* nearest integer during division.
	110	*/
b979ed53	111	c *= (1 << PWM_DUTY_WIDTH);
90241fb9	112	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
0134b932 TR	113
	114	val = (u32)c << PWM_DUTY_SHIFT;
	115
1d7796bd SP	116	/*
	117	* min period = max clock limit >> PWM_DUTY_WIDTH
	118	*/
	119	if (period_ns < pc->min_period_ns)
	120	return -EINVAL;
	121
0134b932 TR	122	/*
	123	* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	124	* cycles at the PWM clock rate will take period_ns nanoseconds.
1d7796bd SP	125	*
	126	* num_channels: If single instance of PWM controller has multiple
	127	* channels (e.g. Tegra210 or older) then it is not possible to
	128	* configure separate clock rates to each of the channels, in such
	129	* case the value stored during probe will be referred.
	130	*
	131	* If every PWM controller instance has one channel respectively, i.e.
	132	* nums_channels == 1 then only the clock rate can be modified
	133	* dynamically (e.g. Tegra186 or Tegra194).
0134b932	134	*/
1d7796bd SP	135	if (pc->soc->num_channels == 1) {
	136	/*
	137	* Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
	138	* with the maximum possible rate that the controller can
	139	* provide. Any further lower value can be derived by setting
	140	* PFM bits[0:12].
	141	*
	142	* required_clk_rate is a reference rate for source clock and
	143	* it is derived based on user requested period. By setting the
	144	* source clock rate as required_clk_rate, PWM controller will
	145	* be able to configure the requested period.
	146	*/
dd1f1da4	147	required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
f2719461	148	period_ns);
1d7796bd	149
5eccd0d9 JH	150	if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
	151	/*
	152	* required_clk_rate is a lower bound for the input
	153	* rate; for lower rates there is no value for PWM_SCALE
	154	* that yields a period less than or equal to the
	155	* requested period. Hence, for lower rates, double the
	156	* required_clk_rate to get a clock rate that can meet
	157	* the requested period.
	158	*/
	159	required_clk_rate *= 2;
	160
3da9b0fe	161	err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
1d7796bd SP	162	if (err < 0)
	163	return -EINVAL;
	164
	165	/* Store the new rate for further references */
	166	pc->clk_rate = clk_get_rate(pc->clk);
	167	}
	168
250b76f4	169	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
8c193f47 UKK	170	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
8c193f47 UKK	171	(u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);
0134b932 TR	172
	173	/*
	174	* Since the actual PWM divider is the register's frequency divider
1d7796bd	175	* field plus 1, we need to decrement to get the correct value to
0134b932 TR	176	* write to the register.
	177	*/
	178	if (rate > 0)
	179	rate--;
8c193f47 UKK	180	else
8c193f47 UKK	181	return -EINVAL;
0134b932 TR	182
	183	/*
	184	* Make sure that the rate will fit in the register's frequency
	185	* divider field.
	186	*/
	187	if (rate >> PWM_SCALE_WIDTH)
	188	return -EINVAL;
	189
	190	val \|= rate << PWM_SCALE_SHIFT;
	191
	192	/*
	193	* If the PWM channel is disabled, make sure to turn on the clock
	194	* before writing the register. Otherwise, keep it enabled.
	195	*/
5c31252c	196	if (!pwm_is_enabled(pwm)) {
3da9b0fe DO	197	err = pm_runtime_resume_and_get(pc->dev);
3da9b0fe DO	198	if (err)
0134b932 TR	199	return err;
	200	} else
	201	val \|= PWM_ENABLE;
	202
	203	pwm_writel(pc, pwm->hwpwm, val);
	204
	205	/*
	206	* If the PWM is not enabled, turn the clock off again to save power.
	207	*/
5c31252c	208	if (!pwm_is_enabled(pwm))
3da9b0fe	209	pm_runtime_put(pc->dev);
0134b932 TR	210
	211	return 0;
	212	}
	213
	214	static int tegra_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	215	{
	216	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	217	int rc = 0;
	218	u32 val;
	219
3da9b0fe DO	220	rc = pm_runtime_resume_and_get(pc->dev);
3da9b0fe DO	221	if (rc)
0134b932 TR	222	return rc;
	223
	224	val = pwm_readl(pc, pwm->hwpwm);
	225	val \|= PWM_ENABLE;
	226	pwm_writel(pc, pwm->hwpwm, val);
	227
	228	return 0;
	229	}
	230
	231	static void tegra_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	232	{
	233	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	234	u32 val;
	235
	236	val = pwm_readl(pc, pwm->hwpwm);
	237	val &= ~PWM_ENABLE;
	238	pwm_writel(pc, pwm->hwpwm, val);
	239
3da9b0fe	240	pm_runtime_put_sync(pc->dev);
0134b932 TR	241	}
0134b932 TR	242
fd3ddd43 UKK	243	static int tegra_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	244	const struct pwm_state *state)
	245	{
	246	int err;
	247	bool enabled = pwm->state.enabled;
	248
	249	if (state->polarity != PWM_POLARITY_NORMAL)
	250	return -EINVAL;
	251
	252	if (!state->enabled) {
	253	if (enabled)
	254	tegra_pwm_disable(chip, pwm);
	255
	256	return 0;
	257	}
	258
	259	err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
	260	if (err)
	261	return err;
	262
	263	if (!enabled)
	264	err = tegra_pwm_enable(chip, pwm);
	265
	266	return err;
	267	}
	268
0134b932	269	static const struct pwm_ops tegra_pwm_ops = {
fd3ddd43	270	.apply = tegra_pwm_apply,
0134b932 TR	271	};
	272
	273	static int tegra_pwm_probe(struct platform_device *pdev)
	274	{
f19460c1	275	struct tegra_pwm_chip *pc;
0134b932 TR	276	int ret;
0134b932 TR	277
f19460c1 UKK	278	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
f19460c1 UKK	279	if (!pc)
0134b932	280	return -ENOMEM;
0134b932	281
f19460c1 UKK	282	pc->soc = of_device_get_match_data(&pdev->dev);
f19460c1 UKK	283	pc->dev = &pdev->dev;
0134b932	284
f19460c1 UKK	285	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	286	if (IS_ERR(pc->regs))
	287	return PTR_ERR(pc->regs);
0134b932	288
f19460c1	289	platform_set_drvdata(pdev, pc);
0134b932	290
f19460c1 UKK	291	pc->clk = devm_clk_get(&pdev->dev, NULL);
	292	if (IS_ERR(pc->clk))
	293	return PTR_ERR(pc->clk);
0134b932	294
3da9b0fe DO	295	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
	296	if (ret)
	297	return ret;
	298
	299	pm_runtime_enable(&pdev->dev);
	300	ret = pm_runtime_resume_and_get(&pdev->dev);
	301	if (ret)
	302	return ret;
	303
0527eb37	304	/* Set maximum frequency of the IP */
f19460c1	305	ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);
0527eb37 LD	306	if (ret < 0) {
0527eb37 LD	307	dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
3da9b0fe	308	goto put_pm;
0527eb37 LD	309	}
	310
	311	/*
	312	* The requested and configured frequency may differ due to
	313	* clock register resolutions. Get the configured frequency
	314	* so that PWM period can be calculated more accurately.
	315	*/
f19460c1	316	pc->clk_rate = clk_get_rate(pc->clk);
46fa8bc0	317
1d7796bd	318	/* Set minimum limit of PWM period for the IP */
f19460c1 UKK	319	pc->min_period_ns =
f19460c1 UKK	320	(NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
1d7796bd	321
f19460c1 UKK	322	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	323	if (IS_ERR(pc->rst)) {
	324	ret = PTR_ERR(pc->rst);
5dfbd2bd	325	dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
3da9b0fe	326	goto put_pm;
5dfbd2bd RS	327	}
5dfbd2bd RS	328
f19460c1	329	reset_control_deassert(pc->rst);
5dfbd2bd	330
f19460c1 UKK	331	pc->chip.dev = &pdev->dev;
	332	pc->chip.ops = &tegra_pwm_ops;
	333	pc->chip.npwm = pc->soc->num_channels;
0134b932	334
f19460c1	335	ret = pwmchip_add(&pc->chip);
0134b932 TR	336	if (ret < 0) {
0134b932 TR	337	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
f19460c1	338	reset_control_assert(pc->rst);
3da9b0fe	339	goto put_pm;
0134b932 TR	340	}
0134b932 TR	341
3da9b0fe DO	342	pm_runtime_put(&pdev->dev);
3da9b0fe DO	343
0134b932	344	return 0;
3da9b0fe DO	345	put_pm:
	346	pm_runtime_put_sync_suspend(&pdev->dev);
	347	pm_runtime_force_suspend(&pdev->dev);
	348	return ret;
0134b932 TR	349	}
0134b932 TR	350
e39cb6f9	351	static void tegra_pwm_remove(struct platform_device *pdev)
0134b932 TR	352	{
0134b932 TR	353	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
5dfbd2bd	354
2f1a3bd4 UKK	355	pwmchip_remove(&pc->chip);
2f1a3bd4 UKK	356
5dfbd2bd	357	reset_control_assert(pc->rst);
5dfbd2bd	358
3da9b0fe	359	pm_runtime_force_suspend(&pdev->dev);
0134b932 TR	360	}
0134b932 TR	361
3da9b0fe	362	static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
4a813b26	363	{
3da9b0fe DO	364	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	365	int err;
	366
	367	clk_disable_unprepare(pc->clk);
	368
	369	err = pinctrl_pm_select_sleep_state(dev);
	370	if (err) {
	371	clk_prepare_enable(pc->clk);
	372	return err;
	373	}
	374
	375	return 0;
4a813b26 LD	376	}
4a813b26 LD	377
3da9b0fe	378	static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
4a813b26	379	{
3da9b0fe DO	380	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	381	int err;
	382
	383	err = pinctrl_pm_select_default_state(dev);
	384	if (err)
	385	return err;
	386
	387	err = clk_prepare_enable(pc->clk);
	388	if (err) {
	389	pinctrl_pm_select_sleep_state(dev);
	390	return err;
	391	}
	392
	393	return 0;
4a813b26	394	}
4a813b26	395
e9be88a2 LD	396	static const struct tegra_pwm_soc tegra20_pwm_soc = {
e9be88a2 LD	397	.num_channels = 4,
0527eb37	398	.max_frequency = 48000000UL,
e9be88a2 LD	399	};
	400
	401	static const struct tegra_pwm_soc tegra186_pwm_soc = {
	402	.num_channels = 1,
0527eb37	403	.max_frequency = 102000000UL,
e9be88a2 LD	404	};
e9be88a2 LD	405
2d0c08fc SP	406	static const struct tegra_pwm_soc tegra194_pwm_soc = {
	407	.num_channels = 1,
	408	.max_frequency = 408000000UL,
	409	};
	410
f1a8870a	411	static const struct of_device_id tegra_pwm_of_match[] = {
e9be88a2 LD	412	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
e9be88a2 LD	413	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
2d0c08fc	414	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
140fd977 TR	415	{ }
140fd977 TR	416	};
140fd977	417	MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
140fd977	418
4a813b26	419	static const struct dev_pm_ops tegra_pwm_pm_ops = {
3da9b0fe DO	420	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
	421	NULL)
	422	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	423	pm_runtime_force_resume)
4a813b26 LD	424	};
4a813b26 LD	425
0134b932 TR	426	static struct platform_driver tegra_pwm_driver = {
	427	.driver = {
	428	.name = "tegra-pwm",
838bf09d	429	.of_match_table = tegra_pwm_of_match,
4a813b26	430	.pm = &tegra_pwm_pm_ops,
0134b932 TR	431	},
0134b932 TR	432	.probe = tegra_pwm_probe,
e39cb6f9	433	.remove_new = tegra_pwm_remove,
0134b932 TR	434	};
	435
	436	module_platform_driver(tegra_pwm_driver);
	437
	438	MODULE_LICENSE("GPL");
1d7796bd SP	439	MODULE_AUTHOR("Sandipan Patra <[email protected]>");
1d7796bd SP	440	MODULE_DESCRIPTION("Tegra PWM controller driver");
0134b932	441	MODULE_ALIAS("platform:tegra-pwm");