[linux.git] / drivers / pwm / pwm-crc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Intel Corporation. All rights reserved.
 *
 * Author: Shobhit Kumar <[email protected]>
 */

#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/pwm.h>

#define PWM0_CLK_DIV		0x4B
#define  PWM_OUTPUT_ENABLE	BIT(7)
#define  PWM_DIV_CLK_0		0x00 /* DIVIDECLK = BASECLK */
#define  PWM_DIV_CLK_100	0x63 /* DIVIDECLK = BASECLK/100 */
#define  PWM_DIV_CLK_128	0x7F /* DIVIDECLK = BASECLK/128 */

#define PWM0_DUTY_CYCLE		0x4E
#define BACKLIGHT_EN		0x51

#define PWM_MAX_LEVEL		0xFF

#define PWM_BASE_CLK_MHZ	6	/* 6 MHz */
#define PWM_MAX_PERIOD_NS	5461334	/* 183 Hz */

/**
 * struct crystalcove_pwm - Crystal Cove PWM controller
 * @chip: the abstract pwm_chip structure.
 * @regmap: the regmap from the parent device.
 */
struct crystalcove_pwm {
	struct pwm_chip chip;
	struct regmap *regmap;
};

static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct crystalcove_pwm, chip);
}

static int crc_pwm_calc_clk_div(int period_ns)
{
	int clk_div;

	clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
	/* clk_div 1 - 128, maps to register values 0-127 */
	if (clk_div > 0)
		clk_div--;

	return clk_div;
}

static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
	struct device *dev = crc_pwm->chip.dev;
	int err;

	if (state->period > PWM_MAX_PERIOD_NS) {
		dev_err(dev, "un-supported period_ns\n");
		return -EINVAL;
	}

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (pwm_is_enabled(pwm) && !state->enabled) {
		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
		if (err) {
			dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
			return err;
		}
	}

	if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||
	    pwm_get_period(pwm) != state->period) {
		u64 level = state->duty_cycle * PWM_MAX_LEVEL;

		do_div(level, state->period);

		err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
		if (err) {
			dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
			return err;
		}
	}

	if (pwm_is_enabled(pwm) && state->enabled &&
	    pwm_get_period(pwm) != state->period) {
		/* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
		if (err) {
			dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
			return err;
		}
	}

	if (pwm_get_period(pwm) != state->period ||
	    pwm_is_enabled(pwm) != state->enabled) {
		int clk_div = crc_pwm_calc_clk_div(state->period);
		int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;

		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
				   clk_div | pwm_output_enable);
		if (err) {
			dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
			return err;
		}
	}

	if (!pwm_is_enabled(pwm) && state->enabled) {
		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
		if (err) {
			dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
			return err;
		}
	}

	return 0;
}

static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
			     struct pwm_state *state)
{
	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
	struct device *dev = crc_pwm->chip.dev;
	unsigned int clk_div, clk_div_reg, duty_cycle_reg;
	int error;

	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
	if (error) {
		dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
		return error;
	}

	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
	if (error) {
		dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
		return error;
	}

	clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;

	state->period =
		DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
	state->duty_cycle =
		DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
	state->polarity = PWM_POLARITY_NORMAL;
	state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);

	return 0;
}

static const struct pwm_ops crc_pwm_ops = {
	.apply = crc_pwm_apply,
	.get_state = crc_pwm_get_state,
};

static int crystalcove_pwm_probe(struct platform_device *pdev)
{
	struct crystalcove_pwm *pwm;
	struct device *dev = pdev->dev.parent;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &crc_pwm_ops;
	pwm->chip.npwm = 1;

	/* get the PMIC regmap */
	pwm->regmap = pmic->regmap;

	return devm_pwmchip_add(&pdev->dev, &pwm->chip);
}

static struct platform_driver crystalcove_pwm_driver = {
	.probe = crystalcove_pwm_probe,
	.driver = {
		.name = "crystal_cove_pwm",
	},
};
module_platform_driver(crystalcove_pwm_driver);

MODULE_ALIAS("platform:crystal_cove_pwm");
MODULE_DESCRIPTION("Intel Crystalcove (CRC) PWM support");
MODULE_LICENSE("GPL");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
a3f37a10 SK	2	/*
	3	* Copyright (C) 2015 Intel Corporation. All rights reserved.
	4	*
a3f37a10 SK	5	* Author: Shobhit Kumar <[email protected]>
	6	*/
	7
	8	#include <linux/platform_device.h>
	9	#include <linux/regmap.h>
	10	#include <linux/mfd/intel_soc_pmic.h>
	11	#include <linux/pwm.h>
	12
	13	#define PWM0_CLK_DIV 0x4B
	14	#define PWM_OUTPUT_ENABLE BIT(7)
	15	#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
	16	#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
	17	#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
	18
	19	#define PWM0_DUTY_CYCLE 0x4E
	20	#define BACKLIGHT_EN 0x51
	21
	22	#define PWM_MAX_LEVEL 0xFF
	23
79e08992	24	#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */
a05af71f	25	#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */
a3f37a10 SK	26
	27	/**
	28	* struct crystalcove_pwm - Crystal Cove PWM controller
	29	* @chip: the abstract pwm_chip structure.
	30	* @regmap: the regmap from the parent device.
	31	*/
	32	struct crystalcove_pwm {
	33	struct pwm_chip chip;
	34	struct regmap *regmap;
	35	};
	36
92f2de28	37	static inline struct crystalcove_pwm to_crc_pwm(struct pwm_chip chip)
a3f37a10	38	{
92f2de28	39	return container_of(chip, struct crystalcove_pwm, chip);
a3f37a10 SK	40	}
a3f37a10 SK	41
a05af71f HG	42	static int crc_pwm_calc_clk_div(int period_ns)
	43	{
	44	int clk_div;
	45
	46	clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
	47	/* clk_div 1 - 128, maps to register values 0-127 */
	48	if (clk_div > 0)
	49	clk_div--;
	50
	51	return clk_div;
	52	}
	53
9fccec82 HG	54	static int crc_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
9fccec82 HG	55	const struct pwm_state *state)
a3f37a10	56	{
9fccec82 HG	57	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
	58	struct device *dev = crc_pwm->chip.dev;
	59	int err;
a3f37a10	60
9fccec82 HG	61	if (state->period > PWM_MAX_PERIOD_NS) {
	62	dev_err(dev, "un-supported period_ns\n");
	63	return -EINVAL;
	64	}
a3f37a10	65
9fccec82	66	if (state->polarity != PWM_POLARITY_NORMAL)
2b1c1a5d	67	return -EINVAL;
a3f37a10	68
9fccec82 HG	69	if (pwm_is_enabled(pwm) && !state->enabled) {
	70	err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
	71	if (err) {
	72	dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
	73	return err;
	74	}
	75	}
a3f37a10	76
9fccec82 HG	77	if (pwm_get_duty_cycle(pwm) != state->duty_cycle \|\|
	78	pwm_get_period(pwm) != state->period) {
	79	u64 level = state->duty_cycle * PWM_MAX_LEVEL;
a3f37a10	80
9fccec82	81	do_div(level, state->period);
a3f37a10	82
9fccec82 HG	83	err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
	84	if (err) {
	85	dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
	86	return err;
	87	}
a3f37a10 SK	88	}
a3f37a10 SK	89
9fccec82 HG	90	if (pwm_is_enabled(pwm) && state->enabled &&
9fccec82 HG	91	pwm_get_period(pwm) != state->period) {
6158231a	92	/* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
9fccec82 HG	93	err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
	94	if (err) {
	95	dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
	96	return err;
	97	}
	98	}
a3f37a10	99
9fccec82 HG	100	if (pwm_get_period(pwm) != state->period \|\|
	101	pwm_is_enabled(pwm) != state->enabled) {
	102	int clk_div = crc_pwm_calc_clk_div(state->period);
	103	int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;
	104
	105	err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
	106	clk_div \| pwm_output_enable);
	107	if (err) {
	108	dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
	109	return err;
	110	}
a3f37a10 SK	111	}
a3f37a10 SK	112
9fccec82 HG	113	if (!pwm_is_enabled(pwm) && state->enabled) {
	114	err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
	115	if (err) {
	116	dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
	117	return err;
	118	}
	119	}
a3f37a10 SK	120
	121	return 0;
	122	}
	123
6c452cff UKK	124	static int crc_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
6c452cff UKK	125	struct pwm_state *state)
c86b155d HG	126	{
	127	struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
	128	struct device *dev = crc_pwm->chip.dev;
	129	unsigned int clk_div, clk_div_reg, duty_cycle_reg;
	130	int error;
	131
	132	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
	133	if (error) {
	134	dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
9c9d5e99	135	return error;
c86b155d HG	136	}
	137
	138	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
	139	if (error) {
	140	dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
9c9d5e99	141	return error;
c86b155d HG	142	}
	143
	144	clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
	145
	146	state->period =
	147	DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
	148	state->duty_cycle =
	149	DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
	150	state->polarity = PWM_POLARITY_NORMAL;
	151	state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
6c452cff UKK	152
6c452cff UKK	153	return 0;
c86b155d HG	154	}
c86b155d HG	155
a3f37a10	156	static const struct pwm_ops crc_pwm_ops = {
9fccec82	157	.apply = crc_pwm_apply,
c86b155d	158	.get_state = crc_pwm_get_state,
a3f37a10 SK	159	};
	160
	161	static int crystalcove_pwm_probe(struct platform_device *pdev)
	162	{
	163	struct crystalcove_pwm *pwm;
	164	struct device *dev = pdev->dev.parent;
	165	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	166
	167	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	168	if (!pwm)
	169	return -ENOMEM;
	170
	171	pwm->chip.dev = &pdev->dev;
	172	pwm->chip.ops = &crc_pwm_ops;
a3f37a10 SK	173	pwm->chip.npwm = 1;
	174
	175	/* get the PMIC regmap */
	176	pwm->regmap = pmic->regmap;
	177
66a03c4f	178	return devm_pwmchip_add(&pdev->dev, &pwm->chip);
a3f37a10 SK	179	}
	180
	181	static struct platform_driver crystalcove_pwm_driver = {
	182	.probe = crystalcove_pwm_probe,
a3f37a10 SK	183	.driver = {
	184	.name = "crystal_cove_pwm",
	185	},
	186	};
91a69d38	187	module_platform_driver(crystalcove_pwm_driver);
a3f37a10	188
91a69d38 UKK	189	MODULE_ALIAS("platform:crystal_cove_pwm");
	190	MODULE_DESCRIPTION("Intel Crystalcove (CRC) PWM support");
	191	MODULE_LICENSE("GPL");