[linux.git] / drivers / ata / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <[email protected]> and
 *		   Jeff Garzik <[email protected]>
 *  		    Please ALWAYS copy [email protected]
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <[email protected]>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi.h>
#include <linux/libata.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif /* CONFIG_PPC_OF */

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"2.3"

enum {
	/* ap->flags bits */
	K2_FLAG_SATA_8_PORTS		= (1 << 24),
	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
	K2_FLAG_BAR_POS_3			= (1 << 26),

	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,

	chip_svw4			= 0,
	chip_svw8			= 1,
	chip_svw42			= 2,	/* bar 3 */
	chip_svw43			= 3,	/* bar 5 */
};

static u8 k2_stat_check_status(struct ata_port *ap);


static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 cmnd = qc->scsicmd->cmnd[0];

	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
		return -1;	/* ATAPI DMA not supported */
	else {
		switch (cmnd) {
		case READ_10:
		case READ_12:
		case READ_16:
		case WRITE_10:
		case WRITE_12:
		case WRITE_16:
			return 0;

		default:
			return -1;
		}

	}
}

static int k2_sata_scr_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int k2_sata_scr_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}

static int k2_sata_softreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return ata_sff_softreset(link, class, deadline);
}

static int k2_sata_hardreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return sata_sff_hardreset(link, class, deadline);
}

static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* This works around possible data corruption.

	   On certain SATA controllers that can be seen when the r/w
	   command is given to the controller before the host DMA is
	   started.

	   On a Read command, the controller would initiate the
	   command to the drive even before it sees the DMA
	   start. When there are very fast drives connected to the
	   controller, or when the data request hits in the drive
	   cache, there is the possibility that the drive returns a
	   part or all of the requested data to the controller before
	   the DMA start is issued.  In this case, the controller
	   would become confused as to what to do with the data.  In
	   the worst case when all the data is returned back to the
	   controller, the controller could hang. In other cases it
	   could return partial data returning in data
	   corruption. This problem has been seen in PPC systems and
	   can also appear on an system with very fast disks, where
	   the SATA controller is sitting behind a number of bridges,
	   and hence there is significant latency between the r/w
	   command and the start command. */
	/* issue r/w command if the access is to ATA */
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
	return readl(ap->ioaddr.status_addr);
}

#ifdef CONFIG_PPC_OF
static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
	struct ata_port *ap;
	struct device_node *np;
	int index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		const u32 *reg = of_get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg) {
			seq_printf(m, "devspec: %s\n", np->full_name);
			break;
		}
	}
	return 0;
}
#endif /* CONFIG_PPC_OF */


static struct scsi_host_template k2_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
#ifdef CONFIG_PPC_OF
	.show_info		= k2_sata_show_info,
#endif
};


static struct ata_port_operations k2_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.softreset              = k2_sata_softreset,
	.hardreset              = k2_sata_hardreset,
	.sff_tf_load		= k2_sata_tf_load,
	.sff_tf_read		= k2_sata_tf_read,
	.sff_check_status	= k2_stat_check_status,
	.check_atapi_dma	= k2_sata_check_atapi_dma,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
};

static const struct ata_port_info k2_port_info[] = {
	/* chip_svw4 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw8 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
				  K2_FLAG_SATA_8_PORTS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw42 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw43 */
	{
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
};

static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct ata_port_info *ppi[] =
		{ &k2_port_info[ent->driver_data], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int n_ports, i, rc, bar_pos;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	n_ports = 4;
	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
		n_ports = 8;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host)
		return -ENOMEM;

	bar_pos = 5;
	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
		bar_pos = 3;
	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, bar_pos) == 0) {
		/* In IDE mode we need to pin the device to ensure that
			pcim_release does not clear the busmaster bit in config
			space, clearing causes busmaster DMA to fail on
			ports 3 & 4 */
		pcim_pin_device(pdev);
		return -ENODEV;
	}

	/* Request and iomap PCI regions */
	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[bar_pos];

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = i * K2_SATA_PORT_OFFSET;

		k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, 5, -1, "mmio");
		ata_port_pbar_desc(ap, 5, offset, "port");
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &k2_sata_sht);
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },

	{ }
};

static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(k2_sata_pci_driver);

MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <[email protected]> and
	5	* Jeff Garzik <[email protected]>
	6	* Please ALWAYS copy [email protected]
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <[email protected]>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
1da177e4 LT	39	#include <linux/kernel.h>
	40	#include <linux/module.h>
	41	#include <linux/pci.h>
	42	#include <linux/init.h>
	43	#include <linux/blkdev.h>
	44	#include <linux/delay.h>
	45	#include <linux/interrupt.h>
a9524a76	46	#include <linux/device.h>
1da177e4	47	#include <scsi/scsi_host.h>
931506d3 AS	48	#include <scsi/scsi_cmnd.h>
931506d3 AS	49	#include <scsi/scsi.h>
1da177e4 LT	50	#include <linux/libata.h>
	51
	52	#ifdef CONFIG_PPC_OF
	53	#include <asm/prom.h>
	54	#include <asm/pci-bridge.h>
	55	#endif /* CONFIG_PPC_OF */
	56
	57	#define DRV_NAME "sata_svw"
2a3103ce	58	#define DRV_VERSION "2.3"
1da177e4	59
55cca65e	60	enum {
4447d351 TH	61	/* ap->flags bits */
	62	K2_FLAG_SATA_8_PORTS = (1 << 24),
	63	K2_FLAG_NO_ATAPI_DMA = (1 << 25),
931506d3	64	K2_FLAG_BAR_POS_3 = (1 << 26),
c10340ac	65
55cca65e JG	66	/* Taskfile registers offsets */
	67	K2_SATA_TF_CMD_OFFSET = 0x00,
	68	K2_SATA_TF_DATA_OFFSET = 0x00,
	69	K2_SATA_TF_ERROR_OFFSET = 0x04,
	70	K2_SATA_TF_NSECT_OFFSET = 0x08,
	71	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	72	K2_SATA_TF_LBAM_OFFSET = 0x10,
	73	K2_SATA_TF_LBAH_OFFSET = 0x14,
	74	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	75	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	76	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	77
55cca65e JG	78	/* DMA base */
55cca65e JG	79	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	80
55cca65e JG	81	/* SCRs base */
	82	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	83	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	84	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	85
55cca65e JG	86	/* Others */
	87	K2_SATA_SICR1_OFFSET = 0x80,
	88	K2_SATA_SICR2_OFFSET = 0x84,
	89	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	90
55cca65e JG	91	/* Port stride */
55cca65e JG	92	K2_SATA_PORT_OFFSET = 0x100,
c10340ac	93
931506d3 AS	94	chip_svw4 = 0,
	95	chip_svw8 = 1,
	96	chip_svw42 = 2, /* bar 3 */
	97	chip_svw43 = 3, /* bar 5 */
c10340ac JG	98	};
c10340ac JG	99
ac19bff2 JG	100	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	101
1da177e4	102
c10340ac JG	103	static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
c10340ac JG	104	{
931506d3 AS	105	u8 cmnd = qc->scsicmd->cmnd[0];
931506d3 AS	106
c10340ac JG	107	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
c10340ac JG	108	return -1; /* ATAPI DMA not supported */
931506d3 AS	109	else {
	110	switch (cmnd) {
	111	case READ_10:
	112	case READ_12:
	113	case READ_16:
	114	case WRITE_10:
	115	case WRITE_12:
	116	case WRITE_16:
	117	return 0;
	118
	119	default:
	120	return -1;
	121	}
c10340ac	122
931506d3	123	}
c10340ac JG	124	}
c10340ac JG	125
82ef04fb TH	126	static int k2_sata_scr_read(struct ata_link *link,
82ef04fb TH	127	unsigned int sc_reg, u32 *val)
1da177e4 LT	128	{
1da177e4 LT	129	if (sc_reg > SCR_CONTROL)
da3dbb17	130	return -EINVAL;
82ef04fb	131	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	132	return 0;
1da177e4 LT	133	}
	134
	135
82ef04fb TH	136	static int k2_sata_scr_write(struct ata_link *link,
82ef04fb TH	137	unsigned int sc_reg, u32 val)
1da177e4 LT	138	{
1da177e4 LT	139	if (sc_reg > SCR_CONTROL)
da3dbb17	140	return -EINVAL;
82ef04fb	141	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	142	return 0;
1da177e4 LT	143	}
1da177e4 LT	144
b03e66a6 DM	145	static int k2_sata_softreset(struct ata_link *link,
	146	unsigned int *class, unsigned long deadline)
	147	{
	148	u8 dmactl;
	149	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	150
	151	dmactl = readb(mmio + ATA_DMA_CMD);
	152
	153	/* Clear the start bit */
	154	if (dmactl & ATA_DMA_START) {
	155	dmactl &= ~ATA_DMA_START;
	156	writeb(dmactl, mmio + ATA_DMA_CMD);
	157	}
	158
	159	return ata_sff_softreset(link, class, deadline);
	160	}
	161
	162	static int k2_sata_hardreset(struct ata_link *link,
	163	unsigned int *class, unsigned long deadline)
	164	{
	165	u8 dmactl;
	166	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	167
	168	dmactl = readb(mmio + ATA_DMA_CMD);
	169
	170	/* Clear the start bit */
	171	if (dmactl & ATA_DMA_START) {
	172	dmactl &= ~ATA_DMA_START;
	173	writeb(dmactl, mmio + ATA_DMA_CMD);
	174	}
	175
	176	return sata_sff_hardreset(link, class, deadline);
	177	}
1da177e4	178
057ace5e	179	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	180	{
	181	struct ata_ioports *ioaddr = &ap->ioaddr;
	182	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	183
	184	if (tf->ctl != ap->last_ctl) {
0d5ff566	185	writeb(tf->ctl, ioaddr->ctl_addr);
1da177e4 LT	186	ap->last_ctl = tf->ctl;
	187	ata_wait_idle(ap);
	188	}
	189	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	190	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	191	ioaddr->feature_addr);
850a9d8a	192	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	193	ioaddr->nsect_addr);
850a9d8a	194	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	195	ioaddr->lbal_addr);
850a9d8a	196	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	197	ioaddr->lbam_addr);
850a9d8a	198	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	199	ioaddr->lbah_addr);
1da177e4	200	} else if (is_addr) {
0d5ff566 TH	201	writew(tf->feature, ioaddr->feature_addr);
	202	writew(tf->nsect, ioaddr->nsect_addr);
	203	writew(tf->lbal, ioaddr->lbal_addr);
	204	writew(tf->lbam, ioaddr->lbam_addr);
	205	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	206	}
	207
	208	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	209	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	210
	211	ata_wait_idle(ap);
	212	}
	213
	214
	215	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	216	{
	217	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	218	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	219
ac19bff2	220	tf->command = k2_stat_check_status(ap);
0d5ff566 TH	221	tf->device = readw(ioaddr->device_addr);
	222	feature = readw(ioaddr->error_addr);
	223	nsect = readw(ioaddr->nsect_addr);
	224	lbal = readw(ioaddr->lbal_addr);
	225	lbam = readw(ioaddr->lbam_addr);
	226	lbah = readw(ioaddr->lbah_addr);
ac19bff2 JG	227
	228	tf->feature = feature;
	229	tf->nsect = nsect;
	230	tf->lbal = lbal;
	231	tf->lbam = lbam;
	232	tf->lbah = lbah;
1da177e4 LT	233
1da177e4 LT	234	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	235	tf->hob_feature = feature >> 8;
1da177e4 LT	236	tf->hob_nsect = nsect >> 8;
	237	tf->hob_lbal = lbal >> 8;
	238	tf->hob_lbam = lbam >> 8;
	239	tf->hob_lbah = lbah >> 8;
5796d1c4	240	}
1da177e4 LT	241	}
	242
	243	/**
	244	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	245	* @qc: Info associated with this ATA transaction.
	246	*
	247	* LOCKING:
cca3974e	248	* spin_lock_irqsave(host lock)
1da177e4 LT	249	*/
1da177e4 LT	250
5796d1c4	251	static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	252	{
	253	struct ata_port *ap = qc->ap;
	254	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	255	u8 dmactl;
59f99880 JG	256	void __iomem *mmio = ap->ioaddr.bmdma_addr;
59f99880 JG	257
1da177e4 LT	258	/* load PRD table addr. */
1da177e4 LT	259	mb(); /* make sure PRD table writes are visible to controller */
f60d7011	260	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
1da177e4 LT	261
	262	/* specify data direction, triple-check start bit is clear */
	263	dmactl = readb(mmio + ATA_DMA_CMD);
	264	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	265	if (!rw)
	266	dmactl \|= ATA_DMA_WR;
	267	writeb(dmactl, mmio + ATA_DMA_CMD);
	268
	269	/* issue r/w command if this is not a ATA DMA command*/
	270	if (qc->tf.protocol != ATA_PROT_DMA)
5682ed33	271	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	272	}
	273
	274	/**
	275	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	276	* @qc: Info associated with this ATA transaction.
	277	*
	278	* LOCKING:
cca3974e	279	* spin_lock_irqsave(host lock)
1da177e4 LT	280	*/
1da177e4 LT	281
5796d1c4	282	static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	283	{
1da177e4 LT	284	struct ata_port *ap = qc->ap;
59f99880	285	void __iomem *mmio = ap->ioaddr.bmdma_addr;
1da177e4 LT	286	u8 dmactl;
	287
	288	/* start host DMA transaction */
	289	dmactl = readb(mmio + ATA_DMA_CMD);
	290	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
ec6add99 PM	291	/* This works around possible data corruption.
	292
	293	On certain SATA controllers that can be seen when the r/w
	294	command is given to the controller before the host DMA is
	295	started.
	296
	297	On a Read command, the controller would initiate the
	298	command to the drive even before it sees the DMA
	299	start. When there are very fast drives connected to the
	300	controller, or when the data request hits in the drive
	301	cache, there is the possibility that the drive returns a
	302	part or all of the requested data to the controller before
	303	the DMA start is issued. In this case, the controller
	304	would become confused as to what to do with the data. In
	305	the worst case when all the data is returned back to the
	306	controller, the controller could hang. In other cases it
	307	could return partial data returning in data
	308	corruption. This problem has been seen in PPC systems and
	309	can also appear on an system with very fast disks, where
	310	the SATA controller is sitting behind a number of bridges,
	311	and hence there is significant latency between the r/w
	312	command and the start command. */
	313	/* issue r/w command if the access is to ATA */
1da177e4	314	if (qc->tf.protocol == ATA_PROT_DMA)
5682ed33	315	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	316	}
1da177e4 LT	317
8a60a071	318
1da177e4 LT	319	static u8 k2_stat_check_status(struct ata_port *ap)
1da177e4 LT	320	{
5796d1c4	321	return readl(ap->ioaddr.status_addr);
1da177e4 LT	322	}
	323
	324	#ifdef CONFIG_PPC_OF
3f025677	325	static int k2_sata_show_info(struct seq_file m, struct Scsi_Host shost)
1da177e4 LT	326	{
	327	struct ata_port *ap;
	328	struct device_node *np;
3f025677	329	int index;
1da177e4 LT	330
1da177e4 LT	331	/* Find the ata_port */
35bb94b1	332	ap = ata_shost_to_port(shost);
1da177e4 LT	333	if (ap == NULL)
	334	return 0;
	335
	336	/* Find the OF node for the PCI device proper */
cca3974e	337	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
1da177e4 LT	338	if (np == NULL)
	339	return 0;
	340
	341	/* Match it to a port node */
cca3974e	342	index = (ap == ap->host->ports[0]) ? 0 : 1;
1da177e4	343	for (np = np->child; np != NULL; np = np->sibling) {
40cd3a45	344	const u32 *reg = of_get_property(np, "reg", NULL);
1da177e4 LT	345	if (!reg)
1da177e4 LT	346	continue;
3f025677 AV	347	if (index == *reg) {
3f025677 AV	348	seq_printf(m, "devspec: %s\n", np->full_name);
1da177e4	349	break;
3f025677	350	}
1da177e4	351	}
3f025677	352	return 0;
1da177e4 LT	353	}
	354	#endif /* CONFIG_PPC_OF */
	355
	356
193515d5	357	static struct scsi_host_template k2_sata_sht = {
68d1d07b	358	ATA_BMDMA_SHT(DRV_NAME),
1da177e4	359	#ifdef CONFIG_PPC_OF
3f025677	360	.show_info = k2_sata_show_info,
1da177e4	361	#endif
1da177e4 LT	362	};
	363
	364
029cfd6b TH	365	static struct ata_port_operations k2_sata_ops = {
029cfd6b TH	366	.inherits = &ata_bmdma_port_ops,
b03e66a6 DM	367	.softreset = k2_sata_softreset,
b03e66a6 DM	368	.hardreset = k2_sata_hardreset,
5682ed33 TH	369	.sff_tf_load = k2_sata_tf_load,
	370	.sff_tf_read = k2_sata_tf_read,
	371	.sff_check_status = k2_stat_check_status,
c10340ac	372	.check_atapi_dma = k2_sata_check_atapi_dma,
1da177e4 LT	373	.bmdma_setup = k2_bmdma_setup_mmio,
1da177e4 LT	374	.bmdma_start = k2_bmdma_start_mmio,
1da177e4 LT	375	.scr_read = k2_sata_scr_read,
1da177e4 LT	376	.scr_write = k2_sata_scr_write,
1da177e4 LT	377	};
1da177e4 LT	378
4447d351	379	static const struct ata_port_info k2_port_info[] = {
931506d3	380	/* chip_svw4 */
4447d351	381	{
9cbe056f	382	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA,
14bdef98 EIB	383	.pio_mask = ATA_PIO4,
14bdef98 EIB	384	.mwdma_mask = ATA_MWDMA2,
bf6263a8	385	.udma_mask = ATA_UDMA6,
4447d351 TH	386	.port_ops = &k2_sata_ops,
4447d351 TH	387	},
931506d3	388	/* chip_svw8 */
4447d351	389	{
9cbe056f SS	390	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA \|
9cbe056f SS	391	K2_FLAG_SATA_8_PORTS,
14bdef98 EIB	392	.pio_mask = ATA_PIO4,
14bdef98 EIB	393	.mwdma_mask = ATA_MWDMA2,
bf6263a8	394	.udma_mask = ATA_UDMA6,
4447d351 TH	395	.port_ops = &k2_sata_ops,
4447d351 TH	396	},
931506d3 AS	397	/* chip_svw42 */
931506d3 AS	398	{
9cbe056f	399	.flags = ATA_FLAG_SATA \| K2_FLAG_BAR_POS_3,
14bdef98 EIB	400	.pio_mask = ATA_PIO4,
14bdef98 EIB	401	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	402	.udma_mask = ATA_UDMA6,
	403	.port_ops = &k2_sata_ops,
	404	},
	405	/* chip_svw43 */
	406	{
9cbe056f	407	.flags = ATA_FLAG_SATA,
14bdef98 EIB	408	.pio_mask = ATA_PIO4,
14bdef98 EIB	409	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	410	.udma_mask = ATA_UDMA6,
	411	.port_ops = &k2_sata_ops,
	412	},
4447d351 TH	413	};
4447d351 TH	414
0d5ff566	415	static void k2_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	416	{
	417	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	418	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	419	port->feature_addr =
	420	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	421	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	422	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	423	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	424	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	425	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	426	port->command_addr =
	427	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	428	port->altstatus_addr =
	429	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	430	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	431	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	432	}
	433
	434
5796d1c4	435	static int k2_sata_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	436	{
4447d351 TH	437	const struct ata_port_info *ppi[] =
	438	{ &k2_port_info[ent->driver_data], NULL };
	439	struct ata_host *host;
ea6ba10b	440	void __iomem *mmio_base;
931506d3	441	int n_ports, i, rc, bar_pos;
1da177e4	442
06296a1e	443	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	444
4447d351 TH	445	/* allocate host */
	446	n_ports = 4;
	447	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
	448	n_ports = 8;
	449
	450	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	451	if (!host)
	452	return -ENOMEM;
	453
931506d3 AS	454	bar_pos = 5;
	455	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
	456	bar_pos = 3;
1da177e4 LT	457	/*
	458	* If this driver happens to only be useful on Apple's K2, then
	459	* we should check that here as it has a normal Serverworks ID
	460	*/
24dc5f33	461	rc = pcim_enable_device(pdev);
1da177e4 LT	462	if (rc)
1da177e4 LT	463	return rc;
4447d351	464
1da177e4 LT	465	/*
	466	* Check if we have resources mapped at all (second function may
	467	* have been disabled by firmware)
	468	*/
931506d3 AS	469	if (pci_resource_len(pdev, bar_pos) == 0) {
	470	/* In IDE mode we need to pin the device to ensure that
	471	pcim_release does not clear the busmaster bit in config
	472	space, clearing causes busmaster DMA to fail on
	473	ports 3 & 4 */
	474	pcim_pin_device(pdev);
1da177e4	475	return -ENODEV;
931506d3	476	}
1da177e4	477
0d5ff566	478	/* Request and iomap PCI regions */
931506d3	479	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0d5ff566	480	if (rc == -EBUSY)
24dc5f33	481	pcim_pin_device(pdev);
0d5ff566	482	if (rc)
24dc5f33	483	return rc;
4447d351	484	host->iomap = pcim_iomap_table(pdev);
931506d3	485	mmio_base = host->iomap[bar_pos];
4447d351 TH	486
	487	/* different controllers have different number of ports - currently 4 or 8 */
	488	/* All ports are on the same function. Multi-function device is no
	489	* longer available. This should not be seen in any system. */
cbcdd875 TH	490	for (i = 0; i < host->n_ports; i++) {
	491	struct ata_port *ap = host->ports[i];
	492	unsigned int offset = i * K2_SATA_PORT_OFFSET;
	493
	494	k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	495
	496	ata_port_pbar_desc(ap, 5, -1, "mmio");
	497	ata_port_pbar_desc(ap, 5, offset, "port");
	498	}
1da177e4 LT	499
	500	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	501	if (rc)
24dc5f33	502	return rc;
1da177e4 LT	503	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1da177e4 LT	504	if (rc)
24dc5f33	505	return rc;
1da177e4	506
0d5ff566 TH	507	/* Clear a magic bit in SCR1 according to Darwin, those help
	508	* some funky seagate drives (though so far, those were already
	509	* set by the firmware on the machines I had access to)
	510	*/
	511	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	512	mmio_base + K2_SATA_SICR1_OFFSET);
	513
	514	/* Clear SATA error & interrupts we don't use */
	515	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	516	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
1da177e4 LT	517
1da177e4 LT	518	pci_set_master(pdev);
c3b28894	519	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	520	IRQF_SHARED, &k2_sata_sht);
1da177e4 LT	521	}
1da177e4 LT	522
60bf09a3 NS	523	/* 0x240 is device ID for Apple K2 device
	524	* 0x241 is device ID for Serverworks Frodo4
	525	* 0x242 is device ID for Serverworks Frodo8
	526	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	527	* controller
	528	* */
3b7d697d	529	static const struct pci_device_id k2_sata_pci_tbl[] = {
931506d3	530	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
aeb74914 JG	531	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
aeb74914 JG	532	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
931506d3 AS	533	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	534	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	535	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	536	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
2d2744fc	537
1da177e4 LT	538	{ }
	539	};
	540
1da177e4 LT	541	static struct pci_driver k2_sata_pci_driver = {
	542	.name = DRV_NAME,
	543	.id_table = k2_sata_pci_tbl,
	544	.probe = k2_sata_init_one,
	545	.remove = ata_pci_remove_one,
	546	};
	547
2fc75da0	548	module_pci_driver(k2_sata_pci_driver);
1da177e4	549
1da177e4 LT	550	MODULE_AUTHOR("Benjamin Herrenschmidt");
	551	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	552	MODULE_LICENSE("GPL");
	553	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	554	MODULE_VERSION(DRV_VERSION);