[linux.git] / arch / arm / mach-s3c2410 / pm.c

/* linux/arch/arm/mach-s3c2410/pm.c
 *
 * Copyright (c) 2004,2006 Simtec Electronics
 *	Ben Dooks <[email protected]>
 *
 * S3C24XX Power Manager (Suspend-To-RAM) support
 *
 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Parts based on arch/arm/mach-pxa/pm.c
 *
 * Thanks to Dimitry Andric for debugging
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/crc32.h>
#include <linux/ioport.h>
#include <linux/delay.h>

#include <asm/cacheflush.h>
#include <asm/hardware.h>
#include <asm/io.h>

#include <asm/arch/regs-serial.h>
#include <asm/arch/regs-clock.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-irq.h>

#include <asm/mach/time.h>

#include "pm.h"

/* for external use */

unsigned long s3c_pm_flags;

#define PFX "s3c24xx-pm: "

static struct sleep_save core_save[] = {
	SAVE_ITEM(S3C2410_LOCKTIME),
	SAVE_ITEM(S3C2410_CLKCON),

	/* we restore the timings here, with the proviso that the board
	 * brings the system up in an slower, or equal frequency setting
	 * to the original system.
	 *
	 * if we cannot guarantee this, then things are going to go very
	 * wrong here, as we modify the refresh and both pll settings.
	 */

	SAVE_ITEM(S3C2410_BWSCON),
	SAVE_ITEM(S3C2410_BANKCON0),
	SAVE_ITEM(S3C2410_BANKCON1),
	SAVE_ITEM(S3C2410_BANKCON2),
	SAVE_ITEM(S3C2410_BANKCON3),
	SAVE_ITEM(S3C2410_BANKCON4),
	SAVE_ITEM(S3C2410_BANKCON5),

	SAVE_ITEM(S3C2410_CLKDIVN),
	SAVE_ITEM(S3C2410_MPLLCON),
	SAVE_ITEM(S3C2410_UPLLCON),
	SAVE_ITEM(S3C2410_CLKSLOW),
	SAVE_ITEM(S3C2410_REFRESH),
};

static struct sleep_save gpio_save[] = {
	SAVE_ITEM(S3C2410_GPACON),
	SAVE_ITEM(S3C2410_GPADAT),

	SAVE_ITEM(S3C2410_GPBCON),
	SAVE_ITEM(S3C2410_GPBDAT),
	SAVE_ITEM(S3C2410_GPBUP),

	SAVE_ITEM(S3C2410_GPCCON),
	SAVE_ITEM(S3C2410_GPCDAT),
	SAVE_ITEM(S3C2410_GPCUP),

	SAVE_ITEM(S3C2410_GPDCON),
	SAVE_ITEM(S3C2410_GPDDAT),
	SAVE_ITEM(S3C2410_GPDUP),

	SAVE_ITEM(S3C2410_GPECON),
	SAVE_ITEM(S3C2410_GPEDAT),
	SAVE_ITEM(S3C2410_GPEUP),

	SAVE_ITEM(S3C2410_GPFCON),
	SAVE_ITEM(S3C2410_GPFDAT),
	SAVE_ITEM(S3C2410_GPFUP),

	SAVE_ITEM(S3C2410_GPGCON),
	SAVE_ITEM(S3C2410_GPGDAT),
	SAVE_ITEM(S3C2410_GPGUP),

	SAVE_ITEM(S3C2410_GPHCON),
	SAVE_ITEM(S3C2410_GPHDAT),
	SAVE_ITEM(S3C2410_GPHUP),

	SAVE_ITEM(S3C2410_DCLKCON),
};

#ifdef CONFIG_S3C2410_PM_DEBUG

#define SAVE_UART(va) \
	SAVE_ITEM((va) + S3C2410_ULCON), \
	SAVE_ITEM((va) + S3C2410_UCON), \
	SAVE_ITEM((va) + S3C2410_UFCON), \
	SAVE_ITEM((va) + S3C2410_UMCON), \
	SAVE_ITEM((va) + S3C2410_UBRDIV)

static struct sleep_save uart_save[] = {
	SAVE_UART(S3C24XX_VA_UART0),
	SAVE_UART(S3C24XX_VA_UART1),
#ifndef CONFIG_CPU_S3C2400
	SAVE_UART(S3C24XX_VA_UART2),
#endif
};

/* debug
 *
 * we send the debug to printascii() to allow it to be seen if the
 * system never wakes up from the sleep
*/

extern void printascii(const char *);

void pm_dbg(const char *fmt, ...)
{
	va_list va;
	char buff[256];

	va_start(va, fmt);
	vsprintf(buff, fmt, va);
	va_end(va);

	printascii(buff);
}

static void s3c2410_pm_debug_init(void)
{
	unsigned long tmp = __raw_readl(S3C2410_CLKCON);

	/* re-start uart clocks */
	tmp |= S3C2410_CLKCON_UART0;
	tmp |= S3C2410_CLKCON_UART1;
	tmp |= S3C2410_CLKCON_UART2;

	__raw_writel(tmp, S3C2410_CLKCON);
	udelay(10);
}

#define DBG(fmt...) pm_dbg(fmt)
#else
#define DBG(fmt...) printk(KERN_DEBUG fmt)

#define s3c2410_pm_debug_init() do { } while(0)

static struct sleep_save uart_save[] = {};
#endif

#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0

/* suspend checking code...
 *
 * this next area does a set of crc checks over all the installed
 * memory, so the system can verify if the resume was ok.
 *
 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
 * increasing it will mean that the area corrupted will be less easy to spot,
 * and reducing the size will cause the CRC save area to grow
*/

#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)

static u32 crc_size;	/* size needed for the crc block */
static u32 *crcs;	/* allocated over suspend/resume */

typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);

/* s3c2410_pm_run_res
 *
 * go thorugh the given resource list, and look for system ram
*/

static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
{
	while (ptr != NULL) {
		if (ptr->child != NULL)
			s3c2410_pm_run_res(ptr->child, fn, arg);

		if ((ptr->flags & IORESOURCE_MEM) &&
		    strcmp(ptr->name, "System RAM") == 0) {
			DBG("Found system RAM at %08lx..%08lx\n",
			    ptr->start, ptr->end);
			arg = (fn)(ptr, arg);
		}

		ptr = ptr->sibling;
	}
}

static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
{
	s3c2410_pm_run_res(&iomem_resource, fn, arg);
}

static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
{
	u32 size = (u32)(res->end - res->start)+1;

	size += CHECK_CHUNKSIZE-1;
	size /= CHECK_CHUNKSIZE;

	DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);

	*val += size * sizeof(u32);
	return val;
}

/* s3c2410_pm_prepare_check
 *
 * prepare the necessary information for creating the CRCs. This
 * must be done before the final save, as it will require memory
 * allocating, and thus touching bits of the kernel we do not
 * know about.
*/

static void s3c2410_pm_check_prepare(void)
{
	crc_size = 0;

	s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);

	DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);

	crcs = kmalloc(crc_size+4, GFP_KERNEL);
	if (crcs == NULL)
		printk(KERN_ERR "Cannot allocated CRC save area\n");
}

static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
{
	unsigned long addr, left;

	for (addr = res->start; addr < res->end;
	     addr += CHECK_CHUNKSIZE) {
		left = res->end - addr;

		if (left > CHECK_CHUNKSIZE)
			left = CHECK_CHUNKSIZE;

		*val = crc32_le(~0, phys_to_virt(addr), left);
		val++;
	}

	return val;
}

/* s3c2410_pm_check_store
 *
 * compute the CRC values for the memory blocks before the final
 * sleep.
*/

static void s3c2410_pm_check_store(void)
{
	if (crcs != NULL)
		s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
}

/* in_region
 *
 * return TRUE if the area defined by ptr..ptr+size contatins the
 * what..what+whatsz
*/

static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
{
	if ((what+whatsz) < ptr)
		return 0;

	if (what > (ptr+size))
		return 0;

	return 1;
}

static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
{
	void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
	unsigned long addr;
	unsigned long left;
	void *ptr;
	u32 calc;

	for (addr = res->start; addr < res->end;
	     addr += CHECK_CHUNKSIZE) {
		left = res->end - addr;

		if (left > CHECK_CHUNKSIZE)
			left = CHECK_CHUNKSIZE;

		ptr = phys_to_virt(addr);

		if (in_region(ptr, left, crcs, crc_size)) {
			DBG("skipping %08lx, has crc block in\n", addr);
			goto skip_check;
		}

		if (in_region(ptr, left, save_at, 32*4 )) {
			DBG("skipping %08lx, has save block in\n", addr);
			goto skip_check;
		}

		/* calculate and check the checksum */

		calc = crc32_le(~0, ptr, left);
		if (calc != *val) {
			printk(KERN_ERR PFX "Restore CRC error at "
			       "%08lx (%08x vs %08x)\n", addr, calc, *val);

			DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
			    addr, calc, *val);
		}

	skip_check:
		val++;
	}

	return val;
}

/* s3c2410_pm_check_restore
 *
 * check the CRCs after the restore event and free the memory used
 * to hold them
*/

static void s3c2410_pm_check_restore(void)
{
	if (crcs != NULL) {
		s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
		kfree(crcs);
		crcs = NULL;
	}
}

#else

#define s3c2410_pm_check_prepare() do { } while(0)
#define s3c2410_pm_check_restore() do { } while(0)
#define s3c2410_pm_check_store()   do { } while(0)
#endif

/* helper functions to save and restore register state */

void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		ptr->val = __raw_readl(ptr->reg);
		DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
	}
}

/* s3c2410_pm_do_restore
 *
 * restore the system from the given list of saved registers
 *
 * Note, we do not use DBG() in here, as the system may not have
 * restore the UARTs state yet
*/

void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
		       ptr->reg, ptr->val, __raw_readl(ptr->reg));

		__raw_writel(ptr->val, ptr->reg);
	}
}

/* s3c2410_pm_do_restore_core
 *
 * similar to s3c2410_pm_do_restore_core
 *
 * WARNING: Do not put any debug in here that may effect memory or use
 * peripherals, as things may be changing!
*/

static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
{
	for (; count > 0; count--, ptr++) {
		__raw_writel(ptr->val, ptr->reg);
	}
}

/* s3c2410_pm_show_resume_irqs
 *
 * print any IRQs asserted at resume time (ie, we woke from)
*/

static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
					unsigned long mask)
{
	int i;

	which &= ~mask;

	for (i = 0; i <= 31; i++) {
		if ((which) & (1L<<i)) {
			DBG("IRQ %d asserted at resume\n", start+i);
		}
	}
}

/* s3c2410_pm_check_resume_pin
 *
 * check to see if the pin is configured correctly for sleep mode, and
 * make any necessary adjustments if it is not
*/

static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
{
	unsigned long irqstate;
	unsigned long pinstate;
	int irq = s3c2410_gpio_getirq(pin);

	if (irqoffs < 4)
		irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
	else
		irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);

	pinstate = s3c2410_gpio_getcfg(pin);
	pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;

	if (!irqstate) {
		if (pinstate == 0x02)
			DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
	} else {
		if (pinstate == 0x02) {
			DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
			s3c2410_gpio_cfgpin(pin, 0x00);
		}
	}
}

/* s3c2410_pm_configure_extint
 *
 * configure all external interrupt pins
*/

static void s3c2410_pm_configure_extint(void)
{
	int pin;

	/* for each of the external interrupts (EINT0..EINT15) we
	 * need to check wether it is an external interrupt source,
	 * and then configure it as an input if it is not
	*/

	for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
		s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
	}

	for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
		s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
	}
}

void (*pm_cpu_prep)(void);
void (*pm_cpu_sleep)(void);

#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))

/* s3c2410_pm_enter
 *
 * central control for sleep/resume process
*/

static int s3c2410_pm_enter(suspend_state_t state)
{
	unsigned long regs_save[16];

	/* ensure the debug is initialised (if enabled) */

	s3c2410_pm_debug_init();

	DBG("s3c2410_pm_enter(%d)\n", state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
		return -EINVAL;
	}

	if (state != PM_SUSPEND_MEM) {
		printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
		printk(KERN_ERR PFX "Aborting sleep\n");
		return -EINVAL;
	}

	/* prepare check area if configured */

	s3c2410_pm_check_prepare();

	/* store the physical address of the register recovery block */

	s3c2410_sleep_save_phys = virt_to_phys(regs_save);

	DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);

	/* save all necessary core registers not covered by the drivers */

	s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
	s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
	s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));

	/* set the irq configuration for wake */

	s3c2410_pm_configure_extint();

	DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
	__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);

	/* ack any outstanding external interrupts before we go to sleep */

	__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
	__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
	__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);

	/* call cpu specific preperation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c2410_pm_check_store();

	/* send the cpu to sleep... */

	__raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */

	/* s3c2410_cpu_save will also act as our return point from when
	 * we resume as it saves its own register state, so use the return
	 * code to differentiate return from save and return from sleep */

	if (s3c2410_cpu_save(regs_save) == 0) {
		flush_cache_all();
		pm_cpu_sleep();
	}

	/* restore the cpu state */

	cpu_init();

	/* restore the system state */

	s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
	s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));

	s3c2410_pm_debug_init();

	/* check what irq (if any) restored the system */

	DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
	    __raw_readl(S3C2410_SRCPND),
	    __raw_readl(S3C2410_EINTPEND));

	s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
				    s3c_irqwake_intmask);

	s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
				    s3c_irqwake_eintmask);

	DBG("post sleep, preparing to return\n");

	s3c2410_pm_check_restore();

	/* ok, let's return from sleep */

	DBG("S3C2410 PM Resume (post-restore)\n");
	return 0;
}

/*
 * Called after processes are frozen, but before we shut down devices.
 */
static int s3c2410_pm_prepare(suspend_state_t state)
{
	return 0;
}

/*
 * Called after devices are re-setup, but before processes are thawed.
 */
static int s3c2410_pm_finish(suspend_state_t state)
{
	return 0;
}

/*
 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
 */
static struct pm_ops s3c2410_pm_ops = {
	.pm_disk_mode	= PM_DISK_FIRMWARE,
	.prepare	= s3c2410_pm_prepare,
	.enter		= s3c2410_pm_enter,
	.finish		= s3c2410_pm_finish,
};

/* s3c2410_pm_init
 *
 * Attach the power management functions. This should be called
 * from the board specific initialisation if the board supports
 * it.
*/

int __init s3c2410_pm_init(void)
{
	printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");

	pm_set_ops(&s3c2410_pm_ops);
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/pm.c
1da177e4 LT	2	*
1e582fc7	3	* Copyright (c) 2004,2006 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <[email protected]>
1da177e4 LT	5	*
1e582fc7	6	* S3C24XX Power Manager (Suspend-To-RAM) support
1da177e4 LT	7	*
	8	* See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* Parts based on arch/arm/mach-pxa/pm.c
	25	*
	26	* Thanks to Dimitry Andric for debugging
1da177e4 LT	27	*/
1da177e4 LT	28
1da177e4 LT	29	#include <linux/init.h>
	30	#include <linux/suspend.h>
	31	#include <linux/errno.h>
	32	#include <linux/time.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/crc32.h>
	35	#include <linux/ioport.h>
	36	#include <linux/delay.h>
	37
58095d7f	38	#include <asm/cacheflush.h>
1da177e4 LT	39	#include <asm/hardware.h>
	40	#include <asm/io.h>
	41
	42	#include <asm/arch/regs-serial.h>
	43	#include <asm/arch/regs-clock.h>
	44	#include <asm/arch/regs-gpio.h>
	45	#include <asm/arch/regs-mem.h>
	46	#include <asm/arch/regs-irq.h>
	47
	48	#include <asm/mach/time.h>
	49
	50	#include "pm.h"
	51
	52	/* for external use */
	53
	54	unsigned long s3c_pm_flags;
	55
1da177e4 LT	56	#define PFX "s3c24xx-pm: "
	57
	58	static struct sleep_save core_save[] = {
	59	SAVE_ITEM(S3C2410_LOCKTIME),
	60	SAVE_ITEM(S3C2410_CLKCON),
	61
	62	/* we restore the timings here, with the proviso that the board
	63	* brings the system up in an slower, or equal frequency setting
	64	* to the original system.
	65	*
	66	* if we cannot guarantee this, then things are going to go very
	67	* wrong here, as we modify the refresh and both pll settings.
	68	*/
	69
	70	SAVE_ITEM(S3C2410_BWSCON),
	71	SAVE_ITEM(S3C2410_BANKCON0),
	72	SAVE_ITEM(S3C2410_BANKCON1),
	73	SAVE_ITEM(S3C2410_BANKCON2),
	74	SAVE_ITEM(S3C2410_BANKCON3),
	75	SAVE_ITEM(S3C2410_BANKCON4),
	76	SAVE_ITEM(S3C2410_BANKCON5),
	77
	78	SAVE_ITEM(S3C2410_CLKDIVN),
	79	SAVE_ITEM(S3C2410_MPLLCON),
	80	SAVE_ITEM(S3C2410_UPLLCON),
	81	SAVE_ITEM(S3C2410_CLKSLOW),
	82	SAVE_ITEM(S3C2410_REFRESH),
	83	};
	84
1da177e4 LT	85	static struct sleep_save gpio_save[] = {
	86	SAVE_ITEM(S3C2410_GPACON),
	87	SAVE_ITEM(S3C2410_GPADAT),
	88
	89	SAVE_ITEM(S3C2410_GPBCON),
	90	SAVE_ITEM(S3C2410_GPBDAT),
	91	SAVE_ITEM(S3C2410_GPBUP),
	92
	93	SAVE_ITEM(S3C2410_GPCCON),
	94	SAVE_ITEM(S3C2410_GPCDAT),
	95	SAVE_ITEM(S3C2410_GPCUP),
	96
	97	SAVE_ITEM(S3C2410_GPDCON),
	98	SAVE_ITEM(S3C2410_GPDDAT),
	99	SAVE_ITEM(S3C2410_GPDUP),
	100
	101	SAVE_ITEM(S3C2410_GPECON),
	102	SAVE_ITEM(S3C2410_GPEDAT),
	103	SAVE_ITEM(S3C2410_GPEUP),
	104
	105	SAVE_ITEM(S3C2410_GPFCON),
	106	SAVE_ITEM(S3C2410_GPFDAT),
	107	SAVE_ITEM(S3C2410_GPFUP),
	108
	109	SAVE_ITEM(S3C2410_GPGCON),
	110	SAVE_ITEM(S3C2410_GPGDAT),
	111	SAVE_ITEM(S3C2410_GPGUP),
	112
	113	SAVE_ITEM(S3C2410_GPHCON),
	114	SAVE_ITEM(S3C2410_GPHDAT),
	115	SAVE_ITEM(S3C2410_GPHUP),
	116
	117	SAVE_ITEM(S3C2410_DCLKCON),
	118	};
	119
	120	#ifdef CONFIG_S3C2410_PM_DEBUG
	121
	122	#define SAVE_UART(va) \
	123	SAVE_ITEM((va) + S3C2410_ULCON), \
	124	SAVE_ITEM((va) + S3C2410_UCON), \
	125	SAVE_ITEM((va) + S3C2410_UFCON), \
	126	SAVE_ITEM((va) + S3C2410_UMCON), \
	127	SAVE_ITEM((va) + S3C2410_UBRDIV)
	128
	129	static struct sleep_save uart_save[] = {
	130	SAVE_UART(S3C24XX_VA_UART0),
	131	SAVE_UART(S3C24XX_VA_UART1),
	132	#ifndef CONFIG_CPU_S3C2400
	133	SAVE_UART(S3C24XX_VA_UART2),
	134	#endif
	135	};
	136
	137	/* debug
	138	*
	139	* we send the debug to printascii() to allow it to be seen if the
	140	* system never wakes up from the sleep
	141	*/
	142
	143	extern void printascii(const char *);
	144
0033a2f0	145	void pm_dbg(const char *fmt, ...)
1da177e4 LT	146	{
	147	va_list va;
	148	char buff[256];
	149
	150	va_start(va, fmt);
	151	vsprintf(buff, fmt, va);
	152	va_end(va);
	153
	154	printascii(buff);
	155	}
	156
	157	static void s3c2410_pm_debug_init(void)
	158	{
	159	unsigned long tmp = __raw_readl(S3C2410_CLKCON);
	160
	161	/* re-start uart clocks */
	162	tmp \|= S3C2410_CLKCON_UART0;
	163	tmp \|= S3C2410_CLKCON_UART1;
	164	tmp \|= S3C2410_CLKCON_UART2;
	165
	166	__raw_writel(tmp, S3C2410_CLKCON);
	167	udelay(10);
	168	}
	169
	170	#define DBG(fmt...) pm_dbg(fmt)
	171	#else
	172	#define DBG(fmt...) printk(KERN_DEBUG fmt)
	173
	174	#define s3c2410_pm_debug_init() do { } while(0)
	175
	176	static struct sleep_save uart_save[] = {};
	177	#endif
	178
	179	#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
	180
	181	/* suspend checking code...
	182	*
	183	* this next area does a set of crc checks over all the installed
	184	* memory, so the system can verify if the resume was ok.
	185	*
	186	* CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
	187	* increasing it will mean that the area corrupted will be less easy to spot,
	188	* and reducing the size will cause the CRC save area to grow
	189	*/
	190
	191	#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
	192
	193	static u32 crc_size; /* size needed for the crc block */
	194	static u32 crcs; / allocated over suspend/resume */
	195
	196	typedef u32 (run_fn_t)(struct resource ptr, u32 *arg);
	197
	198	/* s3c2410_pm_run_res
	199	*
	200	* go thorugh the given resource list, and look for system ram
	201	*/
	202
	203	static void s3c2410_pm_run_res(struct resource ptr, run_fn_t fn, u32 arg)
	204	{
	205	while (ptr != NULL) {
	206	if (ptr->child != NULL)
	207	s3c2410_pm_run_res(ptr->child, fn, arg);
	208
	209	if ((ptr->flags & IORESOURCE_MEM) &&
210	strcmp(ptr->name, "System RAM") == 0) {
211	DBG("Found system RAM at %08lx..%08lx\n",
212	ptr->start, ptr->end);
213	arg = (fn)(ptr, arg);
214	}
215
216	ptr = ptr->sibling;
217	}
218	}
219
220	static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
221	{
222	s3c2410_pm_run_res(&iomem_resource, fn, arg);
223	}
224
225	static u32 s3c2410_pm_countram(struct resource res, u32 *val)
226	{
227	u32 size = (u32)(res->end - res->start)+1;
228
229	size += CHECK_CHUNKSIZE-1;
230	size /= CHECK_CHUNKSIZE;
231
232	DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
233
234	val += size sizeof(u32);
235	return val;
236	}
237
238	/* s3c2410_pm_prepare_check
239	*
240	* prepare the necessary information for creating the CRCs. This
241	* must be done before the final save, as it will require memory
242	* allocating, and thus touching bits of the kernel we do not
243	* know about.
244	*/
245
246	static void s3c2410_pm_check_prepare(void)
247	{
248	crc_size = 0;
249
250	s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
251
252	DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
253
254	crcs = kmalloc(crc_size+4, GFP_KERNEL);
255	if (crcs == NULL)
256	printk(KERN_ERR "Cannot allocated CRC save area\n");
257	}
258
259	static u32 s3c2410_pm_makecheck(struct resource res, u32 *val)
260	{
261	unsigned long addr, left;
262
263	for (addr = res->start; addr < res->end;
264	addr += CHECK_CHUNKSIZE) {
265	left = res->end - addr;
266
267	if (left > CHECK_CHUNKSIZE)
268	left = CHECK_CHUNKSIZE;
269
270	*val = crc32_le(~0, phys_to_virt(addr), left);
271	val++;
272	}
273
274	return val;
275	}
276
277	/* s3c2410_pm_check_store
278	*
279	* compute the CRC values for the memory blocks before the final
280	* sleep.
281	*/
282
283	static void s3c2410_pm_check_store(void)
284	{
285	if (crcs != NULL)
286	s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
287	}
288
289	/* in_region
290	*
291	* return TRUE if the area defined by ptr..ptr+size contatins the
292	* what..what+whatsz
293	*/
294
295	static inline int in_region(void ptr, int size, void what, size_t whatsz)
296	{
297	if ((what+whatsz) < ptr)
298	return 0;
299
300	if (what > (ptr+size))
301	return 0;
302
303	return 1;
304	}
305
306	static u32 s3c2410_pm_runcheck(struct resource res, u32 *val)
307	{
308	void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
309	unsigned long addr;
310	unsigned long left;
311	void *ptr;
312	u32 calc;
313
314	for (addr = res->start; addr < res->end;
315	addr += CHECK_CHUNKSIZE) {
316	left = res->end - addr;
317
318	if (left > CHECK_CHUNKSIZE)
319	left = CHECK_CHUNKSIZE;
320
321	ptr = phys_to_virt(addr);
322
323	if (in_region(ptr, left, crcs, crc_size)) {
324	DBG("skipping %08lx, has crc block in\n", addr);
325	goto skip_check;
326	}
327
328	if (in_region(ptr, left, save_at, 32*4 )) {
329	DBG("skipping %08lx, has save block in\n", addr);
330	goto skip_check;
331	}
332
333	/* calculate and check the checksum */
334
335	calc = crc32_le(~0, ptr, left);
336	if (calc != *val) {
337	printk(KERN_ERR PFX "Restore CRC error at "
338	"%08lx (%08x vs %08x)\n", addr, calc, *val);
339
340	DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
341	addr, calc, *val);
342	}
343
344	skip_check:
345	val++;
346	}
347
348	return val;
349	}
350
351	/* s3c2410_pm_check_restore
352	*
353	* check the CRCs after the restore event and free the memory used
354	* to hold them
355	*/
356
357	static void s3c2410_pm_check_restore(void)
358	{
359	if (crcs != NULL) {
360	s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
361	kfree(crcs);
362	crcs = NULL;
363	}
364	}
365
366	#else
367
368	#define s3c2410_pm_check_prepare() do { } while(0)
369	#define s3c2410_pm_check_restore() do { } while(0)
370	#define s3c2410_pm_check_store() do { } while(0)
371	#endif
372
373	/* helper functions to save and restore register state */
374
375	void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
376	{
377	for (; count > 0; count--, ptr++) {
378	ptr->val = __raw_readl(ptr->reg);
379	DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
380	}
381	}
382
383	/* s3c2410_pm_do_restore
384	*
385	* restore the system from the given list of saved registers
386	*
387	* Note, we do not use DBG() in here, as the system may not have
388	* restore the UARTs state yet
389	*/
390
391	void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
392	{
393	for (; count > 0; count--, ptr++) {
394	printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
395	ptr->reg, ptr->val, __raw_readl(ptr->reg));
396
397	__raw_writel(ptr->val, ptr->reg);
398	}
399	}
400
401	/* s3c2410_pm_do_restore_core
402	*
403	* similar to s3c2410_pm_do_restore_core
404	*
405	* WARNING: Do not put any debug in here that may effect memory or use
406	* peripherals, as things may be changing!
407	*/
408
409	static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
410	{
411	for (; count > 0; count--, ptr++) {
412	__raw_writel(ptr->val, ptr->reg);
413	}
414	}
415
416	/* s3c2410_pm_show_resume_irqs
417	*
418	* print any IRQs asserted at resume time (ie, we woke from)
419	*/
420
421	static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
422	unsigned long mask)
423	{
424	int i;
425
426	which &= ~mask;
427
428	for (i = 0; i <= 31; i++) {
429	if ((which) & (1L<<i)) {
430	DBG("IRQ %d asserted at resume\n", start+i);
431	}
432	}
433	}
434
435	/* s3c2410_pm_check_resume_pin
436	*
437	* check to see if the pin is configured correctly for sleep mode, and
438	* make any necessary adjustments if it is not
439	*/
440
441	static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
442	{
443	unsigned long irqstate;
444	unsigned long pinstate;
445	int irq = s3c2410_gpio_getirq(pin);
446
447	if (irqoffs < 4)
448	irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
449	else
450	irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
451
452	pinstate = s3c2410_gpio_getcfg(pin);
453	pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;
454
455	if (!irqstate) {
456	if (pinstate == 0x02)
457	DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
458	} else {
459	if (pinstate == 0x02) {
460	DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
461	s3c2410_gpio_cfgpin(pin, 0x00);
462	}
463	}
464	}
465
466	/* s3c2410_pm_configure_extint
467	*
468	* configure all external interrupt pins
469	*/
470
471	static void s3c2410_pm_configure_extint(void)
472	{
473	int pin;
474
475	/* for each of the external interrupts (EINT0..EINT15) we
476	* need to check wether it is an external interrupt source,
477	* and then configure it as an input if it is not
478	*/
479
480	for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
481	s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
482	}
483
484	for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
485	s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
486	}
487	}
488
0033a2f0 BD	489	void (*pm_cpu_prep)(void);
	490	void (*pm_cpu_sleep)(void);
	491
1da177e4 LT	492	#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
	493
	494	/* s3c2410_pm_enter
	495	*
	496	* central control for sleep/resume process
	497	*/
	498
	499	static int s3c2410_pm_enter(suspend_state_t state)
	500	{
	501	unsigned long regs_save[16];
1da177e4 LT	502
	503	/* ensure the debug is initialised (if enabled) */
	504
	505	s3c2410_pm_debug_init();
	506
	507	DBG("s3c2410_pm_enter(%d)\n", state);
	508
0033a2f0 BD	509	if (pm_cpu_prep == NULL \|\| pm_cpu_sleep == NULL) {
	510	printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
	511	return -EINVAL;
	512	}
	513
1da177e4 LT	514	if (state != PM_SUSPEND_MEM) {
	515	printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
	516	return -EINVAL;
	517	}
	518
	519	/* check if we have anything to wake-up with... bad things seem
	520	* to happen if you suspend with no wakeup (system will often
	521	* require a full power-cycle)
	522	*/
	523
	524	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	525	!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
	526	printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
	527	printk(KERN_ERR PFX "Aborting sleep\n");
	528	return -EINVAL;
	529	}
	530
	531	/* prepare check area if configured */
	532
	533	s3c2410_pm_check_prepare();
	534
	535	/* store the physical address of the register recovery block */
	536
	537	s3c2410_sleep_save_phys = virt_to_phys(regs_save);
	538
	539	DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
	540
1da177e4 LT	541	/* save all necessary core registers not covered by the drivers */
	542
	543	s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
1da177e4 LT	544	s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
	545	s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
	546
	547	/* set the irq configuration for wake */
	548
	549	s3c2410_pm_configure_extint();
	550
	551	DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	552	s3c_irqwake_intmask, s3c_irqwake_eintmask);
	553
	554	__raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
	555	__raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
	556
	557	/* ack any outstanding external interrupts before we go to sleep */
	558
	559	__raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
cdf3f8e0 BD	560	__raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
cdf3f8e0 BD	561	__raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
1da177e4	562
0033a2f0 BD	563	/* call cpu specific preperation */
	564
	565	pm_cpu_prep();
	566
1da177e4 LT	567	/* flush cache back to ram */
1da177e4 LT	568
58095d7f	569	flush_cache_all();
1da177e4 LT	570
	571	s3c2410_pm_check_store();
	572
1da177e4 LT	573	/* send the cpu to sleep... */
	574
	575	__raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
	576
58095d7f BD	577	/* s3c2410_cpu_save will also act as our return point from when
	578	* we resume as it saves its own register state, so use the return
	579	* code to differentiate return from save and return from sleep */
	580
	581	if (s3c2410_cpu_save(regs_save) == 0) {
	582	flush_cache_all();
0033a2f0	583	pm_cpu_sleep();
58095d7f	584	}
1da177e4	585
9bed07d0 BD	586	/* restore the cpu state */
	587
	588	cpu_init();
	589
1da177e4 LT	590	/* restore the system state */
	591
	592	s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	593	s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
1da177e4 LT	594	s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
	595
	596	s3c2410_pm_debug_init();
	597
	598	/* check what irq (if any) restored the system */
	599
	600	DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
	601	__raw_readl(S3C2410_SRCPND),
	602	__raw_readl(S3C2410_EINTPEND));
	603
	604	s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
	605	s3c_irqwake_intmask);
	606
	607	s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
	608	s3c_irqwake_eintmask);
	609
	610	DBG("post sleep, preparing to return\n");
	611
	612	s3c2410_pm_check_restore();
	613
	614	/* ok, let's return from sleep */
	615
	616	DBG("S3C2410 PM Resume (post-restore)\n");
	617	return 0;
	618	}
	619
	620	/*
	621	* Called after processes are frozen, but before we shut down devices.
	622	*/
	623	static int s3c2410_pm_prepare(suspend_state_t state)
	624	{
	625	return 0;
	626	}
	627
	628	/*
	629	* Called after devices are re-setup, but before processes are thawed.
	630	*/
	631	static int s3c2410_pm_finish(suspend_state_t state)
	632	{
	633	return 0;
	634	}
	635
	636	/*
	637	* Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
	638	*/
	639	static struct pm_ops s3c2410_pm_ops = {
	640	.pm_disk_mode = PM_DISK_FIRMWARE,
	641	.prepare = s3c2410_pm_prepare,
	642	.enter = s3c2410_pm_enter,
	643	.finish = s3c2410_pm_finish,
	644	};
	645
	646	/* s3c2410_pm_init
	647	*
	648	* Attach the power management functions. This should be called
	649	* from the board specific initialisation if the board supports
	650	* it.
	651	*/
	652
	653	int __init s3c2410_pm_init(void)
	654	{
	655	printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
	656
	657	pm_set_ops(&s3c2410_pm_ops);
658	return 0;
659	}