[linux.git] / arch / sh / mm / tlb-sh4.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/sh/mm/tlb-sh4.c
 *
 * SH-4 specific TLB operations
 *
 * Copyright (C) 1999  Niibe Yutaka
 * Copyright (C) 2002 - 2007 Paul Mundt
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
	unsigned long flags, pteval, vpn;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (vma && current->active_mm != vma->vm_mm)
		return;

	local_irq_save(flags);

	/* Set PTEH register */
	vpn = (address & MMU_VPN_MASK) | get_asid();
	__raw_writel(vpn, MMU_PTEH);

	pteval = pte.pte_low;

	/* Set PTEA register */
#ifdef CONFIG_X2TLB
	/*
	 * For the extended mode TLB this is trivial, only the ESZ and
	 * EPR bits need to be written out to PTEA, with the remainder of
	 * the protection bits (with the exception of the compat-mode SZ
	 * and PR bits, which are cleared) being written out in PTEL.
	 */
	__raw_writel(pte.pte_high, MMU_PTEA);
#else
	if (cpu_data->flags & CPU_HAS_PTEA) {
		/* The last 3 bits and the first one of pteval contains
		 * the PTEA timing control and space attribute bits
		 */
		__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
	}
#endif

	/* Set PTEL register */
	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#ifdef CONFIG_CACHE_WRITETHROUGH
	pteval |= _PAGE_WT;
#endif
	/* conveniently, we want all the software flags to be 0 anyway */
	__raw_writel(pteval, MMU_PTEL);

	/* Load the TLB */
	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
	local_irq_restore(flags);
}

void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
	unsigned long addr, data;

	/*
	 * NOTE: PTEH.ASID should be set to this MM
	 *       _AND_ we need to write ASID to the array.
	 *
	 * It would be simple if we didn't need to set PTEH.ASID...
	 */
	addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
	data = page | asid; /* VALID bit is off */
	jump_to_uncached();
	__raw_writel(data, addr);
	back_to_cached();
}

void local_flush_tlb_all(void)
{
	unsigned long flags, status;
	int i;

	/*
	 * Flush all the TLB.
	 */
	local_irq_save(flags);
	jump_to_uncached();

	status = __raw_readl(MMUCR);
	status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);

	if (status == 0)
		status = MMUCR_URB_NENTRIES;

	for (i = 0; i < status; i++)
		__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));

	for (i = 0; i < 4; i++)
		__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));

	back_to_cached();
	ctrl_barrier();
	local_irq_restore(flags);
}
Commit	Line	Data
c456cfc2	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	/*
	3	* arch/sh/mm/tlb-sh4.c
	4	*
	5	* SH-4 specific TLB operations
	6	*
	7	* Copyright (C) 1999 Niibe Yutaka
d04a0f79	8	* Copyright (C) 2002 - 2007 Paul Mundt
1da177e4	9	*/
39e688a9	10	#include <linux/kernel.h>
39e688a9	11	#include <linux/mm.h>
d04a0f79	12	#include <linux/io.h>
1da177e4	13	#include <asm/mmu_context.h>
39e688a9 PM	14	#include <asm/cacheflush.h>
39e688a9 PM	15
9cef7492	16	void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
39e688a9	17	{
9cef7492	18	unsigned long flags, pteval, vpn;
39e688a9	19
9cef7492 PM	20	/*
	21	* Handle debugger faulting in for debugee.
	22	*/
3ed6e129	23	if (vma && current->active_mm != vma->vm_mm)
39e688a9 PM	24	return;
39e688a9 PM	25
39e688a9 PM	26	local_irq_save(flags);
	27
	28	/* Set PTEH register */
	29	vpn = (address & MMU_VPN_MASK) \| get_asid();
9d56dd3b	30	__raw_writel(vpn, MMU_PTEH);
39e688a9	31
d04a0f79	32	pteval = pte.pte_low;
39e688a9 PM	33
39e688a9 PM	34	/* Set PTEA register */
d04a0f79 PM	35	#ifdef CONFIG_X2TLB
	36	/*
	37	* For the extended mode TLB this is trivial, only the ESZ and
	38	* EPR bits need to be written out to PTEA, with the remainder of
	39	* the protection bits (with the exception of the compat-mode SZ
	40	* and PR bits, which are cleared) being written out in PTEL.
	41	*/
9d56dd3b	42	__raw_writel(pte.pte_high, MMU_PTEA);
d04a0f79	43	#else
6503fe4a MT	44	if (cpu_data->flags & CPU_HAS_PTEA) {
	45	/* The last 3 bits and the first one of pteval contains
	46	* the PTEA timing control and space attribute bits
	47	*/
9d56dd3b	48	__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
6503fe4a	49	}
d04a0f79	50	#endif
39e688a9 PM	51
	52	/* Set PTEL register */
	53	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
e7bd34a1	54	#ifdef CONFIG_CACHE_WRITETHROUGH
39e688a9 PM	55	pteval \|= _PAGE_WT;
	56	#endif
	57	/* conveniently, we want all the software flags to be 0 anyway */
9d56dd3b	58	__raw_writel(pteval, MMU_PTEL);
39e688a9 PM	59
	60	/* Load the TLB */
	61	asm volatile("ldtlb": /* no output / : / no input */ : "memory");
	62	local_irq_restore(flags);
	63	}
1da177e4	64
2dc2f8e0	65	void local_flush_tlb_one(unsigned long asid, unsigned long page)
1da177e4 LT	66	{
	67	unsigned long addr, data;
	68
	69	/*
	70	* NOTE: PTEH.ASID should be set to this MM
	71	* _AND_ we need to write ASID to the array.
	72	*
	73	* It would be simple if we didn't need to set PTEH.ASID...
	74	*/
	75	addr = MMU_UTLB_ADDRESS_ARRAY \| MMU_PAGE_ASSOC_BIT;
	76	data = page \| asid; /* VALID bit is off */
cbaa118e	77	jump_to_uncached();
9d56dd3b	78	__raw_writel(data, addr);
cbaa118e	79	back_to_cached();
1da177e4	80	}
be97d758 PM	81
	82	void local_flush_tlb_all(void)
	83	{
	84	unsigned long flags, status;
	85	int i;
	86
	87	/*
	88	* Flush all the TLB.
	89	*/
	90	local_irq_save(flags);
	91	jump_to_uncached();
	92
	93	status = __raw_readl(MMUCR);
	94	status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
	95
	96	if (status == 0)
	97	status = MMUCR_URB_NENTRIES;
	98
	99	for (i = 0; i < status; i++)
	100	__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY \| (i << 8));
	101
	102	for (i = 0; i < 4; i++)
	103	__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY \| (i << 8));
	104
	105	back_to_cached();
	106	ctrl_barrier();
	107	local_irq_restore(flags);
	108	}