[linux.git] / drivers / gpio / gpio-ml-ioh.c

/*
 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#define IOH_EDGE_FALLING	0
#define IOH_EDGE_RISING		BIT(0)
#define IOH_LEVEL_L		BIT(1)
#define IOH_LEVEL_H		(BIT(0) | BIT(1))
#define IOH_EDGE_BOTH		BIT(2)
#define IOH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))

#define IOH_IRQ_BASE		0

#define PCI_VENDOR_ID_ROHM             0x10DB

struct ioh_reg_comn {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im_0;
	u32	im_1;
	u32	reserved;
};

struct ioh_regs {
	struct ioh_reg_comn regs[8];
	u32 reserve1[16];
	u32 ioh_sel_reg[4];
	u32 reserve2[11];
	u32 srst;
};

/**
 * struct ioh_gpio_reg_data - The register store data.
 * @ien_reg	To store contents of interrupt enable register.
 * @imask_reg:	To store contents of interrupt mask regist
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of interrupt mode regist0
 * @im1_reg:	To store contents of interrupt mode regist1
 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
 */
struct ioh_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 use_sel_reg;
};

/**
 * struct ioh_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped IOH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @ioh_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @gpio_use_sel:		Save GPIO_USE_SEL1~4 register for PM
 * @ch:				Indicate GPIO channel
 * @irq_base:		Save base of IRQ number for interrupt
 * @spinlock:		Used for register access protection in
 *				interrupt context ioh_irq_type and PM;
 */
struct ioh_gpio {
	void __iomem *base;
	struct ioh_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct ioh_gpio_reg_data ioh_gpio_reg;
	u32 gpio_use_sel;
	struct mutex lock;
	int ch;
	int irq_base;
	spinlock_t spinlock;
};

static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};

static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	u32 reg_val;
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);

	mutex_lock(&chip->lock);
	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);

	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
	mutex_unlock(&chip->lock);
}

static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);

	return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
}

static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				     int val)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	u32 pm;
	u32 reg_val;

	mutex_lock(&chip->lock);
	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
					((1 << num_ports[chip->ch]) - 1);
	pm |= (1 << nr);
	iowrite32(pm, &chip->reg->regs[chip->ch].pm);

	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);
	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);

	mutex_unlock(&chip->lock);

	return 0;
}

static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	u32 pm;

	mutex_lock(&chip->lock);
	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
				((1 << num_ports[chip->ch]) - 1);
	pm &= ~(1 << nr);
	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	mutex_unlock(&chip->lock);

	return 0;
}

#ifdef CONFIG_PM
/*
 * Save register configuration and disable interrupts.
 */
static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
{
	int i;

	for (i = 0; i < 8; i ++, chip++) {
		chip->ioh_gpio_reg.po_reg =
					ioread32(&chip->reg->regs[chip->ch].po);
		chip->ioh_gpio_reg.pm_reg =
					ioread32(&chip->reg->regs[chip->ch].pm);
		chip->ioh_gpio_reg.ien_reg =
				       ioread32(&chip->reg->regs[chip->ch].ien);
		chip->ioh_gpio_reg.imask_reg =
				     ioread32(&chip->reg->regs[chip->ch].imask);
		chip->ioh_gpio_reg.im0_reg =
				      ioread32(&chip->reg->regs[chip->ch].im_0);
		chip->ioh_gpio_reg.im1_reg =
				      ioread32(&chip->reg->regs[chip->ch].im_1);
		if (i < 4)
			chip->ioh_gpio_reg.use_sel_reg =
					   ioread32(&chip->reg->ioh_sel_reg[i]);
	}
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
{
	int i;

	for (i = 0; i < 8; i ++, chip++) {
		iowrite32(chip->ioh_gpio_reg.po_reg,
			  &chip->reg->regs[chip->ch].po);
		iowrite32(chip->ioh_gpio_reg.pm_reg,
			  &chip->reg->regs[chip->ch].pm);
		iowrite32(chip->ioh_gpio_reg.ien_reg,
			  &chip->reg->regs[chip->ch].ien);
		iowrite32(chip->ioh_gpio_reg.imask_reg,
			  &chip->reg->regs[chip->ch].imask);
		iowrite32(chip->ioh_gpio_reg.im0_reg,
			  &chip->reg->regs[chip->ch].im_0);
		iowrite32(chip->ioh_gpio_reg.im1_reg,
			  &chip->reg->regs[chip->ch].im_1);
		if (i < 4)
			iowrite32(chip->ioh_gpio_reg.use_sel_reg,
				  &chip->reg->ioh_sel_reg[i]);
	}
}
#endif

static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	return chip->irq_base + offset;
}

static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->owner = THIS_MODULE;
	gpio->direction_input = ioh_gpio_direction_input;
	gpio->get = ioh_gpio_get;
	gpio->direction_output = ioh_gpio_direction_output;
	gpio->set = ioh_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = -1;
	gpio->ngpio = num_port;
	gpio->can_sleep = 0;
	gpio->to_irq = ioh_gpio_to_irq;
}

static int ioh_irq_type(struct irq_data *d, unsigned int type)
{
	u32 im;
	void __iomem *im_reg;
	u32 ien;
	u32 im_pos;
	int ch;
	unsigned long flags;
	u32 val;
	int irq = d->irq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	ch = irq - chip->irq_base;
	if (irq <= chip->irq_base + 7) {
		im_reg = &chip->reg->regs[chip->ch].im_0;
		im_pos = ch;
	} else {
		im_reg = &chip->reg->regs[chip->ch].im_1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
		__func__, irq, type, ch, im_pos, type);

	spin_lock_irqsave(&chip->spinlock, flags);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = IOH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = IOH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = IOH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = IOH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = IOH_LEVEL_L;
		break;
	case IRQ_TYPE_PROBE:
		goto end;
	default:
		dev_warn(chip->dev, "%s: unknown type(%dd)",
			__func__, type);
		goto end;
	}

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* iclr */
	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);

	/* IMASKCLR */
	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);

	/* Enable interrupt */
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
end:
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static void ioh_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base),
		  &chip->reg->regs[chip->ch].imaskclr);
}

static void ioh_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base),
		  &chip->reg->regs[chip->ch].imask);
}

static void ioh_irq_disable(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;
	unsigned long flags;
	u32 ien;

	spin_lock_irqsave(&chip->spinlock, flags);
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	ien &= ~(1 << (d->irq - chip->irq_base));
	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static void ioh_irq_enable(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;
	unsigned long flags;
	u32 ien;

	spin_lock_irqsave(&chip->spinlock, flags);
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	ien |= 1 << (d->irq - chip->irq_base);
	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
{
	struct ioh_gpio *chip = dev_id;
	u32 reg_val;
	int i, j;
	int ret = IRQ_NONE;

	for (i = 0; i < 8; i++, chip++) {
		reg_val = ioread32(&chip->reg->regs[i].istatus);
		for (j = 0; j < num_ports[i]; j++) {
			if (reg_val & BIT(j)) {
				dev_dbg(chip->dev,
					"%s:[%d]:irq=%d status=0x%x\n",
					__func__, j, irq, reg_val);
				iowrite32(BIT(j),
					  &chip->reg->regs[chip->ch].iclr);
				generic_handle_irq(chip->irq_base + j);
				ret = IRQ_HANDLED;
			}
		}
	}
	return ret;
}

static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
				unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
				    handle_simple_irq);
	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_mask = ioh_irq_mask;
	ct->chip.irq_unmask = ioh_irq_unmask;
	ct->chip.irq_set_type = ioh_irq_type;
	ct->chip.irq_disable = ioh_irq_disable;
	ct->chip.irq_enable = ioh_irq_enable;

	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	int ret;
	int i, j;
	struct ioh_gpio *chip;
	void __iomem *base;
	void *chip_save;
	int irq_base;

	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
		goto err_pci_enable;
	}

	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
		goto err_request_regions;
	}

	base = pci_iomap(pdev, 1, 0);
	if (!base) {
		dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
		ret = -ENOMEM;
		goto err_iomap;
	}

	chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
	if (chip_save == NULL) {
		dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
		ret = -ENOMEM;
		goto err_kzalloc;
	}

	chip = chip_save;
	for (i = 0; i < 8; i++, chip++) {
		chip->dev = &pdev->dev;
		chip->base = base;
		chip->reg = chip->base;
		chip->ch = i;
		mutex_init(&chip->lock);
		spin_lock_init(&chip->spinlock);
		ioh_gpio_setup(chip, num_ports[i]);
		ret = gpiochip_add(&chip->gpio);
		if (ret) {
			dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
			goto err_gpiochip_add;
		}
	}

	chip = chip_save;
	for (j = 0; j < 8; j++, chip++) {
		irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
					   NUMA_NO_NODE);
		if (irq_base < 0) {
			dev_warn(&pdev->dev,
				"ml_ioh_gpio: Failed to get IRQ base num\n");
			chip->irq_base = -1;
			goto err_irq_alloc_descs;
		}
		chip->irq_base = irq_base;
		ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
	}

	chip = chip_save;
	ret = request_irq(pdev->irq, ioh_gpio_handler,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev,
			"%s request_irq failed\n", __func__);
		goto err_request_irq;
	}

	pci_set_drvdata(pdev, chip);

	return 0;

err_request_irq:
	chip = chip_save;
err_irq_alloc_descs:
	while (--j >= 0) {
		chip--;
		irq_free_descs(chip->irq_base, num_ports[j]);
	}

	chip = chip_save;
err_gpiochip_add:
	while (--i >= 0) {
		chip--;
		ret = gpiochip_remove(&chip->gpio);
		if (ret)
			dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
	}
	kfree(chip_save);

err_kzalloc:
	pci_iounmap(pdev, base);

err_iomap:
	pci_release_regions(pdev);

err_request_regions:
	pci_disable_device(pdev);

err_pci_enable:

	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	return ret;
}

static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
{
	int err;
	int i;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	void *chip_save;

	chip_save = chip;

	free_irq(pdev->irq, chip);

	for (i = 0; i < 8; i++, chip++) {
		irq_free_descs(chip->irq_base, num_ports[i]);
		err = gpiochip_remove(&chip->gpio);
		if (err)
			dev_err(&pdev->dev, "Failed gpiochip_remove\n");
	}

	chip = chip_save;
	pci_iounmap(pdev, chip->base);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	kfree(chip);
}

#ifdef CONFIG_PM
static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
{
	s32 ret;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	ioh_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	ret = pci_save_state(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
		return ret;
	}
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_wake(pdev, PCI_D0, 1);
	if (ret)
		dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);

	return 0;
}

static int ioh_gpio_resume(struct pci_dev *pdev)
{
	s32 ret;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	ret = pci_enable_wake(pdev, PCI_D0, 0);

	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
		return ret;
	}
	pci_restore_state(pdev);

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->srst);
	iowrite32(0x00, &chip->reg->srst);
	ioh_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}
#else
#define ioh_gpio_suspend NULL
#define ioh_gpio_resume NULL
#endif

static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);

static struct pci_driver ioh_gpio_driver = {
	.name = "ml_ioh_gpio",
	.id_table = ioh_gpio_pcidev_id,
	.probe = ioh_gpio_probe,
	.remove = __devexit_p(ioh_gpio_remove),
	.suspend = ioh_gpio_suspend,
	.resume = ioh_gpio_resume
};

module_pci_driver(ioh_gpio_driver);

MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
49a36793 TM	1	/*
	2	* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2 of the License.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
	16	*/
bb207ef1	17	#include <linux/module.h>
49a36793	18	#include <linux/kernel.h>
545554e7	19	#include <linux/slab.h>
49a36793 TM	20	#include <linux/pci.h>
49a36793 TM	21	#include <linux/gpio.h>
54be5663 TM	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24
	25	#define IOH_EDGE_FALLING 0
	26	#define IOH_EDGE_RISING BIT(0)
	27	#define IOH_LEVEL_L BIT(1)
	28	#define IOH_LEVEL_H (BIT(0) \| BIT(1))
	29	#define IOH_EDGE_BOTH BIT(2)
	30	#define IOH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
	31
	32	#define IOH_IRQ_BASE 0
49a36793 TM	33
	34	#define PCI_VENDOR_ID_ROHM 0x10DB
	35
	36	struct ioh_reg_comn {
	37	u32 ien;
	38	u32 istatus;
	39	u32 idisp;
	40	u32 iclr;
	41	u32 imask;
	42	u32 imaskclr;
	43	u32 po;
	44	u32 pi;
	45	u32 pm;
	46	u32 im_0;
	47	u32 im_1;
	48	u32 reserved;
	49	};
	50
	51	struct ioh_regs {
	52	struct ioh_reg_comn regs[8];
	53	u32 reserve1[16];
	54	u32 ioh_sel_reg[4];
	55	u32 reserve2[11];
	56	u32 srst;
	57	};
	58
	59	/**
	60	* struct ioh_gpio_reg_data - The register store data.
54be5663 TM	61	* @ien_reg To store contents of interrupt enable register.
54be5663 TM	62	* @imask_reg: To store contents of interrupt mask regist
49a36793 TM	63	* @po_reg: To store contents of PO register.
49a36793 TM	64	* @pm_reg: To store contents of PM register.
54be5663 TM	65	* @im0_reg: To store contents of interrupt mode regist0
54be5663 TM	66	* @im1_reg: To store contents of interrupt mode regist1
b490fa0b	67	* @use_sel_reg: To store contents of GPIO_USE_SEL0~3
49a36793 TM	68	*/
49a36793 TM	69	struct ioh_gpio_reg_data {
54be5663 TM	70	u32 ien_reg;
54be5663 TM	71	u32 imask_reg;
49a36793 TM	72	u32 po_reg;
49a36793 TM	73	u32 pm_reg;
54be5663 TM	74	u32 im0_reg;
54be5663 TM	75	u32 im1_reg;
b490fa0b	76	u32 use_sel_reg;
49a36793 TM	77	};
	78
	79	/**
	80	* struct ioh_gpio - GPIO private data structure.
	81	* @base: PCI base address of Memory mapped I/O register.
	82	* @reg: Memory mapped IOH GPIO register list.
	83	* @dev: Pointer to device structure.
	84	* @gpio: Data for GPIO infrastructure.
	85	* @ioh_gpio_reg: Memory mapped Register data is saved here
	86	* when suspend.
b490fa0b	87	* @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
49a36793	88	* @ch: Indicate GPIO channel
54be5663 TM	89	* @irq_base: Save base of IRQ number for interrupt
	90	* @spinlock: Used for register access protection in
	91	* interrupt context ioh_irq_type and PM;
49a36793 TM	92	*/
	93	struct ioh_gpio {
	94	void __iomem *base;
	95	struct ioh_regs __iomem *reg;
	96	struct device *dev;
	97	struct gpio_chip gpio;
	98	struct ioh_gpio_reg_data ioh_gpio_reg;
b490fa0b	99	u32 gpio_use_sel;
49a36793 TM	100	struct mutex lock;
49a36793 TM	101	int ch;
54be5663 TM	102	int irq_base;
54be5663 TM	103	spinlock_t spinlock;
49a36793 TM	104	};
	105
	106	static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
	107
	108	static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	109	{
	110	u32 reg_val;
	111	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	112
	113	mutex_lock(&chip->lock);
	114	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	115	if (val)
	116	reg_val \|= (1 << nr);
	117	else
	118	reg_val &= ~(1 << nr);
	119
	120	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
	121	mutex_unlock(&chip->lock);
	122	}
	123
	124	static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
	125	{
	126	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	127
	128	return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
	129	}
	130
	131	static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	132	int val)
	133	{
	134	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	135	u32 pm;
	136	u32 reg_val;
	137
	138	mutex_lock(&chip->lock);
	139	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
	140	((1 << num_ports[chip->ch]) - 1);
	141	pm \|= (1 << nr);
	142	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	143
	144	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	145	if (val)
	146	reg_val \|= (1 << nr);
	147	else
	148	reg_val &= ~(1 << nr);
ba438612	149	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
49a36793 TM	150
	151	mutex_unlock(&chip->lock);
	152
	153	return 0;
	154	}
	155
	156	static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	157	{
	158	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	159	u32 pm;
	160
	161	mutex_lock(&chip->lock);
	162	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
	163	((1 << num_ports[chip->ch]) - 1);
	164	pm &= ~(1 << nr);
	165	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	166	mutex_unlock(&chip->lock);
	167
	168	return 0;
	169	}
	170
545554e7	171	#ifdef CONFIG_PM
49a36793 TM	172	/*
	173	* Save register configuration and disable interrupts.
	174	*/
	175	static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
	176	{
b490fa0b TM	177	int i;
	178
	179	for (i = 0; i < 8; i ++, chip++) {
	180	chip->ioh_gpio_reg.po_reg =
	181	ioread32(&chip->reg->regs[chip->ch].po);
	182	chip->ioh_gpio_reg.pm_reg =
	183	ioread32(&chip->reg->regs[chip->ch].pm);
	184	chip->ioh_gpio_reg.ien_reg =
	185	ioread32(&chip->reg->regs[chip->ch].ien);
	186	chip->ioh_gpio_reg.imask_reg =
	187	ioread32(&chip->reg->regs[chip->ch].imask);
	188	chip->ioh_gpio_reg.im0_reg =
	189	ioread32(&chip->reg->regs[chip->ch].im_0);
	190	chip->ioh_gpio_reg.im1_reg =
	191	ioread32(&chip->reg->regs[chip->ch].im_1);
	192	if (i < 4)
	193	chip->ioh_gpio_reg.use_sel_reg =
	194	ioread32(&chip->reg->ioh_sel_reg[i]);
	195	}
49a36793 TM	196	}
	197
	198	/*
	199	* This function restores the register configuration of the GPIO device.
	200	*/
	201	static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
	202	{
b490fa0b TM	203	int i;
	204
	205	for (i = 0; i < 8; i ++, chip++) {
	206	iowrite32(chip->ioh_gpio_reg.po_reg,
	207	&chip->reg->regs[chip->ch].po);
	208	iowrite32(chip->ioh_gpio_reg.pm_reg,
	209	&chip->reg->regs[chip->ch].pm);
	210	iowrite32(chip->ioh_gpio_reg.ien_reg,
	211	&chip->reg->regs[chip->ch].ien);
	212	iowrite32(chip->ioh_gpio_reg.imask_reg,
	213	&chip->reg->regs[chip->ch].imask);
	214	iowrite32(chip->ioh_gpio_reg.im0_reg,
	215	&chip->reg->regs[chip->ch].im_0);
	216	iowrite32(chip->ioh_gpio_reg.im1_reg,
	217	&chip->reg->regs[chip->ch].im_1);
	218	if (i < 4)
	219	iowrite32(chip->ioh_gpio_reg.use_sel_reg,
	220	&chip->reg->ioh_sel_reg[i]);
	221	}
49a36793	222	}
545554e7	223	#endif
49a36793	224
54be5663 TM	225	static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	226	{
	227	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	228	return chip->irq_base + offset;
	229	}
	230
49a36793 TM	231	static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
	232	{
	233	struct gpio_chip *gpio = &chip->gpio;
	234
	235	gpio->label = dev_name(chip->dev);
	236	gpio->owner = THIS_MODULE;
	237	gpio->direction_input = ioh_gpio_direction_input;
	238	gpio->get = ioh_gpio_get;
	239	gpio->direction_output = ioh_gpio_direction_output;
	240	gpio->set = ioh_gpio_set;
	241	gpio->dbg_show = NULL;
	242	gpio->base = -1;
	243	gpio->ngpio = num_port;
	244	gpio->can_sleep = 0;
54be5663 TM	245	gpio->to_irq = ioh_gpio_to_irq;
	246	}
	247
	248	static int ioh_irq_type(struct irq_data *d, unsigned int type)
	249	{
	250	u32 im;
dd9328a6	251	void __iomem *im_reg;
54be5663 TM	252	u32 ien;
	253	u32 im_pos;
	254	int ch;
	255	unsigned long flags;
	256	u32 val;
	257	int irq = d->irq;
	258	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	259	struct ioh_gpio *chip = gc->private;
	260
	261	ch = irq - chip->irq_base;
	262	if (irq <= chip->irq_base + 7) {
	263	im_reg = &chip->reg->regs[chip->ch].im_0;
	264	im_pos = ch;
	265	} else {
	266	im_reg = &chip->reg->regs[chip->ch].im_1;
	267	im_pos = ch - 8;
	268	}
	269	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
	270	__func__, irq, type, ch, im_pos, type);
	271
	272	spin_lock_irqsave(&chip->spinlock, flags);
	273
	274	switch (type) {
	275	case IRQ_TYPE_EDGE_RISING:
	276	val = IOH_EDGE_RISING;
	277	break;
	278	case IRQ_TYPE_EDGE_FALLING:
	279	val = IOH_EDGE_FALLING;
	280	break;
	281	case IRQ_TYPE_EDGE_BOTH:
	282	val = IOH_EDGE_BOTH;
	283	break;
	284	case IRQ_TYPE_LEVEL_HIGH:
	285	val = IOH_LEVEL_H;
	286	break;
	287	case IRQ_TYPE_LEVEL_LOW:
	288	val = IOH_LEVEL_L;
	289	break;
	290	case IRQ_TYPE_PROBE:
	291	goto end;
	292	default:
	293	dev_warn(chip->dev, "%s: unknown type(%dd)",
	294	__func__, type);
	295	goto end;
	296	}
	297
	298	/* Set interrupt mode */
	299	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
	300	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	301
	302	/* iclr */
	303	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
	304
	305	/* IMASKCLR */
	306	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
	307
	308	/* Enable interrupt */
	309	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	310	iowrite32(ien \| BIT(ch), &chip->reg->regs[chip->ch].ien);
	311	end:
	312	spin_unlock_irqrestore(&chip->spinlock, flags);
	313
	314	return 0;
	315	}
316
317	static void ioh_irq_unmask(struct irq_data *d)
318	{
319	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
320	struct ioh_gpio *chip = gc->private;
321
322	iowrite32(1 << (d->irq - chip->irq_base),
323	&chip->reg->regs[chip->ch].imaskclr);
324	}
325
326	static void ioh_irq_mask(struct irq_data *d)
327	{
328	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
329	struct ioh_gpio *chip = gc->private;
330
331	iowrite32(1 << (d->irq - chip->irq_base),
332	&chip->reg->regs[chip->ch].imask);
333	}
334
4d052213 FT	335	static void ioh_irq_disable(struct irq_data *d)
	336	{
	337	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	338	struct ioh_gpio *chip = gc->private;
	339	unsigned long flags;
	340	u32 ien;
	341
	342	spin_lock_irqsave(&chip->spinlock, flags);
	343	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	344	ien &= ~(1 << (d->irq - chip->irq_base));
	345	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	346	spin_unlock_irqrestore(&chip->spinlock, flags);
	347	}
	348
	349	static void ioh_irq_enable(struct irq_data *d)
	350	{
	351	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	352	struct ioh_gpio *chip = gc->private;
	353	unsigned long flags;
	354	u32 ien;
	355
	356	spin_lock_irqsave(&chip->spinlock, flags);
	357	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	358	ien \|= 1 << (d->irq - chip->irq_base);
	359	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
	360	spin_unlock_irqrestore(&chip->spinlock, flags);
	361	}
	362
54be5663 TM	363	static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
	364	{
	365	struct ioh_gpio *chip = dev_id;
	366	u32 reg_val;
	367	int i, j;
	368	int ret = IRQ_NONE;
	369
f9ea14ef	370	for (i = 0; i < 8; i++, chip++) {
54be5663 TM	371	reg_val = ioread32(&chip->reg->regs[i].istatus);
	372	for (j = 0; j < num_ports[i]; j++) {
	373	if (reg_val & BIT(j)) {
	374	dev_dbg(chip->dev,
	375	"%s:[%d]:irq=%d status=0x%x\n",
	376	__func__, j, irq, reg_val);
	377	iowrite32(BIT(j),
	378	&chip->reg->regs[chip->ch].iclr);
	379	generic_handle_irq(chip->irq_base + j);
	380	ret = IRQ_HANDLED;
	381	}
	382	}
	383	}
	384	return ret;
	385	}
	386
	387	static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
	388	unsigned int irq_start, unsigned int num)
	389	{
	390	struct irq_chip_generic *gc;
	391	struct irq_chip_type *ct;
	392
	393	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
	394	handle_simple_irq);
	395	gc->private = chip;
	396	ct = gc->chip_types;
	397
	398	ct->chip.irq_mask = ioh_irq_mask;
	399	ct->chip.irq_unmask = ioh_irq_unmask;
	400	ct->chip.irq_set_type = ioh_irq_type;
4d052213 FT	401	ct->chip.irq_disable = ioh_irq_disable;
4d052213 FT	402	ct->chip.irq_enable = ioh_irq_enable;
54be5663 TM	403
	404	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	405	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
49a36793 TM	406	}
	407
	408	static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
	409	const struct pci_device_id *id)
	410	{
	411	int ret;
54be5663	412	int i, j;
49a36793 TM	413	struct ioh_gpio *chip;
49a36793 TM	414	void __iomem *base;
dd9328a6	415	void *chip_save;
54be5663	416	int irq_base;
49a36793 TM	417
	418	ret = pci_enable_device(pdev);
	419	if (ret) {
	420	dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
	421	goto err_pci_enable;
	422	}
	423
	424	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	425	if (ret) {
	426	dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
	427	goto err_request_regions;
	428	}
	429
	430	base = pci_iomap(pdev, 1, 0);
2bd1c85e	431	if (!base) {
49a36793 TM	432	dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
	433	ret = -ENOMEM;
	434	goto err_iomap;
	435	}
	436
	437	chip_save = kzalloc(sizeof(chip) 8, GFP_KERNEL);
	438	if (chip_save == NULL) {
	439	dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
	440	ret = -ENOMEM;
	441	goto err_kzalloc;
	442	}
	443
	444	chip = chip_save;
	445	for (i = 0; i < 8; i++, chip++) {
	446	chip->dev = &pdev->dev;
	447	chip->base = base;
	448	chip->reg = chip->base;
	449	chip->ch = i;
	450	mutex_init(&chip->lock);
7e3a70fb	451	spin_lock_init(&chip->spinlock);
49a36793 TM	452	ioh_gpio_setup(chip, num_ports[i]);
	453	ret = gpiochip_add(&chip->gpio);
	454	if (ret) {
	455	dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
	456	goto err_gpiochip_add;
	457	}
	458	}
	459
	460	chip = chip_save;
54be5663 TM	461	for (j = 0; j < 8; j++, chip++) {
54be5663 TM	462	irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
a7aaa4f8	463	NUMA_NO_NODE);
54be5663 TM	464	if (irq_base < 0) {
	465	dev_warn(&pdev->dev,
	466	"ml_ioh_gpio: Failed to get IRQ base num\n");
	467	chip->irq_base = -1;
	468	goto err_irq_alloc_descs;
	469	}
	470	chip->irq_base = irq_base;
	471	ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
	472	}
	473
	474	chip = chip_save;
	475	ret = request_irq(pdev->irq, ioh_gpio_handler,
	476	IRQF_SHARED, KBUILD_MODNAME, chip);
	477	if (ret != 0) {
	478	dev_err(&pdev->dev,
	479	"%s request_irq failed\n", __func__);
	480	goto err_request_irq;
	481	}
	482
49a36793 TM	483	pci_set_drvdata(pdev, chip);
	484
	485	return 0;
	486
54be5663 TM	487	err_request_irq:
	488	chip = chip_save;
	489	err_irq_alloc_descs:
	490	while (--j >= 0) {
	491	chip--;
	492	irq_free_descs(chip->irq_base, num_ports[j]);
	493	}
	494
	495	chip = chip_save;
49a36793	496	err_gpiochip_add:
33300571	497	while (--i >= 0) {
49a36793 TM	498	chip--;
	499	ret = gpiochip_remove(&chip->gpio);
	500	if (ret)
	501	dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
	502	}
	503	kfree(chip_save);
	504
	505	err_kzalloc:
	506	pci_iounmap(pdev, base);
	507
	508	err_iomap:
	509	pci_release_regions(pdev);
	510
	511	err_request_regions:
	512	pci_disable_device(pdev);
	513
	514	err_pci_enable:
	515
	516	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	517	return ret;
	518	}
	519
	520	static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
	521	{
	522	int err;
	523	int i;
	524	struct ioh_gpio *chip = pci_get_drvdata(pdev);
dd9328a6	525	void *chip_save;
49a36793 TM	526
49a36793 TM	527	chip_save = chip;
54be5663 TM	528
	529	free_irq(pdev->irq, chip);
	530
49a36793	531	for (i = 0; i < 8; i++, chip++) {
54be5663	532	irq_free_descs(chip->irq_base, num_ports[i]);
49a36793 TM	533	err = gpiochip_remove(&chip->gpio);
	534	if (err)
	535	dev_err(&pdev->dev, "Failed gpiochip_remove\n");
	536	}
	537
	538	chip = chip_save;
	539	pci_iounmap(pdev, chip->base);
	540	pci_release_regions(pdev);
	541	pci_disable_device(pdev);
	542	kfree(chip);
	543	}
	544
	545	#ifdef CONFIG_PM
	546	static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
	547	{
	548	s32 ret;
	549	struct ioh_gpio *chip = pci_get_drvdata(pdev);
b490fa0b	550	unsigned long flags;
49a36793	551
b490fa0b	552	spin_lock_irqsave(&chip->spinlock, flags);
49a36793	553	ioh_gpio_save_reg_conf(chip);
b490fa0b	554	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	555
	556	ret = pci_save_state(pdev);
	557	if (ret) {
	558	dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
	559	return ret;
	560	}
	561	pci_disable_device(pdev);
	562	pci_set_power_state(pdev, PCI_D0);
	563	ret = pci_enable_wake(pdev, PCI_D0, 1);
	564	if (ret)
	565	dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
	566
	567	return 0;
	568	}
	569
	570	static int ioh_gpio_resume(struct pci_dev *pdev)
	571	{
	572	s32 ret;
	573	struct ioh_gpio *chip = pci_get_drvdata(pdev);
b490fa0b	574	unsigned long flags;
49a36793 TM	575
	576	ret = pci_enable_wake(pdev, PCI_D0, 0);
	577
	578	pci_set_power_state(pdev, PCI_D0);
	579	ret = pci_enable_device(pdev);
	580	if (ret) {
	581	dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
	582	return ret;
	583	}
	584	pci_restore_state(pdev);
	585
b490fa0b	586	spin_lock_irqsave(&chip->spinlock, flags);
49a36793 TM	587	iowrite32(0x01, &chip->reg->srst);
	588	iowrite32(0x00, &chip->reg->srst);
	589	ioh_gpio_restore_reg_conf(chip);
b490fa0b	590	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	591
	592	return 0;
	593	}
	594	#else
	595	#define ioh_gpio_suspend NULL
	596	#define ioh_gpio_resume NULL
	597	#endif
	598
	599	static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
	600	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
	601	{ 0, }
	602	};
19234cdd	603	MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
49a36793 TM	604
	605	static struct pci_driver ioh_gpio_driver = {
	606	.name = "ml_ioh_gpio",
	607	.id_table = ioh_gpio_pcidev_id,
	608	.probe = ioh_gpio_probe,
	609	.remove = __devexit_p(ioh_gpio_remove),
	610	.suspend = ioh_gpio_suspend,
	611	.resume = ioh_gpio_resume
	612	};
	613
93baa65f	614	module_pci_driver(ioh_gpio_driver);
49a36793 TM	615
	616	MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
	617	MODULE_LICENSE("GPL");