projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f8c07de6 HC |
1 | # |
| 2 | # Kconfig for uClinux(non-paged MM) depend configurations | |
| 3 | # Hyok S. Choi <[email protected]> | |
| 4 | # | |
| 5 | ||
| 6 | config SET_MEM_PARAM | |
| 7 | bool "Set flash/sdram size and base addr" | |
| 8 | help | |
| 9 | Say Y to manually set the base addresses and sizes. | |
| 10 | otherwise, the default values are assigned. | |
| 11 | ||
| 12 | config DRAM_BASE | |
| 13 | hex '(S)DRAM Base Address' if SET_MEM_PARAM | |
| 14 | default 0x00800000 | |
| 15 | ||
| 16 | config DRAM_SIZE | |
| 17 | hex '(S)DRAM SIZE' if SET_MEM_PARAM | |
| 18 | default 0x00800000 | |
| 19 | ||
| 20 | config FLASH_MEM_BASE | |
| 21 | hex 'FLASH Base Address' if SET_MEM_PARAM | |
| 22 | default 0x00400000 | |
| 23 | ||
| 24 | config FLASH_SIZE | |
| 25 | hex 'FLASH Size' if SET_MEM_PARAM | |
| 26 | default 0x00400000 | |
| 27 | ||
| f12d0d7c | 28 | config PROCESSOR_ID |
| 7a8be08b | 29 | hex 'Hard wire the processor ID' |
| f12d0d7c | 30 | default 0x00007700 |
| 4477ca45 | 31 | depends on !(CPU_CP15 || CPU_V7M) |
| f12d0d7c HC |
32 | help |
| 33 | If processor has no CP15 register, this processor ID is | |
| 34 | used instead of the auto-probing which utilizes the register. | |
| 35 | ||
| c760fc19 | 36 | config REMAP_VECTORS_TO_RAM |
| 25985edc | 37 | bool 'Install vectors to the beginning of RAM' if DRAM_BASE |
| c760fc19 HC |
38 | depends on DRAM_BASE |
| 39 | help | |
| 40 | The kernel needs to change the hardware exception vectors. | |
| 41 | In nommu mode, the hardware exception vectors are normally | |
| 42 | placed at address 0x00000000. However, this region may be | |
| 43 | occupied by read-only memory depending on H/W design. | |
| 44 | ||
| 45 | If the region contains read-write memory, say 'n' here. | |
| 46 | ||
| 47 | If your CPU provides a remap facility which allows the exception | |
| 48 | vectors to be mapped to writable memory, say 'n' here. | |
| 49 | ||
| 50 | Otherwise, say 'y' here. In this case, the kernel will require | |
| 51 | external support to redirect the hardware exception vectors to | |
| 52 | the writable versions located at DRAM_BASE. | |
| 801bb21c JA |
53 | |
| 54 | config ARM_MPU | |
| 55 | bool 'Use the ARM v7 PMSA Compliant MPU' | |
| de829776 | 56 | depends on CPU_V7 |
| 801bb21c JA |
57 | default y |
| 58 | help | |
| 59 | Some ARM systems without an MMU have instead a Memory Protection | |
| 60 | Unit (MPU) that defines the type and permissions for regions of | |
| 61 | memory. | |
| 62 | ||
| 63 | If your CPU has an MPU then you should choose 'y' here unless you | |
| 64 | know that you do not want to use the MPU. |