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ASoC: rt5677: Fix initialization of rt5677_of_match.data
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
2159ad93
MB		 35#include "wm_adsp.h"
36
37#define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45#define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47
48#define ADSP1_CONTROL_1 0x00
49#define ADSP1_CONTROL_2 0x02
50#define ADSP1_CONTROL_3 0x03
51#define ADSP1_CONTROL_4 0x04
52#define ADSP1_CONTROL_5 0x06
53#define ADSP1_CONTROL_6 0x07
54#define ADSP1_CONTROL_7 0x08
55#define ADSP1_CONTROL_8 0x09
56#define ADSP1_CONTROL_9 0x0A
57#define ADSP1_CONTROL_10 0x0B
58#define ADSP1_CONTROL_11 0x0C
59#define ADSP1_CONTROL_12 0x0D
60#define ADSP1_CONTROL_13 0x0F
61#define ADSP1_CONTROL_14 0x10
62#define ADSP1_CONTROL_15 0x11
63#define ADSP1_CONTROL_16 0x12
64#define ADSP1_CONTROL_17 0x13
65#define ADSP1_CONTROL_18 0x14
66#define ADSP1_CONTROL_19 0x16
67#define ADSP1_CONTROL_20 0x17
68#define ADSP1_CONTROL_21 0x18
69#define ADSP1_CONTROL_22 0x1A
70#define ADSP1_CONTROL_23 0x1B
71#define ADSP1_CONTROL_24 0x1C
72#define ADSP1_CONTROL_25 0x1E
73#define ADSP1_CONTROL_26 0x20
74#define ADSP1_CONTROL_27 0x21
75#define ADSP1_CONTROL_28 0x22
76#define ADSP1_CONTROL_29 0x23
77#define ADSP1_CONTROL_30 0x24
78#define ADSP1_CONTROL_31 0x26
79
80/*
81 * ADSP1 Control 19
82 */
83#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86
87
88/*
89 * ADSP1 Control 30
90 */
91#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103#define ADSP1_START 0x0001 /* DSP1_START */
104#define ADSP1_START_MASK 0x0001 /* DSP1_START */
105#define ADSP1_START_SHIFT 0 /* DSP1_START */
106#define ADSP1_START_WIDTH 1 /* DSP1_START */
107
94e205bf
CR		 108/*
109 * ADSP1 Control 31
110 */
111#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
114
e1ea1879
RF		 115#define ADSP2_CONTROL 0x0
116#define ADSP2_CLOCKING 0x1
117#define ADSP2V2_CLOCKING 0x2
118#define ADSP2_STATUS1 0x4
119#define ADSP2_WDMA_CONFIG_1 0x30
120#define ADSP2_WDMA_CONFIG_2 0x31
121#define ADSP2V2_WDMA_CONFIG_2 0x32
122#define ADSP2_RDMA_CONFIG_1 0x34
123
124#define ADSP2_SCRATCH0 0x40
125#define ADSP2_SCRATCH1 0x41
126#define ADSP2_SCRATCH2 0x42
127#define ADSP2_SCRATCH3 0x43
128
129#define ADSP2V2_SCRATCH0_1 0x40
130#define ADSP2V2_SCRATCH2_3 0x42
10337b07 131
2159ad93
MB		 132/*
133 * ADSP2 Control
134 */
135
136#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
137#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
138#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
139#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
140#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
141#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
142#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
143#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
144#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
145#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
146#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
147#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
148#define ADSP2_START 0x0001 /* DSP1_START */
149#define ADSP2_START_MASK 0x0001 /* DSP1_START */
150#define ADSP2_START_SHIFT 0 /* DSP1_START */
151#define ADSP2_START_WIDTH 1 /* DSP1_START */
152
973838a0
MB		 153/*
154 * ADSP2 clocking
155 */
156#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
157#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
158#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
159
e1ea1879
RF		 160/*
161 * ADSP2V2 clocking
162 */
163#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
164#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
165#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
166
167#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
168#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
169#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
170
2159ad93
MB		 171/*
172 * ADSP2 Status 1
173 */
174#define ADSP2_RAM_RDY 0x0001
175#define ADSP2_RAM_RDY_MASK 0x0001
176#define ADSP2_RAM_RDY_SHIFT 0
177#define ADSP2_RAM_RDY_WIDTH 1
178
51a2c944
MK		 179/*
180 * ADSP2 Lock support
181 */
182#define ADSP2_LOCK_CODE_0 0x5555
183#define ADSP2_LOCK_CODE_1 0xAAAA
184
185#define ADSP2_WATCHDOG 0x0A
186#define ADSP2_BUS_ERR_ADDR 0x52
187#define ADSP2_REGION_LOCK_STATUS 0x64
188#define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
189#define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
190#define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
191#define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
192#define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
193#define ADSP2_LOCK_REGION_CTRL 0x7A
194#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
195
196#define ADSP2_REGION_LOCK_ERR_MASK 0x8000
197#define ADSP2_SLAVE_ERR_MASK 0x4000
198#define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
199#define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
200#define ADSP2_CTRL_ERR_EINT 0x0001
201
202#define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
203#define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
204#define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
205#define ADSP2_PMEM_ERR_ADDR_SHIFT 16
206#define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
207
208#define ADSP2_LOCK_REGION_SHIFT 16
209
9ee78757
CK		 210#define ADSP_MAX_STD_CTRL_SIZE 512
211
f4f0c4c6
RF		 212#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
213#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
a23ebba8
RF		 214#define WM_ADSP_ACKED_CTL_MIN_VALUE 0
215#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
f4f0c4c6
RF		 216
217/*
218 * Event control messages
219 */
220#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
221
cf17c83c
MB		 222struct wm_adsp_buf {
223 struct list_head list;
224 void *buf;
225};
226
227static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
228 struct list_head *list)
229{
230 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
231
232 if (buf == NULL)
233 return NULL;
234
cdcd7f72 235 buf->buf = vmalloc(len);
cf17c83c 236 if (!buf->buf) {
4d41c74d 237 kfree(buf);
cf17c83c
MB		 238 return NULL;
239 }
cdcd7f72 240 memcpy(buf->buf, src, len);
cf17c83c
MB		 241
242 if (list)
243 list_add_tail(&buf->list, list);
244
245 return buf;
246}
247
248static void wm_adsp_buf_free(struct list_head *list)
249{
250 while (!list_empty(list)) {
251 struct wm_adsp_buf *buf = list_first_entry(list,
252 struct wm_adsp_buf,
253 list);
254 list_del(&buf->list);
cdcd7f72 255 vfree(buf->buf);
cf17c83c
MB		 256 kfree(buf);
257 }
258}
259
04d1300f
CK		 260#define WM_ADSP_FW_MBC_VSS 0
261#define WM_ADSP_FW_HIFI 1
262#define WM_ADSP_FW_TX 2
263#define WM_ADSP_FW_TX_SPK 3
264#define WM_ADSP_FW_RX 4
265#define WM_ADSP_FW_RX_ANC 5
266#define WM_ADSP_FW_CTRL 6
267#define WM_ADSP_FW_ASR 7
268#define WM_ADSP_FW_TRACE 8
269#define WM_ADSP_FW_SPK_PROT 9
270#define WM_ADSP_FW_MISC 10
271
272#define WM_ADSP_NUM_FW 11
dd84f925 273
1023dbd9 274static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 275 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
276 [WM_ADSP_FW_HIFI] = "MasterHiFi",
277 [WM_ADSP_FW_TX] = "Tx",
278 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
279 [WM_ADSP_FW_RX] = "Rx",
280 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
281 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
282 [WM_ADSP_FW_ASR] = "ASR Assist",
283 [WM_ADSP_FW_TRACE] = "Dbg Trace",
284 [WM_ADSP_FW_SPK_PROT] = "Protection",
285 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 286};
287
2cd19bdb
CK		 288struct wm_adsp_system_config_xm_hdr {
289 __be32 sys_enable;
290 __be32 fw_id;
291 __be32 fw_rev;
292 __be32 boot_status;
293 __be32 watchdog;
294 __be32 dma_buffer_size;
295 __be32 rdma[6];
296 __be32 wdma[8];
297 __be32 build_job_name[3];
298 __be32 build_job_number;
299};
300
301struct wm_adsp_alg_xm_struct {
302 __be32 magic;
303 __be32 smoothing;
304 __be32 threshold;
305 __be32 host_buf_ptr;
306 __be32 start_seq;
307 __be32 high_water_mark;
308 __be32 low_water_mark;
309 __be64 smoothed_power;
310};
311
312struct wm_adsp_buffer {
313 __be32 X_buf_base; /* XM base addr of first X area */
314 __be32 X_buf_size; /* Size of 1st X area in words */
315 __be32 X_buf_base2; /* XM base addr of 2nd X area */
316 __be32 X_buf_brk; /* Total X size in words */
317 __be32 Y_buf_base; /* YM base addr of Y area */
318 __be32 wrap; /* Total size X and Y in words */
319 __be32 high_water_mark; /* Point at which IRQ is asserted */
320 __be32 irq_count; /* bits 1-31 count IRQ assertions */
321 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
322 __be32 next_write_index; /* word index of next write */
323 __be32 next_read_index; /* word index of next read */
324 __be32 error; /* error if any */
325 __be32 oldest_block_index; /* word index of oldest surviving */
326 __be32 requested_rewind; /* how many blocks rewind was done */
327 __be32 reserved_space; /* internal */
328 __be32 min_free; /* min free space since stream start */
329 __be32 blocks_written[2]; /* total blocks written (64 bit) */
330 __be32 words_written[2]; /* total words written (64 bit) */
331};
332
721be3be
CK		 333struct wm_adsp_compr;
334
2cd19bdb
CK		 335struct wm_adsp_compr_buf {
336 struct wm_adsp *dsp;
721be3be 337 struct wm_adsp_compr *compr;
2cd19bdb
CK		 338
339 struct wm_adsp_buffer_region *regions;
340 u32 host_buf_ptr;
565ace46
CK		 341
342 u32 error;
343 u32 irq_count;
344 int read_index;
345 int avail;
2cd19bdb
CK		 346};
347
406abc95
CK		 348struct wm_adsp_compr {
349 struct wm_adsp *dsp;
95fe9597 350 struct wm_adsp_compr_buf *buf;
406abc95
CK		 351
352 struct snd_compr_stream *stream;
353 struct snd_compressed_buffer size;
565ace46 354
83a40ce9 355 u32 *raw_buf;
565ace46 356 unsigned int copied_total;
da2b3358
CK		 357
358 unsigned int sample_rate;
406abc95
CK		 359};
360
361#define WM_ADSP_DATA_WORD_SIZE 3
362
363#define WM_ADSP_MIN_FRAGMENTS 1
364#define WM_ADSP_MAX_FRAGMENTS 256
365#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
366#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
367
2cd19bdb
CK		 368#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
369
370#define HOST_BUFFER_FIELD(field) \
371 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
372
373#define ALG_XM_FIELD(field) \
374 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
375
376static int wm_adsp_buffer_init(struct wm_adsp *dsp);
377static int wm_adsp_buffer_free(struct wm_adsp *dsp);
378
379struct wm_adsp_buffer_region {
380 unsigned int offset;
381 unsigned int cumulative_size;
382 unsigned int mem_type;
383 unsigned int base_addr;
384};
385
386struct wm_adsp_buffer_region_def {
387 unsigned int mem_type;
388 unsigned int base_offset;
389 unsigned int size_offset;
390};
391
3a9686c4 392static const struct wm_adsp_buffer_region_def default_regions[] = {
2cd19bdb
CK		 393 {
394 .mem_type = WMFW_ADSP2_XM,
395 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
396 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
397 },
398 {
399 .mem_type = WMFW_ADSP2_XM,
400 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
401 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
402 },
403 {
404 .mem_type = WMFW_ADSP2_YM,
405 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
406 .size_offset = HOST_BUFFER_FIELD(wrap),
407 },
408};
409
406abc95
CK		 410struct wm_adsp_fw_caps {
411 u32 id;
412 struct snd_codec_desc desc;
2cd19bdb 413 int num_regions;
3a9686c4 414 const struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 415};
416
e6d00f34 417static const struct wm_adsp_fw_caps ctrl_caps[] = {
406abc95
CK		 418 {
419 .id = SND_AUDIOCODEC_BESPOKE,
420 .desc = {
3bbc2705 421 .max_ch = 8,
406abc95
CK		 422 .sample_rates = { 16000 },
423 .num_sample_rates = 1,
424 .formats = SNDRV_PCM_FMTBIT_S16_LE,
425 },
e6d00f34
CK		 426 .num_regions = ARRAY_SIZE(default_regions),
427 .region_defs = default_regions,
406abc95
CK		 428 },
429};
430
7ce4283c
CK		 431static const struct wm_adsp_fw_caps trace_caps[] = {
432 {
433 .id = SND_AUDIOCODEC_BESPOKE,
434 .desc = {
435 .max_ch = 8,
436 .sample_rates = {
437 4000, 8000, 11025, 12000, 16000, 22050,
438 24000, 32000, 44100, 48000, 64000, 88200,
439 96000, 176400, 192000
440 },
441 .num_sample_rates = 15,
442 .formats = SNDRV_PCM_FMTBIT_S16_LE,
443 },
444 .num_regions = ARRAY_SIZE(default_regions),
445 .region_defs = default_regions,
406abc95
CK		 446 },
447};
448
449static const struct {
1023dbd9 450 const char *file;
406abc95
CK		 451 int compr_direction;
452 int num_caps;
453 const struct wm_adsp_fw_caps *caps;
20b7f7c5 454 bool voice_trigger;
1023dbd9 455} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 456 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
457 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
458 [WM_ADSP_FW_TX] = { .file = "tx" },
459 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
460 [WM_ADSP_FW_RX] = { .file = "rx" },
461 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 462 [WM_ADSP_FW_CTRL] = {
463 .file = "ctrl",
464 .compr_direction = SND_COMPRESS_CAPTURE,
e6d00f34
CK		 465 .num_caps = ARRAY_SIZE(ctrl_caps),
466 .caps = ctrl_caps,
20b7f7c5 467 .voice_trigger = true,
406abc95 468 },
04d1300f 469 [WM_ADSP_FW_ASR] = { .file = "asr" },
7ce4283c
CK		 470 [WM_ADSP_FW_TRACE] = {
471 .file = "trace",
472 .compr_direction = SND_COMPRESS_CAPTURE,
473 .num_caps = ARRAY_SIZE(trace_caps),
474 .caps = trace_caps,
475 },
04d1300f
CK		 476 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
477 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 478};
479
6ab2b7b4
DP		 480struct wm_coeff_ctl_ops {
481 int (*xget)(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol);
483 int (*xput)(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol);
6ab2b7b4
DP		 485};
486
6ab2b7b4
DP		 487struct wm_coeff_ctl {
488 const char *name;
2323736d 489 const char *fw_name;
3809f001 490 struct wm_adsp_alg_region alg_region;
6ab2b7b4 491 struct wm_coeff_ctl_ops ops;
3809f001 492 struct wm_adsp *dsp;
6ab2b7b4
DP		 493 unsigned int enabled:1;
494 struct list_head list;
495 void *cache;
2323736d 496 unsigned int offset;
6ab2b7b4 497 size_t len;
0c2e3f34 498 unsigned int set:1;
9ee78757 499 struct soc_bytes_ext bytes_ext;
26c22a19 500 unsigned int flags;
8eb084d0 501 unsigned int type;
6ab2b7b4
DP		 502};
503
9ce5e6e6
RF		 504static const char *wm_adsp_mem_region_name(unsigned int type)
505{
506 switch (type) {
507 case WMFW_ADSP1_PM:
508 return "PM";
509 case WMFW_ADSP1_DM:
510 return "DM";
511 case WMFW_ADSP2_XM:
512 return "XM";
513 case WMFW_ADSP2_YM:
514 return "YM";
515 case WMFW_ADSP1_ZM:
516 return "ZM";
517 default:
518 return NULL;
519 }
520}
521
f9f55e31
RF		 522#ifdef CONFIG_DEBUG_FS
523static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
524{
525 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
526
f9f55e31
RF		 527 kfree(dsp->wmfw_file_name);
528 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 529}
530
531static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
532{
533 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
534
f9f55e31
RF		 535 kfree(dsp->bin_file_name);
536 dsp->bin_file_name = tmp;
f9f55e31
RF		 537}
538
539static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
540{
f9f55e31
RF		 541 kfree(dsp->wmfw_file_name);
542 kfree(dsp->bin_file_name);
543 dsp->wmfw_file_name = NULL;
544 dsp->bin_file_name = NULL;
f9f55e31
RF		 545}
546
547static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
548 char __user *user_buf,
549 size_t count, loff_t *ppos)
550{
551 struct wm_adsp *dsp = file->private_data;
552 ssize_t ret;
553
078e7183 554 mutex_lock(&dsp->pwr_lock);
f9f55e31 555
28823eba 556 if (!dsp->wmfw_file_name || !dsp->booted)
f9f55e31
RF		 557 ret = 0;
558 else
559 ret = simple_read_from_buffer(user_buf, count, ppos,
560 dsp->wmfw_file_name,
561 strlen(dsp->wmfw_file_name));
562
078e7183 563 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 564 return ret;
565}
566
567static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
568 char __user *user_buf,
569 size_t count, loff_t *ppos)
570{
571 struct wm_adsp *dsp = file->private_data;
572 ssize_t ret;
573
078e7183 574 mutex_lock(&dsp->pwr_lock);
f9f55e31 575
28823eba 576 if (!dsp->bin_file_name || !dsp->booted)
f9f55e31
RF		 577 ret = 0;
578 else
579 ret = simple_read_from_buffer(user_buf, count, ppos,
580 dsp->bin_file_name,
581 strlen(dsp->bin_file_name));
582
078e7183 583 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 584 return ret;
585}
586
587static const struct {
588 const char *name;
589 const struct file_operations fops;
590} wm_adsp_debugfs_fops[] = {
591 {
592 .name = "wmfw_file_name",
593 .fops = {
594 .open = simple_open,
595 .read = wm_adsp_debugfs_wmfw_read,
596 },
597 },
598 {
599 .name = "bin_file_name",
600 .fops = {
601 .open = simple_open,
602 .read = wm_adsp_debugfs_bin_read,
603 },
604 },
605};
606
607static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
0fe1daa6 608 struct snd_soc_component *component)
f9f55e31
RF		 609{
610 struct dentry *root = NULL;
611 char *root_name;
612 int i;
613
0fe1daa6 614 if (!component->debugfs_root) {
f9f55e31
RF		 615 adsp_err(dsp, "No codec debugfs root\n");
616 goto err;
617 }
618
619 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
620 if (!root_name)
621 goto err;
622
623 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
0fe1daa6 624 root = debugfs_create_dir(root_name, component->debugfs_root);
f9f55e31
RF		 625 kfree(root_name);
626
627 if (!root)
628 goto err;
629
6a73cf46 630 if (!debugfs_create_bool("booted", 0444, root, &dsp->booted))
28823eba
CK		 631 goto err;
632
6a73cf46 633 if (!debugfs_create_bool("running", 0444, root, &dsp->running))
f9f55e31
RF		 634 goto err;
635
6a73cf46 636 if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id))
f9f55e31
RF		 637 goto err;
638
6a73cf46 639 if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version))
f9f55e31
RF		 640 goto err;
641
642 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
643 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
6a73cf46 644 0444, root, dsp,
f9f55e31
RF		 645 &wm_adsp_debugfs_fops[i].fops))
646 goto err;
647 }
648
649 dsp->debugfs_root = root;
650 return;
651
652err:
653 debugfs_remove_recursive(root);
654 adsp_err(dsp, "Failed to create debugfs\n");
655}
656
657static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
658{
659 wm_adsp_debugfs_clear(dsp);
660 debugfs_remove_recursive(dsp->debugfs_root);
661}
662#else
663static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
0fe1daa6 664 struct snd_soc_component *component)
f9f55e31
RF		 665{
666}
667
668static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
669{
670}
671
672static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
673 const char *s)
674{
675}
676
677static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
678 const char *s)
679{
680}
681
682static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
683{
684}
685#endif
686
1023dbd9
MB		 687static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
688 struct snd_ctl_elem_value *ucontrol)
689{
0fe1daa6 690 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1023dbd9 691 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0fe1daa6 692 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
1023dbd9 693
15c66570 694 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 695
696 return 0;
697}
698
699static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701{
0fe1daa6 702 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1023dbd9 703 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0fe1daa6 704 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
d27c5e15 705 int ret = 0;
1023dbd9 706
15c66570 707 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 708 return 0;
709
15c66570 710 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
1023dbd9
MB		 711 return -EINVAL;
712
d27c5e15
CK		 713 mutex_lock(&dsp[e->shift_l].pwr_lock);
714
28823eba 715 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
d27c5e15
CK		 716 ret = -EBUSY;
717 else
15c66570 718 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
1023dbd9 719
d27c5e15 720 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 721
d27c5e15 722 return ret;
1023dbd9
MB		 723}
724
725static const struct soc_enum wm_adsp_fw_enum[] = {
726 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
727 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
728 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
729 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
e1ea1879
RF		 730 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
731 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
732 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
1023dbd9
MB		 733};
734
336d0442 735const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 736 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
737 wm_adsp_fw_get, wm_adsp_fw_put),
738 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
739 wm_adsp_fw_get, wm_adsp_fw_put),
740 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
741 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 742 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
743 wm_adsp_fw_get, wm_adsp_fw_put),
e1ea1879
RF		 744 SOC_ENUM_EXT("DSP5 Firmware", wm_adsp_fw_enum[4],
745 wm_adsp_fw_get, wm_adsp_fw_put),
746 SOC_ENUM_EXT("DSP6 Firmware", wm_adsp_fw_enum[5],
747 wm_adsp_fw_get, wm_adsp_fw_put),
748 SOC_ENUM_EXT("DSP7 Firmware", wm_adsp_fw_enum[6],
749 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 750};
336d0442 751EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 752
753static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
754 int type)
755{
756 int i;
757
758 for (i = 0; i < dsp->num_mems; i++)
759 if (dsp->mem[i].type == type)
760 return &dsp->mem[i];
761
762 return NULL;
763}
764
3809f001 765static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 766 unsigned int offset)
767{
3809f001 768 if (WARN_ON(!mem))
6c452bda 769 return offset;
3809f001 770 switch (mem->type) {
45b9ee72 771 case WMFW_ADSP1_PM:
3809f001 772 return mem->base + (offset * 3);
45b9ee72 773 case WMFW_ADSP1_DM:
3809f001 774 return mem->base + (offset * 2);
45b9ee72 775 case WMFW_ADSP2_XM:
3809f001 776 return mem->base + (offset * 2);
45b9ee72 777 case WMFW_ADSP2_YM:
3809f001 778 return mem->base + (offset * 2);
45b9ee72 779 case WMFW_ADSP1_ZM:
3809f001 780 return mem->base + (offset * 2);
45b9ee72 781 default:
6c452bda 782 WARN(1, "Unknown memory region type");
45b9ee72
MB		 783 return offset;
784 }
785}
786
10337b07
RF		 787static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
788{
789 u16 scratch[4];
790 int ret;
791
792 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
793 scratch, sizeof(scratch));
794 if (ret) {
795 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
796 return;
797 }
798
799 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
800 be16_to_cpu(scratch[0]),
801 be16_to_cpu(scratch[1]),
802 be16_to_cpu(scratch[2]),
803 be16_to_cpu(scratch[3]));
804}
805
e1ea1879
RF		 806static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
807{
808 u32 scratch[2];
809 int ret;
810
811 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
812 scratch, sizeof(scratch));
813
814 if (ret) {
815 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
816 return;
817 }
818
819 scratch[0] = be32_to_cpu(scratch[0]);
820 scratch[1] = be32_to_cpu(scratch[1]);
821
822 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
823 scratch[0] & 0xFFFF,
824 scratch[0] >> 16,
825 scratch[1] & 0xFFFF,
826 scratch[1] >> 16);
827}
828
9ee78757
CK		 829static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
830{
831 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
832}
833
b396ebca
RF		 834static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
835{
836 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
837 struct wm_adsp *dsp = ctl->dsp;
838 const struct wm_adsp_region *mem;
839
840 mem = wm_adsp_find_region(dsp, alg_region->type);
841 if (!mem) {
842 adsp_err(dsp, "No base for region %x\n",
843 alg_region->type);
844 return -EINVAL;
845 }
846
847 *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
848
849 return 0;
850}
851
7585a5b0 852static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 853 struct snd_ctl_elem_info *uinfo)
854{
9ee78757
CK		 855 struct soc_bytes_ext *bytes_ext =
856 (struct soc_bytes_ext *)kctl->private_value;
857 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 858
a23ebba8
RF		 859 switch (ctl->type) {
860 case WMFW_CTL_TYPE_ACKED:
861 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
862 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
863 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
864 uinfo->value.integer.step = 1;
865 uinfo->count = 1;
866 break;
867 default:
868 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
869 uinfo->count = ctl->len;
870 break;
871 }
872
6ab2b7b4
DP		 873 return 0;
874}
875
f4f0c4c6
RF		 876static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
877 unsigned int event_id)
878{
879 struct wm_adsp *dsp = ctl->dsp;
880 u32 val = cpu_to_be32(event_id);
881 unsigned int reg;
882 int i, ret;
883
884 ret = wm_coeff_base_reg(ctl, &reg);
885 if (ret)
886 return ret;
887
888 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
889 event_id, ctl->alg_region.alg,
890 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
891
892 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
893 if (ret) {
894 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
895 return ret;
896 }
897
898 /*
899 * Poll for ack, we initially poll at ~1ms intervals for firmwares
900 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
901 * to ack instantly so we do the first 1ms delay before reading the
902 * control to avoid a pointless bus transaction
903 */
904 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
905 switch (i) {
906 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
907 usleep_range(1000, 2000);
908 i++;
909 break;
910 default:
911 usleep_range(10000, 20000);
912 i += 10;
913 break;
914 }
915
916 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
917 if (ret) {
918 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
919 return ret;
920 }
921
922 if (val == 0) {
923 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
924 return 0;
925 }
926 }
927
928 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
929 reg, ctl->alg_region.alg,
930 wm_adsp_mem_region_name(ctl->alg_region.type),
931 ctl->offset);
932
933 return -ETIMEDOUT;
934}
935
c9f8dd71 936static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 937 const void *buf, size_t len)
938{
3809f001 939 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 940 void *scratch;
941 int ret;
942 unsigned int reg;
943
b396ebca
RF		 944 ret = wm_coeff_base_reg(ctl, &reg);
945 if (ret)
946 return ret;
6ab2b7b4 947
4f8ea6d7 948 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 949 if (!scratch)
950 return -ENOMEM;
951
3809f001 952 ret = regmap_raw_write(dsp->regmap, reg, scratch,
4f8ea6d7 953 len);
6ab2b7b4 954 if (ret) {
3809f001 955 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
4f8ea6d7 956 len, reg, ret);
6ab2b7b4
DP		 957 kfree(scratch);
958 return ret;
959 }
4f8ea6d7 960 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
6ab2b7b4
DP		 961
962 kfree(scratch);
963
964 return 0;
965}
966
7585a5b0 967static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 968 struct snd_ctl_elem_value *ucontrol)
969{
9ee78757
CK		 970 struct soc_bytes_ext *bytes_ext =
971 (struct soc_bytes_ext *)kctl->private_value;
972 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 973 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 974 int ret = 0;
975
976 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 977
67430a39
CK		 978 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
979 ret = -EPERM;
980 else
981 memcpy(ctl->cache, p, ctl->len);
6ab2b7b4 982
65d17a9c 983 ctl->set = 1;
cef45771 984 if (ctl->enabled && ctl->dsp->running)
168d10e7 985 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 986
168d10e7
CK		 987 mutex_unlock(&ctl->dsp->pwr_lock);
988
989 return ret;
6ab2b7b4
DP		 990}
991
9ee78757
CK		 992static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
993 const unsigned int __user *bytes, unsigned int size)
994{
995 struct soc_bytes_ext *bytes_ext =
996 (struct soc_bytes_ext *)kctl->private_value;
997 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
998 int ret = 0;
999
1000 mutex_lock(&ctl->dsp->pwr_lock);
1001
1002 if (copy_from_user(ctl->cache, bytes, size)) {
1003 ret = -EFAULT;
1004 } else {
1005 ctl->set = 1;
cef45771 1006 if (ctl->enabled && ctl->dsp->running)
9ee78757 1007 ret = wm_coeff_write_control(ctl, ctl->cache, size);
67430a39
CK		 1008 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1009 ret = -EPERM;
9ee78757
CK		 1010 }
1011
1012 mutex_unlock(&ctl->dsp->pwr_lock);
1013
1014 return ret;
1015}
1016
a23ebba8
RF		 1017static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1018 struct snd_ctl_elem_value *ucontrol)
1019{
1020 struct soc_bytes_ext *bytes_ext =
1021 (struct soc_bytes_ext *)kctl->private_value;
1022 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1023 unsigned int val = ucontrol->value.integer.value[0];
1024 int ret;
1025
1026 if (val == 0)
1027 return 0; /* 0 means no event */
1028
1029 mutex_lock(&ctl->dsp->pwr_lock);
1030
7b4af793 1031 if (ctl->enabled && ctl->dsp->running)
a23ebba8
RF		 1032 ret = wm_coeff_write_acked_control(ctl, val);
1033 else
1034 ret = -EPERM;
1035
1036 mutex_unlock(&ctl->dsp->pwr_lock);
1037
1038 return ret;
1039}
1040
c9f8dd71 1041static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 1042 void *buf, size_t len)
1043{
3809f001 1044 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 1045 void *scratch;
1046 int ret;
1047 unsigned int reg;
1048
b396ebca
RF		 1049 ret = wm_coeff_base_reg(ctl, &reg);
1050 if (ret)
1051 return ret;
6ab2b7b4 1052
4f8ea6d7 1053 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 1054 if (!scratch)
1055 return -ENOMEM;
1056
4f8ea6d7 1057 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
6ab2b7b4 1058 if (ret) {
3809f001 1059 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
5602a643 1060 len, reg, ret);
6ab2b7b4
DP		 1061 kfree(scratch);
1062 return ret;
1063 }
4f8ea6d7 1064 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
6ab2b7b4 1065
4f8ea6d7 1066 memcpy(buf, scratch, len);
6ab2b7b4
DP		 1067 kfree(scratch);
1068
1069 return 0;
1070}
1071
7585a5b0 1072static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 1073 struct snd_ctl_elem_value *ucontrol)
1074{
9ee78757
CK		 1075 struct soc_bytes_ext *bytes_ext =
1076 (struct soc_bytes_ext *)kctl->private_value;
1077 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 1078 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 1079 int ret = 0;
1080
1081 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 1082
26c22a19 1083 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 1084 if (ctl->enabled && ctl->dsp->running)
168d10e7 1085 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 1086 else
168d10e7
CK		 1087 ret = -EPERM;
1088 } else {
cef45771 1089 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
bc1765d6
CK		 1090 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1091
168d10e7 1092 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 1093 }
1094
168d10e7 1095 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 1096
168d10e7 1097 return ret;
6ab2b7b4
DP		 1098}
1099
9ee78757
CK		 1100static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1101 unsigned int __user *bytes, unsigned int size)
1102{
1103 struct soc_bytes_ext *bytes_ext =
1104 (struct soc_bytes_ext *)kctl->private_value;
1105 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1106 int ret = 0;
1107
1108 mutex_lock(&ctl->dsp->pwr_lock);
1109
1110 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 1111 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 1112 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1113 else
1114 ret = -EPERM;
1115 } else {
cef45771 1116 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
9ee78757
CK		 1117 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1118 }
1119
1120 if (!ret && copy_to_user(bytes, ctl->cache, size))
1121 ret = -EFAULT;
1122
1123 mutex_unlock(&ctl->dsp->pwr_lock);
1124
1125 return ret;
1126}
1127
a23ebba8
RF		 1128static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1129 struct snd_ctl_elem_value *ucontrol)
1130{
1131 /*
1132 * Although it's not useful to read an acked control, we must satisfy
1133 * user-side assumptions that all controls are readable and that a
1134 * write of the same value should be filtered out (it's valid to send
1135 * the same event number again to the firmware). We therefore return 0,
1136 * meaning "no event" so valid event numbers will always be a change
1137 */
1138 ucontrol->value.integer.value[0] = 0;
1139
1140 return 0;
1141}
1142
6ab2b7b4 1143struct wmfw_ctl_work {
3809f001 1144 struct wm_adsp *dsp;
6ab2b7b4
DP		 1145 struct wm_coeff_ctl *ctl;
1146 struct work_struct work;
1147};
1148
9ee78757
CK		 1149static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1150{
1151 unsigned int out, rd, wr, vol;
1152
1153 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1154 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1155 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1156 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1157
1158 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1159 } else {
1160 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1161 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1162 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1163
1164 out = 0;
1165 }
1166
1167 if (in) {
1168 if (in & WMFW_CTL_FLAG_READABLE)
1169 out |= rd;
1170 if (in & WMFW_CTL_FLAG_WRITEABLE)
1171 out |= wr;
1172 if (in & WMFW_CTL_FLAG_VOLATILE)
1173 out |= vol;
1174 } else {
1175 out |= rd | wr | vol;
1176 }
1177
1178 return out;
1179}
1180
3809f001 1181static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 1182{
1183 struct snd_kcontrol_new *kcontrol;
1184 int ret;
1185
92bb4c32 1186 if (!ctl || !ctl->name)
6ab2b7b4
DP		 1187 return -EINVAL;
1188
1189 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1190 if (!kcontrol)
1191 return -ENOMEM;
6ab2b7b4
DP		 1192
1193 kcontrol->name = ctl->name;
1194 kcontrol->info = wm_coeff_info;
9ee78757
CK		 1195 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1196 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1197 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
a23ebba8 1198 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
6ab2b7b4 1199
a23ebba8
RF		 1200 switch (ctl->type) {
1201 case WMFW_CTL_TYPE_ACKED:
1202 kcontrol->get = wm_coeff_get_acked;
1203 kcontrol->put = wm_coeff_put_acked;
1204 break;
1205 default:
d7789f5b
RF		 1206 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1207 ctl->bytes_ext.max = ctl->len;
1208 ctl->bytes_ext.get = wm_coeff_tlv_get;
1209 ctl->bytes_ext.put = wm_coeff_tlv_put;
1210 } else {
1211 kcontrol->get = wm_coeff_get;
1212 kcontrol->put = wm_coeff_put;
1213 }
a23ebba8
RF		 1214 break;
1215 }
26c22a19 1216
0fe1daa6 1217 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
6ab2b7b4
DP		 1218 if (ret < 0)
1219 goto err_kcontrol;
1220
1221 kfree(kcontrol);
1222
6ab2b7b4
DP		 1223 return 0;
1224
1225err_kcontrol:
1226 kfree(kcontrol);
1227 return ret;
1228}
1229
b21acc1c
CK		 1230static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1231{
1232 struct wm_coeff_ctl *ctl;
1233 int ret;
1234
1235 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1236 if (!ctl->enabled || ctl->set)
1237 continue;
26c22a19
CK		 1238 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1239 continue;
1240
04ff40a9
RF		 1241 /*
1242 * For readable controls populate the cache from the DSP memory.
1243 * For non-readable controls the cache was zero-filled when
1244 * created so we don't need to do anything.
1245 */
1246 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1247 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1248 if (ret < 0)
1249 return ret;
1250 }
b21acc1c
CK		 1251 }
1252
1253 return 0;
1254}
1255
1256static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1257{
1258 struct wm_coeff_ctl *ctl;
1259 int ret;
1260
1261 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1262 if (!ctl->enabled)
1263 continue;
26c22a19 1264 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
7d00cd97 1265 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1266 if (ret < 0)
1267 return ret;
1268 }
1269 }
1270
1271 return 0;
1272}
1273
f4f0c4c6
RF		 1274static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1275 unsigned int event)
1276{
1277 struct wm_coeff_ctl *ctl;
1278 int ret;
1279
1280 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1281 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1282 continue;
1283
87aa6374
CK		 1284 if (!ctl->enabled)
1285 continue;
1286
f4f0c4c6
RF		 1287 ret = wm_coeff_write_acked_control(ctl, event);
1288 if (ret)
1289 adsp_warn(dsp,
1290 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1291 event, ctl->alg_region.alg, ret);
1292 }
1293}
1294
b21acc1c
CK		 1295static void wm_adsp_ctl_work(struct work_struct *work)
1296{
1297 struct wmfw_ctl_work *ctl_work = container_of(work,
1298 struct wmfw_ctl_work,
1299 work);
1300
1301 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1302 kfree(ctl_work);
1303}
1304
66225e98
RF		 1305static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1306{
1307 kfree(ctl->cache);
1308 kfree(ctl->name);
1309 kfree(ctl);
1310}
1311
b21acc1c
CK		 1312static int wm_adsp_create_control(struct wm_adsp *dsp,
1313 const struct wm_adsp_alg_region *alg_region,
2323736d 1314 unsigned int offset, unsigned int len,
26c22a19 1315 const char *subname, unsigned int subname_len,
8eb084d0 1316 unsigned int flags, unsigned int type)
b21acc1c
CK		 1317{
1318 struct wm_coeff_ctl *ctl;
1319 struct wmfw_ctl_work *ctl_work;
1320 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
9ce5e6e6 1321 const char *region_name;
b21acc1c
CK		 1322 int ret;
1323
9ce5e6e6
RF		 1324 region_name = wm_adsp_mem_region_name(alg_region->type);
1325 if (!region_name) {
2323736d 1326 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 1327 return -EINVAL;
1328 }
1329
cb5b57a9
CK		 1330 switch (dsp->fw_ver) {
1331 case 0:
1332 case 1:
1333 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1334 dsp->num, region_name, alg_region->alg);
1335 break;
1336 default:
1337 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1338 "DSP%d%c %.12s %x", dsp->num, *region_name,
1339 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1340
1341 /* Truncate the subname from the start if it is too long */
1342 if (subname) {
1343 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1344 int skip = 0;
1345
b7ede5af
CK		 1346 if (dsp->component->name_prefix)
1347 avail -= strlen(dsp->component->name_prefix) + 1;
1348
cb5b57a9
CK		 1349 if (subname_len > avail)
1350 skip = subname_len - avail;
1351
1352 snprintf(name + ret,
1353 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1354 subname_len - skip, subname + skip);
1355 }
1356 break;
1357 }
b21acc1c 1358
7585a5b0 1359 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 1360 if (!strcmp(ctl->name, name)) {
1361 if (!ctl->enabled)
1362 ctl->enabled = 1;
1363 return 0;
1364 }
1365 }
1366
1367 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1368 if (!ctl)
1369 return -ENOMEM;
2323736d 1370 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 1371 ctl->alg_region = *alg_region;
1372 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1373 if (!ctl->name) {
1374 ret = -ENOMEM;
1375 goto err_ctl;
1376 }
1377 ctl->enabled = 1;
1378 ctl->set = 0;
1379 ctl->ops.xget = wm_coeff_get;
1380 ctl->ops.xput = wm_coeff_put;
1381 ctl->dsp = dsp;
1382
26c22a19 1383 ctl->flags = flags;
8eb084d0 1384 ctl->type = type;
2323736d 1385 ctl->offset = offset;
b21acc1c
CK		 1386 ctl->len = len;
1387 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1388 if (!ctl->cache) {
1389 ret = -ENOMEM;
1390 goto err_ctl_name;
1391 }
1392
2323736d
CK		 1393 list_add(&ctl->list, &dsp->ctl_list);
1394
8eb084d0
SH		 1395 if (flags & WMFW_CTL_FLAG_SYS)
1396 return 0;
1397
b21acc1c
CK		 1398 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1399 if (!ctl_work) {
1400 ret = -ENOMEM;
1401 goto err_ctl_cache;
1402 }
1403
1404 ctl_work->dsp = dsp;
1405 ctl_work->ctl = ctl;
1406 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1407 schedule_work(&ctl_work->work);
1408
1409 return 0;
1410
1411err_ctl_cache:
1412 kfree(ctl->cache);
1413err_ctl_name:
1414 kfree(ctl->name);
1415err_ctl:
1416 kfree(ctl);
1417
1418 return ret;
1419}
1420
2323736d
CK		 1421struct wm_coeff_parsed_alg {
1422 int id;
1423 const u8 *name;
1424 int name_len;
1425 int ncoeff;
1426};
1427
1428struct wm_coeff_parsed_coeff {
1429 int offset;
1430 int mem_type;
1431 const u8 *name;
1432 int name_len;
1433 int ctl_type;
1434 int flags;
1435 int len;
1436};
1437
cb5b57a9
CK		 1438static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1439{
1440 int length;
1441
1442 switch (bytes) {
1443 case 1:
1444 length = **pos;
1445 break;
1446 case 2:
8299ee81 1447 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1448 break;
1449 default:
1450 return 0;
1451 }
1452
1453 if (str)
1454 *str = *pos + bytes;
1455
1456 *pos += ((length + bytes) + 3) & ~0x03;
1457
1458 return length;
1459}
1460
1461static int wm_coeff_parse_int(int bytes, const u8 **pos)
1462{
1463 int val = 0;
1464
1465 switch (bytes) {
1466 case 2:
8299ee81 1467 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1468 break;
1469 case 4:
8299ee81 1470 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1471 break;
1472 default:
1473 break;
1474 }
1475
1476 *pos += bytes;
1477
1478 return val;
1479}
1480
2323736d
CK		 1481static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1482 struct wm_coeff_parsed_alg *blk)
1483{
1484 const struct wmfw_adsp_alg_data *raw;
1485
cb5b57a9
CK		 1486 switch (dsp->fw_ver) {
1487 case 0:
1488 case 1:
1489 raw = (const struct wmfw_adsp_alg_data *)*data;
1490 *data = raw->data;
2323736d 1491
cb5b57a9
CK		 1492 blk->id = le32_to_cpu(raw->id);
1493 blk->name = raw->name;
1494 blk->name_len = strlen(raw->name);
1495 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1496 break;
1497 default:
1498 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1499 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1500 &blk->name);
1501 wm_coeff_parse_string(sizeof(u16), data, NULL);
1502 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1503 break;
1504 }
2323736d
CK		 1505
1506 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1507 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1508 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1509}
1510
1511static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1512 struct wm_coeff_parsed_coeff *blk)
1513{
1514 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1515 const u8 *tmp;
1516 int length;
2323736d 1517
cb5b57a9
CK		 1518 switch (dsp->fw_ver) {
1519 case 0:
1520 case 1:
1521 raw = (const struct wmfw_adsp_coeff_data *)*data;
1522 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1523
1524 blk->offset = le16_to_cpu(raw->hdr.offset);
1525 blk->mem_type = le16_to_cpu(raw->hdr.type);
1526 blk->name = raw->name;
1527 blk->name_len = strlen(raw->name);
1528 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1529 blk->flags = le16_to_cpu(raw->flags);
1530 blk->len = le32_to_cpu(raw->len);
1531 break;
1532 default:
1533 tmp = *data;
1534 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1535 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1536 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1537 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1538 &blk->name);
1539 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1540 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1541 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1542 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1543 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1544
1545 *data = *data + sizeof(raw->hdr) + length;
1546 break;
1547 }
2323736d
CK		 1548
1549 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1550 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1551 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1552 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1553 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1554 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1555}
1556
f4f0c4c6
RF		 1557static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1558 const struct wm_coeff_parsed_coeff *coeff_blk,
1559 unsigned int f_required,
1560 unsigned int f_illegal)
1561{
1562 if ((coeff_blk->flags & f_illegal) ||
1563 ((coeff_blk->flags & f_required) != f_required)) {
1564 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1565 coeff_blk->flags, coeff_blk->ctl_type);
1566 return -EINVAL;
1567 }
1568
1569 return 0;
1570}
1571
2323736d
CK		 1572static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1573 const struct wmfw_region *region)
1574{
1575 struct wm_adsp_alg_region alg_region = {};
1576 struct wm_coeff_parsed_alg alg_blk;
1577 struct wm_coeff_parsed_coeff coeff_blk;
1578 const u8 *data = region->data;
1579 int i, ret;
1580
1581 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1582 for (i = 0; i < alg_blk.ncoeff; i++) {
1583 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1584
1585 switch (coeff_blk.ctl_type) {
1586 case SNDRV_CTL_ELEM_TYPE_BYTES:
1587 break;
a23ebba8
RF		 1588 case WMFW_CTL_TYPE_ACKED:
1589 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1590 continue; /* ignore */
1591
1592 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1593 WMFW_CTL_FLAG_VOLATILE |
1594 WMFW_CTL_FLAG_WRITEABLE |
1595 WMFW_CTL_FLAG_READABLE,
1596 0);
1597 if (ret)
1598 return -EINVAL;
1599 break;
f4f0c4c6
RF		 1600 case WMFW_CTL_TYPE_HOSTEVENT:
1601 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1602 WMFW_CTL_FLAG_SYS |
1603 WMFW_CTL_FLAG_VOLATILE |
1604 WMFW_CTL_FLAG_WRITEABLE |
1605 WMFW_CTL_FLAG_READABLE,
1606 0);
1607 if (ret)
1608 return -EINVAL;
1609 break;
d52ed4b0
RF		 1610 case WMFW_CTL_TYPE_HOST_BUFFER:
1611 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1612 WMFW_CTL_FLAG_SYS |
1613 WMFW_CTL_FLAG_VOLATILE |
1614 WMFW_CTL_FLAG_READABLE,
1615 0);
1616 if (ret)
1617 return -EINVAL;
1618 break;
2323736d
CK		 1619 default:
1620 adsp_err(dsp, "Unknown control type: %d\n",
1621 coeff_blk.ctl_type);
1622 return -EINVAL;
1623 }
1624
1625 alg_region.type = coeff_blk.mem_type;
1626 alg_region.alg = alg_blk.id;
1627
1628 ret = wm_adsp_create_control(dsp, &alg_region,
1629 coeff_blk.offset,
1630 coeff_blk.len,
1631 coeff_blk.name,
26c22a19 1632 coeff_blk.name_len,
8eb084d0
SH		 1633 coeff_blk.flags,
1634 coeff_blk.ctl_type);
2323736d
CK		 1635 if (ret < 0)
1636 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1637 coeff_blk.name_len, coeff_blk.name, ret);
1638 }
1639
1640 return 0;
1641}
1642
2159ad93
MB		 1643static int wm_adsp_load(struct wm_adsp *dsp)
1644{
cf17c83c 1645 LIST_HEAD(buf_list);
2159ad93
MB		 1646 const struct firmware *firmware;
1647 struct regmap *regmap = dsp->regmap;
1648 unsigned int pos = 0;
1649 const struct wmfw_header *header;
1650 const struct wmfw_adsp1_sizes *adsp1_sizes;
1651 const struct wmfw_adsp2_sizes *adsp2_sizes;
1652 const struct wmfw_footer *footer;
1653 const struct wmfw_region *region;
1654 const struct wm_adsp_region *mem;
1655 const char *region_name;
1cab2a84 1656 char *file, *text = NULL;
cf17c83c 1657 struct wm_adsp_buf *buf;
2159ad93
MB		 1658 unsigned int reg;
1659 int regions = 0;
1660 int ret, offset, type, sizes;
1661
1662 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1663 if (file == NULL)
1664 return -ENOMEM;
1665
1023dbd9
MB		 1666 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1667 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1668 file[PAGE_SIZE - 1] = '\0';
1669
1670 ret = request_firmware(&firmware, file, dsp->dev);
1671 if (ret != 0) {
1672 adsp_err(dsp, "Failed to request '%s'\n", file);
1673 goto out;
1674 }
1675 ret = -EINVAL;
1676
1677 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1678 if (pos >= firmware->size) {
1679 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1680 file, firmware->size);
1681 goto out_fw;
1682 }
1683
7585a5b0 1684 header = (void *)&firmware->data[0];
2159ad93
MB		 1685
1686 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1687 adsp_err(dsp, "%s: invalid magic\n", file);
1688 goto out_fw;
1689 }
1690
2323736d
CK		 1691 switch (header->ver) {
1692 case 0:
c61e59fe
CK		 1693 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1694 file, header->ver);
1695 break;
2323736d 1696 case 1:
cb5b57a9 1697 case 2:
2323736d
CK		 1698 break;
1699 default:
2159ad93
MB		 1700 adsp_err(dsp, "%s: unknown file format %d\n",
1701 file, header->ver);
1702 goto out_fw;
1703 }
2323736d 1704
3626992a 1705 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1706 dsp->fw_ver = header->ver;
2159ad93
MB		 1707
1708 if (header->core != dsp->type) {
1709 adsp_err(dsp, "%s: invalid core %d != %d\n",
1710 file, header->core, dsp->type);
1711 goto out_fw;
1712 }
1713
1714 switch (dsp->type) {
1715 case WMFW_ADSP1:
1716 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1717 adsp1_sizes = (void *)&(header[1]);
1718 footer = (void *)&(adsp1_sizes[1]);
1719 sizes = sizeof(*adsp1_sizes);
1720
1721 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1722 file, le32_to_cpu(adsp1_sizes->dm),
1723 le32_to_cpu(adsp1_sizes->pm),
1724 le32_to_cpu(adsp1_sizes->zm));
1725 break;
1726
1727 case WMFW_ADSP2:
1728 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1729 adsp2_sizes = (void *)&(header[1]);
1730 footer = (void *)&(adsp2_sizes[1]);
1731 sizes = sizeof(*adsp2_sizes);
1732
1733 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1734 file, le32_to_cpu(adsp2_sizes->xm),
1735 le32_to_cpu(adsp2_sizes->ym),
1736 le32_to_cpu(adsp2_sizes->pm),
1737 le32_to_cpu(adsp2_sizes->zm));
1738 break;
1739
1740 default:
6c452bda 1741 WARN(1, "Unknown DSP type");
2159ad93
MB		 1742 goto out_fw;
1743 }
1744
1745 if (le32_to_cpu(header->len) != sizeof(*header) +
1746 sizes + sizeof(*footer)) {
1747 adsp_err(dsp, "%s: unexpected header length %d\n",
1748 file, le32_to_cpu(header->len));
1749 goto out_fw;
1750 }
1751
1752 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1753 le64_to_cpu(footer->timestamp));
1754
1755 while (pos < firmware->size &&
50dd2ea8 1756 sizeof(*region) < firmware->size - pos) {
2159ad93
MB		 1757 region = (void *)&(firmware->data[pos]);
1758 region_name = "Unknown";
1759 reg = 0;
1760 text = NULL;
1761 offset = le32_to_cpu(region->offset) & 0xffffff;
1762 type = be32_to_cpu(region->type) & 0xff;
1763 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1764
2159ad93
MB		 1765 switch (type) {
1766 case WMFW_NAME_TEXT:
1767 region_name = "Firmware name";
1768 text = kzalloc(le32_to_cpu(region->len) + 1,
1769 GFP_KERNEL);
1770 break;
2323736d
CK		 1771 case WMFW_ALGORITHM_DATA:
1772 region_name = "Algorithm";
1773 ret = wm_adsp_parse_coeff(dsp, region);
1774 if (ret != 0)
1775 goto out_fw;
1776 break;
2159ad93
MB		 1777 case WMFW_INFO_TEXT:
1778 region_name = "Information";
1779 text = kzalloc(le32_to_cpu(region->len) + 1,
1780 GFP_KERNEL);
1781 break;
1782 case WMFW_ABSOLUTE:
1783 region_name = "Absolute";
1784 reg = offset;
1785 break;
1786 case WMFW_ADSP1_PM:
2159ad93 1787 case WMFW_ADSP1_DM:
2159ad93 1788 case WMFW_ADSP2_XM:
2159ad93 1789 case WMFW_ADSP2_YM:
2159ad93 1790 case WMFW_ADSP1_ZM:
9ce5e6e6 1791 region_name = wm_adsp_mem_region_name(type);
45b9ee72 1792 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1793 break;
1794 default:
1795 adsp_warn(dsp,
1796 "%s.%d: Unknown region type %x at %d(%x)\n",
1797 file, regions, type, pos, pos);
1798 break;
1799 }
1800
1801 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1802 regions, le32_to_cpu(region->len), offset,
1803 region_name);
1804
50dd2ea8
BH		 1805 if (le32_to_cpu(region->len) >
1806 firmware->size - pos - sizeof(*region)) {
1cab2a84
RF		 1807 adsp_err(dsp,
1808 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1809 file, regions, region_name,
1810 le32_to_cpu(region->len), firmware->size);
1811 ret = -EINVAL;
1812 goto out_fw;
1813 }
1814
2159ad93
MB		 1815 if (text) {
1816 memcpy(text, region->data, le32_to_cpu(region->len));
1817 adsp_info(dsp, "%s: %s\n", file, text);
1818 kfree(text);
1cab2a84 1819 text = NULL;
2159ad93
MB		 1820 }
1821
1822 if (reg) {
cdcd7f72
CK		 1823 buf = wm_adsp_buf_alloc(region->data,
1824 le32_to_cpu(region->len),
1825 &buf_list);
1826 if (!buf) {
1827 adsp_err(dsp, "Out of memory\n");
1828 ret = -ENOMEM;
1829 goto out_fw;
1830 }
c1a7898d 1831
cdcd7f72
CK		 1832 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1833 le32_to_cpu(region->len));
1834 if (ret != 0) {
1835 adsp_err(dsp,
1836 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1837 file, regions,
1838 le32_to_cpu(region->len), offset,
1839 region_name, ret);
1840 goto out_fw;
2159ad93
MB		 1841 }
1842 }
1843
1844 pos += le32_to_cpu(region->len) + sizeof(*region);
1845 regions++;
1846 }
cf17c83c
MB		 1847
1848 ret = regmap_async_complete(regmap);
1849 if (ret != 0) {
1850 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1851 goto out_fw;
1852 }
1853
2159ad93
MB		 1854 if (pos > firmware->size)
1855 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1856 file, regions, pos - firmware->size);
1857
f9f55e31
RF		 1858 wm_adsp_debugfs_save_wmfwname(dsp, file);
1859
2159ad93 1860out_fw:
cf17c83c
MB		 1861 regmap_async_complete(regmap);
1862 wm_adsp_buf_free(&buf_list);
2159ad93 1863 release_firmware(firmware);
1cab2a84 1864 kfree(text);
2159ad93
MB		 1865out:
1866 kfree(file);
1867
1868 return ret;
1869}
1870
2323736d
CK		 1871static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1872 const struct wm_adsp_alg_region *alg_region)
1873{
1874 struct wm_coeff_ctl *ctl;
1875
1876 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1877 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1878 alg_region->alg == ctl->alg_region.alg &&
1879 alg_region->type == ctl->alg_region.type) {
1880 ctl->alg_region.base = alg_region->base;
1881 }
1882 }
1883}
1884
3809f001 1885static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
7f7cca08 1886 const struct wm_adsp_region *mem,
b618a185 1887 unsigned int pos, unsigned int len)
db40517c 1888{
b618a185 1889 void *alg;
7f7cca08 1890 unsigned int reg;
b618a185 1891 int ret;
db40517c 1892 __be32 val;
db40517c 1893
3809f001 1894 if (n_algs == 0) {
b618a185
CK		 1895 adsp_err(dsp, "No algorithms\n");
1896 return ERR_PTR(-EINVAL);
db40517c
MB		 1897 }
1898
3809f001
CK		 1899 if (n_algs > 1024) {
1900 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1901 return ERR_PTR(-EINVAL);
1902 }
db40517c 1903
b618a185 1904 /* Read the terminator first to validate the length */
7f7cca08
CK		 1905 reg = wm_adsp_region_to_reg(mem, pos + len);
1906
1907 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
b618a185
CK		 1908 if (ret != 0) {
1909 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1910 ret);
1911 return ERR_PTR(ret);
1912 }
db40517c 1913
b618a185 1914 if (be32_to_cpu(val) != 0xbedead)
503ada8a 1915 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
7f7cca08
CK		 1916 reg, be32_to_cpu(val));
1917
1918 /* Convert length from DSP words to bytes */
1919 len *= sizeof(u32);
d62f4bc6 1920
517ee74e 1921 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
b618a185
CK		 1922 if (!alg)
1923 return ERR_PTR(-ENOMEM);
db40517c 1924
7f7cca08
CK		 1925 reg = wm_adsp_region_to_reg(mem, pos);
1926
1927 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
b618a185 1928 if (ret != 0) {
7d00cd97 1929 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
b618a185
CK		 1930 kfree(alg);
1931 return ERR_PTR(ret);
1932 }
ac50009f 1933
b618a185
CK		 1934 return alg;
1935}
ac50009f 1936
14197095
CK		 1937static struct wm_adsp_alg_region *
1938 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1939{
1940 struct wm_adsp_alg_region *alg_region;
1941
1942 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1943 if (id == alg_region->alg && type == alg_region->type)
1944 return alg_region;
1945 }
1946
1947 return NULL;
1948}
1949
d9d20e17
CK		 1950static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1951 int type, __be32 id,
1952 __be32 base)
1953{
1954 struct wm_adsp_alg_region *alg_region;
1955
1956 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1957 if (!alg_region)
1958 return ERR_PTR(-ENOMEM);
1959
1960 alg_region->type = type;
1961 alg_region->alg = be32_to_cpu(id);
1962 alg_region->base = be32_to_cpu(base);
1963
1964 list_add_tail(&alg_region->list, &dsp->alg_regions);
1965
2323736d
CK		 1966 if (dsp->fw_ver > 0)
1967 wm_adsp_ctl_fixup_base(dsp, alg_region);
1968
d9d20e17
CK		 1969 return alg_region;
1970}
1971
56574d54
RF		 1972static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1973{
1974 struct wm_adsp_alg_region *alg_region;
1975
1976 while (!list_empty(&dsp->alg_regions)) {
1977 alg_region = list_first_entry(&dsp->alg_regions,
1978 struct wm_adsp_alg_region,
1979 list);
1980 list_del(&alg_region->list);
1981 kfree(alg_region);
1982 }
1983}
1984
b618a185
CK		 1985static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1986{
1987 struct wmfw_adsp1_id_hdr adsp1_id;
1988 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1989 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1990 const struct wm_adsp_region *mem;
1991 unsigned int pos, len;
3809f001 1992 size_t n_algs;
b618a185 1993 int i, ret;
db40517c 1994
b618a185
CK		 1995 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1996 if (WARN_ON(!mem))
1997 return -EINVAL;
1998
1999 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2000 sizeof(adsp1_id));
2001 if (ret != 0) {
2002 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2003 ret);
2004 return ret;
2005 }
db40517c 2006
3809f001 2007 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 2008 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
2009 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2010 dsp->fw_id,
2011 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
2012 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
2013 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 2014 n_algs);
b618a185 2015
d9d20e17
CK		 2016 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2017 adsp1_id.fw.id, adsp1_id.zm);
2018 if (IS_ERR(alg_region))
2019 return PTR_ERR(alg_region);
d62f4bc6 2020
d9d20e17
CK		 2021 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2022 adsp1_id.fw.id, adsp1_id.dm);
2023 if (IS_ERR(alg_region))
2024 return PTR_ERR(alg_region);
db40517c 2025
7f7cca08
CK		 2026 /* Calculate offset and length in DSP words */
2027 pos = sizeof(adsp1_id) / sizeof(u32);
2028 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
b618a185 2029
7f7cca08 2030 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
b618a185
CK		 2031 if (IS_ERR(adsp1_alg))
2032 return PTR_ERR(adsp1_alg);
2033
3809f001 2034 for (i = 0; i < n_algs; i++) {
b618a185
CK		 2035 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2036 i, be32_to_cpu(adsp1_alg[i].alg.id),
2037 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2038 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2039 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2040 be32_to_cpu(adsp1_alg[i].dm),
2041 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 2042
d9d20e17
CK		 2043 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2044 adsp1_alg[i].alg.id,
2045 adsp1_alg[i].dm);
2046 if (IS_ERR(alg_region)) {
2047 ret = PTR_ERR(alg_region);
b618a185
CK		 2048 goto out;
2049 }
2323736d
CK		 2050 if (dsp->fw_ver == 0) {
2051 if (i + 1 < n_algs) {
2052 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2053 len -= be32_to_cpu(adsp1_alg[i].dm);
2054 len *= 4;
2055 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2056 len, NULL, 0, 0,
2057 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2058 } else {
2059 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2060 be32_to_cpu(adsp1_alg[i].alg.id));
2061 }
b618a185 2062 }
ac50009f 2063
d9d20e17
CK		 2064 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2065 adsp1_alg[i].alg.id,
2066 adsp1_alg[i].zm);
2067 if (IS_ERR(alg_region)) {
2068 ret = PTR_ERR(alg_region);
b618a185
CK		 2069 goto out;
2070 }
2323736d
CK		 2071 if (dsp->fw_ver == 0) {
2072 if (i + 1 < n_algs) {
2073 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2074 len -= be32_to_cpu(adsp1_alg[i].zm);
2075 len *= 4;
2076 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2077 len, NULL, 0, 0,
2078 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2079 } else {
2080 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2081 be32_to_cpu(adsp1_alg[i].alg.id));
2082 }
b618a185 2083 }
db40517c
MB		 2084 }
2085
b618a185
CK		 2086out:
2087 kfree(adsp1_alg);
2088 return ret;
2089}
db40517c 2090
b618a185
CK		 2091static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2092{
2093 struct wmfw_adsp2_id_hdr adsp2_id;
2094 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 2095 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 2096 const struct wm_adsp_region *mem;
2097 unsigned int pos, len;
3809f001 2098 size_t n_algs;
b618a185
CK		 2099 int i, ret;
2100
2101 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2102 if (WARN_ON(!mem))
d62f4bc6 2103 return -EINVAL;
d62f4bc6 2104
b618a185
CK		 2105 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2106 sizeof(adsp2_id));
db40517c 2107 if (ret != 0) {
b618a185
CK		 2108 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2109 ret);
db40517c
MB		 2110 return ret;
2111 }
2112
3809f001 2113 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 2114 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 2115 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 2116 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2117 dsp->fw_id,
f9f55e31
RF		 2118 (dsp->fw_id_version & 0xff0000) >> 16,
2119 (dsp->fw_id_version & 0xff00) >> 8,
2120 dsp->fw_id_version & 0xff,
3809f001 2121 n_algs);
b618a185 2122
d9d20e17
CK		 2123 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2124 adsp2_id.fw.id, adsp2_id.xm);
2125 if (IS_ERR(alg_region))
2126 return PTR_ERR(alg_region);
db40517c 2127
d9d20e17
CK		 2128 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2129 adsp2_id.fw.id, adsp2_id.ym);
2130 if (IS_ERR(alg_region))
2131 return PTR_ERR(alg_region);
db40517c 2132
d9d20e17
CK		 2133 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2134 adsp2_id.fw.id, adsp2_id.zm);
2135 if (IS_ERR(alg_region))
2136 return PTR_ERR(alg_region);
db40517c 2137
7f7cca08
CK		 2138 /* Calculate offset and length in DSP words */
2139 pos = sizeof(adsp2_id) / sizeof(u32);
2140 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
db40517c 2141
7f7cca08 2142 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
b618a185
CK		 2143 if (IS_ERR(adsp2_alg))
2144 return PTR_ERR(adsp2_alg);
471f4885 2145
3809f001 2146 for (i = 0; i < n_algs; i++) {
b618a185
CK		 2147 adsp_info(dsp,
2148 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2149 i, be32_to_cpu(adsp2_alg[i].alg.id),
2150 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2151 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2152 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2153 be32_to_cpu(adsp2_alg[i].xm),
2154 be32_to_cpu(adsp2_alg[i].ym),
2155 be32_to_cpu(adsp2_alg[i].zm));
db40517c 2156
d9d20e17
CK		 2157 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2158 adsp2_alg[i].alg.id,
2159 adsp2_alg[i].xm);
2160 if (IS_ERR(alg_region)) {
2161 ret = PTR_ERR(alg_region);
b618a185
CK		 2162 goto out;
2163 }
2323736d
CK		 2164 if (dsp->fw_ver == 0) {
2165 if (i + 1 < n_algs) {
2166 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2167 len -= be32_to_cpu(adsp2_alg[i].xm);
2168 len *= 4;
2169 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2170 len, NULL, 0, 0,
2171 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2172 } else {
2173 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2174 be32_to_cpu(adsp2_alg[i].alg.id));
2175 }
b618a185 2176 }
471f4885 2177
d9d20e17
CK		 2178 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2179 adsp2_alg[i].alg.id,
2180 adsp2_alg[i].ym);
2181 if (IS_ERR(alg_region)) {
2182 ret = PTR_ERR(alg_region);
b618a185
CK		 2183 goto out;
2184 }
2323736d
CK		 2185 if (dsp->fw_ver == 0) {
2186 if (i + 1 < n_algs) {
2187 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2188 len -= be32_to_cpu(adsp2_alg[i].ym);
2189 len *= 4;
2190 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2191 len, NULL, 0, 0,
2192 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2193 } else {
2194 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2195 be32_to_cpu(adsp2_alg[i].alg.id));
2196 }
b618a185 2197 }
471f4885 2198
d9d20e17
CK		 2199 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2200 adsp2_alg[i].alg.id,
2201 adsp2_alg[i].zm);
2202 if (IS_ERR(alg_region)) {
2203 ret = PTR_ERR(alg_region);
b618a185
CK		 2204 goto out;
2205 }
2323736d
CK		 2206 if (dsp->fw_ver == 0) {
2207 if (i + 1 < n_algs) {
2208 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2209 len -= be32_to_cpu(adsp2_alg[i].zm);
2210 len *= 4;
2211 wm_adsp_create_control(dsp, alg_region, 0,
8eb084d0
SH		 2212 len, NULL, 0, 0,
2213 SNDRV_CTL_ELEM_TYPE_BYTES);
2323736d
CK		 2214 } else {
2215 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2216 be32_to_cpu(adsp2_alg[i].alg.id));
2217 }
db40517c
MB		 2218 }
2219 }
2220
2221out:
b618a185 2222 kfree(adsp2_alg);
db40517c
MB		 2223 return ret;
2224}
2225
2159ad93
MB		 2226static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2227{
cf17c83c 2228 LIST_HEAD(buf_list);
2159ad93
MB		 2229 struct regmap *regmap = dsp->regmap;
2230 struct wmfw_coeff_hdr *hdr;
2231 struct wmfw_coeff_item *blk;
2232 const struct firmware *firmware;
471f4885
MB		 2233 const struct wm_adsp_region *mem;
2234 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 2235 const char *region_name;
2236 int ret, pos, blocks, type, offset, reg;
2237 char *file;
cf17c83c 2238 struct wm_adsp_buf *buf;
2159ad93
MB		 2239
2240 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2241 if (file == NULL)
2242 return -ENOMEM;
2243
1023dbd9
MB		 2244 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2245 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 2246 file[PAGE_SIZE - 1] = '\0';
2247
2248 ret = request_firmware(&firmware, file, dsp->dev);
2249 if (ret != 0) {
2250 adsp_warn(dsp, "Failed to request '%s'\n", file);
2251 ret = 0;
2252 goto out;
2253 }
2254 ret = -EINVAL;
2255
2256 if (sizeof(*hdr) >= firmware->size) {
2257 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2258 file, firmware->size);
2259 goto out_fw;
2260 }
2261
7585a5b0 2262 hdr = (void *)&firmware->data[0];
2159ad93
MB		 2263 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2264 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 2265 goto out_fw;
2159ad93
MB		 2266 }
2267
c712326d
MB		 2268 switch (be32_to_cpu(hdr->rev) & 0xff) {
2269 case 1:
2270 break;
2271 default:
2272 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2273 file, be32_to_cpu(hdr->rev) & 0xff);
2274 ret = -EINVAL;
2275 goto out_fw;
2276 }
2277
2159ad93
MB		 2278 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2279 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2280 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2281 le32_to_cpu(hdr->ver) & 0xff);
2282
2283 pos = le32_to_cpu(hdr->len);
2284
2285 blocks = 0;
2286 while (pos < firmware->size &&
50dd2ea8 2287 sizeof(*blk) < firmware->size - pos) {
7585a5b0 2288 blk = (void *)(&firmware->data[pos]);
2159ad93 2289
c712326d
MB		 2290 type = le16_to_cpu(blk->type);
2291 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 2292
2293 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2294 file, blocks, le32_to_cpu(blk->id),
2295 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2296 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2297 le32_to_cpu(blk->ver) & 0xff);
2298 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2299 file, blocks, le32_to_cpu(blk->len), offset, type);
2300
2301 reg = 0;
2302 region_name = "Unknown";
2303 switch (type) {
c712326d
MB		 2304 case (WMFW_NAME_TEXT << 8):
2305 case (WMFW_INFO_TEXT << 8):
2159ad93 2306 break;
c712326d 2307 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 2308 /*
2309 * Old files may use this for global
2310 * coefficients.
2311 */
2312 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2313 offset == 0) {
2314 region_name = "global coefficients";
2315 mem = wm_adsp_find_region(dsp, type);
2316 if (!mem) {
2317 adsp_err(dsp, "No ZM\n");
2318 break;
2319 }
2320 reg = wm_adsp_region_to_reg(mem, 0);
2321
2322 } else {
2323 region_name = "register";
2324 reg = offset;
2325 }
2159ad93 2326 break;
471f4885
MB		 2327
2328 case WMFW_ADSP1_DM:
2329 case WMFW_ADSP1_ZM:
2330 case WMFW_ADSP2_XM:
2331 case WMFW_ADSP2_YM:
2332 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2333 file, blocks, le32_to_cpu(blk->len),
2334 type, le32_to_cpu(blk->id));
2335
2336 mem = wm_adsp_find_region(dsp, type);
2337 if (!mem) {
2338 adsp_err(dsp, "No base for region %x\n", type);
2339 break;
2340 }
2341
14197095
CK		 2342 alg_region = wm_adsp_find_alg_region(dsp, type,
2343 le32_to_cpu(blk->id));
2344 if (alg_region) {
2345 reg = alg_region->base;
2346 reg = wm_adsp_region_to_reg(mem, reg);
2347 reg += offset;
2348 } else {
471f4885
MB		 2349 adsp_err(dsp, "No %x for algorithm %x\n",
2350 type, le32_to_cpu(blk->id));
14197095 2351 }
471f4885
MB		 2352 break;
2353
2159ad93 2354 default:
25c62f7e
MB		 2355 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2356 file, blocks, type, pos);
2159ad93
MB		 2357 break;
2358 }
2359
2360 if (reg) {
50dd2ea8
BH		 2361 if (le32_to_cpu(blk->len) >
2362 firmware->size - pos - sizeof(*blk)) {
1cab2a84
RF		 2363 adsp_err(dsp,
2364 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2365 file, blocks, region_name,
2366 le32_to_cpu(blk->len),
2367 firmware->size);
2368 ret = -EINVAL;
2369 goto out_fw;
2370 }
2371
cf17c83c
MB		 2372 buf = wm_adsp_buf_alloc(blk->data,
2373 le32_to_cpu(blk->len),
2374 &buf_list);
a76fefab
MB		 2375 if (!buf) {
2376 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 2377 ret = -ENOMEM;
2378 goto out_fw;
a76fefab
MB		 2379 }
2380
20da6d5a
MB		 2381 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2382 file, blocks, le32_to_cpu(blk->len),
2383 reg);
cf17c83c
MB		 2384 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2385 le32_to_cpu(blk->len));
2159ad93
MB		 2386 if (ret != 0) {
2387 adsp_err(dsp,
43bc3bf6
DP		 2388 "%s.%d: Failed to write to %x in %s: %d\n",
2389 file, blocks, reg, region_name, ret);
2159ad93
MB		 2390 }
2391 }
2392
be951017 2393 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 2394 blocks++;
2395 }
2396
cf17c83c
MB		 2397 ret = regmap_async_complete(regmap);
2398 if (ret != 0)
2399 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2400
2159ad93
MB		 2401 if (pos > firmware->size)
2402 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2403 file, blocks, pos - firmware->size);
2404
f9f55e31
RF		 2405 wm_adsp_debugfs_save_binname(dsp, file);
2406
2159ad93 2407out_fw:
9da7a5a9 2408 regmap_async_complete(regmap);
2159ad93 2409 release_firmware(firmware);
cf17c83c 2410 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 2411out:
2412 kfree(file);
f4b82812 2413 return ret;
2159ad93
MB		 2414}
2415
3809f001 2416int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 2417{
3809f001 2418 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 2419
078e7183
CK		 2420 mutex_init(&dsp->pwr_lock);
2421
5e7a7a22
MB		 2422 return 0;
2423}
2424EXPORT_SYMBOL_GPL(wm_adsp1_init);
2425
2159ad93
MB		 2426int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2427 struct snd_kcontrol *kcontrol,
2428 int event)
2429{
0fe1daa6
KM		 2430 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2431 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2159ad93 2432 struct wm_adsp *dsp = &dsps[w->shift];
6ab2b7b4 2433 struct wm_coeff_ctl *ctl;
2159ad93 2434 int ret;
7585a5b0 2435 unsigned int val;
2159ad93 2436
0fe1daa6 2437 dsp->component = component;
92bb4c32 2438
078e7183
CK		 2439 mutex_lock(&dsp->pwr_lock);
2440
2159ad93
MB		 2441 switch (event) {
2442 case SND_SOC_DAPM_POST_PMU:
2443 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2444 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2445
94e205bf
CR		 2446 /*
2447 * For simplicity set the DSP clock rate to be the
2448 * SYSCLK rate rather than making it configurable.
2449 */
7585a5b0 2450 if (dsp->sysclk_reg) {
94e205bf
CR		 2451 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2452 if (ret != 0) {
2453 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2454 ret);
078e7183 2455 goto err_mutex;
94e205bf
CR		 2456 }
2457
7d00cd97 2458 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
94e205bf
CR		 2459
2460 ret = regmap_update_bits(dsp->regmap,
2461 dsp->base + ADSP1_CONTROL_31,
2462 ADSP1_CLK_SEL_MASK, val);
2463 if (ret != 0) {
2464 adsp_err(dsp, "Failed to set clock rate: %d\n",
2465 ret);
078e7183 2466 goto err_mutex;
94e205bf
CR		 2467 }
2468 }
2469
2159ad93
MB		 2470 ret = wm_adsp_load(dsp);
2471 if (ret != 0)
078e7183 2472 goto err_ena;
2159ad93 2473
b618a185 2474 ret = wm_adsp1_setup_algs(dsp);
db40517c 2475 if (ret != 0)
078e7183 2476 goto err_ena;
db40517c 2477
2159ad93
MB		 2478 ret = wm_adsp_load_coeff(dsp);
2479 if (ret != 0)
078e7183 2480 goto err_ena;
2159ad93 2481
0c2e3f34 2482 /* Initialize caches for enabled and unset controls */
81ad93ec 2483 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2484 if (ret != 0)
078e7183 2485 goto err_ena;
6ab2b7b4 2486
0c2e3f34 2487 /* Sync set controls */
81ad93ec 2488 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2489 if (ret != 0)
078e7183 2490 goto err_ena;
6ab2b7b4 2491
28823eba
CK		 2492 dsp->booted = true;
2493
2159ad93
MB		 2494 /* Start the core running */
2495 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2496 ADSP1_CORE_ENA | ADSP1_START,
2497 ADSP1_CORE_ENA | ADSP1_START);
28823eba
CK		 2498
2499 dsp->running = true;
2159ad93
MB		 2500 break;
2501
2502 case SND_SOC_DAPM_PRE_PMD:
28823eba
CK		 2503 dsp->running = false;
2504 dsp->booted = false;
2505
2159ad93
MB		 2506 /* Halt the core */
2507 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2508 ADSP1_CORE_ENA | ADSP1_START, 0);
2509
2510 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2511 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2512
2513 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2514 ADSP1_SYS_ENA, 0);
6ab2b7b4 2515
81ad93ec 2516 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2517 ctl->enabled = 0;
b0101b4f 2518
56574d54
RF		 2519
2520 wm_adsp_free_alg_regions(dsp);
2159ad93
MB		 2521 break;
2522
2523 default:
2524 break;
2525 }
2526
078e7183
CK		 2527 mutex_unlock(&dsp->pwr_lock);
2528
2159ad93
MB		 2529 return 0;
2530
078e7183 2531err_ena:
2159ad93
MB		 2532 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2533 ADSP1_SYS_ENA, 0);
078e7183
CK		 2534err_mutex:
2535 mutex_unlock(&dsp->pwr_lock);
2536
2159ad93
MB		 2537 return ret;
2538}
2539EXPORT_SYMBOL_GPL(wm_adsp1_event);
2540
2541static int wm_adsp2_ena(struct wm_adsp *dsp)
2542{
2543 unsigned int val;
2544 int ret, count;
2545
e1ea1879
RF		 2546 switch (dsp->rev) {
2547 case 0:
2548 ret = regmap_update_bits_async(dsp->regmap,
2549 dsp->base + ADSP2_CONTROL,
2550 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2551 if (ret != 0)
2552 return ret;
2553 break;
2554 default:
2555 break;
2556 }
2159ad93
MB		 2557
2558 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2559 for (count = 0; count < 10; ++count) {
7d00cd97 2560 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2159ad93
MB		 2561 if (ret != 0)
2562 return ret;
939fd1e8
CK		 2563
2564 if (val & ADSP2_RAM_RDY)
2565 break;
2566
1fa96f3f 2567 usleep_range(250, 500);
939fd1e8 2568 }
2159ad93
MB		 2569
2570 if (!(val & ADSP2_RAM_RDY)) {
2571 adsp_err(dsp, "Failed to start DSP RAM\n");
2572 return -EBUSY;
2573 }
2574
2575 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2576
2577 return 0;
2578}
2579
18b1a902 2580static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2581{
d8a64d6a
CK		 2582 struct wm_adsp *dsp = container_of(work,
2583 struct wm_adsp,
2584 boot_work);
2159ad93
MB		 2585 int ret;
2586
078e7183
CK		 2587 mutex_lock(&dsp->pwr_lock);
2588
90d19ba5
CK		 2589 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2590 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2591 if (ret != 0)
2592 goto err_mutex;
2593
d8a64d6a
CK		 2594 ret = wm_adsp2_ena(dsp);
2595 if (ret != 0)
d589d8b8 2596 goto err_mem;
2159ad93 2597
d8a64d6a
CK		 2598 ret = wm_adsp_load(dsp);
2599 if (ret != 0)
078e7183 2600 goto err_ena;
2159ad93 2601
b618a185 2602 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2603 if (ret != 0)
078e7183 2604 goto err_ena;
db40517c 2605
d8a64d6a
CK		 2606 ret = wm_adsp_load_coeff(dsp);
2607 if (ret != 0)
078e7183 2608 goto err_ena;
2159ad93 2609
d8a64d6a
CK		 2610 /* Initialize caches for enabled and unset controls */
2611 ret = wm_coeff_init_control_caches(dsp);
2612 if (ret != 0)
078e7183 2613 goto err_ena;
6ab2b7b4 2614
e1ea1879
RF		 2615 switch (dsp->rev) {
2616 case 0:
2617 /* Turn DSP back off until we are ready to run */
2618 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2619 ADSP2_SYS_ENA, 0);
2620 if (ret != 0)
2621 goto err_ena;
2622 break;
2623 default:
2624 break;
2625 }
90d19ba5 2626
e779974b
CK		 2627 dsp->booted = true;
2628
078e7183
CK		 2629 mutex_unlock(&dsp->pwr_lock);
2630
d8a64d6a 2631 return;
6ab2b7b4 2632
078e7183 2633err_ena:
d8a64d6a
CK		 2634 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2635 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
d589d8b8
CK		 2636err_mem:
2637 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2638 ADSP2_MEM_ENA, 0);
078e7183
CK		 2639err_mutex:
2640 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2641}
2642
d82d767f
CK		 2643static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2644{
2645 int ret;
2646
e1ea1879
RF		 2647 switch (dsp->rev) {
2648 case 0:
2649 ret = regmap_update_bits_async(dsp->regmap,
2650 dsp->base + ADSP2_CLOCKING,
2651 ADSP2_CLK_SEL_MASK,
2652 freq << ADSP2_CLK_SEL_SHIFT);
2653 if (ret) {
2654 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2655 return;
2656 }
2657 break;
2658 default:
2659 /* clock is handled by parent codec driver */
2660 break;
2661 }
d82d767f
CK		 2662}
2663
af813a6f
CK		 2664int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
2665 struct snd_ctl_elem_value *ucontrol)
2666{
0fe1daa6
KM		 2667 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2668 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
af813a6f
CK		 2669
2670 ucontrol->value.integer.value[0] = dsp->preloaded;
2671
2672 return 0;
2673}
2674EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
2675
2676int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
2677 struct snd_ctl_elem_value *ucontrol)
2678{
0fe1daa6
KM		 2679 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2680 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
2681 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
af813a6f
CK		 2682 struct soc_mixer_control *mc =
2683 (struct soc_mixer_control *)kcontrol->private_value;
2684 char preload[32];
2685
6298117a 2686 snprintf(preload, ARRAY_SIZE(preload), "DSP%u Preload", mc->shift);
af813a6f
CK		 2687
2688 dsp->preloaded = ucontrol->value.integer.value[0];
2689
2690 if (ucontrol->value.integer.value[0])
95a594d0 2691 snd_soc_component_force_enable_pin(component, preload);
af813a6f 2692 else
95a594d0 2693 snd_soc_component_disable_pin(component, preload);
af813a6f
CK		 2694
2695 snd_soc_dapm_sync(dapm);
2696
2697 return 0;
2698}
2699EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
2700
51a2c944
MK		 2701static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
2702{
2703 switch (dsp->rev) {
2704 case 0:
2705 case 1:
2706 return;
2707 default:
2708 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2709 ADSP2_WDT_ENA_MASK, 0);
2710 }
2711}
2712
12db5edd 2713int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
d82d767f
CK		 2714 struct snd_kcontrol *kcontrol, int event,
2715 unsigned int freq)
12db5edd 2716{
0fe1daa6
KM		 2717 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2718 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
12db5edd 2719 struct wm_adsp *dsp = &dsps[w->shift];
57a60cc3 2720 struct wm_coeff_ctl *ctl;
12db5edd 2721
12db5edd
CK		 2722 switch (event) {
2723 case SND_SOC_DAPM_PRE_PMU:
d82d767f 2724 wm_adsp2_set_dspclk(dsp, freq);
12db5edd
CK		 2725 queue_work(system_unbound_wq, &dsp->boot_work);
2726 break;
57a60cc3 2727 case SND_SOC_DAPM_PRE_PMD:
bb24ee41
CK		 2728 mutex_lock(&dsp->pwr_lock);
2729
57a60cc3
CK		 2730 wm_adsp_debugfs_clear(dsp);
2731
2732 dsp->fw_id = 0;
2733 dsp->fw_id_version = 0;
2734
2735 dsp->booted = false;
2736
2737 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2738 ADSP2_MEM_ENA, 0);
2739
2740 list_for_each_entry(ctl, &dsp->ctl_list, list)
2741 ctl->enabled = 0;
2742
2743 wm_adsp_free_alg_regions(dsp);
2744
bb24ee41
CK		 2745 mutex_unlock(&dsp->pwr_lock);
2746
57a60cc3
CK		 2747 adsp_dbg(dsp, "Shutdown complete\n");
2748 break;
12db5edd
CK		 2749 default:
2750 break;
cab27258 2751 }
12db5edd
CK		 2752
2753 return 0;
2754}
2755EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2756
d8a64d6a
CK		 2757int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2758 struct snd_kcontrol *kcontrol, int event)
2759{
0fe1daa6
KM		 2760 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2761 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
d8a64d6a 2762 struct wm_adsp *dsp = &dsps[w->shift];
d8a64d6a
CK		 2763 int ret;
2764
d8a64d6a
CK		 2765 switch (event) {
2766 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2767 flush_work(&dsp->boot_work);
2768
bb24ee41
CK		 2769 mutex_lock(&dsp->pwr_lock);
2770
2771 if (!dsp->booted) {
2772 ret = -EIO;
2773 goto err;
2774 }
6ab2b7b4 2775
90d19ba5
CK		 2776 ret = wm_adsp2_ena(dsp);
2777 if (ret != 0)
2778 goto err;
2779
cef45771
CK		 2780 /* Sync set controls */
2781 ret = wm_coeff_sync_controls(dsp);
2782 if (ret != 0)
2783 goto err;
2784
51a2c944
MK		 2785 wm_adsp2_lock(dsp, dsp->lock_regions);
2786
d8a64d6a
CK		 2787 ret = regmap_update_bits(dsp->regmap,
2788 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2789 ADSP2_CORE_ENA | ADSP2_START,
2790 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2791 if (ret != 0)
2792 goto err;
2cd19bdb 2793
48c2c993 2794 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
2cd19bdb 2795 ret = wm_adsp_buffer_init(dsp);
bb24ee41 2796 if (ret < 0)
48c2c993 2797 goto err;
48c2c993 2798 }
2cd19bdb 2799
e779974b
CK		 2800 dsp->running = true;
2801
612047f0
CK		 2802 mutex_unlock(&dsp->pwr_lock);
2803
2159ad93
MB		 2804 break;
2805
2806 case SND_SOC_DAPM_PRE_PMD:
f4f0c4c6
RF		 2807 /* Tell the firmware to cleanup */
2808 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2809
51a2c944
MK		 2810 wm_adsp_stop_watchdog(dsp);
2811
10337b07 2812 /* Log firmware state, it can be useful for analysis */
e1ea1879
RF		 2813 switch (dsp->rev) {
2814 case 0:
2815 wm_adsp2_show_fw_status(dsp);
2816 break;
2817 default:
2818 wm_adsp2v2_show_fw_status(dsp);
2819 break;
2820 }
10337b07 2821
078e7183
CK		 2822 mutex_lock(&dsp->pwr_lock);
2823
1023dbd9
MB		 2824 dsp->running = false;
2825
e1ea1879
RF		 2826 regmap_update_bits(dsp->regmap,
2827 dsp->base + ADSP2_CONTROL,
57a60cc3 2828 ADSP2_CORE_ENA | ADSP2_START, 0);
973838a0 2829
2d30b575 2830 /* Make sure DMAs are quiesced */
e1ea1879
RF		 2831 switch (dsp->rev) {
2832 case 0:
2833 regmap_write(dsp->regmap,
2834 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2835 regmap_write(dsp->regmap,
2836 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2837 regmap_write(dsp->regmap,
2838 dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2839
2840 regmap_update_bits(dsp->regmap,
2841 dsp->base + ADSP2_CONTROL,
2842 ADSP2_SYS_ENA, 0);
2843 break;
2844 default:
2845 regmap_write(dsp->regmap,
2846 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2847 regmap_write(dsp->regmap,
2848 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2849 regmap_write(dsp->regmap,
2850 dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2851 break;
2852 }
2d30b575 2853
2cd19bdb
CK		 2854 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2855 wm_adsp_buffer_free(dsp);
2856
078e7183
CK		 2857 mutex_unlock(&dsp->pwr_lock);
2858
57a60cc3 2859 adsp_dbg(dsp, "Execution stopped\n");
2159ad93
MB		 2860 break;
2861
2862 default:
2863 break;
2864 }
2865
2866 return 0;
2867err:
2868 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2869 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
bb24ee41 2870 mutex_unlock(&dsp->pwr_lock);
2159ad93
MB		 2871 return ret;
2872}
2873EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2874
0fe1daa6 2875int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
f5e2ce92 2876{
af813a6f
CK		 2877 char preload[32];
2878
2879 snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", dsp->num);
95a594d0
CK		 2880
2881 snd_soc_component_disable_pin(component, preload);
685f51a5 2882
0fe1daa6 2883 wm_adsp2_init_debugfs(dsp, component);
f9f55e31 2884
0fe1daa6 2885 dsp->component = component;
af813a6f 2886
0fe1daa6 2887 return snd_soc_add_component_controls(component,
336d0442
RF		 2888 &wm_adsp_fw_controls[dsp->num - 1],
2889 1);
f5e2ce92 2890}
0fe1daa6 2891EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
f5e2ce92 2892
0fe1daa6 2893int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
f5e2ce92 2894{
f9f55e31
RF		 2895 wm_adsp2_cleanup_debugfs(dsp);
2896
f5e2ce92
RF		 2897 return 0;
2898}
0fe1daa6 2899EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
f5e2ce92 2900
81ac58b1 2901int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2902{
2903 int ret;
2904
e1ea1879
RF		 2905 switch (dsp->rev) {
2906 case 0:
2907 /*
2908 * Disable the DSP memory by default when in reset for a small
2909 * power saving.
2910 */
2911 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2912 ADSP2_MEM_ENA, 0);
2913 if (ret) {
2914 adsp_err(dsp,
2915 "Failed to clear memory retention: %d\n", ret);
2916 return ret;
2917 }
2918 break;
2919 default:
2920 break;
10a2b662
MB		 2921 }
2922
3809f001
CK		 2923 INIT_LIST_HEAD(&dsp->alg_regions);
2924 INIT_LIST_HEAD(&dsp->ctl_list);
2925 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2926
078e7183
CK		 2927 mutex_init(&dsp->pwr_lock);
2928
973838a0
MB		 2929 return 0;
2930}
2931EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2932
66225e98
RF		 2933void wm_adsp2_remove(struct wm_adsp *dsp)
2934{
2935 struct wm_coeff_ctl *ctl;
2936
2937 while (!list_empty(&dsp->ctl_list)) {
2938 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2939 list);
2940 list_del(&ctl->list);
2941 wm_adsp_free_ctl_blk(ctl);
2942 }
2943}
2944EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2945
edd71350
CK		 2946static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2947{
2948 return compr->buf != NULL;
2949}
2950
2951static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2952{
2953 /*
2954 * Note this will be more complex once each DSP can support multiple
2955 * streams
2956 */
2957 if (!compr->dsp->buffer)
2958 return -EINVAL;
2959
2960 compr->buf = compr->dsp->buffer;
721be3be 2961 compr->buf->compr = compr;
edd71350
CK		 2962
2963 return 0;
2964}
2965
721be3be
CK		 2966static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2967{
2968 if (!compr)
2969 return;
2970
2971 /* Wake the poll so it can see buffer is no longer attached */
2972 if (compr->stream)
2973 snd_compr_fragment_elapsed(compr->stream);
2974
2975 if (wm_adsp_compr_attached(compr)) {
2976 compr->buf->compr = NULL;
2977 compr->buf = NULL;
2978 }
2979}
2980
406abc95
CK		 2981int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2982{
2983 struct wm_adsp_compr *compr;
2984 int ret = 0;
2985
2986 mutex_lock(&dsp->pwr_lock);
2987
2988 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2989 adsp_err(dsp, "Firmware does not support compressed API\n");
2990 ret = -ENXIO;
2991 goto out;
2992 }
2993
2994 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2995 adsp_err(dsp, "Firmware does not support stream direction\n");
2996 ret = -EINVAL;
2997 goto out;
2998 }
2999
95fe9597
CK		 3000 if (dsp->compr) {
3001 /* It is expect this limitation will be removed in future */
3002 adsp_err(dsp, "Only a single stream supported per DSP\n");
3003 ret = -EBUSY;
3004 goto out;
3005 }
3006
406abc95
CK		 3007 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3008 if (!compr) {
3009 ret = -ENOMEM;
3010 goto out;
3011 }
3012
3013 compr->dsp = dsp;
3014 compr->stream = stream;
3015
3016 dsp->compr = compr;
3017
3018 stream->runtime->private_data = compr;
3019
3020out:
3021 mutex_unlock(&dsp->pwr_lock);
3022
3023 return ret;
3024}
3025EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3026
3027int wm_adsp_compr_free(struct snd_compr_stream *stream)
3028{
3029 struct wm_adsp_compr *compr = stream->runtime->private_data;
3030 struct wm_adsp *dsp = compr->dsp;
3031
3032 mutex_lock(&dsp->pwr_lock);
3033
721be3be 3034 wm_adsp_compr_detach(compr);
406abc95
CK		 3035 dsp->compr = NULL;
3036
83a40ce9 3037 kfree(compr->raw_buf);
406abc95
CK		 3038 kfree(compr);
3039
3040 mutex_unlock(&dsp->pwr_lock);
3041
3042 return 0;
3043}
3044EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3045
3046static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3047 struct snd_compr_params *params)
3048{
3049 struct wm_adsp_compr *compr = stream->runtime->private_data;
3050 struct wm_adsp *dsp = compr->dsp;
3051 const struct wm_adsp_fw_caps *caps;
3052 const struct snd_codec_desc *desc;
3053 int i, j;
3054
3055 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3056 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3057 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3058 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3059 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3060 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
3061 params->buffer.fragment_size,
3062 params->buffer.fragments);
3063
3064 return -EINVAL;
3065 }
3066
3067 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3068 caps = &wm_adsp_fw[dsp->fw].caps[i];
3069 desc = &caps->desc;
3070
3071 if (caps->id != params->codec.id)
3072 continue;
3073
3074 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3075 if (desc->max_ch < params->codec.ch_out)
3076 continue;
3077 } else {
3078 if (desc->max_ch < params->codec.ch_in)
3079 continue;
3080 }
3081
3082 if (!(desc->formats & (1 << params->codec.format)))
3083 continue;
3084
3085 for (j = 0; j < desc->num_sample_rates; ++j)
3086 if (desc->sample_rates[j] == params->codec.sample_rate)
3087 return 0;
3088 }
3089
3090 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3091 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3092 params->codec.sample_rate, params->codec.format);
3093 return -EINVAL;
3094}
3095
565ace46
CK		 3096static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3097{
3098 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3099}
3100
406abc95
CK		 3101int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3102 struct snd_compr_params *params)
3103{
3104 struct wm_adsp_compr *compr = stream->runtime->private_data;
83a40ce9 3105 unsigned int size;
406abc95
CK		 3106 int ret;
3107
3108 ret = wm_adsp_compr_check_params(stream, params);
3109 if (ret)
3110 return ret;
3111
3112 compr->size = params->buffer;
3113
3114 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
3115 compr->size.fragment_size, compr->size.fragments);
3116
83a40ce9
CK		 3117 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3118 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3119 if (!compr->raw_buf)
3120 return -ENOMEM;
3121
da2b3358
CK		 3122 compr->sample_rate = params->codec.sample_rate;
3123
406abc95
CK		 3124 return 0;
3125}
3126EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3127
3128int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3129 struct snd_compr_caps *caps)
3130{
3131 struct wm_adsp_compr *compr = stream->runtime->private_data;
3132 int fw = compr->dsp->fw;
3133 int i;
3134
3135 if (wm_adsp_fw[fw].caps) {
3136 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3137 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3138
3139 caps->num_codecs = i;
3140 caps->direction = wm_adsp_fw[fw].compr_direction;
3141
3142 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3143 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3144 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3145 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3146 }
3147
3148 return 0;
3149}
3150EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3151
2cd19bdb
CK		 3152static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3153 unsigned int mem_addr,
3154 unsigned int num_words, u32 *data)
3155{
3156 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3157 unsigned int i, reg;
3158 int ret;
3159
3160 if (!mem)
3161 return -EINVAL;
3162
3163 reg = wm_adsp_region_to_reg(mem, mem_addr);
3164
3165 ret = regmap_raw_read(dsp->regmap, reg, data,
3166 sizeof(*data) * num_words);
3167 if (ret < 0)
3168 return ret;
3169
3170 for (i = 0; i < num_words; ++i)
3171 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3172
3173 return 0;
3174}
3175
3176static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3177 unsigned int mem_addr, u32 *data)
3178{
3179 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3180}
3181
3182static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3183 unsigned int mem_addr, u32 data)
3184{
3185 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3186 unsigned int reg;
3187
3188 if (!mem)
3189 return -EINVAL;
3190
3191 reg = wm_adsp_region_to_reg(mem, mem_addr);
3192
3193 data = cpu_to_be32(data & 0x00ffffffu);
3194
3195 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3196}
3197
3198static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3199 unsigned int field_offset, u32 *data)
3200{
3201 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
3202 buf->host_buf_ptr + field_offset, data);
3203}
3204
3205static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3206 unsigned int field_offset, u32 data)
3207{
3208 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
3209 buf->host_buf_ptr + field_offset, data);
3210}
3211
d52ed4b0 3212static int wm_adsp_legacy_host_buf_addr(struct wm_adsp_compr_buf *buf)
2cd19bdb
CK		 3213{
3214 struct wm_adsp_alg_region *alg_region;
3215 struct wm_adsp *dsp = buf->dsp;
3216 u32 xmalg, addr, magic;
3217 int i, ret;
3218
3219 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3220 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
3221
3222 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3223 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3224 if (ret < 0)
3225 return ret;
3226
3227 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3228 return -EINVAL;
3229
3230 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3231 for (i = 0; i < 5; ++i) {
3232 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3233 &buf->host_buf_ptr);
3234 if (ret < 0)
3235 return ret;
3236
3237 if (buf->host_buf_ptr)
3238 break;
3239
3240 usleep_range(1000, 2000);
3241 }
3242
3243 if (!buf->host_buf_ptr)
3244 return -EIO;
3245
3246 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3247
3248 return 0;
3249}
3250
d52ed4b0
RF		 3251static struct wm_coeff_ctl *
3252wm_adsp_find_host_buffer_ctrl(struct wm_adsp_compr_buf *buf)
3253{
3254 struct wm_adsp *dsp = buf->dsp;
3255 struct wm_coeff_ctl *ctl;
3256
3257 list_for_each_entry(ctl, &dsp->ctl_list, list) {
3258 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3259 continue;
3260
3261 if (!ctl->enabled)
3262 continue;
3263
3264 return ctl;
3265 }
3266
3267 return NULL;
3268}
3269
3270static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
3271{
3272 struct wm_adsp *dsp = buf->dsp;
3273 struct wm_coeff_ctl *ctl;
3274 unsigned int reg;
3275 u32 val;
3276 int i, ret;
3277
3278 ctl = wm_adsp_find_host_buffer_ctrl(buf);
3279 if (!ctl)
3280 return wm_adsp_legacy_host_buf_addr(buf);
3281
3282 ret = wm_coeff_base_reg(ctl, &reg);
3283 if (ret)
3284 return ret;
3285
3286 for (i = 0; i < 5; ++i) {
3287 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
3288 if (ret < 0)
3289 return ret;
3290
3291 if (val)
3292 break;
3293
3294 usleep_range(1000, 2000);
3295 }
3296
3297 if (!val)
3298 return -EIO;
3299
3300 buf->host_buf_ptr = be32_to_cpu(val);
3301 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3302
3303 return 0;
3304}
3305
2cd19bdb
CK		 3306static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3307{
3308 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3309 struct wm_adsp_buffer_region *region;
3310 u32 offset = 0;
3311 int i, ret;
3312
3313 for (i = 0; i < caps->num_regions; ++i) {
3314 region = &buf->regions[i];
3315
3316 region->offset = offset;
3317 region->mem_type = caps->region_defs[i].mem_type;
3318
3319 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3320 &region->base_addr);
3321 if (ret < 0)
3322 return ret;
3323
3324 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3325 &offset);
3326 if (ret < 0)
3327 return ret;
3328
3329 region->cumulative_size = offset;
3330
3331 adsp_dbg(buf->dsp,
3332 "region=%d type=%d base=%04x off=%04x size=%04x\n",
3333 i, region->mem_type, region->base_addr,
3334 region->offset, region->cumulative_size);
3335 }
3336
3337 return 0;
3338}
3339
61fc060c
CK		 3340static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3341{
3342 buf->irq_count = 0xFFFFFFFF;
3343 buf->read_index = -1;
3344 buf->avail = 0;
3345}
3346
2cd19bdb
CK		 3347static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3348{
3349 struct wm_adsp_compr_buf *buf;
3350 int ret;
3351
3352 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3353 if (!buf)
3354 return -ENOMEM;
3355
3356 buf->dsp = dsp;
61fc060c
CK		 3357
3358 wm_adsp_buffer_clear(buf);
2cd19bdb
CK		 3359
3360 ret = wm_adsp_buffer_locate(buf);
3361 if (ret < 0) {
3362 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
3363 goto err_buffer;
3364 }
3365
3366 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
3367 sizeof(*buf->regions), GFP_KERNEL);
3368 if (!buf->regions) {
3369 ret = -ENOMEM;
3370 goto err_buffer;
3371 }
3372
3373 ret = wm_adsp_buffer_populate(buf);
3374 if (ret < 0) {
3375 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
3376 goto err_regions;
3377 }
3378
3379 dsp->buffer = buf;
3380
3381 return 0;
3382
3383err_regions:
3384 kfree(buf->regions);
3385err_buffer:
3386 kfree(buf);
3387 return ret;
3388}
3389
3390static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3391{
3392 if (dsp->buffer) {
721be3be
CK		 3393 wm_adsp_compr_detach(dsp->buffer->compr);
3394
2cd19bdb
CK		 3395 kfree(dsp->buffer->regions);
3396 kfree(dsp->buffer);
3397
3398 dsp->buffer = NULL;
3399 }
3400
3401 return 0;
3402}
3403
95fe9597
CK		 3404int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3405{
3406 struct wm_adsp_compr *compr = stream->runtime->private_data;
3407 struct wm_adsp *dsp = compr->dsp;
3408 int ret = 0;
3409
3410 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3411
3412 mutex_lock(&dsp->pwr_lock);
3413
3414 switch (cmd) {
3415 case SNDRV_PCM_TRIGGER_START:
61fc060c
CK		 3416 if (!wm_adsp_compr_attached(compr)) {
3417 ret = wm_adsp_compr_attach(compr);
3418 if (ret < 0) {
3419 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3420 ret);
3421 break;
3422 }
95fe9597 3423 }
565ace46 3424
61fc060c
CK		 3425 wm_adsp_buffer_clear(compr->buf);
3426
565ace46
CK		 3427 /* Trigger the IRQ at one fragment of data */
3428 ret = wm_adsp_buffer_write(compr->buf,
3429 HOST_BUFFER_FIELD(high_water_mark),
3430 wm_adsp_compr_frag_words(compr));
3431 if (ret < 0) {
3432 adsp_err(dsp, "Failed to set high water mark: %d\n",
3433 ret);
3434 break;
3435 }
95fe9597
CK		 3436 break;
3437 case SNDRV_PCM_TRIGGER_STOP:
3438 break;
3439 default:
3440 ret = -EINVAL;
3441 break;
3442 }
3443
3444 mutex_unlock(&dsp->pwr_lock);
3445
3446 return ret;
3447}
3448EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3449
565ace46
CK		 3450static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3451{
3452 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3453
3454 return buf->regions[last_region].cumulative_size;
3455}
3456
3457static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3458{
3459 u32 next_read_index, next_write_index;
3460 int write_index, read_index, avail;
3461 int ret;
3462
3463 /* Only sync read index if we haven't already read a valid index */
3464 if (buf->read_index < 0) {
3465 ret = wm_adsp_buffer_read(buf,
3466 HOST_BUFFER_FIELD(next_read_index),
3467 &next_read_index);
3468 if (ret < 0)
3469 return ret;
3470
3471 read_index = sign_extend32(next_read_index, 23);
3472
3473 if (read_index < 0) {
3474 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3475 return 0;
3476 }
3477
3478 buf->read_index = read_index;
3479 }
3480
3481 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3482 &next_write_index);
3483 if (ret < 0)
3484 return ret;
3485
3486 write_index = sign_extend32(next_write_index, 23);
3487
3488 avail = write_index - buf->read_index;
3489 if (avail < 0)
3490 avail += wm_adsp_buffer_size(buf);
3491
3492 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
33d740e0 3493 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
565ace46
CK		 3494
3495 buf->avail = avail;
3496
3497 return 0;
3498}
3499
9771b18a
CK		 3500static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3501{
3502 int ret;
3503
3504 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3505 if (ret < 0) {
3506 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3507 return ret;
3508 }
3509 if (buf->error != 0) {
3510 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3511 return -EIO;
3512 }
3513
3514 return 0;
3515}
3516
565ace46
CK		 3517int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3518{
612047f0
CK		 3519 struct wm_adsp_compr_buf *buf;
3520 struct wm_adsp_compr *compr;
565ace46
CK		 3521 int ret = 0;
3522
3523 mutex_lock(&dsp->pwr_lock);
3524
612047f0
CK		 3525 buf = dsp->buffer;
3526 compr = dsp->compr;
3527
565ace46 3528 if (!buf) {
565ace46
CK		 3529 ret = -ENODEV;
3530 goto out;
3531 }
3532
3533 adsp_dbg(dsp, "Handling buffer IRQ\n");
3534
9771b18a
CK		 3535 ret = wm_adsp_buffer_get_error(buf);
3536 if (ret < 0)
5847609e 3537 goto out_notify; /* Wake poll to report error */
565ace46
CK		 3538
3539 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3540 &buf->irq_count);
3541 if (ret < 0) {
3542 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3543 goto out;
3544 }
3545
3546 ret = wm_adsp_buffer_update_avail(buf);
3547 if (ret < 0) {
3548 adsp_err(dsp, "Error reading avail: %d\n", ret);
3549 goto out;
3550 }
3551
20b7f7c5
CK		 3552 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3553 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3554
5847609e 3555out_notify:
c7dae7c4 3556 if (compr && compr->stream)
83a40ce9
CK		 3557 snd_compr_fragment_elapsed(compr->stream);
3558
565ace46
CK		 3559out:
3560 mutex_unlock(&dsp->pwr_lock);
3561
3562 return ret;
3563}
3564EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3565
3566static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3567{
3568 if (buf->irq_count & 0x01)
3569 return 0;
3570
3571 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3572 buf->irq_count);
3573
3574 buf->irq_count |= 0x01;
3575
3576 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3577 buf->irq_count);
3578}
3579
3580int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3581 struct snd_compr_tstamp *tstamp)
3582{
3583 struct wm_adsp_compr *compr = stream->runtime->private_data;
565ace46 3584 struct wm_adsp *dsp = compr->dsp;
612047f0 3585 struct wm_adsp_compr_buf *buf;
565ace46
CK		 3586 int ret = 0;
3587
3588 adsp_dbg(dsp, "Pointer request\n");
3589
3590 mutex_lock(&dsp->pwr_lock);
3591
612047f0
CK		 3592 buf = compr->buf;
3593
28ee3d73 3594 if (!compr->buf || compr->buf->error) {
8d280664 3595 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
565ace46
CK		 3596 ret = -EIO;
3597 goto out;
3598 }
3599
3600 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3601 ret = wm_adsp_buffer_update_avail(buf);
3602 if (ret < 0) {
3603 adsp_err(dsp, "Error reading avail: %d\n", ret);
3604 goto out;
3605 }
3606
3607 /*
3608 * If we really have less than 1 fragment available tell the
3609 * DSP to inform us once a whole fragment is available.
3610 */
3611 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
5847609e 3612 ret = wm_adsp_buffer_get_error(buf);
8d280664
CK		 3613 if (ret < 0) {
3614 if (compr->buf->error)
3615 snd_compr_stop_error(stream,
3616 SNDRV_PCM_STATE_XRUN);
5847609e 3617 goto out;
8d280664 3618 }
5847609e 3619
565ace46
CK		 3620 ret = wm_adsp_buffer_reenable_irq(buf);
3621 if (ret < 0) {
3622 adsp_err(dsp,
3623 "Failed to re-enable buffer IRQ: %d\n",
3624 ret);
3625 goto out;
3626 }
3627 }
3628 }
3629
3630 tstamp->copied_total = compr->copied_total;
3631 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
da2b3358 3632 tstamp->sampling_rate = compr->sample_rate;
565ace46
CK		 3633
3634out:
3635 mutex_unlock(&dsp->pwr_lock);
3636
3637 return ret;
3638}
3639EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3640
83a40ce9
CK		 3641static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3642{
3643 struct wm_adsp_compr_buf *buf = compr->buf;
3644 u8 *pack_in = (u8 *)compr->raw_buf;
3645 u8 *pack_out = (u8 *)compr->raw_buf;
3646 unsigned int adsp_addr;
3647 int mem_type, nwords, max_read;
3648 int i, j, ret;
3649
3650 /* Calculate read parameters */
3651 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3652 if (buf->read_index < buf->regions[i].cumulative_size)
3653 break;
3654
3655 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3656 return -EINVAL;
3657
3658 mem_type = buf->regions[i].mem_type;
3659 adsp_addr = buf->regions[i].base_addr +
3660 (buf->read_index - buf->regions[i].offset);
3661
3662 max_read = wm_adsp_compr_frag_words(compr);
3663 nwords = buf->regions[i].cumulative_size - buf->read_index;
3664
3665 if (nwords > target)
3666 nwords = target;
3667 if (nwords > buf->avail)
3668 nwords = buf->avail;
3669 if (nwords > max_read)
3670 nwords = max_read;
3671 if (!nwords)
3672 return 0;
3673
3674 /* Read data from DSP */
3675 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3676 nwords, compr->raw_buf);
3677 if (ret < 0)
3678 return ret;
3679
3680 /* Remove the padding bytes from the data read from the DSP */
3681 for (i = 0; i < nwords; i++) {
3682 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3683 *pack_out++ = *pack_in++;
3684
3685 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3686 }
3687
3688 /* update read index to account for words read */
3689 buf->read_index += nwords;
3690 if (buf->read_index == wm_adsp_buffer_size(buf))
3691 buf->read_index = 0;
3692
3693 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3694 buf->read_index);
3695 if (ret < 0)
3696 return ret;
3697
3698 /* update avail to account for words read */
3699 buf->avail -= nwords;
3700
3701 return nwords;
3702}
3703
3704static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3705 char __user *buf, size_t count)
3706{
3707 struct wm_adsp *dsp = compr->dsp;
3708 int ntotal = 0;
3709 int nwords, nbytes;
3710
3711 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3712
28ee3d73 3713 if (!compr->buf || compr->buf->error) {
8d280664 3714 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
83a40ce9 3715 return -EIO;
8d280664 3716 }
83a40ce9
CK		 3717
3718 count /= WM_ADSP_DATA_WORD_SIZE;
3719
3720 do {
3721 nwords = wm_adsp_buffer_capture_block(compr, count);
3722 if (nwords < 0) {
3723 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3724 return nwords;
3725 }
3726
3727 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3728
3729 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3730
3731 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3732 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3733 ntotal, nbytes);
3734 return -EFAULT;
3735 }
3736
3737 count -= nwords;
3738 ntotal += nbytes;
3739 } while (nwords > 0 && count > 0);
3740
3741 compr->copied_total += ntotal;
3742
3743 return ntotal;
3744}
3745
3746int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3747 size_t count)
3748{
3749 struct wm_adsp_compr *compr = stream->runtime->private_data;
3750 struct wm_adsp *dsp = compr->dsp;
3751 int ret;
3752
3753 mutex_lock(&dsp->pwr_lock);
3754
3755 if (stream->direction == SND_COMPRESS_CAPTURE)
3756 ret = wm_adsp_compr_read(compr, buf, count);
3757 else
3758 ret = -ENOTSUPP;
3759
3760 mutex_unlock(&dsp->pwr_lock);
3761
3762 return ret;
3763}
3764EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3765
51a2c944
MK		 3766int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
3767{
3768 struct regmap *regmap = dsp->regmap;
3769 unsigned int code0, code1, lock_reg;
3770
3771 if (!(lock_regions & WM_ADSP2_REGION_ALL))
3772 return 0;
3773
3774 lock_regions &= WM_ADSP2_REGION_ALL;
3775 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
3776
3777 while (lock_regions) {
3778 code0 = code1 = 0;
3779 if (lock_regions & BIT(0)) {
3780 code0 = ADSP2_LOCK_CODE_0;
3781 code1 = ADSP2_LOCK_CODE_1;
3782 }
3783 if (lock_regions & BIT(1)) {
3784 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
3785 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
3786 }
3787 regmap_write(regmap, lock_reg, code0);
3788 regmap_write(regmap, lock_reg, code1);
3789 lock_regions >>= 2;
3790 lock_reg += 2;
3791 }
3792
3793 return 0;
3794}
3795EXPORT_SYMBOL_GPL(wm_adsp2_lock);
3796
3797irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
3798{
3799 unsigned int val;
3800 struct regmap *regmap = dsp->regmap;
3801 int ret = 0;
3802
3803 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
3804 if (ret) {
3805 adsp_err(dsp,
3806 "Failed to read Region Lock Ctrl register: %d\n", ret);
3807 return IRQ_HANDLED;
3808 }
3809
3810 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
3811 adsp_err(dsp, "watchdog timeout error\n");
3812 wm_adsp_stop_watchdog(dsp);
3813 }
3814
3815 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
3816 if (val & ADSP2_SLAVE_ERR_MASK)
3817 adsp_err(dsp, "bus error: slave error\n");
3818 else
3819 adsp_err(dsp, "bus error: region lock error\n");
3820
3821 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
3822 if (ret) {
3823 adsp_err(dsp,
3824 "Failed to read Bus Err Addr register: %d\n",
3825 ret);
3826 return IRQ_HANDLED;
3827 }
3828
3829 adsp_err(dsp, "bus error address = 0x%x\n",
3830 val & ADSP2_BUS_ERR_ADDR_MASK);
3831
3832 ret = regmap_read(regmap,
3833 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
3834 &val);
3835 if (ret) {
3836 adsp_err(dsp,
3837 "Failed to read Pmem Xmem Err Addr register: %d\n",
3838 ret);
3839 return IRQ_HANDLED;
3840 }
3841
3842 adsp_err(dsp, "xmem error address = 0x%x\n",
3843 val & ADSP2_XMEM_ERR_ADDR_MASK);
3844 adsp_err(dsp, "pmem error address = 0x%x\n",
3845 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
3846 ADSP2_PMEM_ERR_ADDR_SHIFT);
3847 }
3848
3849 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
3850 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
3851
3852 return IRQ_HANDLED;
3853}
3854EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
3855
0a37c6ef 3856MODULE_LICENSE("GPL v2");
Empty description
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