[linux.git] / include / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _LINUX_NVME_H
#define _LINUX_NVME_H

#include <uapi/linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>

struct nvme_bar {
	__u64			cap;	/* Controller Capabilities */
	__u32			vs;	/* Version */
	__u32			intms;	/* Interrupt Mask Set */
	__u32			intmc;	/* Interrupt Mask Clear */
	__u32			cc;	/* Controller Configuration */
	__u32			rsvd1;	/* Reserved */
	__u32			csts;	/* Controller Status */
	__u32			rsvd2;	/* Reserved */
	__u32			aqa;	/* Admin Queue Attributes */
	__u64			asq;	/* Admin SQ Base Address */
	__u64			acq;	/* Admin CQ Base Address */
};

#define NVME_CAP_MQES(cap)	((cap) & 0xffff)
#define NVME_CAP_TIMEOUT(cap)	(((cap) >> 24) & 0xff)
#define NVME_CAP_STRIDE(cap)	(((cap) >> 32) & 0xf)
#define NVME_CAP_MPSMIN(cap)	(((cap) >> 48) & 0xf)
#define NVME_CAP_MPSMAX(cap)	(((cap) >> 52) & 0xf)

enum {
	NVME_CC_ENABLE		= 1 << 0,
	NVME_CC_CSS_NVM		= 0 << 4,
	NVME_CC_MPS_SHIFT	= 7,
	NVME_CC_ARB_RR		= 0 << 11,
	NVME_CC_ARB_WRRU	= 1 << 11,
	NVME_CC_ARB_VS		= 7 << 11,
	NVME_CC_SHN_NONE	= 0 << 14,
	NVME_CC_SHN_NORMAL	= 1 << 14,
	NVME_CC_SHN_ABRUPT	= 2 << 14,
	NVME_CC_SHN_MASK	= 3 << 14,
	NVME_CC_IOSQES		= 6 << 16,
	NVME_CC_IOCQES		= 4 << 20,
	NVME_CSTS_RDY		= 1 << 0,
	NVME_CSTS_CFS		= 1 << 1,
	NVME_CSTS_SHST_NORMAL	= 0 << 2,
	NVME_CSTS_SHST_OCCUR	= 1 << 2,
	NVME_CSTS_SHST_CMPLT	= 2 << 2,
	NVME_CSTS_SHST_MASK	= 3 << 2,
};

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

/*
 * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 */
struct nvme_dev {
	struct list_head node;
	struct nvme_queue **queues;
	struct request_queue *admin_q;
	struct blk_mq_tag_set tagset;
	struct blk_mq_tag_set admin_tagset;
	u32 __iomem *dbs;
	struct pci_dev *pci_dev;
	struct dma_pool *prp_page_pool;
	struct dma_pool *prp_small_pool;
	int instance;
	unsigned queue_count;
	unsigned online_queues;
	unsigned max_qid;
	int q_depth;
	u32 db_stride;
	u32 ctrl_config;
	struct msix_entry *entry;
	struct nvme_bar __iomem *bar;
	struct list_head namespaces;
	struct kref kref;
	struct device *device;
	work_func_t reset_workfn;
	struct work_struct reset_work;
	struct work_struct probe_work;
	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];
	u32 max_hw_sectors;
	u32 stripe_size;
	u32 page_size;
	u16 oncs;
	u16 abort_limit;
	u8 event_limit;
	u8 vwc;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_dev *dev;
	struct request_queue *queue;
	struct gendisk *disk;

	unsigned ns_id;
	int lba_shift;
	int ms;
	int pi_type;
	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

/*
 * The nvme_iod describes the data in an I/O, including the list of PRP
 * entries.  You can't see it in this data structure because C doesn't let
 * me express that.  Use nvme_alloc_iod to ensure there's enough space
 * allocated to store the PRP list.
 */
struct nvme_iod {
	unsigned long private;	/* For the use of the submitter of the I/O */
	int npages;		/* In the PRP list. 0 means small pool in use */
	int offset;		/* Of PRP list */
	int nents;		/* Used in scatterlist */
	int length;		/* Of data, in bytes */
	dma_addr_t first_dma;
	struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
	struct scatterlist sg[0];
};

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

/**
 * nvme_free_iod - frees an nvme_iod
 * @dev: The device that the I/O was submitted to
 * @iod: The memory to free
 */
void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod);

int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int, gfp_t);
struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
				unsigned long addr, unsigned length);
void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
			struct nvme_iod *iod);
int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_ns *,
						struct nvme_command *, u32 *);
int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns);
int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *,
							u32 *result);
int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
							dma_addr_t dma_addr);
int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
			dma_addr_t dma_addr, u32 *result);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

#endif /* _LINUX_NVME_H */
Commit	Line	Data
b60503ba MW	1	/*
b60503ba MW	2	* Definitions for the NVM Express interface
8757ad65	3	* Copyright (c) 2011-2014, Intel Corporation.
b60503ba MW	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
b60503ba MW	13	*/
	14
	15	#ifndef _LINUX_NVME_H
	16	#define _LINUX_NVME_H
	17
42c77683 MW	18	#include <uapi/linux/nvme.h>
42c77683 MW	19	#include <linux/pci.h>
42c77683	20	#include <linux/kref.h>
a4aea562	21	#include <linux/blk-mq.h>
b60503ba MW	22
	23	struct nvme_bar {
	24	__u64 cap; /* Controller Capabilities */
	25	__u32 vs; /* Version */
897cfe1c MW	26	__u32 intms; /* Interrupt Mask Set */
897cfe1c MW	27	__u32 intmc; /* Interrupt Mask Clear */
b60503ba	28	__u32 cc; /* Controller Configuration */
897cfe1c	29	__u32 rsvd1; /* Reserved */
b60503ba	30	__u32 csts; /* Controller Status */
897cfe1c	31	__u32 rsvd2; /* Reserved */
b60503ba MW	32	__u32 aqa; /* Admin Queue Attributes */
	33	__u64 asq; /* Admin SQ Base Address */
	34	__u64 acq; /* Admin CQ Base Address */
	35	};
	36
a0cadb85	37	#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96	38	#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e	39	#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
8fc23e03	40	#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624	41	#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96	42
b60503ba MW	43	enum {
	44	NVME_CC_ENABLE = 1 << 0,
	45	NVME_CC_CSS_NVM = 0 << 4,
	46	NVME_CC_MPS_SHIFT = 7,
	47	NVME_CC_ARB_RR = 0 << 11,
	48	NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2 MW	49	NVME_CC_ARB_VS = 7 << 11,
	50	NVME_CC_SHN_NONE = 0 << 14,
	51	NVME_CC_SHN_NORMAL = 1 << 14,
	52	NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1	53	NVME_CC_SHN_MASK = 3 << 14,
7f53f9d2 MW	54	NVME_CC_IOSQES = 6 << 16,
7f53f9d2 MW	55	NVME_CC_IOCQES = 4 << 20,
b60503ba MW	56	NVME_CSTS_RDY = 1 << 0,
	57	NVME_CSTS_CFS = 1 << 1,
	58	NVME_CSTS_SHST_NORMAL = 0 << 2,
	59	NVME_CSTS_SHST_OCCUR = 1 << 2,
	60	NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1	61	NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba MW	62	};
b60503ba MW	63
bd67608a MW	64	extern unsigned char nvme_io_timeout;
bd67608a MW	65	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
13c3b0fc VV	66
	67	/*
	68	* Represents an NVM Express device. Each nvme_dev is a PCI function.
	69	*/
	70	struct nvme_dev {
	71	struct list_head node;
a4aea562 MB	72	struct nvme_queue **queues;
	73	struct request_queue *admin_q;
	74	struct blk_mq_tag_set tagset;
	75	struct blk_mq_tag_set admin_tagset;
13c3b0fc VV	76	u32 __iomem *dbs;
	77	struct pci_dev *pci_dev;
	78	struct dma_pool *prp_page_pool;
	79	struct dma_pool *prp_small_pool;
	80	int instance;
42f61420 KB	81	unsigned queue_count;
	82	unsigned online_queues;
	83	unsigned max_qid;
	84	int q_depth;
b80d5ccc	85	u32 db_stride;
13c3b0fc VV	86	u32 ctrl_config;
	87	struct msix_entry *entry;
	88	struct nvme_bar __iomem *bar;
	89	struct list_head namespaces;
5e82e952	90	struct kref kref;
b3fffdef	91	struct device *device;
9ca97374	92	work_func_t reset_workfn;
9a6b9458	93	struct work_struct reset_work;
2e1d8448	94	struct work_struct probe_work;
5e82e952	95	char name[12];
13c3b0fc VV	96	char serial[20];
	97	char model[40];
	98	char firmware_rev[8];
	99	u32 max_hw_sectors;
159b67d7	100	u32 stripe_size;
1d090624	101	u32 page_size;
13c3b0fc	102	u16 oncs;
c30341dc	103	u16 abort_limit;
6fccf938	104	u8 event_limit;
a7d2ce28	105	u8 vwc;
13c3b0fc VV	106	};
	107
	108	/*
	109	* An NVM Express namespace is equivalent to a SCSI LUN
	110	*/
	111	struct nvme_ns {
	112	struct list_head list;
	113
	114	struct nvme_dev *dev;
	115	struct request_queue *queue;
	116	struct gendisk *disk;
	117
c3bfe717	118	unsigned ns_id;
13c3b0fc	119	int lba_shift;
f410c680	120	int ms;
e1e5e564	121	int pi_type;
5d0f6131 VV	122	u64 mode_select_num_blocks;
5d0f6131 VV	123	u32 mode_select_block_len;
13c3b0fc VV	124	};
	125
	126	/*
	127	* The nvme_iod describes the data in an I/O, including the list of PRP
	128	* entries. You can't see it in this data structure because C doesn't let
	129	* me express that. Use nvme_alloc_iod to ensure there's enough space
	130	* allocated to store the PRP list.
	131	*/
	132	struct nvme_iod {
ac3dd5bd	133	unsigned long private; /* For the use of the submitter of the I/O */
13c3b0fc VV	134	int npages; /* In the PRP list. 0 means small pool in use */
	135	int offset; /* Of PRP list */
	136	int nents; /* Used in scatterlist */
	137	int length; /* Of data, in bytes */
	138	dma_addr_t first_dma;
e1e5e564	139	struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
13c3b0fc VV	140	struct scatterlist sg[0];
13c3b0fc VV	141	};
5d0f6131	142
063cc6d5 MW	143	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	144	{
	145	return (sector >> (ns->lba_shift - 9));
	146	}
	147
5d0f6131 VV	148	/**
	149	* nvme_free_iod - frees an nvme_iod
	150	* @dev: The device that the I/O was submitted to
	151	* @iod: The memory to free
	152	*/
	153	void nvme_free_iod(struct nvme_dev dev, struct nvme_iod iod);
	154
a4aea562	155	int nvme_setup_prps(struct nvme_dev , struct nvme_iod , int, gfp_t);
5d0f6131 VV	156	struct nvme_iod nvme_map_user_pages(struct nvme_dev dev, int write,
	157	unsigned long addr, unsigned length);
	158	void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
	159	struct nvme_iod *iod);
a4aea562 MB	160	int nvme_submit_io_cmd(struct nvme_dev , struct nvme_ns ,
	161	struct nvme_command , u32 );
	162	int nvme_submit_flush_data(struct nvme_queue nvmeq, struct nvme_ns ns);
5d0f6131 VV	163	int nvme_submit_admin_cmd(struct nvme_dev , struct nvme_command ,
	164	u32 *result);
	165	int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
	166	dma_addr_t dma_addr);
	167	int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
	168	dma_addr_t dma_addr, u32 *result);
	169	int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
	170	dma_addr_t dma_addr, u32 *result);
	171
	172	struct sg_io_hdr;
	173
	174	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
320a3827	175	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
5d0f6131 VV	176	int nvme_sg_get_version_num(int __user *ip);
5d0f6131 VV	177
b60503ba	178	#endif /* _LINUX_NVME_H */