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Merge tag 'devicetree-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh...
[linux.git] / drivers / media / dvb-frontends / tda10086.c
CommitLineData
6bca3580
AQ		 1 /*
2 Driver for Philips tda10086 DVBS Demodulator
3
4 (c) 2006 Andrew de Quincey
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22
23#include <linux/init.h>
24#include <linux/module.h>
6bca3580
AQ		 25#include <linux/device.h>
26#include <linux/jiffies.h>
27#include <linux/string.h>
28#include <linux/slab.h>
29
30#include "dvb_frontend.h"
31#include "tda10086.h"
32
33#define SACLK 96000000
34
35struct tda10086_state {
36 struct i2c_adapter* i2c;
37 const struct tda10086_config* config;
38 struct dvb_frontend frontend;
39
40 /* private demod data */
41 u32 frequency;
42 u32 symbol_rate;
c6604150 43 bool has_lock;
6bca3580
AQ		 44};
45
ff699e6b 46static int debug;
6bca3580
AQ		 47#define dprintk(args...) \
48 do { \
49 if (debug) printk(KERN_DEBUG "tda10086: " args); \
50 } while (0)
51
52static int tda10086_write_byte(struct tda10086_state *state, int reg, int data)
53{
54 int ret;
55 u8 b0[] = { reg, data };
56 struct i2c_msg msg = { .flags = 0, .buf = b0, .len = 2 };
57
58 msg.addr = state->config->demod_address;
59 ret = i2c_transfer(state->i2c, &msg, 1);
60
61 if (ret != 1)
62 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
271ddbf7 63 __func__, reg, data, ret);
6bca3580
AQ		 64
65 return (ret != 1) ? ret : 0;
66}
67
68static int tda10086_read_byte(struct tda10086_state *state, int reg)
69{
70 int ret;
71 u8 b0[] = { reg };
72 u8 b1[] = { 0 };
73 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
74 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
75
76 msg[0].addr = state->config->demod_address;
77 msg[1].addr = state->config->demod_address;
78 ret = i2c_transfer(state->i2c, msg, 2);
79
80 if (ret != 2) {
271ddbf7 81 dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
6bca3580
AQ		 82 ret);
83 return ret;
84 }
85
86 return b1[0];
87}
88
89static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data)
90{
91 int val;
92
b1c54fe2 93 /* read a byte and check */
6bca3580
AQ		 94 val = tda10086_read_byte(state, reg);
95 if (val < 0)
96 return val;
97
b1c54fe2 98 /* mask if off */
6bca3580
AQ		 99 val = val & ~mask;
100 val |= data & 0xff;
101
b1c54fe2 102 /* write it out again */
6bca3580
AQ		 103 return tda10086_write_byte(state, reg, val);
104}
105
106static int tda10086_init(struct dvb_frontend* fe)
107{
108 struct tda10086_state* state = fe->demodulator_priv;
ea75baf4 109 u8 t22k_off = 0x80;
6bca3580 110
271ddbf7 111 dprintk ("%s\n", __func__);
6bca3580 112
ea75baf4
HH		 113 if (state->config->diseqc_tone)
114 t22k_off = 0;
b1c54fe2 115 /* reset */
6bca3580
AQ		 116 tda10086_write_byte(state, 0x00, 0x00);
117 msleep(10);
118
b1c54fe2 119 /* misc setup */
6bca3580 120 tda10086_write_byte(state, 0x01, 0x94);
b1c54fe2 121 tda10086_write_byte(state, 0x02, 0x35); /* NOTE: TT drivers appear to disable CSWP */
c6604150 122 tda10086_write_byte(state, 0x03, 0xe4);
6bca3580
AQ		 123 tda10086_write_byte(state, 0x04, 0x43);
124 tda10086_write_byte(state, 0x0c, 0x0c);
b1c54fe2
HH		 125 tda10086_write_byte(state, 0x1b, 0xb0); /* noise threshold */
126 tda10086_write_byte(state, 0x20, 0x89); /* misc */
127 tda10086_write_byte(state, 0x30, 0x04); /* acquisition period length */
128 tda10086_write_byte(state, 0x32, 0x00); /* irq off */
129 tda10086_write_byte(state, 0x31, 0x56); /* setup AFC */
130
131 /* setup PLL (this assumes SACLK = 96MHz) */
132 tda10086_write_byte(state, 0x55, 0x2c); /* misc PLL setup */
9a1b04e4 133 if (state->config->xtal_freq == TDA10086_XTAL_16M) {
b1c54fe2
HH		 134 tda10086_write_byte(state, 0x3a, 0x0b); /* M=12 */
135 tda10086_write_byte(state, 0x3b, 0x01); /* P=2 */
9a1b04e4 136 } else {
b1c54fe2
HH		 137 tda10086_write_byte(state, 0x3a, 0x17); /* M=24 */
138 tda10086_write_byte(state, 0x3b, 0x00); /* P=1 */
9a1b04e4 139 }
b1c54fe2 140 tda10086_write_mask(state, 0x55, 0x20, 0x00); /* powerup PLL */
6bca3580 141
b1c54fe2 142 /* setup TS interface */
6bca3580
AQ		 143 tda10086_write_byte(state, 0x11, 0x81);
144 tda10086_write_byte(state, 0x12, 0x81);
b1c54fe2
HH		 145 tda10086_write_byte(state, 0x19, 0x40); /* parallel mode A + MSBFIRST */
146 tda10086_write_byte(state, 0x56, 0x80); /* powerdown WPLL - unused in the mode we use */
147 tda10086_write_byte(state, 0x57, 0x08); /* bypass WPLL - unused in the mode we use */
6bca3580
AQ		 148 tda10086_write_byte(state, 0x10, 0x2a);
149
b1c54fe2
HH		 150 /* setup ADC */
151 tda10086_write_byte(state, 0x58, 0x61); /* ADC setup */
152 tda10086_write_mask(state, 0x58, 0x01, 0x00); /* powerup ADC */
6bca3580 153
b1c54fe2 154 /* setup AGC */
6bca3580
AQ		 155 tda10086_write_byte(state, 0x05, 0x0B);
156 tda10086_write_byte(state, 0x37, 0x63);
b1c54fe2 157 tda10086_write_byte(state, 0x3f, 0x0a); /* NOTE: flydvb varies it */
6bca3580
AQ		 158 tda10086_write_byte(state, 0x40, 0x64);
159 tda10086_write_byte(state, 0x41, 0x4f);
160 tda10086_write_byte(state, 0x42, 0x43);
161
b1c54fe2
HH		 162 /* setup viterbi */
163 tda10086_write_byte(state, 0x1a, 0x11); /* VBER 10^6, DVB, QPSK */
6bca3580 164
b1c54fe2 165 /* setup carrier recovery */
6bca3580
AQ		 166 tda10086_write_byte(state, 0x3d, 0x80);
167
b1c54fe2
HH		 168 /* setup SEC */
169 tda10086_write_byte(state, 0x36, t22k_off); /* all SEC off, 22k tone */
170 tda10086_write_byte(state, 0x34, (((1<<19) * (22000/1000)) / (SACLK/1000)));
171 tda10086_write_byte(state, 0x35, (((1<<19) * (22000/1000)) / (SACLK/1000)) >> 8);
6bca3580
AQ		 172
173 return 0;
174}
175
176static void tda10086_diseqc_wait(struct tda10086_state *state)
177{
178 unsigned long timeout = jiffies + msecs_to_jiffies(200);
179 while (!(tda10086_read_byte(state, 0x50) & 0x01)) {
180 if(time_after(jiffies, timeout)) {
271ddbf7 181 printk("%s: diseqc queue not ready, command may be lost.\n", __func__);
6bca3580
AQ		 182 break;
183 }
184 msleep(10);
185 }
186}
187
0df289a2
MCC		 188static int tda10086_set_tone(struct dvb_frontend *fe,
189 enum fe_sec_tone_mode tone)
6bca3580
AQ		 190{
191 struct tda10086_state* state = fe->demodulator_priv;
ea75baf4 192 u8 t22k_off = 0x80;
6bca3580 193
271ddbf7 194 dprintk ("%s\n", __func__);
6bca3580 195
ea75baf4
HH		 196 if (state->config->diseqc_tone)
197 t22k_off = 0;
198
33f77714 199 switch (tone) {
6bca3580 200 case SEC_TONE_OFF:
ea75baf4 201 tda10086_write_byte(state, 0x36, t22k_off);
6bca3580
AQ		 202 break;
203
204 case SEC_TONE_ON:
ea75baf4 205 tda10086_write_byte(state, 0x36, 0x01 + t22k_off);
6bca3580
AQ		 206 break;
207 }
208
209 return 0;
210}
211
212static int tda10086_send_master_cmd (struct dvb_frontend* fe,
213 struct dvb_diseqc_master_cmd* cmd)
214{
215 struct tda10086_state* state = fe->demodulator_priv;
216 int i;
217 u8 oldval;
ea75baf4 218 u8 t22k_off = 0x80;
6bca3580 219
271ddbf7 220 dprintk ("%s\n", __func__);
6bca3580 221
ea75baf4
HH		 222 if (state->config->diseqc_tone)
223 t22k_off = 0;
224
6bca3580
AQ		 225 if (cmd->msg_len > 6)
226 return -EINVAL;
227 oldval = tda10086_read_byte(state, 0x36);
228
229 for(i=0; i< cmd->msg_len; i++) {
230 tda10086_write_byte(state, 0x48+i, cmd->msg[i]);
231 }
ea75baf4
HH		 232 tda10086_write_byte(state, 0x36, (0x08 + t22k_off)
233 | ((cmd->msg_len - 1) << 4));
6bca3580
AQ		 234
235 tda10086_diseqc_wait(state);
236
237 tda10086_write_byte(state, 0x36, oldval);
238
239 return 0;
240}
241
0df289a2
MCC		 242static int tda10086_send_burst(struct dvb_frontend *fe,
243 enum fe_sec_mini_cmd minicmd)
6bca3580
AQ		 244{
245 struct tda10086_state* state = fe->demodulator_priv;
246 u8 oldval = tda10086_read_byte(state, 0x36);
ea75baf4 247 u8 t22k_off = 0x80;
6bca3580 248
271ddbf7 249 dprintk ("%s\n", __func__);
6bca3580 250
ea75baf4
HH		 251 if (state->config->diseqc_tone)
252 t22k_off = 0;
253
6bca3580
AQ		 254 switch(minicmd) {
255 case SEC_MINI_A:
ea75baf4 256 tda10086_write_byte(state, 0x36, 0x04 + t22k_off);
6bca3580
AQ		 257 break;
258
259 case SEC_MINI_B:
ea75baf4 260 tda10086_write_byte(state, 0x36, 0x06 + t22k_off);
6bca3580
AQ		 261 break;
262 }
263
264 tda10086_diseqc_wait(state);
265
266 tda10086_write_byte(state, 0x36, oldval);
267
268 return 0;
269}
270
271static int tda10086_set_inversion(struct tda10086_state *state,
6714049e 272 struct dtv_frontend_properties *fe_params)
6bca3580
AQ		 273{
274 u8 invval = 0x80;
275
271ddbf7 276 dprintk ("%s %i %i\n", __func__, fe_params->inversion, state->config->invert);
6bca3580
AQ		 277
278 switch(fe_params->inversion) {
279 case INVERSION_OFF:
280 if (state->config->invert)
281 invval = 0x40;
282 break;
283 case INVERSION_ON:
284 if (!state->config->invert)
285 invval = 0x40;
286 break;
287 case INVERSION_AUTO:
288 invval = 0x00;
289 break;
290 }
291 tda10086_write_mask(state, 0x0c, 0xc0, invval);
292
293 return 0;
294}
295
296static int tda10086_set_symbol_rate(struct tda10086_state *state,
6714049e 297 struct dtv_frontend_properties *fe_params)
6bca3580
AQ		 298{
299 u8 dfn = 0;
300 u8 afs = 0;
301 u8 byp = 0;
302 u8 reg37 = 0x43;
303 u8 reg42 = 0x43;
304 u64 big;
305 u32 tmp;
306 u32 bdr;
307 u32 bdri;
6714049e 308 u32 symbol_rate = fe_params->symbol_rate;
6bca3580 309
271ddbf7 310 dprintk ("%s %i\n", __func__, symbol_rate);
6bca3580 311
b1c54fe2 312 /* setup the decimation and anti-aliasing filters.. */
6bca3580
AQ		 313 if (symbol_rate < (u32) (SACLK * 0.0137)) {
314 dfn=4;
315 afs=1;
316 } else if (symbol_rate < (u32) (SACLK * 0.0208)) {
317 dfn=4;
318 afs=0;
319 } else if (symbol_rate < (u32) (SACLK * 0.0270)) {
320 dfn=3;
321 afs=1;
322 } else if (symbol_rate < (u32) (SACLK * 0.0416)) {
323 dfn=3;
324 afs=0;
325 } else if (symbol_rate < (u32) (SACLK * 0.0550)) {
326 dfn=2;
327 afs=1;
328 } else if (symbol_rate < (u32) (SACLK * 0.0833)) {
329 dfn=2;
330 afs=0;
331 } else if (symbol_rate < (u32) (SACLK * 0.1100)) {
332 dfn=1;
333 afs=1;
334 } else if (symbol_rate < (u32) (SACLK * 0.1666)) {
335 dfn=1;
336 afs=0;
337 } else if (symbol_rate < (u32) (SACLK * 0.2200)) {
338 dfn=0;
339 afs=1;
340 } else if (symbol_rate < (u32) (SACLK * 0.3333)) {
341 dfn=0;
342 afs=0;
343 } else {
344 reg37 = 0x63;
345 reg42 = 0x4f;
346 byp=1;
347 }
348
b1c54fe2 349 /* calculate BDR */
6bca3580
AQ		 350 big = (1ULL<<21) * ((u64) symbol_rate/1000ULL) * (1ULL<<dfn);
351 big += ((SACLK/1000ULL)-1ULL);
352 do_div(big, (SACLK/1000ULL));
353 bdr = big & 0xfffff;
354
b1c54fe2 355 /* calculate BDRI */
6bca3580
AQ		 356 tmp = (1<<dfn)*(symbol_rate/1000);
357 bdri = ((32 * (SACLK/1000)) + (tmp-1)) / tmp;
358
359 tda10086_write_byte(state, 0x21, (afs << 7) | dfn);
360 tda10086_write_mask(state, 0x20, 0x08, byp << 3);
361 tda10086_write_byte(state, 0x06, bdr);
362 tda10086_write_byte(state, 0x07, bdr >> 8);
363 tda10086_write_byte(state, 0x08, bdr >> 16);
364 tda10086_write_byte(state, 0x09, bdri);
365 tda10086_write_byte(state, 0x37, reg37);
366 tda10086_write_byte(state, 0x42, reg42);
367
368 return 0;
369}
370
371static int tda10086_set_fec(struct tda10086_state *state,
6714049e 372 struct dtv_frontend_properties *fe_params)
6bca3580
AQ		 373{
374 u8 fecval;
375
6714049e 376 dprintk("%s %i\n", __func__, fe_params->fec_inner);
6bca3580 377
6714049e 378 switch (fe_params->fec_inner) {
6bca3580
AQ		 379 case FEC_1_2:
380 fecval = 0x00;
381 break;
382 case FEC_2_3:
383 fecval = 0x01;
384 break;
385 case FEC_3_4:
386 fecval = 0x02;
387 break;
388 case FEC_4_5:
389 fecval = 0x03;
390 break;
391 case FEC_5_6:
392 fecval = 0x04;
393 break;
394 case FEC_6_7:
395 fecval = 0x05;
396 break;
397 case FEC_7_8:
398 fecval = 0x06;
399 break;
400 case FEC_8_9:
401 fecval = 0x07;
402 break;
403 case FEC_AUTO:
404 fecval = 0x08;
405 break;
406 default:
407 return -1;
408 }
409 tda10086_write_byte(state, 0x0d, fecval);
410
411 return 0;
412}
413
6714049e 414static int tda10086_set_frontend(struct dvb_frontend *fe)
6bca3580 415{
6714049e 416 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
6bca3580
AQ		 417 struct tda10086_state *state = fe->demodulator_priv;
418 int ret;
419 u32 freq = 0;
420 int freqoff;
421
271ddbf7 422 dprintk ("%s\n", __func__);
6bca3580 423
b1c54fe2 424 /* modify parameters for tuning */
c6604150
OE		 425 tda10086_write_byte(state, 0x02, 0x35);
426 state->has_lock = false;
427
b1c54fe2 428 /* set params */
6bca3580 429 if (fe->ops.tuner_ops.set_params) {
14d24d14 430 fe->ops.tuner_ops.set_params(fe);
6bca3580
AQ		 431 if (fe->ops.i2c_gate_ctrl)
432 fe->ops.i2c_gate_ctrl(fe, 0);
433
434 if (fe->ops.tuner_ops.get_frequency)
435 fe->ops.tuner_ops.get_frequency(fe, &freq);
436 if (fe->ops.i2c_gate_ctrl)
437 fe->ops.i2c_gate_ctrl(fe, 0);
438 }
439
b1c54fe2 440 /* calcluate the frequency offset (in *Hz* not kHz) */
6bca3580
AQ		 441 freqoff = fe_params->frequency - freq;
442 freqoff = ((1<<16) * freqoff) / (SACLK/1000);
443 tda10086_write_byte(state, 0x3d, 0x80 | ((freqoff >> 8) & 0x7f));
444 tda10086_write_byte(state, 0x3e, freqoff);
445
446 if ((ret = tda10086_set_inversion(state, fe_params)) < 0)
447 return ret;
448 if ((ret = tda10086_set_symbol_rate(state, fe_params)) < 0)
449 return ret;
450 if ((ret = tda10086_set_fec(state, fe_params)) < 0)
451 return ret;
452
b1c54fe2 453 /* soft reset + disable TS output until lock */
6bca3580
AQ		 454 tda10086_write_mask(state, 0x10, 0x40, 0x40);
455 tda10086_write_mask(state, 0x00, 0x01, 0x00);
456
6714049e 457 state->symbol_rate = fe_params->symbol_rate;
6bca3580
AQ		 458 state->frequency = fe_params->frequency;
459 return 0;
460}
461
7e3e68bc
MCC		 462static int tda10086_get_frontend(struct dvb_frontend *fe,
463 struct dtv_frontend_properties *fe_params)
6bca3580
AQ		 464{
465 struct tda10086_state* state = fe->demodulator_priv;
466 u8 val;
467 int tmp;
468 u64 tmp64;
469
271ddbf7 470 dprintk ("%s\n", __func__);
6bca3580 471
b1c54fe2 472 /* check for invalid symbol rate */
6714049e 473 if (fe_params->symbol_rate < 500000)
221a09d5
AQ		 474 return -EINVAL;
475
b1c54fe2 476 /* calculate the updated frequency (note: we convert from Hz->kHz) */
b674ac29
MCC		 477 tmp64 = ((u64)tda10086_read_byte(state, 0x52)
478 | (tda10086_read_byte(state, 0x51) << 8));
6bca3580
AQ		 479 if (tmp64 & 0x8000)
480 tmp64 |= 0xffffffffffff0000ULL;
481 tmp64 = (tmp64 * (SACLK/1000ULL));
482 do_div(tmp64, (1ULL<<15) * (1ULL<<1));
483 fe_params->frequency = (int) state->frequency + (int) tmp64;
484
b1c54fe2 485 /* the inversion */
6bca3580
AQ		 486 val = tda10086_read_byte(state, 0x0c);
487 if (val & 0x80) {
488 switch(val & 0x40) {
489 case 0x00:
490 fe_params->inversion = INVERSION_OFF;
491 if (state->config->invert)
492 fe_params->inversion = INVERSION_ON;
493 break;
494 default:
495 fe_params->inversion = INVERSION_ON;
496 if (state->config->invert)
497 fe_params->inversion = INVERSION_OFF;
498 break;
499 }
500 } else {
501 tda10086_read_byte(state, 0x0f);
502 switch(val & 0x02) {
503 case 0x00:
504 fe_params->inversion = INVERSION_OFF;
505 if (state->config->invert)
506 fe_params->inversion = INVERSION_ON;
507 break;
508 default:
509 fe_params->inversion = INVERSION_ON;
510 if (state->config->invert)
511 fe_params->inversion = INVERSION_OFF;
512 break;
513 }
514 }
515
b1c54fe2 516 /* calculate the updated symbol rate */
6bca3580
AQ		 517 tmp = tda10086_read_byte(state, 0x1d);
518 if (tmp & 0x80)
519 tmp |= 0xffffff00;
520 tmp = (tmp * 480 * (1<<1)) / 128;
521 tmp = ((state->symbol_rate/1000) * tmp) / (1000000/1000);
6714049e 522 fe_params->symbol_rate = state->symbol_rate + tmp;
6bca3580 523
b1c54fe2 524 /* the FEC */
6bca3580
AQ		 525 val = (tda10086_read_byte(state, 0x0d) & 0x70) >> 4;
526 switch(val) {
527 case 0x00:
6714049e 528 fe_params->fec_inner = FEC_1_2;
6bca3580
AQ		 529 break;
530 case 0x01:
6714049e 531 fe_params->fec_inner = FEC_2_3;
6bca3580
AQ		 532 break;
533 case 0x02:
6714049e 534 fe_params->fec_inner = FEC_3_4;
6bca3580
AQ		 535 break;
536 case 0x03:
6714049e 537 fe_params->fec_inner = FEC_4_5;
6bca3580
AQ		 538 break;
539 case 0x04:
6714049e 540 fe_params->fec_inner = FEC_5_6;
6bca3580
AQ		 541 break;
542 case 0x05:
6714049e 543 fe_params->fec_inner = FEC_6_7;
6bca3580
AQ		 544 break;
545 case 0x06:
6714049e 546 fe_params->fec_inner = FEC_7_8;
6bca3580
AQ		 547 break;
548 case 0x07:
6714049e 549 fe_params->fec_inner = FEC_8_9;
6bca3580
AQ		 550 break;
551 }
552
553 return 0;
554}
555
0df289a2
MCC		 556static int tda10086_read_status(struct dvb_frontend *fe,
557 enum fe_status *fe_status)
6bca3580
AQ		 558{
559 struct tda10086_state* state = fe->demodulator_priv;
560 u8 val;
561
271ddbf7 562 dprintk ("%s\n", __func__);
6bca3580
AQ		 563
564 val = tda10086_read_byte(state, 0x0e);
565 *fe_status = 0;
566 if (val & 0x01)
567 *fe_status |= FE_HAS_SIGNAL;
568 if (val & 0x02)
569 *fe_status |= FE_HAS_CARRIER;
570 if (val & 0x04)
571 *fe_status |= FE_HAS_VITERBI;
572 if (val & 0x08)
573 *fe_status |= FE_HAS_SYNC;
c6604150 574 if (val & 0x10) {
6bca3580 575 *fe_status |= FE_HAS_LOCK;
c6604150
OE		 576 if (!state->has_lock) {
577 state->has_lock = true;
b1c54fe2 578 /* modify parameters for stable reception */
c6604150
OE		 579 tda10086_write_byte(state, 0x02, 0x00);
580 }
581 }
6bca3580
AQ		 582
583 return 0;
584}
585
586static int tda10086_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
587{
588 struct tda10086_state* state = fe->demodulator_priv;
589 u8 _str;
590
271ddbf7 591 dprintk ("%s\n", __func__);
6bca3580 592
c6604150 593 _str = 0xff - tda10086_read_byte(state, 0x43);
6bca3580
AQ		 594 *signal = (_str << 8) | _str;
595
596 return 0;
597}
598
599static int tda10086_read_snr(struct dvb_frontend* fe, u16 * snr)
600{
601 struct tda10086_state* state = fe->demodulator_priv;
602 u8 _snr;
603
271ddbf7 604 dprintk ("%s\n", __func__);
6bca3580 605
c6604150 606 _snr = 0xff - tda10086_read_byte(state, 0x1c);
6bca3580
AQ		 607 *snr = (_snr << 8) | _snr;
608
609 return 0;
610}
611
612static int tda10086_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
613{
614 struct tda10086_state* state = fe->demodulator_priv;
615
271ddbf7 616 dprintk ("%s\n", __func__);
6bca3580 617
b1c54fe2 618 /* read it */
6bca3580
AQ		 619 *ucblocks = tda10086_read_byte(state, 0x18) & 0x7f;
620
b1c54fe2 621 /* reset counter */
6bca3580
AQ		 622 tda10086_write_byte(state, 0x18, 0x00);
623 tda10086_write_byte(state, 0x18, 0x80);
624
625 return 0;
626}
627
628static int tda10086_read_ber(struct dvb_frontend* fe, u32* ber)
629{
630 struct tda10086_state* state = fe->demodulator_priv;
631
271ddbf7 632 dprintk ("%s\n", __func__);
6bca3580 633
b1c54fe2 634 /* read it */
6bca3580
AQ		 635 *ber = 0;
636 *ber |= tda10086_read_byte(state, 0x15);
637 *ber |= tda10086_read_byte(state, 0x16) << 8;
638 *ber |= (tda10086_read_byte(state, 0x17) & 0xf) << 16;
639
640 return 0;
641}
642
643static int tda10086_sleep(struct dvb_frontend* fe)
644{
645 struct tda10086_state* state = fe->demodulator_priv;
646
271ddbf7 647 dprintk ("%s\n", __func__);
6bca3580
AQ		 648
649 tda10086_write_mask(state, 0x00, 0x08, 0x08);
650
651 return 0;
652}
653
654static int tda10086_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
655{
656 struct tda10086_state* state = fe->demodulator_priv;
657
271ddbf7 658 dprintk ("%s\n", __func__);
6bca3580
AQ		 659
660 if (enable) {
661 tda10086_write_mask(state, 0x00, 0x10, 0x10);
662 } else {
663 tda10086_write_mask(state, 0x00, 0x10, 0x00);
664 }
665
666 return 0;
667}
668
669static int tda10086_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
670{
5581e130
MCC		 671 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
672
673 if (p->symbol_rate > 20000000) {
6bca3580
AQ		 674 fesettings->min_delay_ms = 50;
675 fesettings->step_size = 2000;
676 fesettings->max_drift = 8000;
5581e130 677 } else if (p->symbol_rate > 12000000) {
6bca3580
AQ		 678 fesettings->min_delay_ms = 100;
679 fesettings->step_size = 1500;
680 fesettings->max_drift = 9000;
5581e130 681 } else if (p->symbol_rate > 8000000) {
6bca3580
AQ		 682 fesettings->min_delay_ms = 100;
683 fesettings->step_size = 1000;
684 fesettings->max_drift = 8000;
5581e130 685 } else if (p->symbol_rate > 4000000) {
6bca3580
AQ		 686 fesettings->min_delay_ms = 100;
687 fesettings->step_size = 500;
688 fesettings->max_drift = 7000;
5581e130 689 } else if (p->symbol_rate > 2000000) {
6bca3580 690 fesettings->min_delay_ms = 200;
5581e130 691 fesettings->step_size = p->symbol_rate / 8000;
6bca3580
AQ		 692 fesettings->max_drift = 14 * fesettings->step_size;
693 } else {
694 fesettings->min_delay_ms = 200;
5581e130 695 fesettings->step_size = p->symbol_rate / 8000;
6bca3580
AQ		 696 fesettings->max_drift = 18 * fesettings->step_size;
697 }
698
699 return 0;
700}
701
702static void tda10086_release(struct dvb_frontend* fe)
703{
704 struct tda10086_state *state = fe->demodulator_priv;
705 tda10086_sleep(fe);
706 kfree(state);
707}
708
709static struct dvb_frontend_ops tda10086_ops = {
6714049e 710 .delsys = { SYS_DVBS },
6bca3580
AQ		 711 .info = {
712 .name = "Philips TDA10086 DVB-S",
6bca3580
AQ		 713 .frequency_min = 950000,
714 .frequency_max = 2150000,
715 .frequency_stepsize = 125, /* kHz for QPSK frontends */
716 .symbol_rate_min = 1000000,
717 .symbol_rate_max = 45000000,
718 .caps = FE_CAN_INVERSION_AUTO |
719 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
720 FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
721 FE_CAN_QPSK
722 },
723
724 .release = tda10086_release,
725
726 .init = tda10086_init,
727 .sleep = tda10086_sleep,
728 .i2c_gate_ctrl = tda10086_i2c_gate_ctrl,
729
6714049e
MCC		 730 .set_frontend = tda10086_set_frontend,
731 .get_frontend = tda10086_get_frontend,
6bca3580
AQ		 732 .get_tune_settings = tda10086_get_tune_settings,
733
734 .read_status = tda10086_read_status,
735 .read_ber = tda10086_read_ber,
736 .read_signal_strength = tda10086_read_signal_strength,
737 .read_snr = tda10086_read_snr,
738 .read_ucblocks = tda10086_read_ucblocks,
739
740 .diseqc_send_master_cmd = tda10086_send_master_cmd,
741 .diseqc_send_burst = tda10086_send_burst,
742 .set_tone = tda10086_set_tone,
743};
744
745struct dvb_frontend* tda10086_attach(const struct tda10086_config* config,
746 struct i2c_adapter* i2c)
747{
748 struct tda10086_state *state;
749
271ddbf7 750 dprintk ("%s\n", __func__);
6bca3580
AQ		 751
752 /* allocate memory for the internal state */
084e24ac 753 state = kzalloc(sizeof(struct tda10086_state), GFP_KERNEL);
6bca3580
AQ		 754 if (!state)
755 return NULL;
756
757 /* setup the state */
758 state->config = config;
759 state->i2c = i2c;
760
761 /* check if the demod is there */
762 if (tda10086_read_byte(state, 0x1e) != 0xe1) {
763 kfree(state);
764 return NULL;
765 }
766
767 /* create dvb_frontend */
768 memcpy(&state->frontend.ops, &tda10086_ops, sizeof(struct dvb_frontend_ops));
769 state->frontend.demodulator_priv = state;
770 return &state->frontend;
771}
772
773module_param(debug, int, 0644);
774MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
775
776MODULE_DESCRIPTION("Philips TDA10086 DVB-S Demodulator");
777MODULE_AUTHOR("Andrew de Quincey");
778MODULE_LICENSE("GPL");
779
780EXPORT_SYMBOL(tda10086_attach);
Empty description
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