projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 14752412 TI |
1 | /* |
| 2 | * HD-audio controller (Azalia) registers and helpers | |
| 3 | * | |
| 4 | * For traditional reasons, we still use azx_ prefix here | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __SOUND_HDA_REGISTER_H | |
| 8 | #define __SOUND_HDA_REGISTER_H | |
| 9 | ||
| 10 | #include <linux/io.h> | |
| 11 | #include <sound/hdaudio.h> | |
| 12 | ||
| 13 | #define AZX_REG_GCAP 0x00 | |
| 14 | #define AZX_GCAP_64OK (1 << 0) /* 64bit address support */ | |
| 15 | #define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */ | |
| 16 | #define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */ | |
| 17 | #define AZX_GCAP_ISS (15 << 8) /* # of input streams */ | |
| 18 | #define AZX_GCAP_OSS (15 << 12) /* # of output streams */ | |
| 19 | #define AZX_REG_VMIN 0x02 | |
| 20 | #define AZX_REG_VMAJ 0x03 | |
| 21 | #define AZX_REG_OUTPAY 0x04 | |
| 22 | #define AZX_REG_INPAY 0x06 | |
| 23 | #define AZX_REG_GCTL 0x08 | |
| 24 | #define AZX_GCTL_RESET (1 << 0) /* controller reset */ | |
| 25 | #define AZX_GCTL_FCNTRL (1 << 1) /* flush control */ | |
| 26 | #define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ | |
| 27 | #define AZX_REG_WAKEEN 0x0c | |
| 28 | #define AZX_REG_STATESTS 0x0e | |
| 29 | #define AZX_REG_GSTS 0x10 | |
| 30 | #define AZX_GSTS_FSTS (1 << 1) /* flush status */ | |
| 83b0b677 JK |
31 | #define AZX_REG_GCAP2 0x12 |
| 32 | #define AZX_REG_LLCH 0x14 | |
| 33 | #define AZX_REG_OUTSTRMPAY 0x18 | |
| 34 | #define AZX_REG_INSTRMPAY 0x1A | |
| 14752412 TI |
35 | #define AZX_REG_INTCTL 0x20 |
| 36 | #define AZX_REG_INTSTS 0x24 | |
| 37 | #define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ | |
| 38 | #define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ | |
| 39 | #define AZX_REG_SSYNC 0x38 | |
| 40 | #define AZX_REG_CORBLBASE 0x40 | |
| 41 | #define AZX_REG_CORBUBASE 0x44 | |
| 42 | #define AZX_REG_CORBWP 0x48 | |
| 43 | #define AZX_REG_CORBRP 0x4a | |
| 44 | #define AZX_CORBRP_RST (1 << 15) /* read pointer reset */ | |
| 45 | #define AZX_REG_CORBCTL 0x4c | |
| 46 | #define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */ | |
| 47 | #define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ | |
| 48 | #define AZX_REG_CORBSTS 0x4d | |
| 49 | #define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */ | |
| 50 | #define AZX_REG_CORBSIZE 0x4e | |
| 51 | ||
| 52 | #define AZX_REG_RIRBLBASE 0x50 | |
| 53 | #define AZX_REG_RIRBUBASE 0x54 | |
| 54 | #define AZX_REG_RIRBWP 0x58 | |
| 55 | #define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */ | |
| 56 | #define AZX_REG_RINTCNT 0x5a | |
| 57 | #define AZX_REG_RIRBCTL 0x5c | |
| 58 | #define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ | |
| 59 | #define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */ | |
| 60 | #define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ | |
| 61 | #define AZX_REG_RIRBSTS 0x5d | |
| 62 | #define AZX_RBSTS_IRQ (1 << 0) /* response irq */ | |
| 63 | #define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */ | |
| 64 | #define AZX_REG_RIRBSIZE 0x5e | |
| 65 | ||
| 66 | #define AZX_REG_IC 0x60 | |
| 67 | #define AZX_REG_IR 0x64 | |
| 68 | #define AZX_REG_IRS 0x68 | |
| 69 | #define AZX_IRS_VALID (1<<1) | |
| 70 | #define AZX_IRS_BUSY (1<<0) | |
| 71 | ||
| 72 | #define AZX_REG_DPLBASE 0x70 | |
| 73 | #define AZX_REG_DPUBASE 0x74 | |
| 74 | #define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
| 75 | ||
| 76 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
| 77 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
| 78 | ||
| 79 | /* stream register offsets from stream base */ | |
| 80 | #define AZX_REG_SD_CTL 0x00 | |
| 81 | #define AZX_REG_SD_STS 0x03 | |
| 82 | #define AZX_REG_SD_LPIB 0x04 | |
| 83 | #define AZX_REG_SD_CBL 0x08 | |
| 84 | #define AZX_REG_SD_LVI 0x0c | |
| 85 | #define AZX_REG_SD_FIFOW 0x0e | |
| 86 | #define AZX_REG_SD_FIFOSIZE 0x10 | |
| 87 | #define AZX_REG_SD_FORMAT 0x12 | |
| 83b0b677 | 88 | #define AZX_REG_SD_FIFOL 0x14 |
| 14752412 TI |
89 | #define AZX_REG_SD_BDLPL 0x18 |
| 90 | #define AZX_REG_SD_BDLPU 0x1c | |
| 91 | ||
| 98d8fc6c ML |
92 | /* Haswell/Broadwell display HD-A controller Extended Mode registers */ |
| 93 | #define AZX_REG_HSW_EM4 0x100c | |
| 94 | #define AZX_REG_HSW_EM5 0x1010 | |
| 95 | ||
| 7c23b7c1 LH |
96 | /* Skylake/Broxton display HD-A controller Extended Mode registers */ |
| 97 | #define AZX_REG_SKL_EM4L 0x1040 | |
| 98 | ||
| 14752412 TI |
99 | /* PCI space */ |
| 100 | #define AZX_PCIREG_TCSEL 0x44 | |
| 101 | ||
| 102 | /* | |
| 103 | * other constants | |
| 104 | */ | |
| 105 | ||
| 106 | /* max number of fragments - we may use more if allocating more pages for BDL */ | |
| 107 | #define BDL_SIZE 4096 | |
| 108 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) | |
| 109 | #define AZX_MAX_FRAG 32 | |
| 110 | /* max buffer size - no h/w limit, you can increase as you like */ | |
| 111 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
| 112 | ||
| 113 | /* RIRB int mask: overrun[2], response[0] */ | |
| 114 | #define RIRB_INT_RESPONSE 0x01 | |
| 115 | #define RIRB_INT_OVERRUN 0x04 | |
| 116 | #define RIRB_INT_MASK 0x05 | |
| 117 | ||
| 118 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ | |
| 119 | #define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1) | |
| 120 | ||
| 121 | /* SD_CTL bits */ | |
| 122 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
| 123 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
| 124 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ | |
| 125 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ | |
| 126 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ | |
| 127 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
| 128 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
| 129 | ||
| 130 | /* SD_CTL and SD_STS */ | |
| 131 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
| 132 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
| 133 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
| 134 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ | |
| 135 | SD_INT_COMPLETE) | |
| 136 | ||
| 137 | /* SD_STS */ | |
| 138 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
| 139 | ||
| 140 | /* INTCTL and INTSTS */ | |
| 141 | #define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
| 142 | #define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
| 143 | #define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
| 144 | ||
| 145 | /* below are so far hardcoded - should read registers in future */ | |
| 146 | #define AZX_MAX_CORB_ENTRIES 256 | |
| 147 | #define AZX_MAX_RIRB_ENTRIES 256 | |
| 148 | ||
| 83b0b677 JK |
149 | /* Capability header Structure */ |
| 150 | #define AZX_REG_CAP_HDR 0x0 | |
| 151 | #define AZX_CAP_HDR_VER_OFF 28 | |
| 152 | #define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF) | |
| 153 | #define AZX_CAP_HDR_ID_OFF 16 | |
| 154 | #define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF) | |
| 155 | #define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF | |
| 156 | ||
| 157 | /* registers of Software Position Based FIFO Capability Structure */ | |
| 158 | #define AZX_SPB_CAP_ID 0x4 | |
| 159 | #define AZX_REG_SPB_BASE_ADDR 0x700 | |
| 160 | #define AZX_REG_SPB_SPBFCH 0x00 | |
| 161 | #define AZX_REG_SPB_SPBFCCTL 0x04 | |
| 162 | /* Base used to calculate the iterating register offset */ | |
| 163 | #define AZX_SPB_BASE 0x08 | |
| 164 | /* Interval used to calculate the iterating register offset */ | |
| 165 | #define AZX_SPB_INTERVAL 0x08 | |
| ee8bc4df JK |
166 | /* SPIB base */ |
| 167 | #define AZX_SPB_SPIB 0x00 | |
| 168 | /* SPIB MAXFIFO base*/ | |
| 169 | #define AZX_SPB_MAXFIFO 0x04 | |
| 83b0b677 JK |
170 | |
| 171 | /* registers of Global Time Synchronization Capability Structure */ | |
| 172 | #define AZX_GTS_CAP_ID 0x1 | |
| 173 | #define AZX_REG_GTS_GTSCH 0x00 | |
| 174 | #define AZX_REG_GTS_GTSCD 0x04 | |
| 175 | #define AZX_REG_GTS_GTSCTLAC 0x0C | |
| 176 | #define AZX_GTS_BASE 0x20 | |
| 177 | #define AZX_GTS_INTERVAL 0x20 | |
| 178 | ||
| 179 | /* registers for Processing Pipe Capability Structure */ | |
| 180 | #define AZX_PP_CAP_ID 0x3 | |
| 181 | #define AZX_REG_PP_PPCH 0x10 | |
| 182 | #define AZX_REG_PP_PPCTL 0x04 | |
| 183 | #define AZX_PPCTL_PIE (1<<31) | |
| 184 | #define AZX_PPCTL_GPROCEN (1<<30) | |
| 185 | /* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */ | |
| 186 | #define AZX_PPCTL_PROCEN(_X_) (1<<(_X_)) | |
| 187 | ||
| 188 | #define AZX_REG_PP_PPSTS 0x08 | |
| 189 | ||
| 190 | #define AZX_PPHC_BASE 0x10 | |
| 191 | #define AZX_PPHC_INTERVAL 0x10 | |
| 192 | ||
| 193 | #define AZX_REG_PPHCLLPL 0x0 | |
| 194 | #define AZX_REG_PPHCLLPU 0x4 | |
| 195 | #define AZX_REG_PPHCLDPL 0x8 | |
| 196 | #define AZX_REG_PPHCLDPU 0xC | |
| 197 | ||
| 198 | #define AZX_PPLC_BASE 0x10 | |
| 199 | #define AZX_PPLC_MULTI 0x10 | |
| 200 | #define AZX_PPLC_INTERVAL 0x10 | |
| 201 | ||
| 202 | #define AZX_REG_PPLCCTL 0x0 | |
| 203 | #define AZX_PPLCCTL_STRM_BITS 4 | |
| 204 | #define AZX_PPLCCTL_STRM_SHIFT 20 | |
| 205 | #define AZX_REG_MASK(bit_num, offset) \ | |
| 206 | (((1 << (bit_num)) - 1) << (offset)) | |
| 207 | #define AZX_PPLCCTL_STRM_MASK \ | |
| 208 | AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT) | |
| 209 | #define AZX_PPLCCTL_RUN (1<<1) | |
| 210 | #define AZX_PPLCCTL_STRST (1<<0) | |
| 211 | ||
| 212 | #define AZX_REG_PPLCFMT 0x4 | |
| 213 | #define AZX_REG_PPLCLLPL 0x8 | |
| 214 | #define AZX_REG_PPLCLLPU 0xC | |
| 215 | ||
| 216 | /* registers for Multiple Links Capability Structure */ | |
| 217 | #define AZX_ML_CAP_ID 0x2 | |
| 218 | #define AZX_REG_ML_MLCH 0x00 | |
| 219 | #define AZX_REG_ML_MLCD 0x04 | |
| 220 | #define AZX_ML_BASE 0x40 | |
| 221 | #define AZX_ML_INTERVAL 0x40 | |
| 222 | ||
| 223 | #define AZX_REG_ML_LCAP 0x00 | |
| 224 | #define AZX_REG_ML_LCTL 0x04 | |
| 225 | #define AZX_REG_ML_LOSIDV 0x08 | |
| 226 | #define AZX_REG_ML_LSDIID 0x0C | |
| 227 | #define AZX_REG_ML_LPSOO 0x10 | |
| 228 | #define AZX_REG_ML_LPSIO 0x12 | |
| 229 | #define AZX_REG_ML_LWALFC 0x18 | |
| 230 | #define AZX_REG_ML_LOUTPAY 0x20 | |
| 231 | #define AZX_REG_ML_LINPAY 0x30 | |
| 232 | ||
| 233 | #define AZX_MLCTL_SPA (1<<16) | |
| 234 | #define AZX_MLCTL_CPA 23 | |
| 235 | ||
| a9c48f7f JK |
236 | |
| 237 | /* registers for DMA Resume Capability Structure */ | |
| 238 | #define AZX_DRSM_CAP_ID 0x5 | |
| 239 | #define AZX_REG_DRSM_CTL 0x4 | |
| 240 | /* Base used to calculate the iterating register offset */ | |
| 241 | #define AZX_DRSM_BASE 0x08 | |
| 242 | /* Interval used to calculate the iterating register offset */ | |
| 243 | #define AZX_DRSM_INTERVAL 0x08 | |
| 244 | ||
| 14752412 TI |
245 | /* |
| 246 | * helpers to read the stream position | |
| 247 | */ | |
| 248 | static inline unsigned int | |
| 249 | snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream) | |
| 250 | { | |
| 251 | return snd_hdac_stream_readl(stream, SD_LPIB); | |
| 252 | } | |
| 253 | ||
| 254 | static inline unsigned int | |
| 255 | snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream) | |
| 256 | { | |
| 257 | return le32_to_cpu(*stream->posbuf); | |
| 258 | } | |
| 259 | ||
| 260 | #endif /* __SOUND_HDA_REGISTER_H */ |