[linux.git] / drivers / hwmon / k10temp.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
 *		processor hardware monitoring
 *
 * Copyright (c) 2009 Clemens Ladisch <[email protected]>
 * Copyright (c) 2020 Guenter Roeck <[email protected]>
 *
 * Implementation notes:
 * - CCD register address information as well as the calculation to
 *   convert raw register values is from https://github.com/ocerman/zenpower.
 *   The information is not confirmed from chip datasheets, but experiments
 *   suggest that it provides reasonable temperature values.
 * - Register addresses to read chip voltage and current are also from
 *   https://github.com/ocerman/zenpower, and not confirmed from chip
 *   datasheets. Current calibration is board specific and not typically
 *   shared by board vendors. For this reason, current values are
 *   normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
 *   current. Reported values can be adjusted using the sensors configuration
 *   file.
 */

#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <asm/amd_nb.h>
#include <asm/processor.h>

MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
MODULE_LICENSE("GPL");

static bool force;
module_param(force, bool, 0444);
MODULE_PARM_DESC(force, "force loading on processors with erratum 319");

/* Provide lock for writing to NB_SMU_IND_ADDR */
static DEFINE_MUTEX(nb_smu_ind_mutex);

#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3	0x15b3
#endif

/* CPUID function 0x80000001, ebx */
#define CPUID_PKGTYPE_MASK	GENMASK(31, 28)
#define CPUID_PKGTYPE_F		0x00000000
#define CPUID_PKGTYPE_AM2R2_AM3	0x10000000

/* DRAM controller (PCI function 2) */
#define REG_DCT0_CONFIG_HIGH		0x094
#define  DDR3_MODE			BIT(8)

/* miscellaneous (PCI function 3) */
#define REG_HARDWARE_THERMAL_CONTROL	0x64
#define  HTC_ENABLE			BIT(0)

#define REG_REPORTED_TEMPERATURE	0xa4

#define REG_NORTHBRIDGE_CAPABILITIES	0xe8
#define  NB_CAP_HTC			BIT(10)

/*
 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
 * and REG_REPORTED_TEMPERATURE have been moved to
 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
 */
#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET	0xd8200c64
#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET	0xd8200ca4

/* F17h M01h Access througn SMN */
#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET	0x00059800

#define F17H_M70H_CCD_TEMP(x)			(0x00059954 + ((x) * 4))
#define F17H_M70H_CCD_TEMP_VALID		BIT(11)
#define F17H_M70H_CCD_TEMP_MASK			GENMASK(10, 0)

#define F17H_M01H_SVI				0x0005A000
#define F17H_M01H_SVI_TEL_PLANE0		(F17H_M01H_SVI + 0xc)
#define F17H_M01H_SVI_TEL_PLANE1		(F17H_M01H_SVI + 0x10)

#define CUR_TEMP_SHIFT				21
#define CUR_TEMP_RANGE_SEL_MASK			BIT(19)

#define CFACTOR_ICORE				1000000	/* 1A / LSB	*/
#define CFACTOR_ISOC				250000	/* 0.25A / LSB	*/

struct k10temp_data {
	struct pci_dev *pdev;
	void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
	void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
	int temp_offset;
	u32 temp_adjust_mask;
	u32 show_temp;
	u32 svi_addr[2];
	bool is_zen;
	bool show_current;
	int cfactor[2];
};

#define TCTL_BIT	0
#define TDIE_BIT	1
#define TCCD_BIT(x)	((x) + 2)

#define HAVE_TEMP(d, channel)	((d)->show_temp & BIT(channel))
#define HAVE_TDIE(d)		HAVE_TEMP(d, TDIE_BIT)

struct tctl_offset {
	u8 model;
	char const *id;
	int offset;
};

static const struct tctl_offset tctl_offset_table[] = {
	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
	{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
	{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
};

static bool is_threadripper(void)
{
	return strstr(boot_cpu_data.x86_model_id, "Threadripper");
}

static bool is_epyc(void)
{
	return strstr(boot_cpu_data.x86_model_id, "EPYC");
}

static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
}

static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
{
	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
}

static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
			      unsigned int base, int offset, u32 *val)
{
	mutex_lock(&nb_smu_ind_mutex);
	pci_bus_write_config_dword(pdev->bus, devfn,
				   base, offset);
	pci_bus_read_config_dword(pdev->bus, devfn,
				  base + 4, val);
	mutex_unlock(&nb_smu_ind_mutex);
}

static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
{
	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
			  F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
{
	amd_smn_read(amd_pci_dev_to_node_id(pdev),
		     F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
}

static long get_raw_temp(struct k10temp_data *data)
{
	u32 regval;
	long temp;

	data->read_tempreg(data->pdev, &regval);
	temp = (regval >> CUR_TEMP_SHIFT) * 125;
	if (regval & data->temp_adjust_mask)
		temp -= 49000;
	return temp;
}

const char *k10temp_temp_label[] = {
	"Tctl",
	"Tdie",
	"Tccd1",
	"Tccd2",
	"Tccd3",
	"Tccd4",
	"Tccd5",
	"Tccd6",
	"Tccd7",
	"Tccd8",
};

const char *k10temp_in_label[] = {
	"Vcore",
	"Vsoc",
};

const char *k10temp_curr_label[] = {
	"Icore",
	"Isoc",
};

static int k10temp_read_labels(struct device *dev,
			       enum hwmon_sensor_types type,
			       u32 attr, int channel, const char **str)
{
	switch (type) {
	case hwmon_temp:
		*str = k10temp_temp_label[channel];
		break;
	case hwmon_in:
		*str = k10temp_in_label[channel];
		break;
	case hwmon_curr:
		*str = k10temp_curr_label[channel];
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
			     long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_curr_input:
		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
			     data->svi_addr[channel], &regval);
		*val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
					 (regval & 0xff),
					 1000);
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_in_input:
		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
			     data->svi_addr[channel], &regval);
		regval = (regval >> 16) & 0xff;
		*val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
			     long *val)
{
	struct k10temp_data *data = dev_get_drvdata(dev);
	u32 regval;

	switch (attr) {
	case hwmon_temp_input:
		switch (channel) {
		case 0:		/* Tctl */
			*val = get_raw_temp(data);
			if (*val < 0)
				*val = 0;
			break;
		case 1:		/* Tdie */
			*val = get_raw_temp(data) - data->temp_offset;
			if (*val < 0)
				*val = 0;
			break;
		case 2 ... 9:		/* Tccd{1-8} */
			amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
				     F17H_M70H_CCD_TEMP(channel - 2), &regval);
			*val = (regval & F17H_M70H_CCD_TEMP_MASK) * 125 - 49000;
			break;
		default:
			return -EOPNOTSUPP;
		}
		break;
	case hwmon_temp_max:
		*val = 70 * 1000;
		break;
	case hwmon_temp_crit:
		data->read_htcreg(data->pdev, &regval);
		*val = ((regval >> 16) & 0x7f) * 500 + 52000;
		break;
	case hwmon_temp_crit_hyst:
		data->read_htcreg(data->pdev, &regval);
		*val = (((regval >> 16) & 0x7f)
			- ((regval >> 24) & 0xf)) * 500 + 52000;
		break;
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
			u32 attr, int channel, long *val)
{
	switch (type) {
	case hwmon_temp:
		return k10temp_read_temp(dev, attr, channel, val);
	case hwmon_in:
		return k10temp_read_in(dev, attr, channel, val);
	case hwmon_curr:
		return k10temp_read_curr(dev, attr, channel, val);
	default:
		return -EOPNOTSUPP;
	}
}

static umode_t k10temp_is_visible(const void *_data,
				  enum hwmon_sensor_types type,
				  u32 attr, int channel)
{
	const struct k10temp_data *data = _data;
	struct pci_dev *pdev = data->pdev;
	u32 reg;

	switch (type) {
	case hwmon_temp:
		switch (attr) {
		case hwmon_temp_input:
			if (!HAVE_TEMP(data, channel))
				return 0;
			break;
		case hwmon_temp_max:
			if (channel || data->is_zen)
				return 0;
			break;
		case hwmon_temp_crit:
		case hwmon_temp_crit_hyst:
			if (channel || !data->read_htcreg)
				return 0;

			pci_read_config_dword(pdev,
					      REG_NORTHBRIDGE_CAPABILITIES,
					      &reg);
			if (!(reg & NB_CAP_HTC))
				return 0;

			data->read_htcreg(data->pdev, &reg);
			if (!(reg & HTC_ENABLE))
				return 0;
			break;
		case hwmon_temp_label:
			/* Show temperature labels only on Zen CPUs */
			if (!data->is_zen || !HAVE_TEMP(data, channel))
				return 0;
			break;
		default:
			return 0;
		}
		break;
	case hwmon_in:
	case hwmon_curr:
		if (!data->show_current)
			return 0;
		break;
	default:
		return 0;
	}
	return 0444;
}

static bool has_erratum_319(struct pci_dev *pdev)
{
	u32 pkg_type, reg_dram_cfg;

	if (boot_cpu_data.x86 != 0x10)
		return false;

	/*
	 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
	 *              may be unreliable.
	 */
	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	if (pkg_type == CPUID_PKGTYPE_F)
		return true;
	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
		return false;

	/* DDR3 memory implies socket AM3, which is good */
	pci_bus_read_config_dword(pdev->bus,
				  PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
				  REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
	if (reg_dram_cfg & DDR3_MODE)
		return false;

	/*
	 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
	 * memory. We blacklist all the cores which do exist in socket AM2+
	 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	 * and AM3 formats, but that's the best we can do.
	 */
	return boot_cpu_data.x86_model < 4 ||
	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
}

#ifdef CONFIG_DEBUG_FS

static void k10temp_smn_regs_show(struct seq_file *s, struct pci_dev *pdev,
				  u32 addr, int count)
{
	u32 reg;
	int i;

	for (i = 0; i < count; i++) {
		if (!(i & 3))
			seq_printf(s, "0x%06x: ", addr + i * 4);
		amd_smn_read(amd_pci_dev_to_node_id(pdev), addr + i * 4, &reg);
		seq_printf(s, "%08x ", reg);
		if ((i & 3) == 3)
			seq_puts(s, "\n");
	}
}

static int svi_show(struct seq_file *s, void *unused)
{
	struct k10temp_data *data = s->private;

	k10temp_smn_regs_show(s, data->pdev, F17H_M01H_SVI, 32);
	return 0;
}
DEFINE_SHOW_ATTRIBUTE(svi);

static int thm_show(struct seq_file *s, void *unused)
{
	struct k10temp_data *data = s->private;

	k10temp_smn_regs_show(s, data->pdev,
			      F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, 256);
	return 0;
}
DEFINE_SHOW_ATTRIBUTE(thm);

static void k10temp_debugfs_cleanup(void *ddir)
{
	debugfs_remove_recursive(ddir);
}

static void k10temp_init_debugfs(struct k10temp_data *data)
{
	struct dentry *debugfs;
	char name[32];

	/* Only show debugfs data for Family 17h/18h CPUs */
	if (!data->is_zen)
		return;

	scnprintf(name, sizeof(name), "k10temp-%s", pci_name(data->pdev));

	debugfs = debugfs_create_dir(name, NULL);
	if (debugfs) {
		debugfs_create_file("svi", 0444, debugfs, data, &svi_fops);
		debugfs_create_file("thm", 0444, debugfs, data, &thm_fops);
		devm_add_action_or_reset(&data->pdev->dev,
					 k10temp_debugfs_cleanup, debugfs);
	}
}

#else

static void k10temp_init_debugfs(struct k10temp_data *data)
{
}

#endif

static const struct hwmon_channel_info *k10temp_info[] = {
	HWMON_CHANNEL_INFO(temp,
			   HWMON_T_INPUT | HWMON_T_MAX |
			   HWMON_T_CRIT | HWMON_T_CRIT_HYST |
			   HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL,
			   HWMON_T_INPUT | HWMON_T_LABEL),
	HWMON_CHANNEL_INFO(in,
			   HWMON_I_INPUT | HWMON_I_LABEL,
			   HWMON_I_INPUT | HWMON_I_LABEL),
	HWMON_CHANNEL_INFO(curr,
			   HWMON_C_INPUT | HWMON_C_LABEL,
			   HWMON_C_INPUT | HWMON_C_LABEL),
	NULL
};

static const struct hwmon_ops k10temp_hwmon_ops = {
	.is_visible = k10temp_is_visible,
	.read = k10temp_read,
	.read_string = k10temp_read_labels,
};

static const struct hwmon_chip_info k10temp_chip_info = {
	.ops = &k10temp_hwmon_ops,
	.info = k10temp_info,
};

static void k10temp_get_ccd_support(struct pci_dev *pdev,
				    struct k10temp_data *data, int limit)
{
	u32 regval;
	int i;

	for (i = 0; i < limit; i++) {
		amd_smn_read(amd_pci_dev_to_node_id(pdev),
			     F17H_M70H_CCD_TEMP(i), &regval);
		if (regval & F17H_M70H_CCD_TEMP_VALID)
			data->show_temp |= BIT(TCCD_BIT(i));
	}
}

static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	int unreliable = has_erratum_319(pdev);
	struct device *dev = &pdev->dev;
	struct k10temp_data *data;
	struct device *hwmon_dev;
	int i;

	if (unreliable) {
		if (!force) {
			dev_err(dev,
				"unreliable CPU thermal sensor; monitoring disabled\n");
			return -ENODEV;
		}
		dev_warn(dev,
			 "unreliable CPU thermal sensor; check erratum 319\n");
	}

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->pdev = pdev;
	data->show_temp |= BIT(TCTL_BIT);	/* Always show Tctl */

	if (boot_cpu_data.x86 == 0x15 &&
	    ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
	     (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
		data->read_htcreg = read_htcreg_nb_f15;
		data->read_tempreg = read_tempreg_nb_f15;
	} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
		data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
		data->read_tempreg = read_tempreg_nb_f17;
		data->show_temp |= BIT(TDIE_BIT);	/* show Tdie */
		data->is_zen = true;

		switch (boot_cpu_data.x86_model) {
		case 0x1:	/* Zen */
		case 0x8:	/* Zen+ */
		case 0x11:	/* Zen APU */
		case 0x18:	/* Zen+ APU */
			data->show_current = !is_threadripper() && !is_epyc();
			data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
			data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
			data->cfactor[0] = CFACTOR_ICORE;
			data->cfactor[1] = CFACTOR_ISOC;
			k10temp_get_ccd_support(pdev, data, 4);
			break;
		case 0x31:	/* Zen2 Threadripper */
		case 0x71:	/* Zen2 */
			data->show_current = !is_threadripper() && !is_epyc();
			data->cfactor[0] = CFACTOR_ICORE;
			data->cfactor[1] = CFACTOR_ISOC;
			data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
			data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
			k10temp_get_ccd_support(pdev, data, 8);
			break;
		}
	} else {
		data->read_htcreg = read_htcreg_pci;
		data->read_tempreg = read_tempreg_pci;
	}

	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
		const struct tctl_offset *entry = &tctl_offset_table[i];

		if (boot_cpu_data.x86 == entry->model &&
		    strstr(boot_cpu_data.x86_model_id, entry->id)) {
			data->temp_offset = entry->offset;
			break;
		}
	}

	hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
							 &k10temp_chip_info,
							 NULL);
	if (IS_ERR(hwmon_dev))
		return PTR_ERR(hwmon_dev);

	k10temp_init_debugfs(data);

	return 0;
}

static const struct pci_device_id k10temp_id_table[] = {
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);

static struct pci_driver k10temp_driver = {
	.name = "k10temp",
	.id_table = k10temp_id_table,
	.probe = k10temp_probe,
};

module_pci_driver(k10temp_driver);
Commit	Line	Data
6e7c1094	1	// SPDX-License-Identifier: GPL-2.0-or-later
3c57e89b	2	/*
d547552a GR	3	* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
d547552a GR	4	* processor hardware monitoring
3c57e89b CL	5	*
3c57e89b CL	6	* Copyright (c) 2009 Clemens Ladisch <[email protected]>
d547552a	7	* Copyright (c) 2020 Guenter Roeck <[email protected]>
c7579389 GR	8	*
c7579389 GR	9	* Implementation notes:
fd8bdb23	10	* - CCD register address information as well as the calculation to
c7579389 GR	11	* convert raw register values is from https://github.com/ocerman/zenpower.
	12	* The information is not confirmed from chip datasheets, but experiments
	13	* suggest that it provides reasonable temperature values.
b00647c4 GR	14	* - Register addresses to read chip voltage and current are also from
	15	* https://github.com/ocerman/zenpower, and not confirmed from chip
	16	* datasheets. Current calibration is board specific and not typically
	17	* shared by board vendors. For this reason, current values are
	18	* normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
	19	* current. Reported values can be adjusted using the sensors configuration
	20	* file.
3c57e89b CL	21	*/
3c57e89b CL	22
a6d210da	23	#include <linux/bitops.h>
9c4a38f1	24	#include <linux/debugfs.h>
3c57e89b CL	25	#include <linux/err.h>
3c57e89b CL	26	#include <linux/hwmon.h>
3c57e89b CL	27	#include <linux/init.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
dedf7dce	30	#include <linux/pci_ids.h>
3b031622	31	#include <asm/amd_nb.h>
3c57e89b CL	32	#include <asm/processor.h>
3c57e89b CL	33
9e581311	34	MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
3c57e89b CL	35	MODULE_AUTHOR("Clemens Ladisch <[email protected]>");
	36	MODULE_LICENSE("GPL");
	37
	38	static bool force;
	39	module_param(force, bool, 0444);
	40	MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
	41
f89ce270 AG	42	/* Provide lock for writing to NB_SMU_IND_ADDR */
	43	static DEFINE_MUTEX(nb_smu_ind_mutex);
	44
ccaf63b4 GR	45	#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
	46	#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
	47	#endif
	48
c5114a1c	49	/* CPUID function 0x80000001, ebx */
a6d210da	50	#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
c5114a1c CL	51	#define CPUID_PKGTYPE_F 0x00000000
	52	#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
	53
	54	/* DRAM controller (PCI function 2) */
	55	#define REG_DCT0_CONFIG_HIGH 0x094
a6d210da	56	#define DDR3_MODE BIT(8)
c5114a1c CL	57
c5114a1c CL	58	/* miscellaneous (PCI function 3) */
3c57e89b	59	#define REG_HARDWARE_THERMAL_CONTROL 0x64
a6d210da	60	#define HTC_ENABLE BIT(0)
3c57e89b CL	61
	62	#define REG_REPORTED_TEMPERATURE 0xa4
	63
	64	#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
a6d210da	65	#define NB_CAP_HTC BIT(10)
3c57e89b	66
f89ce270	67	/*
40626a1b GR	68	* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
	69	* and REG_REPORTED_TEMPERATURE have been moved to
	70	* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
	71	* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
f89ce270	72	*/
40626a1b	73	#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
f89ce270	74	#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
f89ce270	75
9af0a9ae GR	76	/* F17h M01h Access througn SMN */
9af0a9ae GR	77	#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
fd8bdb23 GR	78
	79	#define F17H_M70H_CCD_TEMP(x) (0x00059954 + ((x) * 4))
	80	#define F17H_M70H_CCD_TEMP_VALID BIT(11)
	81	#define F17H_M70H_CCD_TEMP_MASK GENMASK(10, 0)
9af0a9ae	82
b00647c4 GR	83	#define F17H_M01H_SVI 0x0005A000
	84	#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xc)
	85	#define F17H_M01H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
	86
a6d210da GR	87	#define CUR_TEMP_SHIFT 21
	88	#define CUR_TEMP_RANGE_SEL_MASK BIT(19)
	89
b00647c4 GR	90	#define CFACTOR_ICORE 1000000 /* 1A / LSB */
	91	#define CFACTOR_ISOC 250000 /* 0.25A / LSB */
	92
68546abf GR	93	struct k10temp_data {
68546abf GR	94	struct pci_dev *pdev;
40626a1b	95	void (read_htcreg)(struct pci_dev pdev, u32 *regval);
68546abf	96	void (read_tempreg)(struct pci_dev pdev, u32 *regval);
1b50b776	97	int temp_offset;
1b597889	98	u32 temp_adjust_mask;
60465245	99	u32 show_temp;
b00647c4	100	u32 svi_addr[2];
60465245	101	bool is_zen;
b00647c4 GR	102	bool show_current;
b00647c4 GR	103	int cfactor[2];
1b50b776 GR	104	};
1b50b776 GR	105
60465245 GR	106	#define TCTL_BIT 0
	107	#define TDIE_BIT 1
	108	#define TCCD_BIT(x) ((x) + 2)
	109
	110	#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
	111	#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
	112
1b50b776 GR	113	struct tctl_offset {
	114	u8 model;
	115	char const *id;
	116	int offset;
	117	};
	118
	119	static const struct tctl_offset tctl_offset_table[] = {
ab5ee246	120	{ 0x17, "AMD Ryzen 5 1600X", 20000 },
1b50b776 GR	121	{ 0x17, "AMD Ryzen 7 1700X", 20000 },
1b50b776 GR	122	{ 0x17, "AMD Ryzen 7 1800X", 20000 },
1b597889	123	{ 0x17, "AMD Ryzen 7 2700X", 10000 },
cd6a2064 GR	124	{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
cd6a2064 GR	125	{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
68546abf GR	126	};
68546abf GR	127
b00647c4 GR	128	static bool is_threadripper(void)
	129	{
	130	return strstr(boot_cpu_data.x86_model_id, "Threadripper");
	131	}
	132
	133	static bool is_epyc(void)
	134	{
	135	return strstr(boot_cpu_data.x86_model_id, "EPYC");
	136	}
	137
40626a1b GR	138	static void read_htcreg_pci(struct pci_dev pdev, u32 regval)
	139	{
	140	pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
	141	}
	142
68546abf GR	143	static void read_tempreg_pci(struct pci_dev pdev, u32 regval)
	144	{
	145	pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
	146	}
	147
	148	static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
	149	unsigned int base, int offset, u32 *val)
f89ce270 AG	150	{
	151	mutex_lock(&nb_smu_ind_mutex);
	152	pci_bus_write_config_dword(pdev->bus, devfn,
68546abf	153	base, offset);
f89ce270	154	pci_bus_read_config_dword(pdev->bus, devfn,
68546abf	155	base + 4, val);
f89ce270 AG	156	mutex_unlock(&nb_smu_ind_mutex);
	157	}
	158
40626a1b GR	159	static void read_htcreg_nb_f15(struct pci_dev pdev, u32 regval)
	160	{
	161	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	162	F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
	163	}
	164
68546abf GR	165	static void read_tempreg_nb_f15(struct pci_dev pdev, u32 regval)
	166	{
	167	amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
	168	F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
	169	}
	170
9af0a9ae GR	171	static void read_tempreg_nb_f17(struct pci_dev pdev, u32 regval)
9af0a9ae GR	172	{
3b031622 GR	173	amd_smn_read(amd_pci_dev_to_node_id(pdev),
3b031622 GR	174	F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
9af0a9ae GR	175	}
9af0a9ae GR	176
d547552a	177	static long get_raw_temp(struct k10temp_data *data)
3c57e89b	178	{
f934c059	179	u32 regval;
d547552a	180	long temp;
68546abf GR	181
68546abf GR	182	data->read_tempreg(data->pdev, &regval);
a6d210da	183	temp = (regval >> CUR_TEMP_SHIFT) * 125;
1b597889 GR	184	if (regval & data->temp_adjust_mask)
1b597889 GR	185	temp -= 49000;
f934c059 GR	186	return temp;
	187	}
	188
d547552a	189	const char *k10temp_temp_label[] = {
d547552a	190	"Tctl",
b02c6857	191	"Tdie",
c7579389 GR	192	"Tccd1",
c7579389 GR	193	"Tccd2",
fd8bdb23 GR	194	"Tccd3",
	195	"Tccd4",
	196	"Tccd5",
	197	"Tccd6",
	198	"Tccd7",
	199	"Tccd8",
d547552a	200	};
f934c059	201
b00647c4 GR	202	const char *k10temp_in_label[] = {
	203	"Vcore",
	204	"Vsoc",
	205	};
	206
	207	const char *k10temp_curr_label[] = {
	208	"Icore",
	209	"Isoc",
	210	};
	211
d547552a GR	212	static int k10temp_read_labels(struct device *dev,
	213	enum hwmon_sensor_types type,
	214	u32 attr, int channel, const char **str)
3c57e89b	215	{
b00647c4 GR	216	switch (type) {
	217	case hwmon_temp:
	218	*str = k10temp_temp_label[channel];
	219	break;
	220	case hwmon_in:
	221	*str = k10temp_in_label[channel];
	222	break;
	223	case hwmon_curr:
	224	*str = k10temp_curr_label[channel];
	225	break;
	226	default:
	227	return -EOPNOTSUPP;
	228	}
d547552a	229	return 0;
3c57e89b CL	230	}
3c57e89b CL	231
b00647c4 GR	232	static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
	233	long *val)
	234	{
	235	struct k10temp_data *data = dev_get_drvdata(dev);
	236	u32 regval;
	237
	238	switch (attr) {
	239	case hwmon_curr_input:
	240	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
	241	data->svi_addr[channel], &regval);
	242	val = DIV_ROUND_CLOSEST(data->cfactor[channel]
	243	(regval & 0xff),
	244	1000);
	245	break;
	246	default:
	247	return -EOPNOTSUPP;
	248	}
	249	return 0;
	250	}
	251
	252	static int k10temp_read_in(struct device dev, u32 attr, int channel, long val)
	253	{
	254	struct k10temp_data *data = dev_get_drvdata(dev);
	255	u32 regval;
	256
	257	switch (attr) {
	258	case hwmon_in_input:
	259	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
	260	data->svi_addr[channel], &regval);
	261	regval = (regval >> 16) & 0xff;
	262	val = DIV_ROUND_CLOSEST(155000 - regval 625, 100);
	263	break;
	264	default:
	265	return -EOPNOTSUPP;
	266	}
	267	return 0;
	268	}
	269
	270	static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
	271	long *val)
3c57e89b	272	{
68546abf	273	struct k10temp_data *data = dev_get_drvdata(dev);
3c57e89b	274	u32 regval;
3c57e89b	275
d547552a GR	276	switch (attr) {
	277	case hwmon_temp_input:
	278	switch (channel) {
b02c6857 GR	279	case 0: /* Tctl */
b02c6857 GR	280	*val = get_raw_temp(data);
d547552a GR	281	if (*val < 0)
	282	*val = 0;
	283	break;
b02c6857 GR	284	case 1: /* Tdie */
b02c6857 GR	285	*val = get_raw_temp(data) - data->temp_offset;
d547552a GR	286	if (*val < 0)
	287	*val = 0;
	288	break;
fd8bdb23	289	case 2 ... 9: /* Tccd{1-8} */
c7579389	290	amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
fd8bdb23 GR	291	F17H_M70H_CCD_TEMP(channel - 2), &regval);
fd8bdb23 GR	292	val = (regval & F17H_M70H_CCD_TEMP_MASK) 125 - 49000;
c7579389	293	break;
d547552a GR	294	default:
	295	return -EOPNOTSUPP;
	296	}
	297	break;
	298	case hwmon_temp_max:
	299	val = 70 1000;
	300	break;
	301	case hwmon_temp_crit:
	302	data->read_htcreg(data->pdev, &regval);
	303	val = ((regval >> 16) & 0x7f) 500 + 52000;
	304	break;
	305	case hwmon_temp_crit_hyst:
	306	data->read_htcreg(data->pdev, &regval);
	307	*val = (((regval >> 16) & 0x7f)
	308	- ((regval >> 24) & 0xf)) * 500 + 52000;
	309	break;
	310	default:
	311	return -EOPNOTSUPP;
	312	}
	313	return 0;
3c57e89b CL	314	}
3c57e89b CL	315
b00647c4 GR	316	static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
	317	u32 attr, int channel, long *val)
	318	{
	319	switch (type) {
	320	case hwmon_temp:
	321	return k10temp_read_temp(dev, attr, channel, val);
	322	case hwmon_in:
	323	return k10temp_read_in(dev, attr, channel, val);
	324	case hwmon_curr:
	325	return k10temp_read_curr(dev, attr, channel, val);
	326	default:
	327	return -EOPNOTSUPP;
	328	}
	329	}
	330
d547552a GR	331	static umode_t k10temp_is_visible(const void *_data,
	332	enum hwmon_sensor_types type,
	333	u32 attr, int channel)
3e3e1022	334	{
d547552a	335	const struct k10temp_data *data = _data;
68546abf	336	struct pci_dev *pdev = data->pdev;
f934c059	337	u32 reg;
3e3e1022	338
d547552a GR	339	switch (type) {
	340	case hwmon_temp:
	341	switch (attr) {
	342	case hwmon_temp_input:
60465245	343	if (!HAVE_TEMP(data, channel))
d547552a GR	344	return 0;
	345	break;
	346	case hwmon_temp_max:
60465245	347	if (channel \|\| data->is_zen)
d547552a GR	348	return 0;
	349	break;
	350	case hwmon_temp_crit:
	351	case hwmon_temp_crit_hyst:
	352	if (channel \|\| !data->read_htcreg)
	353	return 0;
	354
	355	pci_read_config_dword(pdev,
	356	REG_NORTHBRIDGE_CAPABILITIES,
	357	&reg);
	358	if (!(reg & NB_CAP_HTC))
	359	return 0;
	360
	361	data->read_htcreg(data->pdev, &reg);
	362	if (!(reg & HTC_ENABLE))
	363	return 0;
	364	break;
	365	case hwmon_temp_label:
60465245 GR	366	/* Show temperature labels only on Zen CPUs */
60465245 GR	367	if (!data->is_zen \|\| !HAVE_TEMP(data, channel))
c7579389	368	return 0;
d547552a GR	369	break;
d547552a GR	370	default:
f934c059	371	return 0;
d547552a	372	}
f934c059	373	break;
b00647c4 GR	374	case hwmon_in:
	375	case hwmon_curr:
	376	if (!data->show_current)
	377	return 0;
	378	break;
d547552a GR	379	default:
d547552a GR	380	return 0;
3e3e1022	381	}
d547552a	382	return 0444;
3e3e1022 GR	383	}
3e3e1022 GR	384
6c931ae1	385	static bool has_erratum_319(struct pci_dev *pdev)
3c57e89b	386	{
c5114a1c CL	387	u32 pkg_type, reg_dram_cfg;
	388
	389	if (boot_cpu_data.x86 != 0x10)
	390	return false;
	391
3c57e89b	392	/*
c5114a1c CL	393	* Erratum 319: The thermal sensor of Socket F/AM2+ processors
c5114a1c CL	394	* may be unreliable.
3c57e89b	395	*/
c5114a1c CL	396	pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
	397	if (pkg_type == CPUID_PKGTYPE_F)
	398	return true;
	399	if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
	400	return false;
	401
eefc2d9e	402	/* DDR3 memory implies socket AM3, which is good */
c5114a1c CL	403	pci_bus_read_config_dword(pdev->bus,
	404	PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
	405	REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
eefc2d9e JD	406	if (reg_dram_cfg & DDR3_MODE)
	407	return false;
	408
	409	/*
	410	* Unfortunately it is possible to run a socket AM3 CPU with DDR2
	411	* memory. We blacklist all the cores which do exist in socket AM2+
	412	* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
	413	* and AM3 formats, but that's the best we can do.
	414	*/
	415	return boot_cpu_data.x86_model < 4 \|\|
b399151c	416	(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
3c57e89b CL	417	}
3c57e89b CL	418
9c4a38f1 GR	419	#ifdef CONFIG_DEBUG_FS
	420
	421	static void k10temp_smn_regs_show(struct seq_file s, struct pci_dev pdev,
	422	u32 addr, int count)
	423	{
	424	u32 reg;
	425	int i;
	426
	427	for (i = 0; i < count; i++) {
	428	if (!(i & 3))
	429	seq_printf(s, "0x%06x: ", addr + i * 4);
	430	amd_smn_read(amd_pci_dev_to_node_id(pdev), addr + i * 4, &reg);
	431	seq_printf(s, "%08x ", reg);
	432	if ((i & 3) == 3)
	433	seq_puts(s, "\n");
	434	}
	435	}
	436
	437	static int svi_show(struct seq_file s, void unused)
	438	{
	439	struct k10temp_data *data = s->private;
	440
	441	k10temp_smn_regs_show(s, data->pdev, F17H_M01H_SVI, 32);
	442	return 0;
	443	}
	444	DEFINE_SHOW_ATTRIBUTE(svi);
	445
	446	static int thm_show(struct seq_file s, void unused)
	447	{
	448	struct k10temp_data *data = s->private;
	449
	450	k10temp_smn_regs_show(s, data->pdev,
	451	F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, 256);
	452	return 0;
	453	}
	454	DEFINE_SHOW_ATTRIBUTE(thm);
	455
	456	static void k10temp_debugfs_cleanup(void *ddir)
	457	{
	458	debugfs_remove_recursive(ddir);
	459	}
	460
	461	static void k10temp_init_debugfs(struct k10temp_data *data)
	462	{
	463	struct dentry *debugfs;
	464	char name[32];
	465
	466	/* Only show debugfs data for Family 17h/18h CPUs */
60465245	467	if (!data->is_zen)
9c4a38f1 GR	468	return;
	469
	470	scnprintf(name, sizeof(name), "k10temp-%s", pci_name(data->pdev));
	471
	472	debugfs = debugfs_create_dir(name, NULL);
	473	if (debugfs) {
	474	debugfs_create_file("svi", 0444, debugfs, data, &svi_fops);
	475	debugfs_create_file("thm", 0444, debugfs, data, &thm_fops);
	476	devm_add_action_or_reset(&data->pdev->dev,
	477	k10temp_debugfs_cleanup, debugfs);
	478	}
	479	}
	480
	481	#else
	482
	483	static void k10temp_init_debugfs(struct k10temp_data *data)
	484	{
	485	}
	486
	487	#endif
	488
d547552a GR	489	static const struct hwmon_channel_info *k10temp_info[] = {
	490	HWMON_CHANNEL_INFO(temp,
	491	HWMON_T_INPUT \| HWMON_T_MAX \|
	492	HWMON_T_CRIT \| HWMON_T_CRIT_HYST \|
	493	HWMON_T_LABEL,
c7579389 GR	494	HWMON_T_INPUT \| HWMON_T_LABEL,
c7579389 GR	495	HWMON_T_INPUT \| HWMON_T_LABEL,
fd8bdb23 GR	496	HWMON_T_INPUT \| HWMON_T_LABEL,
	497	HWMON_T_INPUT \| HWMON_T_LABEL,
	498	HWMON_T_INPUT \| HWMON_T_LABEL,
	499	HWMON_T_INPUT \| HWMON_T_LABEL,
	500	HWMON_T_INPUT \| HWMON_T_LABEL,
	501	HWMON_T_INPUT \| HWMON_T_LABEL,
d547552a	502	HWMON_T_INPUT \| HWMON_T_LABEL),
b00647c4 GR	503	HWMON_CHANNEL_INFO(in,
	504	HWMON_I_INPUT \| HWMON_I_LABEL,
	505	HWMON_I_INPUT \| HWMON_I_LABEL),
	506	HWMON_CHANNEL_INFO(curr,
	507	HWMON_C_INPUT \| HWMON_C_LABEL,
	508	HWMON_C_INPUT \| HWMON_C_LABEL),
d547552a GR	509	NULL
	510	};
	511
	512	static const struct hwmon_ops k10temp_hwmon_ops = {
	513	.is_visible = k10temp_is_visible,
	514	.read = k10temp_read,
	515	.read_string = k10temp_read_labels,
	516	};
	517
	518	static const struct hwmon_chip_info k10temp_chip_info = {
	519	.ops = &k10temp_hwmon_ops,
	520	.info = k10temp_info,
	521	};
	522
fd8bdb23 GR	523	static void k10temp_get_ccd_support(struct pci_dev *pdev,
	524	struct k10temp_data *data, int limit)
	525	{
	526	u32 regval;
	527	int i;
	528
	529	for (i = 0; i < limit; i++) {
	530	amd_smn_read(amd_pci_dev_to_node_id(pdev),
	531	F17H_M70H_CCD_TEMP(i), &regval);
	532	if (regval & F17H_M70H_CCD_TEMP_VALID)
60465245	533	data->show_temp \|= BIT(TCCD_BIT(i));
fd8bdb23 GR	534	}
	535	}
	536
d547552a	537	static int k10temp_probe(struct pci_dev pdev, const struct pci_device_id id)
3c57e89b	538	{
c5114a1c	539	int unreliable = has_erratum_319(pdev);
3e3e1022	540	struct device *dev = &pdev->dev;
68546abf	541	struct k10temp_data *data;
3e3e1022	542	struct device *hwmon_dev;
1b50b776	543	int i;
3c57e89b	544
3e3e1022 GR	545	if (unreliable) {
	546	if (!force) {
	547	dev_err(dev,
	548	"unreliable CPU thermal sensor; monitoring disabled\n");
	549	return -ENODEV;
	550	}
	551	dev_warn(dev,
3c57e89b	552	"unreliable CPU thermal sensor; check erratum 319\n");
3e3e1022	553	}
3c57e89b	554
68546abf GR	555	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	556	if (!data)
	557	return -ENOMEM;
	558
	559	data->pdev = pdev;
60465245	560	data->show_temp \|= BIT(TCTL_BIT); /* Always show Tctl */
68546abf	561
53dfa008 GR	562	if (boot_cpu_data.x86 == 0x15 &&
	563	((boot_cpu_data.x86_model & 0xf0) == 0x60 \|\|
	564	(boot_cpu_data.x86_model & 0xf0) == 0x70)) {
40626a1b	565	data->read_htcreg = read_htcreg_nb_f15;
68546abf	566	data->read_tempreg = read_tempreg_nb_f15;
d93217d8	567	} else if (boot_cpu_data.x86 == 0x17 \|\| boot_cpu_data.x86 == 0x18) {
a6d210da	568	data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
9af0a9ae	569	data->read_tempreg = read_tempreg_nb_f17;
60465245 GR	570	data->show_temp \|= BIT(TDIE_BIT); /* show Tdie */
60465245 GR	571	data->is_zen = true;
c7579389 GR	572
	573	switch (boot_cpu_data.x86_model) {
	574	case 0x1: /* Zen */
	575	case 0x8: /* Zen+ */
	576	case 0x11: /* Zen APU */
	577	case 0x18: /* Zen+ APU */
b00647c4 GR	578	data->show_current = !is_threadripper() && !is_epyc();
	579	data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
	580	data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
	581	data->cfactor[0] = CFACTOR_ICORE;
	582	data->cfactor[1] = CFACTOR_ISOC;
fd8bdb23	583	k10temp_get_ccd_support(pdev, data, 4);
c7579389 GR	584	break;
	585	case 0x31: /* Zen2 Threadripper */
	586	case 0x71: /* Zen2 */
b00647c4 GR	587	data->show_current = !is_threadripper() && !is_epyc();
	588	data->cfactor[0] = CFACTOR_ICORE;
	589	data->cfactor[1] = CFACTOR_ISOC;
	590	data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
	591	data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
fd8bdb23	592	k10temp_get_ccd_support(pdev, data, 8);
c7579389 GR	593	break;
c7579389 GR	594	}
1b597889	595	} else {
40626a1b	596	data->read_htcreg = read_htcreg_pci;
68546abf	597	data->read_tempreg = read_tempreg_pci;
1b597889	598	}
68546abf	599
1b50b776 GR	600	for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
	601	const struct tctl_offset *entry = &tctl_offset_table[i];
	602
	603	if (boot_cpu_data.x86 == entry->model &&
	604	strstr(boot_cpu_data.x86_model_id, entry->id)) {
	605	data->temp_offset = entry->offset;
	606	break;
	607	}
	608	}
	609
d547552a GR	610	hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
	611	&k10temp_chip_info,
	612	NULL);
9c4a38f1 GR	613	if (IS_ERR(hwmon_dev))
	614	return PTR_ERR(hwmon_dev);
	615
	616	k10temp_init_debugfs(data);
	617
	618	return 0;
3c57e89b CL	619	}
3c57e89b CL	620
cd9bb056	621	static const struct pci_device_id k10temp_id_table[] = {
3c57e89b CL	622	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
3c57e89b CL	623	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
aa4790a6	624	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
9e581311	625	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	626	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
d303b1b5	627	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
f89ce270	628	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
ccaf63b4	629	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
30b146d1	630	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
ec015950	631	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
9af0a9ae	632	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3b031622	633	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
210ba120	634	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
12163cfb	635	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
d93217d8	636	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
3c57e89b CL	637	{}
	638	};
	639	MODULE_DEVICE_TABLE(pci, k10temp_id_table);
	640
	641	static struct pci_driver k10temp_driver = {
	642	.name = "k10temp",
	643	.id_table = k10temp_id_table,
	644	.probe = k10temp_probe,
3c57e89b CL	645	};
3c57e89b CL	646
f71f5a55	647	module_pci_driver(k10temp_driver);