[linux.git] / drivers / rtc / rtc-twl.c

/*
 * rtc-twl.c -- TWL Real Time Clock interface
 *
 * Copyright (C) 2007 MontaVista Software, Inc
 * Author: Alexandre Rusev <[email protected]>
 *
 * Based on original TI driver twl4030-rtc.c
 *   Copyright (C) 2006 Texas Instruments, Inc.
 *
 * Based on rtc-omap.c
 *   Copyright (C) 2003 MontaVista Software, Inc.
 *   Author: George G. Davis <[email protected]> or <[email protected]>
 *   Copyright (C) 2006 David Brownell
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/of.h>

#include <linux/i2c/twl.h>


/*
 * RTC block register offsets (use TWL_MODULE_RTC)
 */
enum {
	REG_SECONDS_REG = 0,
	REG_MINUTES_REG,
	REG_HOURS_REG,
	REG_DAYS_REG,
	REG_MONTHS_REG,
	REG_YEARS_REG,
	REG_WEEKS_REG,

	REG_ALARM_SECONDS_REG,
	REG_ALARM_MINUTES_REG,
	REG_ALARM_HOURS_REG,
	REG_ALARM_DAYS_REG,
	REG_ALARM_MONTHS_REG,
	REG_ALARM_YEARS_REG,

	REG_RTC_CTRL_REG,
	REG_RTC_STATUS_REG,
	REG_RTC_INTERRUPTS_REG,

	REG_RTC_COMP_LSB_REG,
	REG_RTC_COMP_MSB_REG,
};
static const u8 twl4030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x07,
	[REG_ALARM_MINUTES_REG] = 0x08,
	[REG_ALARM_HOURS_REG] = 0x09,
	[REG_ALARM_DAYS_REG] = 0x0A,
	[REG_ALARM_MONTHS_REG] = 0x0B,
	[REG_ALARM_YEARS_REG] = 0x0C,

	[REG_RTC_CTRL_REG] = 0x0D,
	[REG_RTC_STATUS_REG] = 0x0E,
	[REG_RTC_INTERRUPTS_REG] = 0x0F,

	[REG_RTC_COMP_LSB_REG] = 0x10,
	[REG_RTC_COMP_MSB_REG] = 0x11,
};
static const u8 twl6030_rtc_reg_map[] = {
	[REG_SECONDS_REG] = 0x00,
	[REG_MINUTES_REG] = 0x01,
	[REG_HOURS_REG] = 0x02,
	[REG_DAYS_REG] = 0x03,
	[REG_MONTHS_REG] = 0x04,
	[REG_YEARS_REG] = 0x05,
	[REG_WEEKS_REG] = 0x06,

	[REG_ALARM_SECONDS_REG] = 0x08,
	[REG_ALARM_MINUTES_REG] = 0x09,
	[REG_ALARM_HOURS_REG] = 0x0A,
	[REG_ALARM_DAYS_REG] = 0x0B,
	[REG_ALARM_MONTHS_REG] = 0x0C,
	[REG_ALARM_YEARS_REG] = 0x0D,

	[REG_RTC_CTRL_REG] = 0x10,
	[REG_RTC_STATUS_REG] = 0x11,
	[REG_RTC_INTERRUPTS_REG] = 0x12,

	[REG_RTC_COMP_LSB_REG] = 0x13,
	[REG_RTC_COMP_MSB_REG] = 0x14,
};

/* RTC_CTRL_REG bitfields */
#define BIT_RTC_CTRL_REG_STOP_RTC_M              0x01
#define BIT_RTC_CTRL_REG_ROUND_30S_M             0x02
#define BIT_RTC_CTRL_REG_AUTO_COMP_M             0x04
#define BIT_RTC_CTRL_REG_MODE_12_24_M            0x08
#define BIT_RTC_CTRL_REG_TEST_MODE_M             0x10
#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M        0x20
#define BIT_RTC_CTRL_REG_GET_TIME_M              0x40
#define BIT_RTC_CTRL_REG_RTC_V_OPT               0x80

/* RTC_STATUS_REG bitfields */
#define BIT_RTC_STATUS_REG_RUN_M                 0x02
#define BIT_RTC_STATUS_REG_1S_EVENT_M            0x04
#define BIT_RTC_STATUS_REG_1M_EVENT_M            0x08
#define BIT_RTC_STATUS_REG_1H_EVENT_M            0x10
#define BIT_RTC_STATUS_REG_1D_EVENT_M            0x20
#define BIT_RTC_STATUS_REG_ALARM_M               0x40
#define BIT_RTC_STATUS_REG_POWER_UP_M            0x80

/* RTC_INTERRUPTS_REG bitfields */
#define BIT_RTC_INTERRUPTS_REG_EVERY_M           0x03
#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M        0x04
#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M        0x08


/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
#define ALL_TIME_REGS		6

/*----------------------------------------------------------------------*/
static u8  *rtc_reg_map;

/*
 * Supports 1 byte read from TWL RTC register.
 */
static int twl_rtc_read_u8(u8 *data, u8 reg)
{
	int ret;

	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("twl_rtc: Could not read TWL"
		       "register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Supports 1 byte write to TWL RTC registers.
 */
static int twl_rtc_write_u8(u8 data, u8 reg)
{
	int ret;

	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
	if (ret < 0)
		pr_err("twl_rtc: Could not write TWL"
		       "register %X - error %d\n", reg, ret);
	return ret;
}

/*
 * Cache the value for timer/alarm interrupts register; this is
 * only changed by callers holding rtc ops lock (or resume).
 */
static unsigned char rtc_irq_bits;

/*
 * Enable 1/second update and/or alarm interrupts.
 */
static int set_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	/* if the bit is set, return from here */
	if (rtc_irq_bits & bit)
		return 0;

	val = rtc_irq_bits | bit;
	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

/*
 * Disable update and/or alarm interrupts.
 */
static int mask_rtc_irq_bit(unsigned char bit)
{
	unsigned char val;
	int ret;

	/* if the bit is clear, return from here */
	if (!(rtc_irq_bits & bit))
		return 0;

	val = rtc_irq_bits & ~bit;
	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
	if (ret == 0)
		rtc_irq_bits = val;

	return ret;
}

static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq(pdev, 0);
	static bool twl_rtc_wake_enabled;
	int ret;

	if (enabled) {
		ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
		if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
			enable_irq_wake(irq);
			twl_rtc_wake_enabled = true;
		}
	} else {
		ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
		if (twl_rtc_wake_enabled) {
			disable_irq_wake(irq);
			twl_rtc_wake_enabled = false;
		}
	}

	return ret;
}

/*
 * Gets current TWL RTC time and date parameters.
 *
 * The RTC's time/alarm representation is not what gmtime(3) requires
 * Linux to use:
 *
 *  - Months are 1..12 vs Linux 0-11
 *  - Years are 0..99 vs Linux 1900..N (we assume 21st century)
 */
static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char rtc_data[ALL_TIME_REGS];
	int ret;
	u8 save_control;
	u8 rtc_control;

	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0) {
		dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
		return ret;
	}
	/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
	if (twl_class_is_6030()) {
		if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
			save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
			ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
			if (ret < 0) {
				dev_err(dev, "%s clr GET_TIME, error %d\n",
					__func__, ret);
				return ret;
			}
		}
	}

	/* Copy RTC counting registers to static registers or latches */
	rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;

	/* for twl6030/32 enable read access to static shadowed registers */
	if (twl_class_is_6030())
		rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;

	ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
	if (ret < 0) {
		dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
		return ret;
	}

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);

	if (ret < 0) {
		dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
		return ret;
	}

	/* for twl6030 restore original state of rtc control register */
	if (twl_class_is_6030()) {
		ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
		if (ret < 0) {
			dev_err(dev, "%s: restore CTRL_REG, error %d\n",
				__func__, ret);
			return ret;
		}
	}

	tm->tm_sec = bcd2bin(rtc_data[0]);
	tm->tm_min = bcd2bin(rtc_data[1]);
	tm->tm_hour = bcd2bin(rtc_data[2]);
	tm->tm_mday = bcd2bin(rtc_data[3]);
	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	tm->tm_year = bcd2bin(rtc_data[5]) + 100;

	return ret;
}

static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char save_control;
	unsigned char rtc_data[ALL_TIME_REGS];
	int ret;

	rtc_data[0] = bin2bcd(tm->tm_sec);
	rtc_data[1] = bin2bcd(tm->tm_min);
	rtc_data[2] = bin2bcd(tm->tm_hour);
	rtc_data[3] = bin2bcd(tm->tm_mday);
	rtc_data[4] = bin2bcd(tm->tm_mon + 1);
	rtc_data[5] = bin2bcd(tm->tm_year - 100);

	/* Stop RTC while updating the TC registers */
	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	if (ret < 0)
		goto out;

	/* update all the time registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
		(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_set_time error %d\n", ret);
		goto out;
	}

	/* Start back RTC */
	save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);

out:
	return ret;
}

/*
 * Gets current TWL RTC alarm time.
 */
static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char rtc_data[ALL_TIME_REGS];
	int ret;

	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
			(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret < 0) {
		dev_err(dev, "rtc_read_alarm error %d\n", ret);
		return ret;
	}

	/* some of these fields may be wildcard/"match all" */
	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	alm->time.tm_min = bcd2bin(rtc_data[1]);
	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;

	/* report cached alarm enable state */
	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
		alm->enabled = 1;

	return ret;
}

static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	unsigned char alarm_data[ALL_TIME_REGS];
	int ret;

	ret = twl_rtc_alarm_irq_enable(dev, 0);
	if (ret)
		goto out;

	alarm_data[0] = bin2bcd(alm->time.tm_sec);
	alarm_data[1] = bin2bcd(alm->time.tm_min);
	alarm_data[2] = bin2bcd(alm->time.tm_hour);
	alarm_data[3] = bin2bcd(alm->time.tm_mday);
	alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
	alarm_data[5] = bin2bcd(alm->time.tm_year - 100);

	/* update all the alarm registers in one shot */
	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
		(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
	if (ret) {
		dev_err(dev, "rtc_set_alarm error %d\n", ret);
		goto out;
	}

	if (alm->enabled)
		ret = twl_rtc_alarm_irq_enable(dev, 1);
out:
	return ret;
}

static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
{
	unsigned long events;
	int ret = IRQ_NONE;
	int res;
	u8 rd_reg;

	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (res)
		goto out;
	/*
	 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	 * only one (ALARM or RTC) interrupt source may be enabled
	 * at time, we also could check our results
	 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	 */
	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		events = RTC_IRQF | RTC_AF;
	else
		events = RTC_IRQF | RTC_PF;

	res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
				   REG_RTC_STATUS_REG);
	if (res)
		goto out;

	if (twl_class_is_4030()) {
		/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
		 * needs 2 reads to clear the interrupt. One read is done in
		 * do_twl_pwrirq(). Doing the second read, to clear
		 * the bit.
		 *
		 * FIXME the reason PWR_ISR1 needs an extra read is that
		 * RTC_IF retriggered until we cleared REG_ALARM_M above.
		 * But re-reading like this is a bad hack; by doing so we
		 * risk wrongly clearing status for some other IRQ (losing
		 * the interrupt).  Be smarter about handling RTC_UF ...
		 */
		res = twl_i2c_read_u8(TWL4030_MODULE_INT,
			&rd_reg, TWL4030_INT_PWR_ISR1);
		if (res)
			goto out;
	}

	/* Notify RTC core on event */
	rtc_update_irq(rtc, 1, events);

	ret = IRQ_HANDLED;
out:
	return ret;
}

static struct rtc_class_ops twl_rtc_ops = {
	.read_time	= twl_rtc_read_time,
	.set_time	= twl_rtc_set_time,
	.read_alarm	= twl_rtc_read_alarm,
	.set_alarm	= twl_rtc_set_alarm,
	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
};

/*----------------------------------------------------------------------*/

static int twl_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;
	int ret = -EINVAL;
	int irq = platform_get_irq(pdev, 0);
	u8 rd_reg;

	if (irq <= 0)
		return ret;

	/* Initialize the register map */
	if (twl_class_is_4030())
		rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
	else
		rtc_reg_map = (u8 *)twl6030_rtc_reg_map;

	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		return ret;

	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
		dev_warn(&pdev->dev, "Power up reset detected.\n");

	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
		dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");

	/* Clear RTC Power up reset and pending alarm interrupts */
	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
	if (ret < 0)
		return ret;

	if (twl_class_is_6030()) {
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}

	dev_info(&pdev->dev, "Enabling TWL-RTC\n");
	ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
	if (ret < 0)
		return ret;

	/* ensure interrupts are disabled, bootloaders can be strange */
	ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		dev_warn(&pdev->dev, "unable to disable interrupt\n");

	/* init cached IRQ enable bits */
	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
	if (ret < 0)
		return ret;

	device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
					&twl_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
			PTR_ERR(rtc));
		return PTR_ERR(rtc);
	}

	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
					twl_rtc_interrupt,
					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
					dev_name(&rtc->dev), rtc);
	if (ret < 0) {
		dev_err(&pdev->dev, "IRQ is not free.\n");
		return ret;
	}

	platform_set_drvdata(pdev, rtc);
	return 0;
}

/*
 * Disable all TWL RTC module interrupts.
 * Sets status flag to free.
 */
static int twl_rtc_remove(struct platform_device *pdev)
{
	/* leave rtc running, but disable irqs */
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	if (twl_class_is_6030()) {
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_LINE_A);
		twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
			REG_INT_MSK_STS_A);
	}

	return 0;
}

static void twl_rtc_shutdown(struct platform_device *pdev)
{
	/* mask timer interrupts, but leave alarm interrupts on to enable
	   power-on when alarm is triggered */
	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
}

#ifdef CONFIG_PM_SLEEP
static unsigned char irqstat;

static int twl_rtc_suspend(struct device *dev)
{
	irqstat = rtc_irq_bits;

	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
	return 0;
}

static int twl_rtc_resume(struct device *dev)
{
	set_rtc_irq_bit(irqstat);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);

#ifdef CONFIG_OF
static const struct of_device_id twl_rtc_of_match[] = {
	{.compatible = "ti,twl4030-rtc", },
	{ },
};
MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
#endif

MODULE_ALIAS("platform:twl_rtc");

static struct platform_driver twl4030rtc_driver = {
	.probe		= twl_rtc_probe,
	.remove		= twl_rtc_remove,
	.shutdown	= twl_rtc_shutdown,
	.driver		= {
		.name		= "twl_rtc",
		.pm		= &twl_rtc_pm_ops,
		.of_match_table = of_match_ptr(twl_rtc_of_match),
	},
};

module_platform_driver(twl4030rtc_driver);

MODULE_AUTHOR("Texas Instruments, MontaVista Software");
MODULE_LICENSE("GPL");
Commit	Line	Data
f96411ab	1	/*
ef3b7d0d	2	* rtc-twl.c -- TWL Real Time Clock interface
f96411ab DB	3	*
	4	* Copyright (C) 2007 MontaVista Software, Inc
	5	* Author: Alexandre Rusev <[email protected]>
	6	*
	7	* Based on original TI driver twl4030-rtc.c
	8	* Copyright (C) 2006 Texas Instruments, Inc.
	9	*
	10	* Based on rtc-omap.c
	11	* Copyright (C) 2003 MontaVista Software, Inc.
	12	* Author: George G. Davis <[email protected]> or <[email protected]>
	13	* Copyright (C) 2006 David Brownell
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version
	18	* 2 of the License, or (at your option) any later version.
	19	*/
	20
	21	#include <linux/kernel.h>
2fac6674	22	#include <linux/errno.h>
f96411ab DB	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/types.h>
	26	#include <linux/rtc.h>
	27	#include <linux/bcd.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/interrupt.h>
c8a6046e	30	#include <linux/of.h>
f96411ab	31
b07682b6	32	#include <linux/i2c/twl.h>
f96411ab DB	33
	34
	35	/*
	36	* RTC block register offsets (use TWL_MODULE_RTC)
	37	*/
a6b49ffd B	38	enum {
	39	REG_SECONDS_REG = 0,
	40	REG_MINUTES_REG,
	41	REG_HOURS_REG,
	42	REG_DAYS_REG,
	43	REG_MONTHS_REG,
	44	REG_YEARS_REG,
	45	REG_WEEKS_REG,
	46
	47	REG_ALARM_SECONDS_REG,
	48	REG_ALARM_MINUTES_REG,
	49	REG_ALARM_HOURS_REG,
	50	REG_ALARM_DAYS_REG,
	51	REG_ALARM_MONTHS_REG,
	52	REG_ALARM_YEARS_REG,
	53
	54	REG_RTC_CTRL_REG,
	55	REG_RTC_STATUS_REG,
	56	REG_RTC_INTERRUPTS_REG,
	57
	58	REG_RTC_COMP_LSB_REG,
	59	REG_RTC_COMP_MSB_REG,
	60	};
2e84067b	61	static const u8 twl4030_rtc_reg_map[] = {
a6b49ffd B	62	[REG_SECONDS_REG] = 0x00,
	63	[REG_MINUTES_REG] = 0x01,
	64	[REG_HOURS_REG] = 0x02,
	65	[REG_DAYS_REG] = 0x03,
	66	[REG_MONTHS_REG] = 0x04,
	67	[REG_YEARS_REG] = 0x05,
	68	[REG_WEEKS_REG] = 0x06,
	69
	70	[REG_ALARM_SECONDS_REG] = 0x07,
	71	[REG_ALARM_MINUTES_REG] = 0x08,
	72	[REG_ALARM_HOURS_REG] = 0x09,
	73	[REG_ALARM_DAYS_REG] = 0x0A,
	74	[REG_ALARM_MONTHS_REG] = 0x0B,
	75	[REG_ALARM_YEARS_REG] = 0x0C,
	76
	77	[REG_RTC_CTRL_REG] = 0x0D,
	78	[REG_RTC_STATUS_REG] = 0x0E,
	79	[REG_RTC_INTERRUPTS_REG] = 0x0F,
	80
	81	[REG_RTC_COMP_LSB_REG] = 0x10,
	82	[REG_RTC_COMP_MSB_REG] = 0x11,
	83	};
2e84067b	84	static const u8 twl6030_rtc_reg_map[] = {
a6b49ffd B	85	[REG_SECONDS_REG] = 0x00,
	86	[REG_MINUTES_REG] = 0x01,
	87	[REG_HOURS_REG] = 0x02,
	88	[REG_DAYS_REG] = 0x03,
	89	[REG_MONTHS_REG] = 0x04,
	90	[REG_YEARS_REG] = 0x05,
	91	[REG_WEEKS_REG] = 0x06,
	92
	93	[REG_ALARM_SECONDS_REG] = 0x08,
	94	[REG_ALARM_MINUTES_REG] = 0x09,
	95	[REG_ALARM_HOURS_REG] = 0x0A,
	96	[REG_ALARM_DAYS_REG] = 0x0B,
	97	[REG_ALARM_MONTHS_REG] = 0x0C,
	98	[REG_ALARM_YEARS_REG] = 0x0D,
	99
	100	[REG_RTC_CTRL_REG] = 0x10,
	101	[REG_RTC_STATUS_REG] = 0x11,
	102	[REG_RTC_INTERRUPTS_REG] = 0x12,
	103
	104	[REG_RTC_COMP_LSB_REG] = 0x13,
	105	[REG_RTC_COMP_MSB_REG] = 0x14,
	106	};
f96411ab DB	107
	108	/* RTC_CTRL_REG bitfields */
	109	#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
	110	#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
	111	#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
	112	#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
	113	#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
	114	#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
	115	#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
f3ec434c	116	#define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
f96411ab DB	117
	118	/* RTC_STATUS_REG bitfields */
	119	#define BIT_RTC_STATUS_REG_RUN_M 0x02
	120	#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
	121	#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
	122	#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
	123	#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
	124	#define BIT_RTC_STATUS_REG_ALARM_M 0x40
	125	#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
	126
	127	/* RTC_INTERRUPTS_REG bitfields */
	128	#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
	129	#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
	130	#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
	131
	132
	133	/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
	134	#define ALL_TIME_REGS 6
	135
	136	/----------------------------------------------------------------------/
a6b49ffd	137	static u8 *rtc_reg_map;
f96411ab DB	138
f96411ab DB	139	/*
ef3b7d0d	140	* Supports 1 byte read from TWL RTC register.
f96411ab	141	*/
ef3b7d0d	142	static int twl_rtc_read_u8(u8 *data, u8 reg)
f96411ab DB	143	{
	144	int ret;
	145
a6b49ffd	146	ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	147	if (ret < 0)
ef3b7d0d	148	pr_err("twl_rtc: Could not read TWL"
f96411ab DB	149	"register %X - error %d\n", reg, ret);
	150	return ret;
	151	}
	152
	153	/*
ef3b7d0d	154	* Supports 1 byte write to TWL RTC registers.
f96411ab	155	*/
ef3b7d0d	156	static int twl_rtc_write_u8(u8 data, u8 reg)
f96411ab DB	157	{
	158	int ret;
	159
a6b49ffd	160	ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
f96411ab	161	if (ret < 0)
ef3b7d0d	162	pr_err("twl_rtc: Could not write TWL"
f96411ab DB	163	"register %X - error %d\n", reg, ret);
	164	return ret;
	165	}
	166
	167	/*
	168	* Cache the value for timer/alarm interrupts register; this is
	169	* only changed by callers holding rtc ops lock (or resume).
	170	*/
	171	static unsigned char rtc_irq_bits;
	172
	173	/*
a748384b	174	* Enable 1/second update and/or alarm interrupts.
f96411ab DB	175	*/
	176	static int set_rtc_irq_bit(unsigned char bit)
	177	{
	178	unsigned char val;
	179	int ret;
	180
ce9f6506 VB	181	/* if the bit is set, return from here */
	182	if (rtc_irq_bits & bit)
	183	return 0;
	184
f96411ab	185	val = rtc_irq_bits \| bit;
a748384b	186	val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
ef3b7d0d	187	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	188	if (ret == 0)
	189	rtc_irq_bits = val;
	190
	191	return ret;
	192	}
	193
	194	/*
a748384b	195	* Disable update and/or alarm interrupts.
f96411ab DB	196	*/
	197	static int mask_rtc_irq_bit(unsigned char bit)
	198	{
	199	unsigned char val;
	200	int ret;
	201
ce9f6506 VB	202	/* if the bit is clear, return from here */
	203	if (!(rtc_irq_bits & bit))
	204	return 0;
	205
f96411ab	206	val = rtc_irq_bits & ~bit;
ef3b7d0d	207	ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
f96411ab DB	208	if (ret == 0)
	209	rtc_irq_bits = val;
	210
	211	return ret;
	212	}
	213
ef3b7d0d	214	static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
f96411ab	215	{
ae845894 KH	216	struct platform_device *pdev = to_platform_device(dev);
	217	int irq = platform_get_irq(pdev, 0);
	218	static bool twl_rtc_wake_enabled;
f96411ab DB	219	int ret;
f96411ab DB	220
ae845894	221	if (enabled) {
f96411ab	222	ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
ae845894 KH	223	if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
	224	enable_irq_wake(irq);
	225	twl_rtc_wake_enabled = true;
	226	}
	227	} else {
f96411ab	228	ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
ae845894 KH	229	if (twl_rtc_wake_enabled) {
	230	disable_irq_wake(irq);
	231	twl_rtc_wake_enabled = false;
	232	}
	233	}
f96411ab DB	234
	235	return ret;
	236	}
	237
f96411ab	238	/*
ef3b7d0d	239	* Gets current TWL RTC time and date parameters.
f96411ab DB	240	*
	241	* The RTC's time/alarm representation is not what gmtime(3) requires
	242	* Linux to use:
	243	*
	244	* - Months are 1..12 vs Linux 0-11
	245	* - Years are 0..99 vs Linux 1900..N (we assume 21st century)
	246	*/
ef3b7d0d	247	static int twl_rtc_read_time(struct device dev, struct rtc_time tm)
f96411ab	248	{
14591d88	249	unsigned char rtc_data[ALL_TIME_REGS];
f96411ab DB	250	int ret;
f96411ab DB	251	u8 save_control;
f3ec434c	252	u8 rtc_control;
f96411ab	253
ef3b7d0d	254	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f3ec434c KS	255	if (ret < 0) {
f3ec434c KS	256	dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
f96411ab	257	return ret;
f3ec434c KS	258	}
	259	/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
	260	if (twl_class_is_6030()) {
	261	if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
	262	save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
	263	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	264	if (ret < 0) {
	265	dev_err(dev, "%s clr GET_TIME, error %d\n",
	266	__func__, ret);
	267	return ret;
	268	}
	269	}
	270	}
f96411ab	271
f3ec434c KS	272	/* Copy RTC counting registers to static registers or latches */
f3ec434c KS	273	rtc_control = save_control \| BIT_RTC_CTRL_REG_GET_TIME_M;
f96411ab	274
f3ec434c KS	275	/* for twl6030/32 enable read access to static shadowed registers */
	276	if (twl_class_is_6030())
	277	rtc_control \|= BIT_RTC_CTRL_REG_RTC_V_OPT;
	278
	279	ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
	280	if (ret < 0) {
	281	dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
f96411ab	282	return ret;
f3ec434c	283	}
f96411ab	284
ef3b7d0d	285	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	286	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	287
f96411ab DB	288	if (ret < 0) {
f3ec434c	289	dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
f96411ab DB	290	return ret;
	291	}
	292
f3ec434c KS	293	/* for twl6030 restore original state of rtc control register */
	294	if (twl_class_is_6030()) {
	295	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
	296	if (ret < 0) {
	297	dev_err(dev, "%s: restore CTRL_REG, error %d\n",
	298	__func__, ret);
	299	return ret;
	300	}
	301	}
	302
f96411ab DB	303	tm->tm_sec = bcd2bin(rtc_data[0]);
	304	tm->tm_min = bcd2bin(rtc_data[1]);
	305	tm->tm_hour = bcd2bin(rtc_data[2]);
	306	tm->tm_mday = bcd2bin(rtc_data[3]);
	307	tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
	308	tm->tm_year = bcd2bin(rtc_data[5]) + 100;
	309
	310	return ret;
	311	}
	312
ef3b7d0d	313	static int twl_rtc_set_time(struct device dev, struct rtc_time tm)
f96411ab DB	314	{
f96411ab DB	315	unsigned char save_control;
14591d88	316	unsigned char rtc_data[ALL_TIME_REGS];
f96411ab DB	317	int ret;
f96411ab DB	318
14591d88 PU	319	rtc_data[0] = bin2bcd(tm->tm_sec);
	320	rtc_data[1] = bin2bcd(tm->tm_min);
	321	rtc_data[2] = bin2bcd(tm->tm_hour);
	322	rtc_data[3] = bin2bcd(tm->tm_mday);
	323	rtc_data[4] = bin2bcd(tm->tm_mon + 1);
	324	rtc_data[5] = bin2bcd(tm->tm_year - 100);
f96411ab DB	325
f96411ab DB	326	/* Stop RTC while updating the TC registers */
ef3b7d0d	327	ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
f96411ab DB	328	if (ret < 0)
	329	goto out;
	330
	331	save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
8f6b0dd3	332	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	333	if (ret < 0)
	334	goto out;
	335
	336	/* update all the time registers in one shot */
ef3b7d0d	337	ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
a6b49ffd	338	(rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	339	if (ret < 0) {
	340	dev_err(dev, "rtc_set_time error %d\n", ret);
	341	goto out;
	342	}
	343
	344	/* Start back RTC */
	345	save_control \|= BIT_RTC_CTRL_REG_STOP_RTC_M;
ef3b7d0d	346	ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
f96411ab DB	347
	348	out:
	349	return ret;
	350	}
	351
	352	/*
ef3b7d0d	353	* Gets current TWL RTC alarm time.
f96411ab	354	*/
ef3b7d0d	355	static int twl_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab	356	{
14591d88	357	unsigned char rtc_data[ALL_TIME_REGS];
f96411ab DB	358	int ret;
f96411ab DB	359
ef3b7d0d	360	ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
a6b49ffd	361	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	362	if (ret < 0) {
	363	dev_err(dev, "rtc_read_alarm error %d\n", ret);
	364	return ret;
	365	}
	366
	367	/* some of these fields may be wildcard/"match all" */
	368	alm->time.tm_sec = bcd2bin(rtc_data[0]);
	369	alm->time.tm_min = bcd2bin(rtc_data[1]);
	370	alm->time.tm_hour = bcd2bin(rtc_data[2]);
	371	alm->time.tm_mday = bcd2bin(rtc_data[3]);
	372	alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
	373	alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
	374
	375	/* report cached alarm enable state */
	376	if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
	377	alm->enabled = 1;
	378
	379	return ret;
	380	}
	381
ef3b7d0d	382	static int twl_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
f96411ab	383	{
14591d88	384	unsigned char alarm_data[ALL_TIME_REGS];
f96411ab DB	385	int ret;
f96411ab DB	386
ef3b7d0d	387	ret = twl_rtc_alarm_irq_enable(dev, 0);
f96411ab DB	388	if (ret)
	389	goto out;
	390
14591d88 PU	391	alarm_data[0] = bin2bcd(alm->time.tm_sec);
	392	alarm_data[1] = bin2bcd(alm->time.tm_min);
	393	alarm_data[2] = bin2bcd(alm->time.tm_hour);
	394	alarm_data[3] = bin2bcd(alm->time.tm_mday);
	395	alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
	396	alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
f96411ab DB	397
f96411ab DB	398	/* update all the alarm registers in one shot */
ef3b7d0d	399	ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
a6b49ffd	400	(rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
f96411ab DB	401	if (ret) {
	402	dev_err(dev, "rtc_set_alarm error %d\n", ret);
	403	goto out;
	404	}
	405
	406	if (alm->enabled)
ef3b7d0d	407	ret = twl_rtc_alarm_irq_enable(dev, 1);
f96411ab DB	408	out:
	409	return ret;
	410	}
	411
ef3b7d0d	412	static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
f96411ab	413	{
2778ebcc	414	unsigned long events;
f96411ab DB	415	int ret = IRQ_NONE;
	416	int res;
	417	u8 rd_reg;
	418
ef3b7d0d	419	res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab DB	420	if (res)
	421	goto out;
	422	/*
	423	* Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
	424	* only one (ALARM or RTC) interrupt source may be enabled
	425	* at time, we also could check our results
	426	* by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
	427	*/
	428	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
2778ebcc	429	events = RTC_IRQF \| RTC_AF;
f96411ab	430	else
2778ebcc	431	events = RTC_IRQF \| RTC_PF;
f96411ab	432
94a339d0	433	res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
f96411ab DB	434	REG_RTC_STATUS_REG);
	435	if (res)
	436	goto out;
	437
a6b49ffd B	438	if (twl_class_is_4030()) {
	439	/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
	440	* needs 2 reads to clear the interrupt. One read is done in
	441	* do_twl_pwrirq(). Doing the second read, to clear
	442	* the bit.
	443	*
	444	* FIXME the reason PWR_ISR1 needs an extra read is that
	445	* RTC_IF retriggered until we cleared REG_ALARM_M above.
	446	* But re-reading like this is a bad hack; by doing so we
	447	* risk wrongly clearing status for some other IRQ (losing
	448	* the interrupt). Be smarter about handling RTC_UF ...
	449	*/
	450	res = twl_i2c_read_u8(TWL4030_MODULE_INT,
f96411ab	451	&rd_reg, TWL4030_INT_PWR_ISR1);
a6b49ffd B	452	if (res)
	453	goto out;
	454	}
f96411ab DB	455
	456	/* Notify RTC core on event */
	457	rtc_update_irq(rtc, 1, events);
	458
	459	ret = IRQ_HANDLED;
	460	out:
	461	return ret;
	462	}
	463
ef3b7d0d B	464	static struct rtc_class_ops twl_rtc_ops = {
	465	.read_time = twl_rtc_read_time,
	466	.set_time = twl_rtc_set_time,
	467	.read_alarm = twl_rtc_read_alarm,
	468	.set_alarm = twl_rtc_set_alarm,
	469	.alarm_irq_enable = twl_rtc_alarm_irq_enable,
f96411ab DB	470	};
	471
	472	/----------------------------------------------------------------------/
	473
5a167f45	474	static int twl_rtc_probe(struct platform_device *pdev)
f96411ab DB	475	{
f96411ab DB	476	struct rtc_device *rtc;
7e72c686	477	int ret = -EINVAL;
f96411ab DB	478	int irq = platform_get_irq(pdev, 0);
	479	u8 rd_reg;
	480
2fac6674	481	if (irq <= 0)
f53eeb85	482	return ret;
f96411ab	483
d3869ff6 PU	484	/* Initialize the register map */
	485	if (twl_class_is_4030())
	486	rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
	487	else
	488	rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
	489
ef3b7d0d	490	ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
f96411ab	491	if (ret < 0)
f53eeb85	492	return ret;
f96411ab DB	493
	494	if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
	495	dev_warn(&pdev->dev, "Power up reset detected.\n");
	496
	497	if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
	498	dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
	499
	500	/* Clear RTC Power up reset and pending alarm interrupts */
ef3b7d0d	501	ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
f96411ab	502	if (ret < 0)
f53eeb85	503	return ret;
f96411ab	504
a6b49ffd B	505	if (twl_class_is_6030()) {
	506	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	507	REG_INT_MSK_LINE_A);
	508	twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
	509	REG_INT_MSK_STS_A);
	510	}
	511
f7439bcb VB	512	dev_info(&pdev->dev, "Enabling TWL-RTC\n");
f7439bcb VB	513	ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
f96411ab	514	if (ret < 0)
f53eeb85	515	return ret;
f96411ab	516
8dcebaa9 KH	517	/* ensure interrupts are disabled, bootloaders can be strange */
	518	ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
	519	if (ret < 0)
	520	dev_warn(&pdev->dev, "unable to disable interrupt\n");
	521
f96411ab	522	/* init cached IRQ enable bits */
ef3b7d0d	523	ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
f96411ab	524	if (ret < 0)
f53eeb85	525	return ret;
7e72c686	526
b99b94b5 GS	527	device_init_wakeup(&pdev->dev, 1);
b99b94b5 GS	528
f53eeb85 JH	529	rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
f53eeb85 JH	530	&twl_rtc_ops, THIS_MODULE);
7e72c686	531	if (IS_ERR(rtc)) {
7e72c686 TP	532	dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
7e72c686 TP	533	PTR_ERR(rtc));
f53eeb85	534	return PTR_ERR(rtc);
7e72c686 TP	535	}
7e72c686 TP	536
f53eeb85 JH	537	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	538	twl_rtc_interrupt,
	539	IRQF_TRIGGER_RISING \| IRQF_ONESHOT,
	540	dev_name(&rtc->dev), rtc);
7e72c686 TP	541	if (ret < 0) {
7e72c686 TP	542	dev_err(&pdev->dev, "IRQ is not free.\n");
f53eeb85	543	return ret;
7e72c686	544	}
f96411ab	545
7e72c686 TP	546	platform_set_drvdata(pdev, rtc);
7e72c686 TP	547	return 0;
f96411ab DB	548	}
	549
	550	/*
ef3b7d0d	551	* Disable all TWL RTC module interrupts.
f96411ab DB	552	* Sets status flag to free.
f96411ab DB	553	*/
5a167f45	554	static int twl_rtc_remove(struct platform_device *pdev)
f96411ab DB	555	{
f96411ab DB	556	/* leave rtc running, but disable irqs */
f96411ab DB	557	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
f96411ab DB	558	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
a6b49ffd B	559	if (twl_class_is_6030()) {
	560	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	561	REG_INT_MSK_LINE_A);
	562	twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
	563	REG_INT_MSK_STS_A);
	564	}
	565
f96411ab DB	566	return 0;
	567	}
	568
ef3b7d0d	569	static void twl_rtc_shutdown(struct platform_device *pdev)
f96411ab	570	{
cafa1d8b MH	571	/* mask timer interrupts, but leave alarm interrupts on to enable
	572	power-on when alarm is triggered */
	573	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	574	}
f96411ab DB	575
b9d8c460	576	#ifdef CONFIG_PM_SLEEP
f96411ab DB	577	static unsigned char irqstat;
f96411ab DB	578
b9d8c460	579	static int twl_rtc_suspend(struct device *dev)
f96411ab DB	580	{
	581	irqstat = rtc_irq_bits;
	582
f993004d	583	mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
f96411ab DB	584	return 0;
	585	}
	586
b9d8c460	587	static int twl_rtc_resume(struct device *dev)
f96411ab DB	588	{
	589	set_rtc_irq_bit(irqstat);
	590	return 0;
	591	}
f96411ab DB	592	#endif
f96411ab DB	593
b9d8c460 JH	594	static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
b9d8c460 JH	595
c8a6046e	596	#ifdef CONFIG_OF
948170f8 BC	597	static const struct of_device_id twl_rtc_of_match[] = {
	598	{.compatible = "ti,twl4030-rtc", },
	599	{ },
	600	};
	601	MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
c8a6046e SK	602	#endif
c8a6046e SK	603
ef3b7d0d	604	MODULE_ALIAS("platform:twl_rtc");
f96411ab DB	605
f96411ab DB	606	static struct platform_driver twl4030rtc_driver = {
ef3b7d0d	607	.probe = twl_rtc_probe,
5a167f45	608	.remove = twl_rtc_remove,
ef3b7d0d	609	.shutdown = twl_rtc_shutdown,
f96411ab	610	.driver = {
948170f8	611	.name = "twl_rtc",
b9d8c460	612	.pm = &twl_rtc_pm_ops,
c8a6046e	613	.of_match_table = of_match_ptr(twl_rtc_of_match),
f96411ab DB	614	},
	615	};
	616
5ee67484	617	module_platform_driver(twl4030rtc_driver);
f96411ab DB	618
	619	MODULE_AUTHOR("Texas Instruments, MontaVista Software");
	620	MODULE_LICENSE("GPL");