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ASoC: wm_adsp: Signal firmware shutdown through event control
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
2159ad93
MB		 35#include "wm_adsp.h"
36
37#define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45#define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47
48#define ADSP1_CONTROL_1 0x00
49#define ADSP1_CONTROL_2 0x02
50#define ADSP1_CONTROL_3 0x03
51#define ADSP1_CONTROL_4 0x04
52#define ADSP1_CONTROL_5 0x06
53#define ADSP1_CONTROL_6 0x07
54#define ADSP1_CONTROL_7 0x08
55#define ADSP1_CONTROL_8 0x09
56#define ADSP1_CONTROL_9 0x0A
57#define ADSP1_CONTROL_10 0x0B
58#define ADSP1_CONTROL_11 0x0C
59#define ADSP1_CONTROL_12 0x0D
60#define ADSP1_CONTROL_13 0x0F
61#define ADSP1_CONTROL_14 0x10
62#define ADSP1_CONTROL_15 0x11
63#define ADSP1_CONTROL_16 0x12
64#define ADSP1_CONTROL_17 0x13
65#define ADSP1_CONTROL_18 0x14
66#define ADSP1_CONTROL_19 0x16
67#define ADSP1_CONTROL_20 0x17
68#define ADSP1_CONTROL_21 0x18
69#define ADSP1_CONTROL_22 0x1A
70#define ADSP1_CONTROL_23 0x1B
71#define ADSP1_CONTROL_24 0x1C
72#define ADSP1_CONTROL_25 0x1E
73#define ADSP1_CONTROL_26 0x20
74#define ADSP1_CONTROL_27 0x21
75#define ADSP1_CONTROL_28 0x22
76#define ADSP1_CONTROL_29 0x23
77#define ADSP1_CONTROL_30 0x24
78#define ADSP1_CONTROL_31 0x26
79
80/*
81 * ADSP1 Control 19
82 */
83#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86
87
88/*
89 * ADSP1 Control 30
90 */
91#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103#define ADSP1_START 0x0001 /* DSP1_START */
104#define ADSP1_START_MASK 0x0001 /* DSP1_START */
105#define ADSP1_START_SHIFT 0 /* DSP1_START */
106#define ADSP1_START_WIDTH 1 /* DSP1_START */
107
94e205bf
CR		 108/*
109 * ADSP1 Control 31
110 */
111#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
114
2d30b575
MB		 115#define ADSP2_CONTROL 0x0
116#define ADSP2_CLOCKING 0x1
117#define ADSP2_STATUS1 0x4
118#define ADSP2_WDMA_CONFIG_1 0x30
119#define ADSP2_WDMA_CONFIG_2 0x31
120#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 121
10337b07
RF		 122#define ADSP2_SCRATCH0 0x40
123#define ADSP2_SCRATCH1 0x41
124#define ADSP2_SCRATCH2 0x42
125#define ADSP2_SCRATCH3 0x43
126
2159ad93
MB		 127/*
128 * ADSP2 Control
129 */
130
131#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
132#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
133#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
134#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
135#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
136#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
137#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
138#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
139#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
140#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
141#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
142#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
143#define ADSP2_START 0x0001 /* DSP1_START */
144#define ADSP2_START_MASK 0x0001 /* DSP1_START */
145#define ADSP2_START_SHIFT 0 /* DSP1_START */
146#define ADSP2_START_WIDTH 1 /* DSP1_START */
147
973838a0
MB		 148/*
149 * ADSP2 clocking
150 */
151#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
152#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
153#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
154
2159ad93
MB		 155/*
156 * ADSP2 Status 1
157 */
158#define ADSP2_RAM_RDY 0x0001
159#define ADSP2_RAM_RDY_MASK 0x0001
160#define ADSP2_RAM_RDY_SHIFT 0
161#define ADSP2_RAM_RDY_WIDTH 1
162
9ee78757
CK		 163#define ADSP_MAX_STD_CTRL_SIZE 512
164
f4f0c4c6
RF		 165#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
166#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
167
168/*
169 * Event control messages
170 */
171#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
172
cf17c83c
MB		 173struct wm_adsp_buf {
174 struct list_head list;
175 void *buf;
176};
177
178static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
179 struct list_head *list)
180{
181 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
182
183 if (buf == NULL)
184 return NULL;
185
cdcd7f72 186 buf->buf = vmalloc(len);
cf17c83c 187 if (!buf->buf) {
cdcd7f72 188 vfree(buf);
cf17c83c
MB		 189 return NULL;
190 }
cdcd7f72 191 memcpy(buf->buf, src, len);
cf17c83c
MB		 192
193 if (list)
194 list_add_tail(&buf->list, list);
195
196 return buf;
197}
198
199static void wm_adsp_buf_free(struct list_head *list)
200{
201 while (!list_empty(list)) {
202 struct wm_adsp_buf *buf = list_first_entry(list,
203 struct wm_adsp_buf,
204 list);
205 list_del(&buf->list);
cdcd7f72 206 vfree(buf->buf);
cf17c83c
MB		 207 kfree(buf);
208 }
209}
210
04d1300f
CK		 211#define WM_ADSP_FW_MBC_VSS 0
212#define WM_ADSP_FW_HIFI 1
213#define WM_ADSP_FW_TX 2
214#define WM_ADSP_FW_TX_SPK 3
215#define WM_ADSP_FW_RX 4
216#define WM_ADSP_FW_RX_ANC 5
217#define WM_ADSP_FW_CTRL 6
218#define WM_ADSP_FW_ASR 7
219#define WM_ADSP_FW_TRACE 8
220#define WM_ADSP_FW_SPK_PROT 9
221#define WM_ADSP_FW_MISC 10
222
223#define WM_ADSP_NUM_FW 11
dd84f925 224
1023dbd9 225static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 226 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
227 [WM_ADSP_FW_HIFI] = "MasterHiFi",
228 [WM_ADSP_FW_TX] = "Tx",
229 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
230 [WM_ADSP_FW_RX] = "Rx",
231 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
232 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
233 [WM_ADSP_FW_ASR] = "ASR Assist",
234 [WM_ADSP_FW_TRACE] = "Dbg Trace",
235 [WM_ADSP_FW_SPK_PROT] = "Protection",
236 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 237};
238
2cd19bdb
CK		 239struct wm_adsp_system_config_xm_hdr {
240 __be32 sys_enable;
241 __be32 fw_id;
242 __be32 fw_rev;
243 __be32 boot_status;
244 __be32 watchdog;
245 __be32 dma_buffer_size;
246 __be32 rdma[6];
247 __be32 wdma[8];
248 __be32 build_job_name[3];
249 __be32 build_job_number;
250};
251
252struct wm_adsp_alg_xm_struct {
253 __be32 magic;
254 __be32 smoothing;
255 __be32 threshold;
256 __be32 host_buf_ptr;
257 __be32 start_seq;
258 __be32 high_water_mark;
259 __be32 low_water_mark;
260 __be64 smoothed_power;
261};
262
263struct wm_adsp_buffer {
264 __be32 X_buf_base; /* XM base addr of first X area */
265 __be32 X_buf_size; /* Size of 1st X area in words */
266 __be32 X_buf_base2; /* XM base addr of 2nd X area */
267 __be32 X_buf_brk; /* Total X size in words */
268 __be32 Y_buf_base; /* YM base addr of Y area */
269 __be32 wrap; /* Total size X and Y in words */
270 __be32 high_water_mark; /* Point at which IRQ is asserted */
271 __be32 irq_count; /* bits 1-31 count IRQ assertions */
272 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
273 __be32 next_write_index; /* word index of next write */
274 __be32 next_read_index; /* word index of next read */
275 __be32 error; /* error if any */
276 __be32 oldest_block_index; /* word index of oldest surviving */
277 __be32 requested_rewind; /* how many blocks rewind was done */
278 __be32 reserved_space; /* internal */
279 __be32 min_free; /* min free space since stream start */
280 __be32 blocks_written[2]; /* total blocks written (64 bit) */
281 __be32 words_written[2]; /* total words written (64 bit) */
282};
283
721be3be
CK		 284struct wm_adsp_compr;
285
2cd19bdb
CK		 286struct wm_adsp_compr_buf {
287 struct wm_adsp *dsp;
721be3be 288 struct wm_adsp_compr *compr;
2cd19bdb
CK		 289
290 struct wm_adsp_buffer_region *regions;
291 u32 host_buf_ptr;
565ace46
CK		 292
293 u32 error;
294 u32 irq_count;
295 int read_index;
296 int avail;
2cd19bdb
CK		 297};
298
406abc95
CK		 299struct wm_adsp_compr {
300 struct wm_adsp *dsp;
95fe9597 301 struct wm_adsp_compr_buf *buf;
406abc95
CK		 302
303 struct snd_compr_stream *stream;
304 struct snd_compressed_buffer size;
565ace46 305
83a40ce9 306 u32 *raw_buf;
565ace46 307 unsigned int copied_total;
da2b3358
CK		 308
309 unsigned int sample_rate;
406abc95
CK		 310};
311
312#define WM_ADSP_DATA_WORD_SIZE 3
313
314#define WM_ADSP_MIN_FRAGMENTS 1
315#define WM_ADSP_MAX_FRAGMENTS 256
316#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
317#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
318
2cd19bdb
CK		 319#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
320
321#define HOST_BUFFER_FIELD(field) \
322 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
323
324#define ALG_XM_FIELD(field) \
325 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
326
327static int wm_adsp_buffer_init(struct wm_adsp *dsp);
328static int wm_adsp_buffer_free(struct wm_adsp *dsp);
329
330struct wm_adsp_buffer_region {
331 unsigned int offset;
332 unsigned int cumulative_size;
333 unsigned int mem_type;
334 unsigned int base_addr;
335};
336
337struct wm_adsp_buffer_region_def {
338 unsigned int mem_type;
339 unsigned int base_offset;
340 unsigned int size_offset;
341};
342
3a9686c4 343static const struct wm_adsp_buffer_region_def default_regions[] = {
2cd19bdb
CK		 344 {
345 .mem_type = WMFW_ADSP2_XM,
346 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
347 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
348 },
349 {
350 .mem_type = WMFW_ADSP2_XM,
351 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
352 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
353 },
354 {
355 .mem_type = WMFW_ADSP2_YM,
356 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
357 .size_offset = HOST_BUFFER_FIELD(wrap),
358 },
359};
360
406abc95
CK		 361struct wm_adsp_fw_caps {
362 u32 id;
363 struct snd_codec_desc desc;
2cd19bdb 364 int num_regions;
3a9686c4 365 const struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 366};
367
e6d00f34 368static const struct wm_adsp_fw_caps ctrl_caps[] = {
406abc95
CK		 369 {
370 .id = SND_AUDIOCODEC_BESPOKE,
371 .desc = {
372 .max_ch = 1,
373 .sample_rates = { 16000 },
374 .num_sample_rates = 1,
375 .formats = SNDRV_PCM_FMTBIT_S16_LE,
376 },
e6d00f34
CK		 377 .num_regions = ARRAY_SIZE(default_regions),
378 .region_defs = default_regions,
406abc95
CK		 379 },
380};
381
7ce4283c
CK		 382static const struct wm_adsp_fw_caps trace_caps[] = {
383 {
384 .id = SND_AUDIOCODEC_BESPOKE,
385 .desc = {
386 .max_ch = 8,
387 .sample_rates = {
388 4000, 8000, 11025, 12000, 16000, 22050,
389 24000, 32000, 44100, 48000, 64000, 88200,
390 96000, 176400, 192000
391 },
392 .num_sample_rates = 15,
393 .formats = SNDRV_PCM_FMTBIT_S16_LE,
394 },
395 .num_regions = ARRAY_SIZE(default_regions),
396 .region_defs = default_regions,
406abc95
CK		 397 },
398};
399
400static const struct {
1023dbd9 401 const char *file;
406abc95
CK		 402 int compr_direction;
403 int num_caps;
404 const struct wm_adsp_fw_caps *caps;
20b7f7c5 405 bool voice_trigger;
1023dbd9 406} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 407 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
408 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
409 [WM_ADSP_FW_TX] = { .file = "tx" },
410 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
411 [WM_ADSP_FW_RX] = { .file = "rx" },
412 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 413 [WM_ADSP_FW_CTRL] = {
414 .file = "ctrl",
415 .compr_direction = SND_COMPRESS_CAPTURE,
e6d00f34
CK		 416 .num_caps = ARRAY_SIZE(ctrl_caps),
417 .caps = ctrl_caps,
20b7f7c5 418 .voice_trigger = true,
406abc95 419 },
04d1300f 420 [WM_ADSP_FW_ASR] = { .file = "asr" },
7ce4283c
CK		 421 [WM_ADSP_FW_TRACE] = {
422 .file = "trace",
423 .compr_direction = SND_COMPRESS_CAPTURE,
424 .num_caps = ARRAY_SIZE(trace_caps),
425 .caps = trace_caps,
426 },
04d1300f
CK		 427 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
428 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 429};
430
6ab2b7b4
DP		 431struct wm_coeff_ctl_ops {
432 int (*xget)(struct snd_kcontrol *kcontrol,
433 struct snd_ctl_elem_value *ucontrol);
434 int (*xput)(struct snd_kcontrol *kcontrol,
435 struct snd_ctl_elem_value *ucontrol);
436 int (*xinfo)(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_info *uinfo);
438};
439
6ab2b7b4
DP		 440struct wm_coeff_ctl {
441 const char *name;
2323736d 442 const char *fw_name;
3809f001 443 struct wm_adsp_alg_region alg_region;
6ab2b7b4 444 struct wm_coeff_ctl_ops ops;
3809f001 445 struct wm_adsp *dsp;
6ab2b7b4
DP		 446 unsigned int enabled:1;
447 struct list_head list;
448 void *cache;
2323736d 449 unsigned int offset;
6ab2b7b4 450 size_t len;
0c2e3f34 451 unsigned int set:1;
6ab2b7b4 452 struct snd_kcontrol *kcontrol;
9ee78757 453 struct soc_bytes_ext bytes_ext;
26c22a19 454 unsigned int flags;
6ab2b7b4
DP		 455};
456
f9f55e31
RF		 457#ifdef CONFIG_DEBUG_FS
458static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
459{
460 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
461
f9f55e31
RF		 462 kfree(dsp->wmfw_file_name);
463 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 464}
465
466static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
467{
468 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
469
f9f55e31
RF		 470 kfree(dsp->bin_file_name);
471 dsp->bin_file_name = tmp;
f9f55e31
RF		 472}
473
474static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
475{
f9f55e31
RF		 476 kfree(dsp->wmfw_file_name);
477 kfree(dsp->bin_file_name);
478 dsp->wmfw_file_name = NULL;
479 dsp->bin_file_name = NULL;
f9f55e31
RF		 480}
481
482static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
483 char __user *user_buf,
484 size_t count, loff_t *ppos)
485{
486 struct wm_adsp *dsp = file->private_data;
487 ssize_t ret;
488
078e7183 489 mutex_lock(&dsp->pwr_lock);
f9f55e31 490
28823eba 491 if (!dsp->wmfw_file_name || !dsp->booted)
f9f55e31
RF		 492 ret = 0;
493 else
494 ret = simple_read_from_buffer(user_buf, count, ppos,
495 dsp->wmfw_file_name,
496 strlen(dsp->wmfw_file_name));
497
078e7183 498 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 499 return ret;
500}
501
502static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
503 char __user *user_buf,
504 size_t count, loff_t *ppos)
505{
506 struct wm_adsp *dsp = file->private_data;
507 ssize_t ret;
508
078e7183 509 mutex_lock(&dsp->pwr_lock);
f9f55e31 510
28823eba 511 if (!dsp->bin_file_name || !dsp->booted)
f9f55e31
RF		 512 ret = 0;
513 else
514 ret = simple_read_from_buffer(user_buf, count, ppos,
515 dsp->bin_file_name,
516 strlen(dsp->bin_file_name));
517
078e7183 518 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 519 return ret;
520}
521
522static const struct {
523 const char *name;
524 const struct file_operations fops;
525} wm_adsp_debugfs_fops[] = {
526 {
527 .name = "wmfw_file_name",
528 .fops = {
529 .open = simple_open,
530 .read = wm_adsp_debugfs_wmfw_read,
531 },
532 },
533 {
534 .name = "bin_file_name",
535 .fops = {
536 .open = simple_open,
537 .read = wm_adsp_debugfs_bin_read,
538 },
539 },
540};
541
542static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
543 struct snd_soc_codec *codec)
544{
545 struct dentry *root = NULL;
546 char *root_name;
547 int i;
548
549 if (!codec->component.debugfs_root) {
550 adsp_err(dsp, "No codec debugfs root\n");
551 goto err;
552 }
553
554 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
555 if (!root_name)
556 goto err;
557
558 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
559 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
560 kfree(root_name);
561
562 if (!root)
563 goto err;
564
28823eba
CK		 565 if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted))
566 goto err;
567
f9f55e31
RF		 568 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
569 goto err;
570
571 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
572 goto err;
573
574 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
575 &dsp->fw_id_version))
576 goto err;
577
578 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
579 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
580 S_IRUGO, root, dsp,
581 &wm_adsp_debugfs_fops[i].fops))
582 goto err;
583 }
584
585 dsp->debugfs_root = root;
586 return;
587
588err:
589 debugfs_remove_recursive(root);
590 adsp_err(dsp, "Failed to create debugfs\n");
591}
592
593static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
594{
595 wm_adsp_debugfs_clear(dsp);
596 debugfs_remove_recursive(dsp->debugfs_root);
597}
598#else
599static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
600 struct snd_soc_codec *codec)
601{
602}
603
604static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
605{
606}
607
608static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
609 const char *s)
610{
611}
612
613static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
614 const char *s)
615{
616}
617
618static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
619{
620}
621#endif
622
1023dbd9
MB		 623static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
624 struct snd_ctl_elem_value *ucontrol)
625{
ea53bf77 626 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 627 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 628 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 629
15c66570 630 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 631
632 return 0;
633}
634
635static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
636 struct snd_ctl_elem_value *ucontrol)
637{
ea53bf77 638 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 639 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 640 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 641 int ret = 0;
1023dbd9 642
15c66570 643 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 644 return 0;
645
15c66570 646 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
1023dbd9
MB		 647 return -EINVAL;
648
d27c5e15
CK		 649 mutex_lock(&dsp[e->shift_l].pwr_lock);
650
28823eba 651 if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
d27c5e15
CK		 652 ret = -EBUSY;
653 else
15c66570 654 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
1023dbd9 655
d27c5e15 656 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 657
d27c5e15 658 return ret;
1023dbd9
MB		 659}
660
661static const struct soc_enum wm_adsp_fw_enum[] = {
662 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
663 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
664 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
665 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
666};
667
336d0442 668const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 669 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
670 wm_adsp_fw_get, wm_adsp_fw_put),
671 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
672 wm_adsp_fw_get, wm_adsp_fw_put),
673 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
674 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 675 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
676 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 677};
336d0442 678EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 679
680static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
681 int type)
682{
683 int i;
684
685 for (i = 0; i < dsp->num_mems; i++)
686 if (dsp->mem[i].type == type)
687 return &dsp->mem[i];
688
689 return NULL;
690}
691
3809f001 692static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 693 unsigned int offset)
694{
3809f001 695 if (WARN_ON(!mem))
6c452bda 696 return offset;
3809f001 697 switch (mem->type) {
45b9ee72 698 case WMFW_ADSP1_PM:
3809f001 699 return mem->base + (offset * 3);
45b9ee72 700 case WMFW_ADSP1_DM:
3809f001 701 return mem->base + (offset * 2);
45b9ee72 702 case WMFW_ADSP2_XM:
3809f001 703 return mem->base + (offset * 2);
45b9ee72 704 case WMFW_ADSP2_YM:
3809f001 705 return mem->base + (offset * 2);
45b9ee72 706 case WMFW_ADSP1_ZM:
3809f001 707 return mem->base + (offset * 2);
45b9ee72 708 default:
6c452bda 709 WARN(1, "Unknown memory region type");
45b9ee72
MB		 710 return offset;
711 }
712}
713
10337b07
RF		 714static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
715{
716 u16 scratch[4];
717 int ret;
718
719 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
720 scratch, sizeof(scratch));
721 if (ret) {
722 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
723 return;
724 }
725
726 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
727 be16_to_cpu(scratch[0]),
728 be16_to_cpu(scratch[1]),
729 be16_to_cpu(scratch[2]),
730 be16_to_cpu(scratch[3]));
731}
732
9ee78757
CK		 733static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
734{
735 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
736}
737
7585a5b0 738static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 739 struct snd_ctl_elem_info *uinfo)
740{
9ee78757
CK		 741 struct soc_bytes_ext *bytes_ext =
742 (struct soc_bytes_ext *)kctl->private_value;
743 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4
DP		 744
745 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
746 uinfo->count = ctl->len;
747 return 0;
748}
749
f4f0c4c6
RF		 750static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
751 unsigned int event_id)
752{
753 struct wm_adsp *dsp = ctl->dsp;
754 u32 val = cpu_to_be32(event_id);
755 unsigned int reg;
756 int i, ret;
757
758 ret = wm_coeff_base_reg(ctl, &reg);
759 if (ret)
760 return ret;
761
762 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
763 event_id, ctl->alg_region.alg,
764 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
765
766 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
767 if (ret) {
768 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
769 return ret;
770 }
771
772 /*
773 * Poll for ack, we initially poll at ~1ms intervals for firmwares
774 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
775 * to ack instantly so we do the first 1ms delay before reading the
776 * control to avoid a pointless bus transaction
777 */
778 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
779 switch (i) {
780 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
781 usleep_range(1000, 2000);
782 i++;
783 break;
784 default:
785 usleep_range(10000, 20000);
786 i += 10;
787 break;
788 }
789
790 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
791 if (ret) {
792 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
793 return ret;
794 }
795
796 if (val == 0) {
797 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
798 return 0;
799 }
800 }
801
802 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
803 reg, ctl->alg_region.alg,
804 wm_adsp_mem_region_name(ctl->alg_region.type),
805 ctl->offset);
806
807 return -ETIMEDOUT;
808}
809
c9f8dd71 810static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 811 const void *buf, size_t len)
812{
3809f001 813 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 814 const struct wm_adsp_region *mem;
3809f001 815 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 816 void *scratch;
817 int ret;
818 unsigned int reg;
819
3809f001 820 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 821 if (!mem) {
3809f001
CK		 822 adsp_err(dsp, "No base for region %x\n",
823 alg_region->type);
6ab2b7b4
DP		 824 return -EINVAL;
825 }
826
2323736d 827 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 828 reg = wm_adsp_region_to_reg(mem, reg);
829
4f8ea6d7 830 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 831 if (!scratch)
832 return -ENOMEM;
833
3809f001 834 ret = regmap_raw_write(dsp->regmap, reg, scratch,
4f8ea6d7 835 len);
6ab2b7b4 836 if (ret) {
3809f001 837 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
4f8ea6d7 838 len, reg, ret);
6ab2b7b4
DP		 839 kfree(scratch);
840 return ret;
841 }
4f8ea6d7 842 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
6ab2b7b4
DP		 843
844 kfree(scratch);
845
846 return 0;
847}
848
7585a5b0 849static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 850 struct snd_ctl_elem_value *ucontrol)
851{
9ee78757
CK		 852 struct soc_bytes_ext *bytes_ext =
853 (struct soc_bytes_ext *)kctl->private_value;
854 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 855 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 856 int ret = 0;
857
858 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 859
860 memcpy(ctl->cache, p, ctl->len);
861
65d17a9c 862 ctl->set = 1;
cef45771 863 if (ctl->enabled && ctl->dsp->running)
168d10e7 864 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 865
168d10e7
CK		 866 mutex_unlock(&ctl->dsp->pwr_lock);
867
868 return ret;
6ab2b7b4
DP		 869}
870
9ee78757
CK		 871static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
872 const unsigned int __user *bytes, unsigned int size)
873{
874 struct soc_bytes_ext *bytes_ext =
875 (struct soc_bytes_ext *)kctl->private_value;
876 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
877 int ret = 0;
878
879 mutex_lock(&ctl->dsp->pwr_lock);
880
881 if (copy_from_user(ctl->cache, bytes, size)) {
882 ret = -EFAULT;
883 } else {
884 ctl->set = 1;
cef45771 885 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 886 ret = wm_coeff_write_control(ctl, ctl->cache, size);
887 }
888
889 mutex_unlock(&ctl->dsp->pwr_lock);
890
891 return ret;
892}
893
c9f8dd71 894static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 895 void *buf, size_t len)
896{
3809f001 897 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 898 const struct wm_adsp_region *mem;
3809f001 899 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 900 void *scratch;
901 int ret;
902 unsigned int reg;
903
3809f001 904 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 905 if (!mem) {
3809f001
CK		 906 adsp_err(dsp, "No base for region %x\n",
907 alg_region->type);
6ab2b7b4
DP		 908 return -EINVAL;
909 }
910
2323736d 911 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 912 reg = wm_adsp_region_to_reg(mem, reg);
913
4f8ea6d7 914 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 915 if (!scratch)
916 return -ENOMEM;
917
4f8ea6d7 918 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
6ab2b7b4 919 if (ret) {
3809f001 920 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
5602a643 921 len, reg, ret);
6ab2b7b4
DP		 922 kfree(scratch);
923 return ret;
924 }
4f8ea6d7 925 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
6ab2b7b4 926
4f8ea6d7 927 memcpy(buf, scratch, len);
6ab2b7b4
DP		 928 kfree(scratch);
929
930 return 0;
931}
932
7585a5b0 933static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 934 struct snd_ctl_elem_value *ucontrol)
935{
9ee78757
CK		 936 struct soc_bytes_ext *bytes_ext =
937 (struct soc_bytes_ext *)kctl->private_value;
938 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
6ab2b7b4 939 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 940 int ret = 0;
941
942 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 943
26c22a19 944 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 945 if (ctl->enabled && ctl->dsp->running)
168d10e7 946 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 947 else
168d10e7
CK		 948 ret = -EPERM;
949 } else {
cef45771 950 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
bc1765d6
CK		 951 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
952
168d10e7 953 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 954 }
955
168d10e7 956 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 957
168d10e7 958 return ret;
6ab2b7b4
DP		 959}
960
9ee78757
CK		 961static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
962 unsigned int __user *bytes, unsigned int size)
963{
964 struct soc_bytes_ext *bytes_ext =
965 (struct soc_bytes_ext *)kctl->private_value;
966 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
967 int ret = 0;
968
969 mutex_lock(&ctl->dsp->pwr_lock);
970
971 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
cef45771 972 if (ctl->enabled && ctl->dsp->running)
9ee78757
CK		 973 ret = wm_coeff_read_control(ctl, ctl->cache, size);
974 else
975 ret = -EPERM;
976 } else {
cef45771 977 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
9ee78757
CK		 978 ret = wm_coeff_read_control(ctl, ctl->cache, size);
979 }
980
981 if (!ret && copy_to_user(bytes, ctl->cache, size))
982 ret = -EFAULT;
983
984 mutex_unlock(&ctl->dsp->pwr_lock);
985
986 return ret;
987}
988
6ab2b7b4 989struct wmfw_ctl_work {
3809f001 990 struct wm_adsp *dsp;
6ab2b7b4
DP		 991 struct wm_coeff_ctl *ctl;
992 struct work_struct work;
993};
994
9ee78757
CK		 995static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
996{
997 unsigned int out, rd, wr, vol;
998
999 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1000 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1001 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1002 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1003
1004 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1005 } else {
1006 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1007 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1008 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1009
1010 out = 0;
1011 }
1012
1013 if (in) {
1014 if (in & WMFW_CTL_FLAG_READABLE)
1015 out |= rd;
1016 if (in & WMFW_CTL_FLAG_WRITEABLE)
1017 out |= wr;
1018 if (in & WMFW_CTL_FLAG_VOLATILE)
1019 out |= vol;
1020 } else {
1021 out |= rd | wr | vol;
1022 }
1023
1024 return out;
1025}
1026
3809f001 1027static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 1028{
1029 struct snd_kcontrol_new *kcontrol;
1030 int ret;
1031
92bb4c32 1032 if (!ctl || !ctl->name)
6ab2b7b4
DP		 1033 return -EINVAL;
1034
1035 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1036 if (!kcontrol)
1037 return -ENOMEM;
6ab2b7b4
DP		 1038
1039 kcontrol->name = ctl->name;
1040 kcontrol->info = wm_coeff_info;
1041 kcontrol->get = wm_coeff_get;
1042 kcontrol->put = wm_coeff_put;
9ee78757
CK		 1043 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1044 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1045 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
6ab2b7b4 1046
9ee78757
CK		 1047 ctl->bytes_ext.max = ctl->len;
1048 ctl->bytes_ext.get = wm_coeff_tlv_get;
1049 ctl->bytes_ext.put = wm_coeff_tlv_put;
1050
1051 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
26c22a19 1052
7d00cd97 1053 ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1);
6ab2b7b4
DP		 1054 if (ret < 0)
1055 goto err_kcontrol;
1056
1057 kfree(kcontrol);
1058
7d00cd97 1059 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name);
81ad93ec 1060
6ab2b7b4
DP		 1061 return 0;
1062
1063err_kcontrol:
1064 kfree(kcontrol);
1065 return ret;
1066}
1067
b21acc1c
CK		 1068static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1069{
1070 struct wm_coeff_ctl *ctl;
1071 int ret;
1072
1073 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1074 if (!ctl->enabled || ctl->set)
1075 continue;
26c22a19
CK		 1076 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1077 continue;
1078
7d00cd97 1079 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1080 if (ret < 0)
1081 return ret;
1082 }
1083
1084 return 0;
1085}
1086
1087static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1088{
1089 struct wm_coeff_ctl *ctl;
1090 int ret;
1091
1092 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1093 if (!ctl->enabled)
1094 continue;
26c22a19 1095 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
7d00cd97 1096 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 1097 if (ret < 0)
1098 return ret;
1099 }
1100 }
1101
1102 return 0;
1103}
1104
f4f0c4c6
RF		 1105static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1106 unsigned int event)
1107{
1108 struct wm_coeff_ctl *ctl;
1109 int ret;
1110
1111 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1112 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1113 continue;
1114
1115 ret = wm_coeff_write_acked_control(ctl, event);
1116 if (ret)
1117 adsp_warn(dsp,
1118 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1119 event, ctl->alg_region.alg, ret);
1120 }
1121}
1122
b21acc1c
CK		 1123static void wm_adsp_ctl_work(struct work_struct *work)
1124{
1125 struct wmfw_ctl_work *ctl_work = container_of(work,
1126 struct wmfw_ctl_work,
1127 work);
1128
1129 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1130 kfree(ctl_work);
1131}
1132
66225e98
RF		 1133static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1134{
1135 kfree(ctl->cache);
1136 kfree(ctl->name);
1137 kfree(ctl);
1138}
1139
b21acc1c
CK		 1140static int wm_adsp_create_control(struct wm_adsp *dsp,
1141 const struct wm_adsp_alg_region *alg_region,
2323736d 1142 unsigned int offset, unsigned int len,
26c22a19
CK		 1143 const char *subname, unsigned int subname_len,
1144 unsigned int flags)
b21acc1c
CK		 1145{
1146 struct wm_coeff_ctl *ctl;
1147 struct wmfw_ctl_work *ctl_work;
1148 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1149 char *region_name;
1150 int ret;
1151
26c22a19
CK		 1152 if (flags & WMFW_CTL_FLAG_SYS)
1153 return 0;
1154
b21acc1c
CK		 1155 switch (alg_region->type) {
1156 case WMFW_ADSP1_PM:
1157 region_name = "PM";
1158 break;
1159 case WMFW_ADSP1_DM:
1160 region_name = "DM";
1161 break;
1162 case WMFW_ADSP2_XM:
1163 region_name = "XM";
1164 break;
1165 case WMFW_ADSP2_YM:
1166 region_name = "YM";
1167 break;
1168 case WMFW_ADSP1_ZM:
1169 region_name = "ZM";
1170 break;
1171 default:
2323736d 1172 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 1173 return -EINVAL;
1174 }
1175
cb5b57a9
CK		 1176 switch (dsp->fw_ver) {
1177 case 0:
1178 case 1:
1179 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
1180 dsp->num, region_name, alg_region->alg);
1181 break;
1182 default:
1183 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1184 "DSP%d%c %.12s %x", dsp->num, *region_name,
1185 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1186
1187 /* Truncate the subname from the start if it is too long */
1188 if (subname) {
1189 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1190 int skip = 0;
1191
1192 if (subname_len > avail)
1193 skip = subname_len - avail;
1194
1195 snprintf(name + ret,
1196 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1197 subname_len - skip, subname + skip);
1198 }
1199 break;
1200 }
b21acc1c 1201
7585a5b0 1202 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 1203 if (!strcmp(ctl->name, name)) {
1204 if (!ctl->enabled)
1205 ctl->enabled = 1;
1206 return 0;
1207 }
1208 }
1209
1210 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1211 if (!ctl)
1212 return -ENOMEM;
2323736d 1213 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 1214 ctl->alg_region = *alg_region;
1215 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1216 if (!ctl->name) {
1217 ret = -ENOMEM;
1218 goto err_ctl;
1219 }
1220 ctl->enabled = 1;
1221 ctl->set = 0;
1222 ctl->ops.xget = wm_coeff_get;
1223 ctl->ops.xput = wm_coeff_put;
1224 ctl->dsp = dsp;
1225
26c22a19 1226 ctl->flags = flags;
2323736d 1227 ctl->offset = offset;
b21acc1c
CK		 1228 ctl->len = len;
1229 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1230 if (!ctl->cache) {
1231 ret = -ENOMEM;
1232 goto err_ctl_name;
1233 }
1234
2323736d
CK		 1235 list_add(&ctl->list, &dsp->ctl_list);
1236
b21acc1c
CK		 1237 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1238 if (!ctl_work) {
1239 ret = -ENOMEM;
1240 goto err_ctl_cache;
1241 }
1242
1243 ctl_work->dsp = dsp;
1244 ctl_work->ctl = ctl;
1245 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1246 schedule_work(&ctl_work->work);
1247
1248 return 0;
1249
1250err_ctl_cache:
1251 kfree(ctl->cache);
1252err_ctl_name:
1253 kfree(ctl->name);
1254err_ctl:
1255 kfree(ctl);
1256
1257 return ret;
1258}
1259
2323736d
CK		 1260struct wm_coeff_parsed_alg {
1261 int id;
1262 const u8 *name;
1263 int name_len;
1264 int ncoeff;
1265};
1266
1267struct wm_coeff_parsed_coeff {
1268 int offset;
1269 int mem_type;
1270 const u8 *name;
1271 int name_len;
1272 int ctl_type;
1273 int flags;
1274 int len;
1275};
1276
cb5b57a9
CK		 1277static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1278{
1279 int length;
1280
1281 switch (bytes) {
1282 case 1:
1283 length = **pos;
1284 break;
1285 case 2:
8299ee81 1286 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1287 break;
1288 default:
1289 return 0;
1290 }
1291
1292 if (str)
1293 *str = *pos + bytes;
1294
1295 *pos += ((length + bytes) + 3) & ~0x03;
1296
1297 return length;
1298}
1299
1300static int wm_coeff_parse_int(int bytes, const u8 **pos)
1301{
1302 int val = 0;
1303
1304 switch (bytes) {
1305 case 2:
8299ee81 1306 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1307 break;
1308 case 4:
8299ee81 1309 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1310 break;
1311 default:
1312 break;
1313 }
1314
1315 *pos += bytes;
1316
1317 return val;
1318}
1319
2323736d
CK		 1320static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1321 struct wm_coeff_parsed_alg *blk)
1322{
1323 const struct wmfw_adsp_alg_data *raw;
1324
cb5b57a9
CK		 1325 switch (dsp->fw_ver) {
1326 case 0:
1327 case 1:
1328 raw = (const struct wmfw_adsp_alg_data *)*data;
1329 *data = raw->data;
2323736d 1330
cb5b57a9
CK		 1331 blk->id = le32_to_cpu(raw->id);
1332 blk->name = raw->name;
1333 blk->name_len = strlen(raw->name);
1334 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1335 break;
1336 default:
1337 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1338 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1339 &blk->name);
1340 wm_coeff_parse_string(sizeof(u16), data, NULL);
1341 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1342 break;
1343 }
2323736d
CK		 1344
1345 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1346 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1347 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1348}
1349
1350static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1351 struct wm_coeff_parsed_coeff *blk)
1352{
1353 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1354 const u8 *tmp;
1355 int length;
2323736d 1356
cb5b57a9
CK		 1357 switch (dsp->fw_ver) {
1358 case 0:
1359 case 1:
1360 raw = (const struct wmfw_adsp_coeff_data *)*data;
1361 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1362
1363 blk->offset = le16_to_cpu(raw->hdr.offset);
1364 blk->mem_type = le16_to_cpu(raw->hdr.type);
1365 blk->name = raw->name;
1366 blk->name_len = strlen(raw->name);
1367 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1368 blk->flags = le16_to_cpu(raw->flags);
1369 blk->len = le32_to_cpu(raw->len);
1370 break;
1371 default:
1372 tmp = *data;
1373 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1374 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1375 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1376 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1377 &blk->name);
1378 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1379 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1380 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1381 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1382 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1383
1384 *data = *data + sizeof(raw->hdr) + length;
1385 break;
1386 }
2323736d
CK		 1387
1388 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1389 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1390 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1391 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1392 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1393 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1394}
1395
f4f0c4c6
RF		 1396static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1397 const struct wm_coeff_parsed_coeff *coeff_blk,
1398 unsigned int f_required,
1399 unsigned int f_illegal)
1400{
1401 if ((coeff_blk->flags & f_illegal) ||
1402 ((coeff_blk->flags & f_required) != f_required)) {
1403 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1404 coeff_blk->flags, coeff_blk->ctl_type);
1405 return -EINVAL;
1406 }
1407
1408 return 0;
1409}
1410
2323736d
CK		 1411static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1412 const struct wmfw_region *region)
1413{
1414 struct wm_adsp_alg_region alg_region = {};
1415 struct wm_coeff_parsed_alg alg_blk;
1416 struct wm_coeff_parsed_coeff coeff_blk;
1417 const u8 *data = region->data;
1418 int i, ret;
1419
1420 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1421 for (i = 0; i < alg_blk.ncoeff; i++) {
1422 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1423
1424 switch (coeff_blk.ctl_type) {
1425 case SNDRV_CTL_ELEM_TYPE_BYTES:
1426 break;
f4f0c4c6
RF		 1427 case WMFW_CTL_TYPE_HOSTEVENT:
1428 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1429 WMFW_CTL_FLAG_SYS |
1430 WMFW_CTL_FLAG_VOLATILE |
1431 WMFW_CTL_FLAG_WRITEABLE |
1432 WMFW_CTL_FLAG_READABLE,
1433 0);
1434 if (ret)
1435 return -EINVAL;
1436 break;
2323736d
CK		 1437 default:
1438 adsp_err(dsp, "Unknown control type: %d\n",
1439 coeff_blk.ctl_type);
1440 return -EINVAL;
1441 }
1442
1443 alg_region.type = coeff_blk.mem_type;
1444 alg_region.alg = alg_blk.id;
1445
1446 ret = wm_adsp_create_control(dsp, &alg_region,
1447 coeff_blk.offset,
1448 coeff_blk.len,
1449 coeff_blk.name,
26c22a19
CK		 1450 coeff_blk.name_len,
1451 coeff_blk.flags);
2323736d
CK		 1452 if (ret < 0)
1453 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1454 coeff_blk.name_len, coeff_blk.name, ret);
1455 }
1456
1457 return 0;
1458}
1459
2159ad93
MB		 1460static int wm_adsp_load(struct wm_adsp *dsp)
1461{
cf17c83c 1462 LIST_HEAD(buf_list);
2159ad93
MB		 1463 const struct firmware *firmware;
1464 struct regmap *regmap = dsp->regmap;
1465 unsigned int pos = 0;
1466 const struct wmfw_header *header;
1467 const struct wmfw_adsp1_sizes *adsp1_sizes;
1468 const struct wmfw_adsp2_sizes *adsp2_sizes;
1469 const struct wmfw_footer *footer;
1470 const struct wmfw_region *region;
1471 const struct wm_adsp_region *mem;
1472 const char *region_name;
1473 char *file, *text;
cf17c83c 1474 struct wm_adsp_buf *buf;
2159ad93
MB		 1475 unsigned int reg;
1476 int regions = 0;
1477 int ret, offset, type, sizes;
1478
1479 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1480 if (file == NULL)
1481 return -ENOMEM;
1482
1023dbd9
MB		 1483 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1484 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1485 file[PAGE_SIZE - 1] = '\0';
1486
1487 ret = request_firmware(&firmware, file, dsp->dev);
1488 if (ret != 0) {
1489 adsp_err(dsp, "Failed to request '%s'\n", file);
1490 goto out;
1491 }
1492 ret = -EINVAL;
1493
1494 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1495 if (pos >= firmware->size) {
1496 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1497 file, firmware->size);
1498 goto out_fw;
1499 }
1500
7585a5b0 1501 header = (void *)&firmware->data[0];
2159ad93
MB		 1502
1503 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1504 adsp_err(dsp, "%s: invalid magic\n", file);
1505 goto out_fw;
1506 }
1507
2323736d
CK		 1508 switch (header->ver) {
1509 case 0:
c61e59fe
CK		 1510 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1511 file, header->ver);
1512 break;
2323736d 1513 case 1:
cb5b57a9 1514 case 2:
2323736d
CK		 1515 break;
1516 default:
2159ad93
MB		 1517 adsp_err(dsp, "%s: unknown file format %d\n",
1518 file, header->ver);
1519 goto out_fw;
1520 }
2323736d 1521
3626992a 1522 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1523 dsp->fw_ver = header->ver;
2159ad93
MB		 1524
1525 if (header->core != dsp->type) {
1526 adsp_err(dsp, "%s: invalid core %d != %d\n",
1527 file, header->core, dsp->type);
1528 goto out_fw;
1529 }
1530
1531 switch (dsp->type) {
1532 case WMFW_ADSP1:
1533 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1534 adsp1_sizes = (void *)&(header[1]);
1535 footer = (void *)&(adsp1_sizes[1]);
1536 sizes = sizeof(*adsp1_sizes);
1537
1538 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1539 file, le32_to_cpu(adsp1_sizes->dm),
1540 le32_to_cpu(adsp1_sizes->pm),
1541 le32_to_cpu(adsp1_sizes->zm));
1542 break;
1543
1544 case WMFW_ADSP2:
1545 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1546 adsp2_sizes = (void *)&(header[1]);
1547 footer = (void *)&(adsp2_sizes[1]);
1548 sizes = sizeof(*adsp2_sizes);
1549
1550 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1551 file, le32_to_cpu(adsp2_sizes->xm),
1552 le32_to_cpu(adsp2_sizes->ym),
1553 le32_to_cpu(adsp2_sizes->pm),
1554 le32_to_cpu(adsp2_sizes->zm));
1555 break;
1556
1557 default:
6c452bda 1558 WARN(1, "Unknown DSP type");
2159ad93
MB		 1559 goto out_fw;
1560 }
1561
1562 if (le32_to_cpu(header->len) != sizeof(*header) +
1563 sizes + sizeof(*footer)) {
1564 adsp_err(dsp, "%s: unexpected header length %d\n",
1565 file, le32_to_cpu(header->len));
1566 goto out_fw;
1567 }
1568
1569 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1570 le64_to_cpu(footer->timestamp));
1571
1572 while (pos < firmware->size &&
1573 pos - firmware->size > sizeof(*region)) {
1574 region = (void *)&(firmware->data[pos]);
1575 region_name = "Unknown";
1576 reg = 0;
1577 text = NULL;
1578 offset = le32_to_cpu(region->offset) & 0xffffff;
1579 type = be32_to_cpu(region->type) & 0xff;
1580 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1581
2159ad93
MB		 1582 switch (type) {
1583 case WMFW_NAME_TEXT:
1584 region_name = "Firmware name";
1585 text = kzalloc(le32_to_cpu(region->len) + 1,
1586 GFP_KERNEL);
1587 break;
2323736d
CK		 1588 case WMFW_ALGORITHM_DATA:
1589 region_name = "Algorithm";
1590 ret = wm_adsp_parse_coeff(dsp, region);
1591 if (ret != 0)
1592 goto out_fw;
1593 break;
2159ad93
MB		 1594 case WMFW_INFO_TEXT:
1595 region_name = "Information";
1596 text = kzalloc(le32_to_cpu(region->len) + 1,
1597 GFP_KERNEL);
1598 break;
1599 case WMFW_ABSOLUTE:
1600 region_name = "Absolute";
1601 reg = offset;
1602 break;
1603 case WMFW_ADSP1_PM:
2159ad93 1604 region_name = "PM";
45b9ee72 1605 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1606 break;
1607 case WMFW_ADSP1_DM:
2159ad93 1608 region_name = "DM";
45b9ee72 1609 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1610 break;
1611 case WMFW_ADSP2_XM:
2159ad93 1612 region_name = "XM";
45b9ee72 1613 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1614 break;
1615 case WMFW_ADSP2_YM:
2159ad93 1616 region_name = "YM";
45b9ee72 1617 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1618 break;
1619 case WMFW_ADSP1_ZM:
2159ad93 1620 region_name = "ZM";
45b9ee72 1621 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1622 break;
1623 default:
1624 adsp_warn(dsp,
1625 "%s.%d: Unknown region type %x at %d(%x)\n",
1626 file, regions, type, pos, pos);
1627 break;
1628 }
1629
1630 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1631 regions, le32_to_cpu(region->len), offset,
1632 region_name);
1633
1634 if (text) {
1635 memcpy(text, region->data, le32_to_cpu(region->len));
1636 adsp_info(dsp, "%s: %s\n", file, text);
1637 kfree(text);
1638 }
1639
1640 if (reg) {
cdcd7f72
CK		 1641 buf = wm_adsp_buf_alloc(region->data,
1642 le32_to_cpu(region->len),
1643 &buf_list);
1644 if (!buf) {
1645 adsp_err(dsp, "Out of memory\n");
1646 ret = -ENOMEM;
1647 goto out_fw;
1648 }
c1a7898d 1649
cdcd7f72
CK		 1650 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1651 le32_to_cpu(region->len));
1652 if (ret != 0) {
1653 adsp_err(dsp,
1654 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1655 file, regions,
1656 le32_to_cpu(region->len), offset,
1657 region_name, ret);
1658 goto out_fw;
2159ad93
MB		 1659 }
1660 }
1661
1662 pos += le32_to_cpu(region->len) + sizeof(*region);
1663 regions++;
1664 }
cf17c83c
MB		 1665
1666 ret = regmap_async_complete(regmap);
1667 if (ret != 0) {
1668 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1669 goto out_fw;
1670 }
1671
2159ad93
MB		 1672 if (pos > firmware->size)
1673 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1674 file, regions, pos - firmware->size);
1675
f9f55e31
RF		 1676 wm_adsp_debugfs_save_wmfwname(dsp, file);
1677
2159ad93 1678out_fw:
cf17c83c
MB		 1679 regmap_async_complete(regmap);
1680 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1681 release_firmware(firmware);
1682out:
1683 kfree(file);
1684
1685 return ret;
1686}
1687
2323736d
CK		 1688static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1689 const struct wm_adsp_alg_region *alg_region)
1690{
1691 struct wm_coeff_ctl *ctl;
1692
1693 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1694 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1695 alg_region->alg == ctl->alg_region.alg &&
1696 alg_region->type == ctl->alg_region.type) {
1697 ctl->alg_region.base = alg_region->base;
1698 }
1699 }
1700}
1701
3809f001 1702static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1703 unsigned int pos, unsigned int len)
db40517c 1704{
b618a185
CK		 1705 void *alg;
1706 int ret;
db40517c 1707 __be32 val;
db40517c 1708
3809f001 1709 if (n_algs == 0) {
b618a185
CK		 1710 adsp_err(dsp, "No algorithms\n");
1711 return ERR_PTR(-EINVAL);
db40517c
MB		 1712 }
1713
3809f001
CK		 1714 if (n_algs > 1024) {
1715 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1716 return ERR_PTR(-EINVAL);
1717 }
db40517c 1718
b618a185
CK		 1719 /* Read the terminator first to validate the length */
1720 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1721 if (ret != 0) {
1722 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1723 ret);
1724 return ERR_PTR(ret);
1725 }
db40517c 1726
b618a185
CK		 1727 if (be32_to_cpu(val) != 0xbedead)
1728 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1729 pos + len, be32_to_cpu(val));
d62f4bc6 1730
b618a185
CK		 1731 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1732 if (!alg)
1733 return ERR_PTR(-ENOMEM);
db40517c 1734
b618a185
CK		 1735 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1736 if (ret != 0) {
7d00cd97 1737 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
b618a185
CK		 1738 kfree(alg);
1739 return ERR_PTR(ret);
1740 }
ac50009f 1741
b618a185
CK		 1742 return alg;
1743}
ac50009f 1744
14197095
CK		 1745static struct wm_adsp_alg_region *
1746 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1747{
1748 struct wm_adsp_alg_region *alg_region;
1749
1750 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1751 if (id == alg_region->alg && type == alg_region->type)
1752 return alg_region;
1753 }
1754
1755 return NULL;
1756}
1757
d9d20e17
CK		 1758static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1759 int type, __be32 id,
1760 __be32 base)
1761{
1762 struct wm_adsp_alg_region *alg_region;
1763
1764 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1765 if (!alg_region)
1766 return ERR_PTR(-ENOMEM);
1767
1768 alg_region->type = type;
1769 alg_region->alg = be32_to_cpu(id);
1770 alg_region->base = be32_to_cpu(base);
1771
1772 list_add_tail(&alg_region->list, &dsp->alg_regions);
1773
2323736d
CK		 1774 if (dsp->fw_ver > 0)
1775 wm_adsp_ctl_fixup_base(dsp, alg_region);
1776
d9d20e17
CK		 1777 return alg_region;
1778}
1779
56574d54
RF		 1780static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1781{
1782 struct wm_adsp_alg_region *alg_region;
1783
1784 while (!list_empty(&dsp->alg_regions)) {
1785 alg_region = list_first_entry(&dsp->alg_regions,
1786 struct wm_adsp_alg_region,
1787 list);
1788 list_del(&alg_region->list);
1789 kfree(alg_region);
1790 }
1791}
1792
b618a185
CK		 1793static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1794{
1795 struct wmfw_adsp1_id_hdr adsp1_id;
1796 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1797 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1798 const struct wm_adsp_region *mem;
1799 unsigned int pos, len;
3809f001 1800 size_t n_algs;
b618a185 1801 int i, ret;
db40517c 1802
b618a185
CK		 1803 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1804 if (WARN_ON(!mem))
1805 return -EINVAL;
1806
1807 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1808 sizeof(adsp1_id));
1809 if (ret != 0) {
1810 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1811 ret);
1812 return ret;
1813 }
db40517c 1814
3809f001 1815 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1816 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1817 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1818 dsp->fw_id,
1819 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1820 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1821 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1822 n_algs);
b618a185 1823
d9d20e17
CK		 1824 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1825 adsp1_id.fw.id, adsp1_id.zm);
1826 if (IS_ERR(alg_region))
1827 return PTR_ERR(alg_region);
d62f4bc6 1828
d9d20e17
CK		 1829 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1830 adsp1_id.fw.id, adsp1_id.dm);
1831 if (IS_ERR(alg_region))
1832 return PTR_ERR(alg_region);
db40517c 1833
b618a185 1834 pos = sizeof(adsp1_id) / 2;
3809f001 1835 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1836
3809f001 1837 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1838 if (IS_ERR(adsp1_alg))
1839 return PTR_ERR(adsp1_alg);
1840
3809f001 1841 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1842 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1843 i, be32_to_cpu(adsp1_alg[i].alg.id),
1844 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1845 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1846 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1847 be32_to_cpu(adsp1_alg[i].dm),
1848 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1849
d9d20e17
CK		 1850 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1851 adsp1_alg[i].alg.id,
1852 adsp1_alg[i].dm);
1853 if (IS_ERR(alg_region)) {
1854 ret = PTR_ERR(alg_region);
b618a185
CK		 1855 goto out;
1856 }
2323736d
CK		 1857 if (dsp->fw_ver == 0) {
1858 if (i + 1 < n_algs) {
1859 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1860 len -= be32_to_cpu(adsp1_alg[i].dm);
1861 len *= 4;
1862 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1863 len, NULL, 0, 0);
2323736d
CK		 1864 } else {
1865 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1866 be32_to_cpu(adsp1_alg[i].alg.id));
1867 }
b618a185 1868 }
ac50009f 1869
d9d20e17
CK		 1870 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1871 adsp1_alg[i].alg.id,
1872 adsp1_alg[i].zm);
1873 if (IS_ERR(alg_region)) {
1874 ret = PTR_ERR(alg_region);
b618a185
CK		 1875 goto out;
1876 }
2323736d
CK		 1877 if (dsp->fw_ver == 0) {
1878 if (i + 1 < n_algs) {
1879 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1880 len -= be32_to_cpu(adsp1_alg[i].zm);
1881 len *= 4;
1882 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1883 len, NULL, 0, 0);
2323736d
CK		 1884 } else {
1885 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1886 be32_to_cpu(adsp1_alg[i].alg.id));
1887 }
b618a185 1888 }
db40517c
MB		 1889 }
1890
b618a185
CK		 1891out:
1892 kfree(adsp1_alg);
1893 return ret;
1894}
db40517c 1895
b618a185
CK		 1896static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1897{
1898 struct wmfw_adsp2_id_hdr adsp2_id;
1899 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1900 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1901 const struct wm_adsp_region *mem;
1902 unsigned int pos, len;
3809f001 1903 size_t n_algs;
b618a185
CK		 1904 int i, ret;
1905
1906 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1907 if (WARN_ON(!mem))
d62f4bc6 1908 return -EINVAL;
d62f4bc6 1909
b618a185
CK		 1910 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1911 sizeof(adsp2_id));
db40517c 1912 if (ret != 0) {
b618a185
CK		 1913 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1914 ret);
db40517c
MB		 1915 return ret;
1916 }
1917
3809f001 1918 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1919 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1920 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1921 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1922 dsp->fw_id,
f9f55e31
RF		 1923 (dsp->fw_id_version & 0xff0000) >> 16,
1924 (dsp->fw_id_version & 0xff00) >> 8,
1925 dsp->fw_id_version & 0xff,
3809f001 1926 n_algs);
b618a185 1927
d9d20e17
CK		 1928 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1929 adsp2_id.fw.id, adsp2_id.xm);
1930 if (IS_ERR(alg_region))
1931 return PTR_ERR(alg_region);
db40517c 1932
d9d20e17
CK		 1933 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1934 adsp2_id.fw.id, adsp2_id.ym);
1935 if (IS_ERR(alg_region))
1936 return PTR_ERR(alg_region);
db40517c 1937
d9d20e17
CK		 1938 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1939 adsp2_id.fw.id, adsp2_id.zm);
1940 if (IS_ERR(alg_region))
1941 return PTR_ERR(alg_region);
db40517c 1942
b618a185 1943 pos = sizeof(adsp2_id) / 2;
3809f001 1944 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1945
3809f001 1946 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1947 if (IS_ERR(adsp2_alg))
1948 return PTR_ERR(adsp2_alg);
471f4885 1949
3809f001 1950 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1951 adsp_info(dsp,
1952 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1953 i, be32_to_cpu(adsp2_alg[i].alg.id),
1954 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1955 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1956 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1957 be32_to_cpu(adsp2_alg[i].xm),
1958 be32_to_cpu(adsp2_alg[i].ym),
1959 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1960
d9d20e17
CK		 1961 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1962 adsp2_alg[i].alg.id,
1963 adsp2_alg[i].xm);
1964 if (IS_ERR(alg_region)) {
1965 ret = PTR_ERR(alg_region);
b618a185
CK		 1966 goto out;
1967 }
2323736d
CK		 1968 if (dsp->fw_ver == 0) {
1969 if (i + 1 < n_algs) {
1970 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1971 len -= be32_to_cpu(adsp2_alg[i].xm);
1972 len *= 4;
1973 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1974 len, NULL, 0, 0);
2323736d
CK		 1975 } else {
1976 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1977 be32_to_cpu(adsp2_alg[i].alg.id));
1978 }
b618a185 1979 }
471f4885 1980
d9d20e17
CK		 1981 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1982 adsp2_alg[i].alg.id,
1983 adsp2_alg[i].ym);
1984 if (IS_ERR(alg_region)) {
1985 ret = PTR_ERR(alg_region);
b618a185
CK		 1986 goto out;
1987 }
2323736d
CK		 1988 if (dsp->fw_ver == 0) {
1989 if (i + 1 < n_algs) {
1990 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1991 len -= be32_to_cpu(adsp2_alg[i].ym);
1992 len *= 4;
1993 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1994 len, NULL, 0, 0);
2323736d
CK		 1995 } else {
1996 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1997 be32_to_cpu(adsp2_alg[i].alg.id));
1998 }
b618a185 1999 }
471f4885 2000
d9d20e17
CK		 2001 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2002 adsp2_alg[i].alg.id,
2003 adsp2_alg[i].zm);
2004 if (IS_ERR(alg_region)) {
2005 ret = PTR_ERR(alg_region);
b618a185
CK		 2006 goto out;
2007 }
2323736d
CK		 2008 if (dsp->fw_ver == 0) {
2009 if (i + 1 < n_algs) {
2010 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2011 len -= be32_to_cpu(adsp2_alg[i].zm);
2012 len *= 4;
2013 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 2014 len, NULL, 0, 0);
2323736d
CK		 2015 } else {
2016 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2017 be32_to_cpu(adsp2_alg[i].alg.id));
2018 }
db40517c
MB		 2019 }
2020 }
2021
2022out:
b618a185 2023 kfree(adsp2_alg);
db40517c
MB		 2024 return ret;
2025}
2026
2159ad93
MB		 2027static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2028{
cf17c83c 2029 LIST_HEAD(buf_list);
2159ad93
MB		 2030 struct regmap *regmap = dsp->regmap;
2031 struct wmfw_coeff_hdr *hdr;
2032 struct wmfw_coeff_item *blk;
2033 const struct firmware *firmware;
471f4885
MB		 2034 const struct wm_adsp_region *mem;
2035 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 2036 const char *region_name;
2037 int ret, pos, blocks, type, offset, reg;
2038 char *file;
cf17c83c 2039 struct wm_adsp_buf *buf;
2159ad93
MB		 2040
2041 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2042 if (file == NULL)
2043 return -ENOMEM;
2044
1023dbd9
MB		 2045 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
2046 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 2047 file[PAGE_SIZE - 1] = '\0';
2048
2049 ret = request_firmware(&firmware, file, dsp->dev);
2050 if (ret != 0) {
2051 adsp_warn(dsp, "Failed to request '%s'\n", file);
2052 ret = 0;
2053 goto out;
2054 }
2055 ret = -EINVAL;
2056
2057 if (sizeof(*hdr) >= firmware->size) {
2058 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2059 file, firmware->size);
2060 goto out_fw;
2061 }
2062
7585a5b0 2063 hdr = (void *)&firmware->data[0];
2159ad93
MB		 2064 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2065 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 2066 goto out_fw;
2159ad93
MB		 2067 }
2068
c712326d
MB		 2069 switch (be32_to_cpu(hdr->rev) & 0xff) {
2070 case 1:
2071 break;
2072 default:
2073 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2074 file, be32_to_cpu(hdr->rev) & 0xff);
2075 ret = -EINVAL;
2076 goto out_fw;
2077 }
2078
2159ad93
MB		 2079 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2080 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2081 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2082 le32_to_cpu(hdr->ver) & 0xff);
2083
2084 pos = le32_to_cpu(hdr->len);
2085
2086 blocks = 0;
2087 while (pos < firmware->size &&
2088 pos - firmware->size > sizeof(*blk)) {
7585a5b0 2089 blk = (void *)(&firmware->data[pos]);
2159ad93 2090
c712326d
MB		 2091 type = le16_to_cpu(blk->type);
2092 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 2093
2094 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2095 file, blocks, le32_to_cpu(blk->id),
2096 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2097 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2098 le32_to_cpu(blk->ver) & 0xff);
2099 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2100 file, blocks, le32_to_cpu(blk->len), offset, type);
2101
2102 reg = 0;
2103 region_name = "Unknown";
2104 switch (type) {
c712326d
MB		 2105 case (WMFW_NAME_TEXT << 8):
2106 case (WMFW_INFO_TEXT << 8):
2159ad93 2107 break;
c712326d 2108 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 2109 /*
2110 * Old files may use this for global
2111 * coefficients.
2112 */
2113 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2114 offset == 0) {
2115 region_name = "global coefficients";
2116 mem = wm_adsp_find_region(dsp, type);
2117 if (!mem) {
2118 adsp_err(dsp, "No ZM\n");
2119 break;
2120 }
2121 reg = wm_adsp_region_to_reg(mem, 0);
2122
2123 } else {
2124 region_name = "register";
2125 reg = offset;
2126 }
2159ad93 2127 break;
471f4885
MB		 2128
2129 case WMFW_ADSP1_DM:
2130 case WMFW_ADSP1_ZM:
2131 case WMFW_ADSP2_XM:
2132 case WMFW_ADSP2_YM:
2133 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2134 file, blocks, le32_to_cpu(blk->len),
2135 type, le32_to_cpu(blk->id));
2136
2137 mem = wm_adsp_find_region(dsp, type);
2138 if (!mem) {
2139 adsp_err(dsp, "No base for region %x\n", type);
2140 break;
2141 }
2142
14197095
CK		 2143 alg_region = wm_adsp_find_alg_region(dsp, type,
2144 le32_to_cpu(blk->id));
2145 if (alg_region) {
2146 reg = alg_region->base;
2147 reg = wm_adsp_region_to_reg(mem, reg);
2148 reg += offset;
2149 } else {
471f4885
MB		 2150 adsp_err(dsp, "No %x for algorithm %x\n",
2151 type, le32_to_cpu(blk->id));
14197095 2152 }
471f4885
MB		 2153 break;
2154
2159ad93 2155 default:
25c62f7e
MB		 2156 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2157 file, blocks, type, pos);
2159ad93
MB		 2158 break;
2159 }
2160
2161 if (reg) {
cf17c83c
MB		 2162 buf = wm_adsp_buf_alloc(blk->data,
2163 le32_to_cpu(blk->len),
2164 &buf_list);
a76fefab
MB		 2165 if (!buf) {
2166 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 2167 ret = -ENOMEM;
2168 goto out_fw;
a76fefab
MB		 2169 }
2170
20da6d5a
MB		 2171 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2172 file, blocks, le32_to_cpu(blk->len),
2173 reg);
cf17c83c
MB		 2174 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2175 le32_to_cpu(blk->len));
2159ad93
MB		 2176 if (ret != 0) {
2177 adsp_err(dsp,
43bc3bf6
DP		 2178 "%s.%d: Failed to write to %x in %s: %d\n",
2179 file, blocks, reg, region_name, ret);
2159ad93
MB		 2180 }
2181 }
2182
be951017 2183 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 2184 blocks++;
2185 }
2186
cf17c83c
MB		 2187 ret = regmap_async_complete(regmap);
2188 if (ret != 0)
2189 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2190
2159ad93
MB		 2191 if (pos > firmware->size)
2192 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2193 file, blocks, pos - firmware->size);
2194
f9f55e31
RF		 2195 wm_adsp_debugfs_save_binname(dsp, file);
2196
2159ad93 2197out_fw:
9da7a5a9 2198 regmap_async_complete(regmap);
2159ad93 2199 release_firmware(firmware);
cf17c83c 2200 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 2201out:
2202 kfree(file);
f4b82812 2203 return ret;
2159ad93
MB		 2204}
2205
3809f001 2206int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 2207{
3809f001 2208 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 2209
078e7183
CK		 2210 mutex_init(&dsp->pwr_lock);
2211
5e7a7a22
MB		 2212 return 0;
2213}
2214EXPORT_SYMBOL_GPL(wm_adsp1_init);
2215
2159ad93
MB		 2216int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2217 struct snd_kcontrol *kcontrol,
2218 int event)
2219{
72718517 2220 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 2221 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2222 struct wm_adsp *dsp = &dsps[w->shift];
6ab2b7b4 2223 struct wm_coeff_ctl *ctl;
2159ad93 2224 int ret;
7585a5b0 2225 unsigned int val;
2159ad93 2226
00200107 2227 dsp->card = codec->component.card;
92bb4c32 2228
078e7183
CK		 2229 mutex_lock(&dsp->pwr_lock);
2230
2159ad93
MB		 2231 switch (event) {
2232 case SND_SOC_DAPM_POST_PMU:
2233 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2234 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2235
94e205bf
CR		 2236 /*
2237 * For simplicity set the DSP clock rate to be the
2238 * SYSCLK rate rather than making it configurable.
2239 */
7585a5b0 2240 if (dsp->sysclk_reg) {
94e205bf
CR		 2241 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2242 if (ret != 0) {
2243 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2244 ret);
078e7183 2245 goto err_mutex;
94e205bf
CR		 2246 }
2247
7d00cd97 2248 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
94e205bf
CR		 2249
2250 ret = regmap_update_bits(dsp->regmap,
2251 dsp->base + ADSP1_CONTROL_31,
2252 ADSP1_CLK_SEL_MASK, val);
2253 if (ret != 0) {
2254 adsp_err(dsp, "Failed to set clock rate: %d\n",
2255 ret);
078e7183 2256 goto err_mutex;
94e205bf
CR		 2257 }
2258 }
2259
2159ad93
MB		 2260 ret = wm_adsp_load(dsp);
2261 if (ret != 0)
078e7183 2262 goto err_ena;
2159ad93 2263
b618a185 2264 ret = wm_adsp1_setup_algs(dsp);
db40517c 2265 if (ret != 0)
078e7183 2266 goto err_ena;
db40517c 2267
2159ad93
MB		 2268 ret = wm_adsp_load_coeff(dsp);
2269 if (ret != 0)
078e7183 2270 goto err_ena;
2159ad93 2271
0c2e3f34 2272 /* Initialize caches for enabled and unset controls */
81ad93ec 2273 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2274 if (ret != 0)
078e7183 2275 goto err_ena;
6ab2b7b4 2276
0c2e3f34 2277 /* Sync set controls */
81ad93ec 2278 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2279 if (ret != 0)
078e7183 2280 goto err_ena;
6ab2b7b4 2281
28823eba
CK		 2282 dsp->booted = true;
2283
2159ad93
MB		 2284 /* Start the core running */
2285 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2286 ADSP1_CORE_ENA | ADSP1_START,
2287 ADSP1_CORE_ENA | ADSP1_START);
28823eba
CK		 2288
2289 dsp->running = true;
2159ad93
MB		 2290 break;
2291
2292 case SND_SOC_DAPM_PRE_PMD:
28823eba
CK		 2293 dsp->running = false;
2294 dsp->booted = false;
2295
2159ad93
MB		 2296 /* Halt the core */
2297 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2298 ADSP1_CORE_ENA | ADSP1_START, 0);
2299
2300 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2301 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2302
2303 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2304 ADSP1_SYS_ENA, 0);
6ab2b7b4 2305
81ad93ec 2306 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2307 ctl->enabled = 0;
b0101b4f 2308
56574d54
RF		 2309
2310 wm_adsp_free_alg_regions(dsp);
2159ad93
MB		 2311 break;
2312
2313 default:
2314 break;
2315 }
2316
078e7183
CK		 2317 mutex_unlock(&dsp->pwr_lock);
2318
2159ad93
MB		 2319 return 0;
2320
078e7183 2321err_ena:
2159ad93
MB		 2322 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2323 ADSP1_SYS_ENA, 0);
078e7183
CK		 2324err_mutex:
2325 mutex_unlock(&dsp->pwr_lock);
2326
2159ad93
MB		 2327 return ret;
2328}
2329EXPORT_SYMBOL_GPL(wm_adsp1_event);
2330
2331static int wm_adsp2_ena(struct wm_adsp *dsp)
2332{
2333 unsigned int val;
2334 int ret, count;
2335
1552c325
MB		 2336 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2337 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 2338 if (ret != 0)
2339 return ret;
2340
2341 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2342 for (count = 0; count < 10; ++count) {
7d00cd97 2343 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2159ad93
MB		 2344 if (ret != 0)
2345 return ret;
939fd1e8
CK		 2346
2347 if (val & ADSP2_RAM_RDY)
2348 break;
2349
1fa96f3f 2350 usleep_range(250, 500);
939fd1e8 2351 }
2159ad93
MB		 2352
2353 if (!(val & ADSP2_RAM_RDY)) {
2354 adsp_err(dsp, "Failed to start DSP RAM\n");
2355 return -EBUSY;
2356 }
2357
2358 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2359
2360 return 0;
2361}
2362
18b1a902 2363static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2364{
d8a64d6a
CK		 2365 struct wm_adsp *dsp = container_of(work,
2366 struct wm_adsp,
2367 boot_work);
2159ad93
MB		 2368 int ret;
2369
078e7183
CK		 2370 mutex_lock(&dsp->pwr_lock);
2371
90d19ba5
CK		 2372 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2373 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2374 if (ret != 0)
2375 goto err_mutex;
2376
d8a64d6a
CK		 2377 ret = wm_adsp2_ena(dsp);
2378 if (ret != 0)
078e7183 2379 goto err_mutex;
2159ad93 2380
d8a64d6a
CK		 2381 ret = wm_adsp_load(dsp);
2382 if (ret != 0)
078e7183 2383 goto err_ena;
2159ad93 2384
b618a185 2385 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2386 if (ret != 0)
078e7183 2387 goto err_ena;
db40517c 2388
d8a64d6a
CK		 2389 ret = wm_adsp_load_coeff(dsp);
2390 if (ret != 0)
078e7183 2391 goto err_ena;
2159ad93 2392
d8a64d6a
CK		 2393 /* Initialize caches for enabled and unset controls */
2394 ret = wm_coeff_init_control_caches(dsp);
2395 if (ret != 0)
078e7183 2396 goto err_ena;
6ab2b7b4 2397
28823eba 2398 dsp->booted = true;
d8a64d6a 2399
90d19ba5
CK		 2400 /* Turn DSP back off until we are ready to run */
2401 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2402 ADSP2_SYS_ENA, 0);
2403 if (ret != 0)
2404 goto err_ena;
2405
078e7183
CK		 2406 mutex_unlock(&dsp->pwr_lock);
2407
d8a64d6a 2408 return;
6ab2b7b4 2409
078e7183 2410err_ena:
d8a64d6a
CK		 2411 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2412 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2413err_mutex:
2414 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2415}
2416
d82d767f
CK		 2417static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2418{
2419 int ret;
2420
2421 ret = regmap_update_bits_async(dsp->regmap,
2422 dsp->base + ADSP2_CLOCKING,
2423 ADSP2_CLK_SEL_MASK,
2424 freq << ADSP2_CLK_SEL_SHIFT);
2425 if (ret != 0)
2426 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2427}
2428
12db5edd 2429int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
d82d767f
CK		 2430 struct snd_kcontrol *kcontrol, int event,
2431 unsigned int freq)
12db5edd 2432{
72718517 2433 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2434 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2435 struct wm_adsp *dsp = &dsps[w->shift];
57a60cc3 2436 struct wm_coeff_ctl *ctl;
12db5edd 2437
00200107 2438 dsp->card = codec->component.card;
12db5edd
CK		 2439
2440 switch (event) {
2441 case SND_SOC_DAPM_PRE_PMU:
d82d767f 2442 wm_adsp2_set_dspclk(dsp, freq);
12db5edd
CK		 2443 queue_work(system_unbound_wq, &dsp->boot_work);
2444 break;
57a60cc3
CK		 2445 case SND_SOC_DAPM_PRE_PMD:
2446 wm_adsp_debugfs_clear(dsp);
2447
2448 dsp->fw_id = 0;
2449 dsp->fw_id_version = 0;
2450
2451 dsp->booted = false;
2452
2453 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2454 ADSP2_MEM_ENA, 0);
2455
2456 list_for_each_entry(ctl, &dsp->ctl_list, list)
2457 ctl->enabled = 0;
2458
2459 wm_adsp_free_alg_regions(dsp);
2460
2461 adsp_dbg(dsp, "Shutdown complete\n");
2462 break;
12db5edd
CK		 2463 default:
2464 break;
cab27258 2465 }
12db5edd
CK		 2466
2467 return 0;
2468}
2469EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2470
d8a64d6a
CK		 2471int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2472 struct snd_kcontrol *kcontrol, int event)
2473{
72718517 2474 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2475 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2476 struct wm_adsp *dsp = &dsps[w->shift];
d8a64d6a
CK		 2477 int ret;
2478
d8a64d6a
CK		 2479 switch (event) {
2480 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2481 flush_work(&dsp->boot_work);
2482
28823eba 2483 if (!dsp->booted)
d8a64d6a 2484 return -EIO;
6ab2b7b4 2485
90d19ba5
CK		 2486 ret = wm_adsp2_ena(dsp);
2487 if (ret != 0)
2488 goto err;
2489
cef45771
CK		 2490 /* Sync set controls */
2491 ret = wm_coeff_sync_controls(dsp);
2492 if (ret != 0)
2493 goto err;
2494
d8a64d6a
CK		 2495 ret = regmap_update_bits(dsp->regmap,
2496 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2497 ADSP2_CORE_ENA | ADSP2_START,
2498 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2499 if (ret != 0)
2500 goto err;
2cd19bdb 2501
28823eba
CK		 2502 dsp->running = true;
2503
612047f0
CK		 2504 mutex_lock(&dsp->pwr_lock);
2505
2cd19bdb
CK		 2506 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2507 ret = wm_adsp_buffer_init(dsp);
2508
612047f0
CK		 2509 mutex_unlock(&dsp->pwr_lock);
2510
2159ad93
MB		 2511 break;
2512
2513 case SND_SOC_DAPM_PRE_PMD:
f4f0c4c6
RF		 2514 /* Tell the firmware to cleanup */
2515 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2516
10337b07
RF		 2517 /* Log firmware state, it can be useful for analysis */
2518 wm_adsp2_show_fw_status(dsp);
2519
078e7183
CK		 2520 mutex_lock(&dsp->pwr_lock);
2521
1023dbd9
MB		 2522 dsp->running = false;
2523
2159ad93 2524 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
57a60cc3 2525 ADSP2_CORE_ENA | ADSP2_START, 0);
973838a0 2526
2d30b575 2527 /* Make sure DMAs are quiesced */
6facd2d1 2528 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2d30b575
MB		 2529 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2530 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
6facd2d1
ST		 2531
2532 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2533 ADSP2_SYS_ENA, 0);
2d30b575 2534
2cd19bdb
CK		 2535 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2536 wm_adsp_buffer_free(dsp);
2537
078e7183
CK		 2538 mutex_unlock(&dsp->pwr_lock);
2539
57a60cc3 2540 adsp_dbg(dsp, "Execution stopped\n");
2159ad93
MB		 2541 break;
2542
2543 default:
2544 break;
2545 }
2546
2547 return 0;
2548err:
2549 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2550 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2551 return ret;
2552}
2553EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2554
f5e2ce92
RF		 2555int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2556{
f9f55e31
RF		 2557 wm_adsp2_init_debugfs(dsp, codec);
2558
218e5087 2559 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2560 &wm_adsp_fw_controls[dsp->num - 1],
2561 1);
f5e2ce92
RF		 2562}
2563EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2564
2565int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2566{
f9f55e31
RF		 2567 wm_adsp2_cleanup_debugfs(dsp);
2568
f5e2ce92
RF		 2569 return 0;
2570}
2571EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2572
81ac58b1 2573int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2574{
2575 int ret;
2576
10a2b662
MB		 2577 /*
2578 * Disable the DSP memory by default when in reset for a small
2579 * power saving.
2580 */
3809f001 2581 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2582 ADSP2_MEM_ENA, 0);
2583 if (ret != 0) {
3809f001 2584 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2585 return ret;
2586 }
2587
3809f001
CK		 2588 INIT_LIST_HEAD(&dsp->alg_regions);
2589 INIT_LIST_HEAD(&dsp->ctl_list);
2590 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2591
078e7183
CK		 2592 mutex_init(&dsp->pwr_lock);
2593
973838a0
MB		 2594 return 0;
2595}
2596EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2597
66225e98
RF		 2598void wm_adsp2_remove(struct wm_adsp *dsp)
2599{
2600 struct wm_coeff_ctl *ctl;
2601
2602 while (!list_empty(&dsp->ctl_list)) {
2603 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2604 list);
2605 list_del(&ctl->list);
2606 wm_adsp_free_ctl_blk(ctl);
2607 }
2608}
2609EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2610
edd71350
CK		 2611static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2612{
2613 return compr->buf != NULL;
2614}
2615
2616static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2617{
2618 /*
2619 * Note this will be more complex once each DSP can support multiple
2620 * streams
2621 */
2622 if (!compr->dsp->buffer)
2623 return -EINVAL;
2624
2625 compr->buf = compr->dsp->buffer;
721be3be 2626 compr->buf->compr = compr;
edd71350
CK		 2627
2628 return 0;
2629}
2630
721be3be
CK		 2631static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
2632{
2633 if (!compr)
2634 return;
2635
2636 /* Wake the poll so it can see buffer is no longer attached */
2637 if (compr->stream)
2638 snd_compr_fragment_elapsed(compr->stream);
2639
2640 if (wm_adsp_compr_attached(compr)) {
2641 compr->buf->compr = NULL;
2642 compr->buf = NULL;
2643 }
2644}
2645
406abc95
CK		 2646int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2647{
2648 struct wm_adsp_compr *compr;
2649 int ret = 0;
2650
2651 mutex_lock(&dsp->pwr_lock);
2652
2653 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2654 adsp_err(dsp, "Firmware does not support compressed API\n");
2655 ret = -ENXIO;
2656 goto out;
2657 }
2658
2659 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2660 adsp_err(dsp, "Firmware does not support stream direction\n");
2661 ret = -EINVAL;
2662 goto out;
2663 }
2664
95fe9597
CK		 2665 if (dsp->compr) {
2666 /* It is expect this limitation will be removed in future */
2667 adsp_err(dsp, "Only a single stream supported per DSP\n");
2668 ret = -EBUSY;
2669 goto out;
2670 }
2671
406abc95
CK		 2672 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2673 if (!compr) {
2674 ret = -ENOMEM;
2675 goto out;
2676 }
2677
2678 compr->dsp = dsp;
2679 compr->stream = stream;
2680
2681 dsp->compr = compr;
2682
2683 stream->runtime->private_data = compr;
2684
2685out:
2686 mutex_unlock(&dsp->pwr_lock);
2687
2688 return ret;
2689}
2690EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2691
2692int wm_adsp_compr_free(struct snd_compr_stream *stream)
2693{
2694 struct wm_adsp_compr *compr = stream->runtime->private_data;
2695 struct wm_adsp *dsp = compr->dsp;
2696
2697 mutex_lock(&dsp->pwr_lock);
2698
721be3be 2699 wm_adsp_compr_detach(compr);
406abc95
CK		 2700 dsp->compr = NULL;
2701
83a40ce9 2702 kfree(compr->raw_buf);
406abc95
CK		 2703 kfree(compr);
2704
2705 mutex_unlock(&dsp->pwr_lock);
2706
2707 return 0;
2708}
2709EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
2710
2711static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
2712 struct snd_compr_params *params)
2713{
2714 struct wm_adsp_compr *compr = stream->runtime->private_data;
2715 struct wm_adsp *dsp = compr->dsp;
2716 const struct wm_adsp_fw_caps *caps;
2717 const struct snd_codec_desc *desc;
2718 int i, j;
2719
2720 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
2721 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
2722 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
2723 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
2724 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
2725 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
2726 params->buffer.fragment_size,
2727 params->buffer.fragments);
2728
2729 return -EINVAL;
2730 }
2731
2732 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
2733 caps = &wm_adsp_fw[dsp->fw].caps[i];
2734 desc = &caps->desc;
2735
2736 if (caps->id != params->codec.id)
2737 continue;
2738
2739 if (stream->direction == SND_COMPRESS_PLAYBACK) {
2740 if (desc->max_ch < params->codec.ch_out)
2741 continue;
2742 } else {
2743 if (desc->max_ch < params->codec.ch_in)
2744 continue;
2745 }
2746
2747 if (!(desc->formats & (1 << params->codec.format)))
2748 continue;
2749
2750 for (j = 0; j < desc->num_sample_rates; ++j)
2751 if (desc->sample_rates[j] == params->codec.sample_rate)
2752 return 0;
2753 }
2754
2755 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
2756 params->codec.id, params->codec.ch_in, params->codec.ch_out,
2757 params->codec.sample_rate, params->codec.format);
2758 return -EINVAL;
2759}
2760
565ace46
CK		 2761static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
2762{
2763 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
2764}
2765
406abc95
CK		 2766int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
2767 struct snd_compr_params *params)
2768{
2769 struct wm_adsp_compr *compr = stream->runtime->private_data;
83a40ce9 2770 unsigned int size;
406abc95
CK		 2771 int ret;
2772
2773 ret = wm_adsp_compr_check_params(stream, params);
2774 if (ret)
2775 return ret;
2776
2777 compr->size = params->buffer;
2778
2779 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
2780 compr->size.fragment_size, compr->size.fragments);
2781
83a40ce9
CK		 2782 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
2783 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
2784 if (!compr->raw_buf)
2785 return -ENOMEM;
2786
da2b3358
CK		 2787 compr->sample_rate = params->codec.sample_rate;
2788
406abc95
CK		 2789 return 0;
2790}
2791EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
2792
2793int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
2794 struct snd_compr_caps *caps)
2795{
2796 struct wm_adsp_compr *compr = stream->runtime->private_data;
2797 int fw = compr->dsp->fw;
2798 int i;
2799
2800 if (wm_adsp_fw[fw].caps) {
2801 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
2802 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
2803
2804 caps->num_codecs = i;
2805 caps->direction = wm_adsp_fw[fw].compr_direction;
2806
2807 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
2808 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
2809 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
2810 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
2811 }
2812
2813 return 0;
2814}
2815EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
2816
2cd19bdb
CK		 2817static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
2818 unsigned int mem_addr,
2819 unsigned int num_words, u32 *data)
2820{
2821 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2822 unsigned int i, reg;
2823 int ret;
2824
2825 if (!mem)
2826 return -EINVAL;
2827
2828 reg = wm_adsp_region_to_reg(mem, mem_addr);
2829
2830 ret = regmap_raw_read(dsp->regmap, reg, data,
2831 sizeof(*data) * num_words);
2832 if (ret < 0)
2833 return ret;
2834
2835 for (i = 0; i < num_words; ++i)
2836 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
2837
2838 return 0;
2839}
2840
2841static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
2842 unsigned int mem_addr, u32 *data)
2843{
2844 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
2845}
2846
2847static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
2848 unsigned int mem_addr, u32 data)
2849{
2850 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2851 unsigned int reg;
2852
2853 if (!mem)
2854 return -EINVAL;
2855
2856 reg = wm_adsp_region_to_reg(mem, mem_addr);
2857
2858 data = cpu_to_be32(data & 0x00ffffffu);
2859
2860 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
2861}
2862
2863static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
2864 unsigned int field_offset, u32 *data)
2865{
2866 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
2867 buf->host_buf_ptr + field_offset, data);
2868}
2869
2870static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
2871 unsigned int field_offset, u32 data)
2872{
2873 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
2874 buf->host_buf_ptr + field_offset, data);
2875}
2876
2877static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
2878{
2879 struct wm_adsp_alg_region *alg_region;
2880 struct wm_adsp *dsp = buf->dsp;
2881 u32 xmalg, addr, magic;
2882 int i, ret;
2883
2884 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
2885 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
2886
2887 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
2888 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
2889 if (ret < 0)
2890 return ret;
2891
2892 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
2893 return -EINVAL;
2894
2895 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
2896 for (i = 0; i < 5; ++i) {
2897 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
2898 &buf->host_buf_ptr);
2899 if (ret < 0)
2900 return ret;
2901
2902 if (buf->host_buf_ptr)
2903 break;
2904
2905 usleep_range(1000, 2000);
2906 }
2907
2908 if (!buf->host_buf_ptr)
2909 return -EIO;
2910
2911 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
2912
2913 return 0;
2914}
2915
2916static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
2917{
2918 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
2919 struct wm_adsp_buffer_region *region;
2920 u32 offset = 0;
2921 int i, ret;
2922
2923 for (i = 0; i < caps->num_regions; ++i) {
2924 region = &buf->regions[i];
2925
2926 region->offset = offset;
2927 region->mem_type = caps->region_defs[i].mem_type;
2928
2929 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
2930 &region->base_addr);
2931 if (ret < 0)
2932 return ret;
2933
2934 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
2935 &offset);
2936 if (ret < 0)
2937 return ret;
2938
2939 region->cumulative_size = offset;
2940
2941 adsp_dbg(buf->dsp,
2942 "region=%d type=%d base=%04x off=%04x size=%04x\n",
2943 i, region->mem_type, region->base_addr,
2944 region->offset, region->cumulative_size);
2945 }
2946
2947 return 0;
2948}
2949
2950static int wm_adsp_buffer_init(struct wm_adsp *dsp)
2951{
2952 struct wm_adsp_compr_buf *buf;
2953 int ret;
2954
2955 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
2956 if (!buf)
2957 return -ENOMEM;
2958
2959 buf->dsp = dsp;
565ace46
CK		 2960 buf->read_index = -1;
2961 buf->irq_count = 0xFFFFFFFF;
2cd19bdb
CK		 2962
2963 ret = wm_adsp_buffer_locate(buf);
2964 if (ret < 0) {
2965 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
2966 goto err_buffer;
2967 }
2968
2969 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
2970 sizeof(*buf->regions), GFP_KERNEL);
2971 if (!buf->regions) {
2972 ret = -ENOMEM;
2973 goto err_buffer;
2974 }
2975
2976 ret = wm_adsp_buffer_populate(buf);
2977 if (ret < 0) {
2978 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
2979 goto err_regions;
2980 }
2981
2982 dsp->buffer = buf;
2983
2984 return 0;
2985
2986err_regions:
2987 kfree(buf->regions);
2988err_buffer:
2989 kfree(buf);
2990 return ret;
2991}
2992
2993static int wm_adsp_buffer_free(struct wm_adsp *dsp)
2994{
2995 if (dsp->buffer) {
721be3be
CK		 2996 wm_adsp_compr_detach(dsp->buffer->compr);
2997
2cd19bdb
CK		 2998 kfree(dsp->buffer->regions);
2999 kfree(dsp->buffer);
3000
3001 dsp->buffer = NULL;
3002 }
3003
3004 return 0;
3005}
3006
95fe9597
CK		 3007int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3008{
3009 struct wm_adsp_compr *compr = stream->runtime->private_data;
3010 struct wm_adsp *dsp = compr->dsp;
3011 int ret = 0;
3012
3013 adsp_dbg(dsp, "Trigger: %d\n", cmd);
3014
3015 mutex_lock(&dsp->pwr_lock);
3016
3017 switch (cmd) {
3018 case SNDRV_PCM_TRIGGER_START:
3019 if (wm_adsp_compr_attached(compr))
3020 break;
3021
3022 ret = wm_adsp_compr_attach(compr);
3023 if (ret < 0) {
3024 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
3025 ret);
3026 break;
3027 }
565ace46
CK		 3028
3029 /* Trigger the IRQ at one fragment of data */
3030 ret = wm_adsp_buffer_write(compr->buf,
3031 HOST_BUFFER_FIELD(high_water_mark),
3032 wm_adsp_compr_frag_words(compr));
3033 if (ret < 0) {
3034 adsp_err(dsp, "Failed to set high water mark: %d\n",
3035 ret);
3036 break;
3037 }
95fe9597
CK		 3038 break;
3039 case SNDRV_PCM_TRIGGER_STOP:
3040 break;
3041 default:
3042 ret = -EINVAL;
3043 break;
3044 }
3045
3046 mutex_unlock(&dsp->pwr_lock);
3047
3048 return ret;
3049}
3050EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3051
565ace46
CK		 3052static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3053{
3054 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3055
3056 return buf->regions[last_region].cumulative_size;
3057}
3058
3059static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3060{
3061 u32 next_read_index, next_write_index;
3062 int write_index, read_index, avail;
3063 int ret;
3064
3065 /* Only sync read index if we haven't already read a valid index */
3066 if (buf->read_index < 0) {
3067 ret = wm_adsp_buffer_read(buf,
3068 HOST_BUFFER_FIELD(next_read_index),
3069 &next_read_index);
3070 if (ret < 0)
3071 return ret;
3072
3073 read_index = sign_extend32(next_read_index, 23);
3074
3075 if (read_index < 0) {
3076 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
3077 return 0;
3078 }
3079
3080 buf->read_index = read_index;
3081 }
3082
3083 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3084 &next_write_index);
3085 if (ret < 0)
3086 return ret;
3087
3088 write_index = sign_extend32(next_write_index, 23);
3089
3090 avail = write_index - buf->read_index;
3091 if (avail < 0)
3092 avail += wm_adsp_buffer_size(buf);
3093
3094 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
33d740e0 3095 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
565ace46
CK		 3096
3097 buf->avail = avail;
3098
3099 return 0;
3100}
3101
9771b18a
CK		 3102static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3103{
3104 int ret;
3105
3106 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3107 if (ret < 0) {
3108 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3109 return ret;
3110 }
3111 if (buf->error != 0) {
3112 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3113 return -EIO;
3114 }
3115
3116 return 0;
3117}
3118
565ace46
CK		 3119int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3120{
612047f0
CK		 3121 struct wm_adsp_compr_buf *buf;
3122 struct wm_adsp_compr *compr;
565ace46
CK		 3123 int ret = 0;
3124
3125 mutex_lock(&dsp->pwr_lock);
3126
612047f0
CK		 3127 buf = dsp->buffer;
3128 compr = dsp->compr;
3129
565ace46 3130 if (!buf) {
565ace46
CK		 3131 ret = -ENODEV;
3132 goto out;
3133 }
3134
3135 adsp_dbg(dsp, "Handling buffer IRQ\n");
3136
9771b18a
CK		 3137 ret = wm_adsp_buffer_get_error(buf);
3138 if (ret < 0)
5847609e 3139 goto out_notify; /* Wake poll to report error */
565ace46
CK		 3140
3141 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3142 &buf->irq_count);
3143 if (ret < 0) {
3144 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
3145 goto out;
3146 }
3147
3148 ret = wm_adsp_buffer_update_avail(buf);
3149 if (ret < 0) {
3150 adsp_err(dsp, "Error reading avail: %d\n", ret);
3151 goto out;
3152 }
3153
20b7f7c5
CK		 3154 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3155 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3156
5847609e 3157out_notify:
c7dae7c4 3158 if (compr && compr->stream)
83a40ce9
CK		 3159 snd_compr_fragment_elapsed(compr->stream);
3160
565ace46
CK		 3161out:
3162 mutex_unlock(&dsp->pwr_lock);
3163
3164 return ret;
3165}
3166EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3167
3168static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3169{
3170 if (buf->irq_count & 0x01)
3171 return 0;
3172
3173 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
3174 buf->irq_count);
3175
3176 buf->irq_count |= 0x01;
3177
3178 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3179 buf->irq_count);
3180}
3181
3182int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3183 struct snd_compr_tstamp *tstamp)
3184{
3185 struct wm_adsp_compr *compr = stream->runtime->private_data;
565ace46 3186 struct wm_adsp *dsp = compr->dsp;
612047f0 3187 struct wm_adsp_compr_buf *buf;
565ace46
CK		 3188 int ret = 0;
3189
3190 adsp_dbg(dsp, "Pointer request\n");
3191
3192 mutex_lock(&dsp->pwr_lock);
3193
612047f0
CK		 3194 buf = compr->buf;
3195
28ee3d73 3196 if (!compr->buf || compr->buf->error) {
8d280664 3197 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
565ace46
CK		 3198 ret = -EIO;
3199 goto out;
3200 }
3201
3202 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3203 ret = wm_adsp_buffer_update_avail(buf);
3204 if (ret < 0) {
3205 adsp_err(dsp, "Error reading avail: %d\n", ret);
3206 goto out;
3207 }
3208
3209 /*
3210 * If we really have less than 1 fragment available tell the
3211 * DSP to inform us once a whole fragment is available.
3212 */
3213 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
5847609e 3214 ret = wm_adsp_buffer_get_error(buf);
8d280664
CK		 3215 if (ret < 0) {
3216 if (compr->buf->error)
3217 snd_compr_stop_error(stream,
3218 SNDRV_PCM_STATE_XRUN);
5847609e 3219 goto out;
8d280664 3220 }
5847609e 3221
565ace46
CK		 3222 ret = wm_adsp_buffer_reenable_irq(buf);
3223 if (ret < 0) {
3224 adsp_err(dsp,
3225 "Failed to re-enable buffer IRQ: %d\n",
3226 ret);
3227 goto out;
3228 }
3229 }
3230 }
3231
3232 tstamp->copied_total = compr->copied_total;
3233 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
da2b3358 3234 tstamp->sampling_rate = compr->sample_rate;
565ace46
CK		 3235
3236out:
3237 mutex_unlock(&dsp->pwr_lock);
3238
3239 return ret;
3240}
3241EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3242
83a40ce9
CK		 3243static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3244{
3245 struct wm_adsp_compr_buf *buf = compr->buf;
3246 u8 *pack_in = (u8 *)compr->raw_buf;
3247 u8 *pack_out = (u8 *)compr->raw_buf;
3248 unsigned int adsp_addr;
3249 int mem_type, nwords, max_read;
3250 int i, j, ret;
3251
3252 /* Calculate read parameters */
3253 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3254 if (buf->read_index < buf->regions[i].cumulative_size)
3255 break;
3256
3257 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3258 return -EINVAL;
3259
3260 mem_type = buf->regions[i].mem_type;
3261 adsp_addr = buf->regions[i].base_addr +
3262 (buf->read_index - buf->regions[i].offset);
3263
3264 max_read = wm_adsp_compr_frag_words(compr);
3265 nwords = buf->regions[i].cumulative_size - buf->read_index;
3266
3267 if (nwords > target)
3268 nwords = target;
3269 if (nwords > buf->avail)
3270 nwords = buf->avail;
3271 if (nwords > max_read)
3272 nwords = max_read;
3273 if (!nwords)
3274 return 0;
3275
3276 /* Read data from DSP */
3277 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3278 nwords, compr->raw_buf);
3279 if (ret < 0)
3280 return ret;
3281
3282 /* Remove the padding bytes from the data read from the DSP */
3283 for (i = 0; i < nwords; i++) {
3284 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
3285 *pack_out++ = *pack_in++;
3286
3287 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
3288 }
3289
3290 /* update read index to account for words read */
3291 buf->read_index += nwords;
3292 if (buf->read_index == wm_adsp_buffer_size(buf))
3293 buf->read_index = 0;
3294
3295 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3296 buf->read_index);
3297 if (ret < 0)
3298 return ret;
3299
3300 /* update avail to account for words read */
3301 buf->avail -= nwords;
3302
3303 return nwords;
3304}
3305
3306static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3307 char __user *buf, size_t count)
3308{
3309 struct wm_adsp *dsp = compr->dsp;
3310 int ntotal = 0;
3311 int nwords, nbytes;
3312
3313 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3314
28ee3d73 3315 if (!compr->buf || compr->buf->error) {
8d280664 3316 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
83a40ce9 3317 return -EIO;
8d280664 3318 }
83a40ce9
CK		 3319
3320 count /= WM_ADSP_DATA_WORD_SIZE;
3321
3322 do {
3323 nwords = wm_adsp_buffer_capture_block(compr, count);
3324 if (nwords < 0) {
3325 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3326 return nwords;
3327 }
3328
3329 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3330
3331 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3332
3333 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3334 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3335 ntotal, nbytes);
3336 return -EFAULT;
3337 }
3338
3339 count -= nwords;
3340 ntotal += nbytes;
3341 } while (nwords > 0 && count > 0);
3342
3343 compr->copied_total += ntotal;
3344
3345 return ntotal;
3346}
3347
3348int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3349 size_t count)
3350{
3351 struct wm_adsp_compr *compr = stream->runtime->private_data;
3352 struct wm_adsp *dsp = compr->dsp;
3353 int ret;
3354
3355 mutex_lock(&dsp->pwr_lock);
3356
3357 if (stream->direction == SND_COMPRESS_CAPTURE)
3358 ret = wm_adsp_compr_read(compr, buf, count);
3359 else
3360 ret = -ENOTSUPP;
3361
3362 mutex_unlock(&dsp->pwr_lock);
3363
3364 return ret;
3365}
3366EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3367
0a37c6ef 3368MODULE_LICENSE("GPL v2");
Empty description
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