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Merge tag 'trace-v4.19-rc8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/rosted...
[linux.git] / drivers / pci / quirks.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
df62ab5e
BH		 3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
1da177e4 6 *
df62ab5e 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
1da177e4 8 *
df62ab5e 9 * Copyright (c) 1999 Martin Mares <[email protected]>
1da177e4 10 *
df62ab5e
BH		 11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
1da177e4
LT		 13 */
14
1da177e4
LT		 15#include <linux/types.h>
16#include <linux/kernel.h>
363c75db 17#include <linux/export.h>
1da177e4
LT		 18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
25be5e6c 21#include <linux/acpi.h>
75e07fc3 22#include <linux/dmi.h>
649426ef 23#include <linux/pci-aspm.h>
32a9a682 24#include <linux/ioport.h>
3209874a
AV		 25#include <linux/sched.h>
26#include <linux/ktime.h>
9fe373f9 27#include <linux/mm.h>
ffb08634 28#include <linux/nvme.h>
630b3aff 29#include <linux/platform_data/x86/apple.h>
07f4f97d 30#include <linux/pm_runtime.h>
ad281ecf 31#include <linux/switchtec.h>
93177a74 32#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 33#include "pci.h"
1da177e4 34
78047350
BH		 35static ktime_t fixup_debug_start(struct pci_dev *dev,
36 void (*fn)(struct pci_dev *dev))
37{
38 if (initcall_debug)
39 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current));
40
41 return ktime_get();
42}
43
44static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
45 void (*fn)(struct pci_dev *dev))
46{
47 ktime_t delta, rettime;
48 unsigned long long duration;
49
50 rettime = ktime_get();
51 delta = ktime_sub(rettime, calltime);
52 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
53 if (initcall_debug || duration > 10000)
54 pci_info(dev, "%pF took %lld usecs\n", fn, duration);
55}
56
57static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
58 struct pci_fixup *end)
59{
60 ktime_t calltime;
61
62 for (; f < end; f++)
63 if ((f->class == (u32) (dev->class >> f->class_shift) ||
64 f->class == (u32) PCI_ANY_ID) &&
65 (f->vendor == dev->vendor ||
66 f->vendor == (u16) PCI_ANY_ID) &&
67 (f->device == dev->device ||
68 f->device == (u16) PCI_ANY_ID)) {
c9d8b55f
AB		 69 void (*hook)(struct pci_dev *dev);
70#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
71 hook = offset_to_ptr(&f->hook_offset);
72#else
73 hook = f->hook;
74#endif
75 calltime = fixup_debug_start(dev, hook);
76 hook(dev);
77 fixup_debug_report(dev, calltime, hook);
78047350
BH		 78 }
79}
80
81extern struct pci_fixup __start_pci_fixups_early[];
82extern struct pci_fixup __end_pci_fixups_early[];
83extern struct pci_fixup __start_pci_fixups_header[];
84extern struct pci_fixup __end_pci_fixups_header[];
85extern struct pci_fixup __start_pci_fixups_final[];
86extern struct pci_fixup __end_pci_fixups_final[];
87extern struct pci_fixup __start_pci_fixups_enable[];
88extern struct pci_fixup __end_pci_fixups_enable[];
89extern struct pci_fixup __start_pci_fixups_resume[];
90extern struct pci_fixup __end_pci_fixups_resume[];
91extern struct pci_fixup __start_pci_fixups_resume_early[];
92extern struct pci_fixup __end_pci_fixups_resume_early[];
93extern struct pci_fixup __start_pci_fixups_suspend[];
94extern struct pci_fixup __end_pci_fixups_suspend[];
95extern struct pci_fixup __start_pci_fixups_suspend_late[];
96extern struct pci_fixup __end_pci_fixups_suspend_late[];
97
98static bool pci_apply_fixup_final_quirks;
99
100void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
101{
102 struct pci_fixup *start, *end;
103
104 switch (pass) {
105 case pci_fixup_early:
106 start = __start_pci_fixups_early;
107 end = __end_pci_fixups_early;
108 break;
109
110 case pci_fixup_header:
111 start = __start_pci_fixups_header;
112 end = __end_pci_fixups_header;
113 break;
114
115 case pci_fixup_final:
116 if (!pci_apply_fixup_final_quirks)
117 return;
118 start = __start_pci_fixups_final;
119 end = __end_pci_fixups_final;
120 break;
121
122 case pci_fixup_enable:
123 start = __start_pci_fixups_enable;
124 end = __end_pci_fixups_enable;
125 break;
126
127 case pci_fixup_resume:
128 start = __start_pci_fixups_resume;
129 end = __end_pci_fixups_resume;
130 break;
131
132 case pci_fixup_resume_early:
133 start = __start_pci_fixups_resume_early;
134 end = __end_pci_fixups_resume_early;
135 break;
136
137 case pci_fixup_suspend:
138 start = __start_pci_fixups_suspend;
139 end = __end_pci_fixups_suspend;
140 break;
141
142 case pci_fixup_suspend_late:
143 start = __start_pci_fixups_suspend_late;
144 end = __end_pci_fixups_suspend_late;
145 break;
146
147 default:
148 /* stupid compiler warning, you would think with an enum... */
149 return;
150 }
151 pci_do_fixups(dev, start, end);
152}
153EXPORT_SYMBOL(pci_fixup_device);
154
155static int __init pci_apply_final_quirks(void)
156{
157 struct pci_dev *dev = NULL;
158 u8 cls = 0;
159 u8 tmp;
160
161 if (pci_cache_line_size)
162 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
163 pci_cache_line_size << 2);
164
165 pci_apply_fixup_final_quirks = true;
166 for_each_pci_dev(dev) {
167 pci_fixup_device(pci_fixup_final, dev);
168 /*
169 * If arch hasn't set it explicitly yet, use the CLS
170 * value shared by all PCI devices. If there's a
171 * mismatch, fall back to the default value.
172 */
173 if (!pci_cache_line_size) {
174 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
175 if (!cls)
176 cls = tmp;
177 if (!tmp || cls == tmp)
178 continue;
179
180 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
181 cls << 2, tmp << 2,
182 pci_dfl_cache_line_size << 2);
183 pci_cache_line_size = pci_dfl_cache_line_size;
184 }
185 }
186
187 if (!pci_cache_line_size) {
188 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
189 cls << 2, pci_dfl_cache_line_size << 2);
190 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
191 }
192
193 return 0;
194}
195fs_initcall_sync(pci_apply_final_quirks);
196
253d2e54
JP		 197/*
198 * Decoding should be disabled for a PCI device during BAR sizing to avoid
199 * conflict. But doing so may cause problems on host bridge and perhaps other
200 * key system devices. For devices that need to have mmio decoding always-on,
201 * we need to set the dev->mmio_always_on bit.
202 */
15856ad5 203static void quirk_mmio_always_on(struct pci_dev *dev)
253d2e54 204{
52d21b5e 205 dev->mmio_always_on = 1;
253d2e54 206}
52d21b5e
YL		 207DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
208 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
253d2e54 209
82e1719c
BH		 210/*
211 * The Mellanox Tavor device gives false positive parity errors. Mark this
212 * device with a broken_parity_status to allow PCI scanning code to "skip"
213 * this now blacklisted device.
bd8481e1 214 */
15856ad5 215static void quirk_mellanox_tavor(struct pci_dev *dev)
bd8481e1
DT		 216{
217 dev->broken_parity_status = 1; /* This device gives false positives */
218}
3c78bc61
RD		 219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
bd8481e1 221
82e1719c
BH		 222/*
223 * Deal with broken BIOSes that neglect to enable passive release,
224 * which can cause problems in combination with the 82441FX/PPro MTRRs
225 */
1597cacb 226static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 227{
228 struct pci_dev *d = NULL;
229 unsigned char dlc;
230
82e1719c
BH		 231 /*
232 * We have to make sure a particular bit is set in the PIIX3
233 * ISA bridge, so we have to go out and find it.
234 */
1da177e4
LT		 235 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
236 pci_read_config_byte(d, 0x82, &dlc);
237 if (!(dlc & 1<<1)) {
7506dc79 238 pci_info(d, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 239 dlc |= 1<<1;
240 pci_write_config_byte(d, 0x82, dlc);
241 }
242 }
243}
652c538e
AM		 244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
245DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4 246
82e1719c
BH		 247/*
248 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
249 * workaround but VIA don't answer queries. If you happen to have good
250 * contacts at VIA ask them for me please -- Alan
251 *
252 * This appears to be BIOS not version dependent. So presumably there is a
253 * chipset level fix.
254 */
15856ad5 255static void quirk_isa_dma_hangs(struct pci_dev *dev)
1da177e4
LT		 256{
257 if (!isa_dma_bridge_buggy) {
3c78bc61 258 isa_dma_bridge_buggy = 1;
7506dc79 259 pci_info(dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 260 }
261}
82e1719c
BH		 262/*
263 * It's not totally clear which chipsets are the problematic ones. We know
264 * 82C586 and 82C596 variants are affected.
265 */
652c538e
AM		 266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
267DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
f7625980 269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
652c538e
AM		 270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
271DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 273
4731fdcf
LB		 274/*
275 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
276 * for some HT machines to use C4 w/o hanging.
277 */
15856ad5 278static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
4731fdcf
LB		 279{
280 u32 pmbase;
281 u16 pm1a;
282
283 pci_read_config_dword(dev, 0x40, &pmbase);
284 pmbase = pmbase & 0xff80;
285 pm1a = inw(pmbase);
286
287 if (pm1a & 0x10) {
7506dc79 288 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
4731fdcf
LB		 289 outw(0x10, pmbase);
290 }
291}
292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
293
82e1719c 294/* Chipsets where PCI->PCI transfers vanish or hang */
15856ad5 295static void quirk_nopcipci(struct pci_dev *dev)
1da177e4 296{
3c78bc61 297 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
7506dc79 298 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 299 pci_pci_problems |= PCIPCI_FAIL;
300 }
301}
652c538e
AM		 302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
303DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5 304
15856ad5 305static void quirk_nopciamd(struct pci_dev *dev)
236561e5
AC		 306{
307 u8 rev;
308 pci_read_config_byte(dev, 0x08, &rev);
309 if (rev == 0x13) {
310 /* Erratum 24 */
7506dc79 311 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 312 pci_pci_problems |= PCIAGP_FAIL;
313 }
314}
652c538e 315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4 316
82e1719c 317/* Triton requires workarounds to be used by the drivers */
15856ad5 318static void quirk_triton(struct pci_dev *dev)
1da177e4 319{
3c78bc61 320 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
7506dc79 321 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 322 pci_pci_problems |= PCIPCI_TRITON;
323 }
324}
f7625980
BH		 325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 329
330/*
82e1719c
BH		 331 * VIA Apollo KT133 needs PCI latency patch
332 * Made according to a Windows driver-based patch by George E. Breese;
333 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
334 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
335 * which Mr Breese based his work.
1da177e4 336 *
82e1719c
BH		 337 * Updated based on further information from the site and also on
338 * information provided by VIA
1da177e4 339 */
1597cacb 340static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 341{
342 struct pci_dev *p;
1da177e4 343 u8 busarb;
f7625980 344
82e1719c
BH		 345 /*
346 * Ok, we have a potential problem chipset here. Now see if we have
347 * a buggy southbridge.
348 */
1da177e4 349 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
3c78bc61 350 if (p != NULL) {
82e1719c
BH		 351
352 /*
353 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
354 * thanks Dan Hollis.
355 * Check for buggy part revisions
356 */
2b1afa87 357 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 358 goto exit;
359 } else {
360 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
3c78bc61 361 if (p == NULL) /* No problem parts */
1da177e4 362 goto exit;
82e1719c 363
1da177e4 364 /* Check for buggy part revisions */
2b1afa87 365 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 366 goto exit;
367 }
f7625980 368
1da177e4 369 /*
82e1719c
BH		 370 * Ok we have the problem. Now set the PCI master grant to occur
371 * every master grant. The apparent bug is that under high PCI load
372 * (quite common in Linux of course) you can get data loss when the
373 * CPU is held off the bus for 3 bus master requests. This happens
374 * to include the IDE controllers....
1da177e4 375 *
82e1719c
BH		 376 * VIA only apply this fix when an SB Live! is present but under
377 * both Linux and Windows this isn't enough, and we have seen
378 * corruption without SB Live! but with things like 3 UDMA IDE
379 * controllers. So we ignore that bit of the VIA recommendation..
1da177e4 380 */
1da177e4 381 pci_read_config_byte(dev, 0x76, &busarb);
82e1719c
BH		 382
383 /*
384 * Set bit 4 and bit 5 of byte 76 to 0x01
385 * "Master priority rotation on every PCI master grant"
386 */
1da177e4
LT		 387 busarb &= ~(1<<5);
388 busarb |= (1<<4);
389 pci_write_config_byte(dev, 0x76, busarb);
7506dc79 390 pci_info(dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 391exit:
392 pci_dev_put(p);
393}
652c538e
AM		 394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 397/* Must restore this on a resume from RAM */
652c538e
AM		 398DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
399DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
400DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4 401
82e1719c 402/* VIA Apollo VP3 needs ETBF on BT848/878 */
15856ad5 403static void quirk_viaetbf(struct pci_dev *dev)
1da177e4 404{
3c78bc61 405 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
7506dc79 406 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 407 pci_pci_problems |= PCIPCI_VIAETBF;
408 }
409}
652c538e 410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4 411
15856ad5 412static void quirk_vsfx(struct pci_dev *dev)
1da177e4 413{
3c78bc61 414 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
7506dc79 415 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 416 pci_pci_problems |= PCIPCI_VSFX;
417 }
418}
652c538e 419DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 420
421/*
82e1719c
BH		 422 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
423 * space. Latency must be set to 0xA and Triton workaround applied too.
424 * [Info kindly provided by ALi]
f7625980 425 */
15856ad5 426static void quirk_alimagik(struct pci_dev *dev)
1da177e4 427{
3c78bc61 428 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
7506dc79 429 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 430 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
431 }
432}
f7625980
BH		 433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4 435
82e1719c 436/* Natoma has some interesting boundary conditions with Zoran stuff at least */
15856ad5 437static void quirk_natoma(struct pci_dev *dev)
1da177e4 438{
3c78bc61 439 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
7506dc79 440 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 441 pci_pci_problems |= PCIPCI_NATOMA;
442 }
443}
f7625980
BH		 444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 450
451/*
82e1719c
BH		 452 * This chip can cause PCI parity errors if config register 0xA0 is read
453 * while DMAs are occurring.
1da177e4 454 */
15856ad5 455static void quirk_citrine(struct pci_dev *dev)
1da177e4
LT		 456{
457 dev->cfg_size = 0xA0;
458}
652c538e 459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4 460
9f33a2ae
JM		 461/*
462 * This chip can cause bus lockups if config addresses above 0x600
463 * are read or written.
464 */
465static void quirk_nfp6000(struct pci_dev *dev)
466{
467 dev->cfg_size = 0x600;
468}
c2e771b0 469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
9f33a2ae 470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
2538fb89 471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
9f33a2ae
JM		 472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
473
9fe373f9
DL		 474/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
475static void quirk_extend_bar_to_page(struct pci_dev *dev)
476{
477 int i;
478
2f686f1d 479 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
9fe373f9
DL		 480 struct resource *r = &dev->resource[i];
481
482 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
483 r->end = PAGE_SIZE - 1;
484 r->start = 0;
485 r->flags |= IORESOURCE_UNSET;
7506dc79 486 pci_info(dev, "expanded BAR %d to page size: %pR\n",
9fe373f9
DL		 487 i, r);
488 }
489 }
490}
491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
492
1da177e4 493/*
82e1719c
BH		 494 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
495 * If it's needed, re-allocate the region.
1da177e4 496 */
15856ad5 497static void quirk_s3_64M(struct pci_dev *dev)
1da177e4
LT		 498{
499 struct resource *r = &dev->resource[0];
500
501 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
bd064f0a 502 r->flags |= IORESOURCE_UNSET;
1da177e4
LT		 503 r->start = 0;
504 r->end = 0x3ffffff;
505 }
506}
652c538e
AM		 507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 509
06cf35f9
MS		 510static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
511 const char *name)
512{
513 u32 region;
514 struct pci_bus_region bus_region;
515 struct resource *res = dev->resource + pos;
516
517 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
518
519 if (!region)
520 return;
521
522 res->name = pci_name(dev);
523 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
524 res->flags |=
525 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
526 region &= ~(size - 1);
527
528 /* Convert from PCI bus to resource space */
529 bus_region.start = region;
530 bus_region.end = region + size - 1;
531 pcibios_bus_to_resource(dev->bus, res, &bus_region);
532
7506dc79 533 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
06cf35f9
MS		 534 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
535}
536
73d2eaac
AS		 537/*
538 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
539 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
540 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
541 * (which conflicts w/ BAR1's memory range).
06cf35f9
MS		 542 *
543 * CS553x's ISA PCI BARs may also be read-only (ref:
544 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
73d2eaac 545 */
15856ad5 546static void quirk_cs5536_vsa(struct pci_dev *dev)
73d2eaac 547{
06cf35f9
MS		 548 static char *name = "CS5536 ISA bridge";
549
73d2eaac 550 if (pci_resource_len(dev, 0) != 8) {
06cf35f9
MS		 551 quirk_io(dev, 0, 8, name); /* SMB */
552 quirk_io(dev, 1, 256, name); /* GPIO */
553 quirk_io(dev, 2, 64, name); /* MFGPT */
7506dc79 554 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
06cf35f9 555 name);
73d2eaac
AS		 556 }
557}
558DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
559
65195c76
YL		 560static void quirk_io_region(struct pci_dev *dev, int port,
561 unsigned size, int nr, const char *name)
562{
563 u16 region;
564 struct pci_bus_region bus_region;
565 struct resource *res = dev->resource + nr;
566
567 pci_read_config_word(dev, port, &region);
568 region &= ~(size - 1);
569
570 if (!region)
571 return;
572
573 res->name = pci_name(dev);
574 res->flags = IORESOURCE_IO;
575
576 /* Convert from PCI bus to resource space */
577 bus_region.start = region;
578 bus_region.end = region + size - 1;
fc279850 579 pcibios_bus_to_resource(dev->bus, res, &bus_region);
65195c76
YL		 580
581 if (!pci_claim_resource(dev, nr))
7506dc79 582 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
65195c76 583}
1da177e4
LT		 584
585/*
82e1719c
BH		 586 * ATI Northbridge setups MCE the processor if you even read somewhere
587 * between 0x3b0->0x3bb or read 0x3d3
1da177e4 588 */
15856ad5 589static void quirk_ati_exploding_mce(struct pci_dev *dev)
1da177e4 590{
7506dc79 591 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 592 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
593 request_region(0x3b0, 0x0C, "RadeonIGP");
594 request_region(0x3d3, 0x01, "RadeonIGP");
595}
652c538e 596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4 597
be6646bf
HR		 598/*
599 * In the AMD NL platform, this device ([1022:7912]) has a class code of
600 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
601 * claim it.
82e1719c 602 *
be6646bf
HR		 603 * But the dwc3 driver is a more specific driver for this device, and we'd
604 * prefer to use it instead of xhci. To prevent xhci from claiming the
605 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
606 * defines as "USB device (not host controller)". The dwc3 driver can then
607 * claim it based on its Vendor and Device ID.
608 */
609static void quirk_amd_nl_class(struct pci_dev *pdev)
610{
cd76d10b
BH		 611 u32 class = pdev->class;
612
613 /* Use "USB Device (not host controller)" class */
7b78f48a 614 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
7506dc79 615 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
cd76d10b 616 class, pdev->class);
be6646bf
HR		 617}
618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
619 quirk_amd_nl_class);
620
1da177e4 621/*
82e1719c
BH		 622 * Let's make the southbridge information explicit instead of having to
623 * worry about people probing the ACPI areas, for example.. (Yes, it
624 * happens, and if you read the wrong ACPI register it will put the machine
625 * to sleep with no way of waking it up again. Bummer).
1da177e4
LT		 626 *
627 * ALI M7101: Two IO regions pointed to by words at
628 * 0xE0 (64 bytes of ACPI registers)
629 * 0xE2 (32 bytes of SMB registers)
630 */
15856ad5 631static void quirk_ali7101_acpi(struct pci_dev *dev)
1da177e4 632{
65195c76
YL		 633 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
634 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 635}
652c538e 636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 637
6693e74a
LT		 638static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
639{
640 u32 devres;
641 u32 mask, size, base;
642
643 pci_read_config_dword(dev, port, &devres);
644 if ((devres & enable) != enable)
645 return;
646 mask = (devres >> 16) & 15;
647 base = devres & 0xffff;
648 size = 16;
649 for (;;) {
650 unsigned bit = size >> 1;
651 if ((bit & mask) == bit)
652 break;
653 size = bit;
654 }
655 /*
656 * For now we only print it out. Eventually we'll want to
657 * reserve it (at least if it's in the 0x1000+ range), but
f7625980 658 * let's get enough confirmation reports first.
6693e74a
LT		 659 */
660 base &= -size;
7506dc79 661 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 662}
663
664static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
665{
666 u32 devres;
667 u32 mask, size, base;
668
669 pci_read_config_dword(dev, port, &devres);
670 if ((devres & enable) != enable)
671 return;
672 base = devres & 0xffff0000;
673 mask = (devres & 0x3f) << 16;
674 size = 128 << 16;
675 for (;;) {
676 unsigned bit = size >> 1;
677 if ((bit & mask) == bit)
678 break;
679 size = bit;
680 }
82e1719c 681
6693e74a
LT		 682 /*
683 * For now we only print it out. Eventually we'll want to
f7625980 684 * reserve it, but let's get enough confirmation reports first.
6693e74a
LT		 685 */
686 base &= -size;
7506dc79 687 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 688}
689
1da177e4
LT		 690/*
691 * PIIX4 ACPI: Two IO regions pointed to by longwords at
692 * 0x40 (64 bytes of ACPI registers)
08db2a70 693 * 0x90 (16 bytes of SMB registers)
6693e74a 694 * and a few strange programmable PIIX4 device resources.
1da177e4 695 */
15856ad5 696static void quirk_piix4_acpi(struct pci_dev *dev)
1da177e4 697{
65195c76 698 u32 res_a;
1da177e4 699
65195c76
YL		 700 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
701 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 702
703 /* Device resource A has enables for some of the other ones */
704 pci_read_config_dword(dev, 0x5c, &res_a);
705
706 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
707 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
708
709 /* Device resource D is just bitfields for static resources */
710
711 /* Device 12 enabled? */
712 if (res_a & (1 << 29)) {
713 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
714 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
715 }
716 /* Device 13 enabled? */
717 if (res_a & (1 << 30)) {
718 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
719 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
720 }
721 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
722 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 723}
652c538e
AM		 724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
725DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4 726
cdb97558
JS		 727#define ICH_PMBASE 0x40
728#define ICH_ACPI_CNTL 0x44
729#define ICH4_ACPI_EN 0x10
730#define ICH6_ACPI_EN 0x80
731#define ICH4_GPIOBASE 0x58
732#define ICH4_GPIO_CNTL 0x5c
733#define ICH4_GPIO_EN 0x10
734#define ICH6_GPIOBASE 0x48
735#define ICH6_GPIO_CNTL 0x4c
736#define ICH6_GPIO_EN 0x10
737
1da177e4
LT		 738/*
739 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
740 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
741 * 0x58 (64 bytes of GPIO I/O space)
742 */
15856ad5 743static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
1da177e4 744{
cdb97558 745 u8 enable;
1da177e4 746
87e3dc38
JS		 747 /*
748 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
749 * with low legacy (and fixed) ports. We don't know the decoding
750 * priority and can't tell whether the legacy device or the one created
751 * here is really at that address. This happens on boards with broken
752 * BIOSes.
82e1719c 753 */
cdb97558 754 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
65195c76
YL		 755 if (enable & ICH4_ACPI_EN)
756 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
757 "ICH4 ACPI/GPIO/TCO");
1da177e4 758
cdb97558 759 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
65195c76
YL		 760 if (enable & ICH4_GPIO_EN)
761 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
762 "ICH4 GPIO");
1da177e4 763}
652c538e
AM		 764DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
765DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
767DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
768DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
769DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
770DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
771DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
772DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
773DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 774
15856ad5 775static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f 776{
cdb97558 777 u8 enable;
2cea752f 778
cdb97558 779 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
65195c76
YL		 780 if (enable & ICH6_ACPI_EN)
781 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
782 "ICH6 ACPI/GPIO/TCO");
2cea752f 783
cdb97558 784 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
65195c76
YL		 785 if (enable & ICH6_GPIO_EN)
786 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
787 "ICH6 GPIO");
2cea752f 788}
894886e5 789
82e1719c
BH		 790static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
791 const char *name, int dynsize)
894886e5
LT		 792{
793 u32 val;
794 u32 size, base;
795
796 pci_read_config_dword(dev, reg, &val);
797
798 /* Enabled? */
799 if (!(val & 1))
800 return;
801 base = val & 0xfffc;
802 if (dynsize) {
803 /*
804 * This is not correct. It is 16, 32 or 64 bytes depending on
805 * register D31:F0:ADh bits 5:4.
806 *
807 * But this gets us at least _part_ of it.
808 */
809 size = 16;
810 } else {
811 size = 128;
812 }
813 base &= ~(size-1);
814
82e1719c
BH		 815 /*
816 * Just print it out for now. We should reserve it after more
817 * debugging.
818 */
7506dc79 819 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
894886e5
LT		 820}
821
15856ad5 822static void quirk_ich6_lpc(struct pci_dev *dev)
894886e5
LT		 823{
824 /* Shared ACPI/GPIO decode with all ICH6+ */
825 ich6_lpc_acpi_gpio(dev);
826
827 /* ICH6-specific generic IO decode */
828 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
829 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
830}
831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
833
82e1719c
BH		 834static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
835 const char *name)
894886e5
LT		 836{
837 u32 val;
838 u32 mask, base;
839
840 pci_read_config_dword(dev, reg, &val);
841
842 /* Enabled? */
843 if (!(val & 1))
844 return;
845
82e1719c 846 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
894886e5
LT		 847 base = val & 0xfffc;
848 mask = (val >> 16) & 0xfc;
849 mask |= 3;
850
82e1719c
BH		 851 /*
852 * Just print it out for now. We should reserve it after more
853 * debugging.
854 */
7506dc79 855 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
894886e5
LT		 856}
857
858/* ICH7-10 has the same common LPC generic IO decode registers */
15856ad5 859static void quirk_ich7_lpc(struct pci_dev *dev)
894886e5 860{
5d9c0a79 861 /* We share the common ACPI/GPIO decode with ICH6 */
894886e5
LT		 862 ich6_lpc_acpi_gpio(dev);
863
864 /* And have 4 ICH7+ generic decodes */
865 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
866 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
867 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
868 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
869}
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
877DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
880DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 883
1da177e4
LT		 884/*
885 * VIA ACPI: One IO region pointed to by longword at
886 * 0x48 or 0x20 (256 bytes of ACPI registers)
887 */
15856ad5 888static void quirk_vt82c586_acpi(struct pci_dev *dev)
1da177e4 889{
65195c76
YL		 890 if (dev->revision & 0x10)
891 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
892 "vt82c586 ACPI");
1da177e4 893}
652c538e 894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 895
896/*
897 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
898 * 0x48 (256 bytes of ACPI registers)
899 * 0x70 (128 bytes of hardware monitoring register)
900 * 0x90 (16 bytes of SMB registers)
901 */
15856ad5 902static void quirk_vt82c686_acpi(struct pci_dev *dev)
1da177e4 903{
1da177e4
LT		 904 quirk_vt82c586_acpi(dev);
905
65195c76
YL		 906 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
907 "vt82c686 HW-mon");
1da177e4 908
65195c76 909 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
1da177e4 910}
652c538e 911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 912
6d85f29b
IK		 913/*
914 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
915 * 0x88 (128 bytes of power management registers)
916 * 0xd0 (16 bytes of SMB registers)
917 */
15856ad5 918static void quirk_vt8235_acpi(struct pci_dev *dev)
6d85f29b 919{
65195c76
YL		 920 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
921 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
6d85f29b
IK		 922}
923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
924
1f56f4a2 925/*
82e1719c
BH		 926 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
927 * back-to-back: Disable fast back-to-back on the secondary bus segment
1f56f4a2 928 */
15856ad5 929static void quirk_xio2000a(struct pci_dev *dev)
1f56f4a2
GB		 930{
931 struct pci_dev *pdev;
932 u16 command;
933
7506dc79 934 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
1f56f4a2
GB		 935 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
936 pci_read_config_word(pdev, PCI_COMMAND, &command);
937 if (command & PCI_COMMAND_FAST_BACK)
938 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
939 }
940}
941DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
942 quirk_xio2000a);
1da177e4 943
f7625980 944#ifdef CONFIG_X86_IO_APIC
1da177e4
LT		 945
946#include <asm/io_apic.h>
947
948/*
949 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
950 * devices to the external APIC.
951 *
82e1719c
BH		 952 * TODO: When we have device-specific interrupt routers, this code will go
953 * away from quirks.
1da177e4 954 */
1597cacb 955static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 956{
957 u8 tmp;
f7625980 958
1da177e4
LT		 959 if (nr_ioapics < 1)
960 tmp = 0; /* nothing routed to external APIC */
961 else
962 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
f7625980 963
7506dc79 964 pci_info(dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 965 tmp == 0 ? "Disa" : "Ena");
966
967 /* Offset 0x58: External APIC IRQ output control */
3c78bc61 968 pci_write_config_byte(dev, 0x58, tmp);
1da177e4 969}
652c538e 970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 971DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 972
a1740913 973/*
f7625980 974 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
a1740913
KW		 975 * This leads to doubled level interrupt rates.
976 * Set this bit to get rid of cycle wastage.
977 * Otherwise uncritical.
978 */
1597cacb 979static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 980{
981 u8 misc_control2;
982#define BYPASS_APIC_DEASSERT 8
983
984 pci_read_config_byte(dev, 0x5B, &misc_control2);
985 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
7506dc79 986 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 987 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
988 }
989}
990DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 991DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 992
1da177e4 993/*
82e1719c 994 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1da177e4
LT		 995 * We check all revs >= B0 (yet not in the pre production!) as the bug
996 * is currently marked NoFix
997 *
998 * We have multiple reports of hangs with this chipset that went away with
236561e5 999 * noapic specified. For the moment we assume it's the erratum. We may be wrong
82e1719c 1000 * of course. However the advice is demonstrably good even if so.
1da177e4 1001 */
15856ad5 1002static void quirk_amd_ioapic(struct pci_dev *dev)
1da177e4 1003{
44c10138 1004 if (dev->revision >= 0x02) {
7506dc79
FL		 1005 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1006 pci_warn(dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 1007 }
1008}
652c538e 1009DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 1010#endif /* CONFIG_X86_IO_APIC */
1011
0bec9057 1012#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
21b5b8ee
AJ		 1013
1014static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1015{
82e1719c 1016 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
21b5b8ee
AJ		 1017 if (dev->subsystem_device == 0xa118)
1018 dev->sriov->link = dev->devfn;
1019}
1020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1021#endif
1022
d556ad4b
PO		 1023/*
1024 * Some settings of MMRBC can lead to data corruption so block changes.
1025 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1026 */
15856ad5 1027static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
d556ad4b 1028{
aa288d4d 1029 if (dev->subordinate && dev->revision <= 0x12) {
7506dc79 1030 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
227f0647 1031 dev->revision);
d556ad4b
PO		 1032 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1033 }
1034}
1035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 1036
1da177e4 1037/*
82e1719c
BH		 1038 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1039 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1040 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1041 * of the ACPI SCI interrupt is only done for convenience.
1da177e4
LT		 1042 * -jgarzik
1043 */
15856ad5 1044static void quirk_via_acpi(struct pci_dev *d)
1da177e4 1045{
1da177e4 1046 u8 irq;
82e1719c
BH		 1047
1048 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1da177e4
LT		 1049 pci_read_config_byte(d, 0x42, &irq);
1050 irq &= 0xf;
1051 if (irq && (irq != 2))
1052 d->irq = irq;
1053}
652c538e
AM		 1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 1056
82e1719c 1057/* VIA bridges which have VLink */
c06bb5d4
JD		 1058static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1059
1060static void quirk_via_bridge(struct pci_dev *dev)
1061{
1062 /* See what bridge we have and find the device ranges */
1063 switch (dev->device) {
1064 case PCI_DEVICE_ID_VIA_82C686:
82e1719c
BH		 1065 /*
1066 * The VT82C686 is special; it attaches to PCI and can have
1067 * any device number. All its subdevices are functions of
1068 * that single device.
1069 */
cb7468ef
JD		 1070 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1071 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 1072 break;
1073 case PCI_DEVICE_ID_VIA_8237:
1074 case PCI_DEVICE_ID_VIA_8237A:
1075 via_vlink_dev_lo = 15;
1076 break;
1077 case PCI_DEVICE_ID_VIA_8235:
1078 via_vlink_dev_lo = 16;
1079 break;
1080 case PCI_DEVICE_ID_VIA_8231:
1081 case PCI_DEVICE_ID_VIA_8233_0:
1082 case PCI_DEVICE_ID_VIA_8233A:
1083 case PCI_DEVICE_ID_VIA_8233C_0:
1084 via_vlink_dev_lo = 17;
1085 break;
1086 }
1087}
1088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 1096
82e1719c
BH		 1097/*
1098 * quirk_via_vlink - VIA VLink IRQ number update
1099 * @dev: PCI device
1597cacb 1100 *
82e1719c
BH		 1101 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1102 * the IRQ line register which usually is not relevant for PCI cards, is
1103 * actually written so that interrupts get sent to the right place.
1104 *
1105 * We only do this on systems where a VIA south bridge was detected, and
1106 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1597cacb 1107 */
1597cacb 1108static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 1109{
1110 u8 irq, new_irq;
1111
c06bb5d4
JD		 1112 /* Check if we have VLink at all */
1113 if (via_vlink_dev_lo == -1)
09d6029f
DD		 1114 return;
1115
1116 new_irq = dev->irq;
1117
1118 /* Don't quirk interrupts outside the legacy IRQ range */
1119 if (!new_irq || new_irq > 15)
1120 return;
1121
1597cacb 1122 /* Internal device ? */
c06bb5d4
JD		 1123 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1124 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 1125 return;
1126
82e1719c
BH		 1127 /*
1128 * This is an internal VLink device on a PIC interrupt. The BIOS
1129 * ought to have set this but may not have, so we redo it.
1130 */
25be5e6c
LB		 1131 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1132 if (new_irq != irq) {
7506dc79 1133 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
f0fda801 1134 irq, new_irq);
25be5e6c
LB		 1135 udelay(15); /* unknown if delay really needed */
1136 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1137 }
1138}
1597cacb 1139DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 1140
1da177e4 1141/*
82e1719c
BH		 1142 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1143 * of VT82C597 for backward compatibility. We need to switch it off to be
1144 * able to recognize the real type of the chip.
1da177e4 1145 */
15856ad5 1146static void quirk_vt82c598_id(struct pci_dev *dev)
1da177e4
LT		 1147{
1148 pci_write_config_byte(dev, 0xfc, 0);
1149 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1150}
652c538e 1151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 1152
1153/*
82e1719c
BH		 1154 * CardBus controllers have a legacy base address that enables them to
1155 * respond as i82365 pcmcia controllers. We don't want them to do this
1156 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1157 * driver does not (and should not) handle CardBus.
1da177e4 1158 */
1597cacb 1159static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4 1160{
1da177e4
LT		 1161 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1162}
ae9de56b
YL		 1163DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1164 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1165DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1166 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1da177e4
LT		 1167
1168/*
82e1719c
BH		 1169 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1170 * what the designers were smoking but let's not inhale...
1da177e4 1171 *
82e1719c
BH		 1172 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1173 * turn it off!
1da177e4 1174 */
1597cacb 1175static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 1176{
1177 u32 pcic;
1178 pci_read_config_dword(dev, 0x4C, &pcic);
3c78bc61 1179 if ((pcic & 6) != 6) {
1da177e4 1180 pcic |= 6;
7506dc79 1181 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 1182 pci_write_config_dword(dev, 0x4C, pcic);
1183 pci_read_config_dword(dev, 0x84, &pcic);
3c78bc61 1184 pcic |= (1 << 23); /* Required in this mode */
1da177e4
LT		 1185 pci_write_config_dword(dev, 0x84, pcic);
1186 }
1187}
652c538e 1188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 1189DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 1190
1191/*
82e1719c 1192 * DreamWorks-provided workaround for Dunord I-3000 problem
1da177e4 1193 *
82e1719c
BH		 1194 * This card decodes and responds to addresses not apparently assigned to
1195 * it. We force a larger allocation to ensure that nothing gets put too
1196 * close to it.
1da177e4 1197 */
15856ad5 1198static void quirk_dunord(struct pci_dev *dev)
1da177e4 1199{
3c78bc61 1200 struct resource *r = &dev->resource[1];
bd064f0a
BH		 1201
1202 r->flags |= IORESOURCE_UNSET;
1da177e4
LT		 1203 r->start = 0;
1204 r->end = 0xffffff;
1205}
652c538e 1206DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 1207
1208/*
82e1719c
BH		 1209 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1210 * decoding (transparent), and does indicate this in the ProgIf.
1211 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1da177e4 1212 */
15856ad5 1213static void quirk_transparent_bridge(struct pci_dev *dev)
1da177e4
LT		 1214{
1215 dev->transparent = 1;
1216}
652c538e
AM		 1217DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1218DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 1219
1220/*
82e1719c
BH		 1221 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1222 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1223 * found at http://www.national.com/analog for info on what these bits do.
1224 * <[email protected]>
1da177e4 1225 */
1597cacb 1226static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 1227{
1228 u8 reg;
3c78bc61 1229
1da177e4
LT		 1230 pci_read_config_byte(dev, 0x41, &reg);
1231 if (reg & 2) {
1232 reg &= ~2;
7506dc79 1233 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
227f0647 1234 reg);
3c78bc61 1235 pci_write_config_byte(dev, 0x41, reg);
1da177e4
LT		 1236 }
1237}
652c538e
AM		 1238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1239DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 1240
1da177e4 1241/*
82e1719c
BH		 1242 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1243 * in the odd case it is not the results are corruption hence the presence
1244 * of a Linux check.
1da177e4 1245 */
1597cacb 1246static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 1247{
1248 u16 config;
f7625980 1249
44c10138 1250 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 1251 return;
1252 pci_read_config_word(pdev, 0x40, &config);
1253 if (config & (1<<6)) {
1254 config &= ~(1<<6);
1255 pci_write_config_word(pdev, 0x40, config);
7506dc79 1256 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 1257 }
1258}
652c538e 1259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1260DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1261
25e742b2 1262static void quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1263{
5deab536 1264 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1265 u8 tmp;
ab17443a 1266
05a7d22b
CC		 1267 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1268 if (tmp == 0x01) {
ab17443a
CH		 1269 pci_read_config_byte(pdev, 0x40, &tmp);
1270 pci_write_config_byte(pdev, 0x40, tmp|1);
1271 pci_write_config_byte(pdev, 0x9, 1);
1272 pci_write_config_byte(pdev, 0xa, 6);
1273 pci_write_config_byte(pdev, 0x40, tmp);
1274
c9f89475 1275 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
7506dc79 1276 pci_info(pdev, "set SATA to AHCI mode\n");
ab17443a
CH		 1277 }
1278}
05a7d22b 1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1280DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1282DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1284DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
fafe5c3d
SH		 1285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1286DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
ab17443a 1287
82e1719c 1288/* Serverworks CSB5 IDE does not fully support native mode */
15856ad5 1289static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1da177e4
LT		 1290{
1291 u8 prog;
1292 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1293 if (prog & 5) {
1294 prog &= ~5;
1295 pdev->class &= ~5;
1296 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1297 /* PCI layer will sort out resources */
1da177e4
LT		 1298 }
1299}
652c538e 1300DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4 1301
82e1719c 1302/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
15856ad5 1303static void quirk_ide_samemode(struct pci_dev *pdev)
1da177e4
LT		 1304{
1305 u8 prog;
1306
1307 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1308
1309 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
7506dc79 1310 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1311 prog &= ~5;
1312 pdev->class &= ~5;
1313 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1314 }
1315}
368c73d4 1316DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1317
82e1719c 1318/* Some ATA devices break if put into D3 */
15856ad5 1319static void quirk_no_ata_d3(struct pci_dev *pdev)
979b1791 1320{
faa738bb 1321 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
979b1791 1322}
faa738bb
YL		 1323/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1324DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1325 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1326DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1327 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f 1328/* ALi loses some register settings that we cannot then restore */
faa738bb
YL		 1329DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1330 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f
AC		 1331/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1332 occur when mode detecting */
faa738bb
YL		 1333DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1334 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
979b1791 1335
82e1719c
BH		 1336/*
1337 * This was originally an Alpha-specific thing, but it really fits here.
1da177e4
LT		 1338 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1339 */
15856ad5 1340static void quirk_eisa_bridge(struct pci_dev *dev)
1da177e4
LT		 1341{
1342 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1343}
652c538e 1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4
LT		 1345
1346/*
1347 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1348 * is not activated. The myth is that Asus said that they do not want the
1349 * users to be irritated by just another PCI Device in the Win98 device
f7625980 1350 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1da177e4
LT		 1351 * package 2.7.0 for details)
1352 *
f7625980
BH		 1353 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1354 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1355 * becomes necessary to do this tweak in two steps -- the chosen trigger
1356 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1357 *
1358 * Note that we used to unhide the SMBus that way on Toshiba laptops
1359 * (Satellite A40 and Tecra M2) but then found that the thermal management
1360 * was done by SMM code, which could cause unsynchronized concurrent
1361 * accesses to the SMBus registers, with potentially bad effects. Thus you
1362 * should be very careful when adding new entries: if SMM is accessing the
1363 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1364 *
1365 * Likewise, many recent laptops use ACPI for thermal management. If the
1366 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1367 * natively, and keeping the SMBus hidden is the right thing to do. If you
1368 * are about to add an entry in the table below, please first disassemble
1369 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1370 */
9d24a81e 1371static int asus_hides_smbus;
1da177e4 1372
15856ad5 1373static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1da177e4
LT		 1374{
1375 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1376 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
3c78bc61 1377 switch (dev->subsystem_device) {
a00db371 1378 case 0x8025: /* P4B-LX */
1da177e4
LT		 1379 case 0x8070: /* P4B */
1380 case 0x8088: /* P4B533 */
1381 case 0x1626: /* L3C notebook */
1382 asus_hides_smbus = 1;
1383 }
2f2d39d2 1384 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
3c78bc61 1385 switch (dev->subsystem_device) {
1da177e4
LT		 1386 case 0x80b1: /* P4GE-V */
1387 case 0x80b2: /* P4PE */
1388 case 0x8093: /* P4B533-V */
1389 asus_hides_smbus = 1;
1390 }
2f2d39d2 1391 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
3c78bc61 1392 switch (dev->subsystem_device) {
1da177e4
LT		 1393 case 0x8030: /* P4T533 */
1394 asus_hides_smbus = 1;
1395 }
2f2d39d2 1396 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1397 switch (dev->subsystem_device) {
1398 case 0x8070: /* P4G8X Deluxe */
1399 asus_hides_smbus = 1;
1400 }
2f2d39d2 1401 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1402 switch (dev->subsystem_device) {
1403 case 0x80c9: /* PU-DLS */
1404 asus_hides_smbus = 1;
1405 }
2f2d39d2 1406 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1407 switch (dev->subsystem_device) {
1408 case 0x1751: /* M2N notebook */
1409 case 0x1821: /* M5N notebook */
4096ed0f 1410 case 0x1897: /* A6L notebook */
1da177e4
LT		 1411 asus_hides_smbus = 1;
1412 }
2f2d39d2 1413 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1414 switch (dev->subsystem_device) {
1415 case 0x184b: /* W1N notebook */
1416 case 0x186a: /* M6Ne notebook */
1417 asus_hides_smbus = 1;
1418 }
2f2d39d2 1419 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1420 switch (dev->subsystem_device) {
1421 case 0x80f2: /* P4P800-X */
1422 asus_hides_smbus = 1;
1423 }
2f2d39d2 1424 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1425 switch (dev->subsystem_device) {
1426 case 0x1882: /* M6V notebook */
2d1e1c75 1427 case 0x1977: /* A6VA notebook */
acc06632
RM		 1428 asus_hides_smbus = 1;
1429 }
1da177e4
LT		 1430 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1431 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
3c78bc61 1432 switch (dev->subsystem_device) {
1da177e4
LT		 1433 case 0x088C: /* HP Compaq nc8000 */
1434 case 0x0890: /* HP Compaq nc6000 */
1435 asus_hides_smbus = 1;
1436 }
2f2d39d2 1437 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1438 switch (dev->subsystem_device) {
1439 case 0x12bc: /* HP D330L */
e3b1bd57 1440 case 0x12bd: /* HP D530 */
74c57428 1441 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1442 asus_hides_smbus = 1;
1443 }
677cc644
JD		 1444 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1445 switch (dev->subsystem_device) {
1446 case 0x12bf: /* HP xw4100 */
1447 asus_hides_smbus = 1;
1448 }
3c78bc61
RD		 1449 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1450 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1451 switch (dev->subsystem_device) {
1452 case 0xC00C: /* Samsung P35 notebook */
1453 asus_hides_smbus = 1;
1454 }
c87f883e
RIZ		 1455 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1456 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
3c78bc61 1457 switch (dev->subsystem_device) {
c87f883e
RIZ		 1458 case 0x0058: /* Compaq Evo N620c */
1459 asus_hides_smbus = 1;
1460 }
d7698edc 1461 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
3c78bc61 1462 switch (dev->subsystem_device) {
d7698edc 1463 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1464 /* Motherboard doesn't have Host bridge
1465 * subvendor/subdevice IDs, therefore checking
1466 * its on-board VGA controller */
1467 asus_hides_smbus = 1;
1468 }
8293b0f6 1469 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
3c78bc61 1470 switch (dev->subsystem_device) {
10260d9a
JD		 1471 case 0x00b8: /* Compaq Evo D510 CMT */
1472 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1473 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1474 /* Motherboard doesn't have Host bridge
1475 * subvendor/subdevice IDs and on-board VGA
1476 * controller is disabled if an AGP card is
1477 * inserted, therefore checking USB UHCI
1478 * Controller #1 */
10260d9a
JD		 1479 asus_hides_smbus = 1;
1480 }
27e46859
KH		 1481 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1482 switch (dev->subsystem_device) {
1483 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1484 /* Motherboard doesn't have host bridge
1485 * subvendor/subdevice IDs, therefore checking
1486 * its on-board VGA controller */
1487 asus_hides_smbus = 1;
1488 }
1da177e4
LT		 1489 }
1490}
652c538e
AM		 1491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1492DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1493DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1499DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1500DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1501
1502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1503DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1505
1597cacb 1506static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1507{
1508 u16 val;
f7625980 1509
1da177e4
LT		 1510 if (likely(!asus_hides_smbus))
1511 return;
1512
1513 pci_read_config_word(dev, 0xF2, &val);
1514 if (val & 0x8) {
1515 pci_write_config_word(dev, 0xF2, val & (~0x8));
1516 pci_read_config_word(dev, 0xF2, &val);
1517 if (val & 0x8)
7506dc79 1518 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
227f0647 1519 val);
1da177e4 1520 else
7506dc79 1521 pci_info(dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1522 }
1523}
652c538e
AM		 1524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1531DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1533DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1534DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1536DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1537DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1538
e1a2a51e
RW		 1539/* It appears we just have one such device. If not, we have a warning */
1540static void __iomem *asus_rcba_base;
1541static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1542{
e1a2a51e 1543 u32 rcba;
acc06632
RM		 1544
1545 if (likely(!asus_hides_smbus))
1546 return;
e1a2a51e
RW		 1547 WARN_ON(asus_rcba_base);
1548
acc06632 1549 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1550 /* use bits 31:14, 16 kB aligned */
1551 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1552 if (asus_rcba_base == NULL)
1553 return;
1554}
1555
1556static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1557{
1558 u32 val;
1559
1560 if (likely(!asus_hides_smbus || !asus_rcba_base))
1561 return;
82e1719c 1562
e1a2a51e
RW		 1563 /* read the Function Disable register, dword mode only */
1564 val = readl(asus_rcba_base + 0x3418);
82e1719c
BH		 1565
1566 /* enable the SMBus device */
1567 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
e1a2a51e
RW		 1568}
1569
1570static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1571{
1572 if (likely(!asus_hides_smbus || !asus_rcba_base))
1573 return;
82e1719c 1574
e1a2a51e
RW		 1575 iounmap(asus_rcba_base);
1576 asus_rcba_base = NULL;
7506dc79 1577 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1578}
e1a2a51e
RW		 1579
1580static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1581{
1582 asus_hides_smbus_lpc_ich6_suspend(dev);
1583 asus_hides_smbus_lpc_ich6_resume_early(dev);
1584 asus_hides_smbus_lpc_ich6_resume(dev);
1585}
652c538e 1586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1587DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1588DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1590
82e1719c 1591/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1597cacb 1592static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1593{
1594 u8 val = 0;
1da177e4 1595 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1596 if (val & 0x10) {
7506dc79 1597 pci_info(dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1598 pci_write_config_byte(dev, 0x77, val & ~0x10);
1599 }
1da177e4 1600}
652c538e
AM		 1601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1604DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1605DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1606DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1607DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1608DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1609
1da177e4
LT		 1610/*
1611 * ... This is further complicated by the fact that some SiS96x south
1612 * bridges pretend to be 85C503/5513 instead. In that case see if we
1613 * spotted a compatible north bridge to make sure.
82e1719c 1614 * (pci_find_device() doesn't work yet)
1da177e4
LT		 1615 *
1616 * We can also enable the sis96x bit in the discovery register..
1617 */
1da177e4
LT		 1618#define SIS_DETECT_REGISTER 0x40
1619
1597cacb 1620static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1621{
1622 u8 reg;
1623 u16 devid;
1624
1625 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1626 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1627 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1628 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1629 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1630 return;
1631 }
1632
1da177e4 1633 /*
82e1719c
BH		 1634 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1635 * it has already been processed. (Depends on link order, which is
1636 * apparently not guaranteed)
1da177e4
LT		 1637 */
1638 dev->device = devid;
2f5c33b3 1639 quirk_sis_96x_smbus(dev);
1da177e4 1640}
652c538e 1641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1642DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1643
e5548e96
BJD		 1644/*
1645 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1646 * and MC97 modem controller are disabled when a second PCI soundcard is
1647 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1648 * -- bjd
1649 */
1597cacb 1650static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1651{
1652 u8 val;
1653 int asus_hides_ac97 = 0;
1654
1655 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1656 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1657 asus_hides_ac97 = 1;
1658 }
1659
1660 if (!asus_hides_ac97)
1661 return;
1662
1663 pci_read_config_byte(dev, 0x50, &val);
1664 if (val & 0xc0) {
1665 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1666 pci_read_config_byte(dev, 0x50, &val);
1667 if (val & 0xc0)
7506dc79 1668 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
227f0647 1669 val);
e5548e96 1670 else
7506dc79 1671 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1672 }
1673}
652c538e 1674DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1675DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1676
77967052 1677#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1678
1679/*
82e1719c
BH		 1680 * If we are using libata we can drive this chip properly but must do this
1681 * early on to make the additional device appear during the PCI scanning.
15e0c694 1682 */
5ee2ae7f 1683static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1684{
e34bb370 1685 u32 conf1, conf5, class;
15e0c694
AC		 1686 u8 hdr;
1687
1688 /* Only poke fn 0 */
1689 if (PCI_FUNC(pdev->devfn))
1690 return;
1691
5ee2ae7f
TH		 1692 pci_read_config_dword(pdev, 0x40, &conf1);
1693 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1694
5ee2ae7f
TH		 1695 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1696 conf5 &= ~(1 << 24); /* Clear bit 24 */
1697
1698 switch (pdev->device) {
4daedcfe
TH		 1699 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1700 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
5b6ae5ba 1701 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
5ee2ae7f
TH		 1702 /* The controller should be in single function ahci mode */
1703 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1704 break;
1705
1706 case PCI_DEVICE_ID_JMICRON_JMB365:
1707 case PCI_DEVICE_ID_JMICRON_JMB366:
1708 /* Redirect IDE second PATA port to the right spot */
1709 conf5 |= (1 << 24);
1710 /* Fall through */
1711 case PCI_DEVICE_ID_JMICRON_JMB361:
1712 case PCI_DEVICE_ID_JMICRON_JMB363:
5b6ae5ba 1713 case PCI_DEVICE_ID_JMICRON_JMB369:
5ee2ae7f
TH		 1714 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1715 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1716 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1717 break;
1718
1719 case PCI_DEVICE_ID_JMICRON_JMB368:
1720 /* The controller should be in single function IDE mode */
1721 conf1 |= 0x00C00000; /* Set 22, 23 */
1722 break;
15e0c694 1723 }
5ee2ae7f
TH		 1724
1725 pci_write_config_dword(pdev, 0x40, conf1);
1726 pci_write_config_dword(pdev, 0x80, conf5);
1727
1728 /* Update pdev accordingly */
1729 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1730 pdev->hdr_type = hdr & 0x7f;
1731 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1732
1733 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1734 pdev->class = class >> 8;
15e0c694 1735}
5ee2ae7f
TH		 1736DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1737DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1738DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
5ee2ae7f 1739DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1740DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
5ee2ae7f
TH		 1741DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1742DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1743DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1744DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
e1a2a51e
RW		 1745DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1746DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1747DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
e1a2a51e 1748DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1749DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
e1a2a51e
RW		 1750DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1751DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1753DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
15e0c694
AC		 1754
1755#endif
1756
91f15fb3
ZR		 1757static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1758{
1759 if (dev->multifunction) {
1760 device_disable_async_suspend(&dev->dev);
7506dc79 1761 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
91f15fb3
ZR		 1762 }
1763}
1764DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1765DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1767DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1768
1da177e4 1769#ifdef CONFIG_X86_IO_APIC
15856ad5 1770static void quirk_alder_ioapic(struct pci_dev *pdev)
1da177e4
LT		 1771{
1772 int i;
1773
1774 if ((pdev->class >> 8) != 0xff00)
1775 return;
1776
82e1719c
BH		 1777 /*
1778 * The first BAR is the location of the IO-APIC... we must
1da177e4 1779 * not touch this (and it's already covered by the fixmap), so
82e1719c
BH		 1780 * forcibly insert it into the resource tree.
1781 */
1da177e4
LT		 1782 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1783 insert_resource(&iomem_resource, &pdev->resource[0]);
1784
82e1719c
BH		 1785 /*
1786 * The next five BARs all seem to be rubbish, so just clean
1787 * them out.
1788 */
3c78bc61 1789 for (i = 1; i < 6; i++)
1da177e4 1790 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1da177e4 1791}
652c538e 1792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1793#endif
1794
15856ad5 1795static void quirk_pcie_mch(struct pci_dev *pdev)
1da177e4 1796{
0ba379ec 1797 pdev->no_msi = 1;
1da177e4 1798}
652c538e
AM		 1799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1800DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1801DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1802
deb86999 1803DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
4602b88d
KA		 1804
1805/*
82e1719c
BH		 1806 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1807 * together on certain PXH-based systems.
4602b88d 1808 */
15856ad5 1809static void quirk_pcie_pxh(struct pci_dev *dev)
4602b88d 1810{
4602b88d 1811 dev->no_msi = 1;
7506dc79 1812 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1813}
1814DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1815DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1816DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1817DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1818DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1819
ffadcc2f 1820/*
82e1719c
BH		 1821 * Some Intel PCI Express chipsets have trouble with downstream device
1822 * power management.
ffadcc2f 1823 */
3c78bc61 1824static void quirk_intel_pcie_pm(struct pci_dev *dev)
ffadcc2f
KCA		 1825{
1826 pci_pm_d3_delay = 120;
1827 dev->no_d1d2 = 1;
1828}
ffadcc2f
KCA		 1829DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1830DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1831DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1832DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1833DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1835DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1836DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1837DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1838DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1839DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1840DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1841DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1842DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1843DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1844DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1845DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1847DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1848DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1850
5938628c
BH		 1851static void quirk_radeon_pm(struct pci_dev *dev)
1852{
1853 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1854 dev->subsystem_device == 0x00e2) {
1855 if (dev->d3_delay < 20) {
1856 dev->d3_delay = 20;
7506dc79 1857 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
5938628c
BH		 1858 dev->d3_delay);
1859 }
1860 }
1861}
1862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1863
426b3b8d 1864#ifdef CONFIG_X86_IO_APIC
c4e649b0
SA		 1865static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1866{
1867 noioapicreroute = 1;
1868 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1869
1870 return 0;
1871}
1872
6faadbbb 1873static const struct dmi_system_id boot_interrupt_dmi_table[] = {
c4e649b0
SA		 1874 /*
1875 * Systems to exclude from boot interrupt reroute quirks
1876 */
1877 {
1878 .callback = dmi_disable_ioapicreroute,
1879 .ident = "ASUSTek Computer INC. M2N-LR",
1880 .matches = {
1881 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1882 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1883 },
1884 },
1885 {}
1886};
1887
e1d3a908
SA		 1888/*
1889 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
82e1719c 1890 * remap the original interrupt in the Linux kernel to the boot interrupt, so
e1d3a908
SA		 1891 * that a PCI device's interrupt handler is installed on the boot interrupt
1892 * line instead.
1893 */
1894static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1895{
c4e649b0 1896 dmi_check_system(boot_interrupt_dmi_table);
41b9eb26 1897 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1898 return;
1899
1900 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
7506dc79 1901 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
fdcdaf6c 1902 dev->vendor, dev->device);
e1d3a908 1903}
88d1dce3
OD		 1904DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1905DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1906DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1907DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1912DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1913DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1914DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1915DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1916DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1917DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1918DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1919DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1920
426b3b8d
SA		 1921/*
1922 * On some chipsets we can disable the generation of legacy INTx boot
1923 * interrupts.
1924 */
1925
1926/*
82e1719c 1927 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
426b3b8d
SA		 1928 * 300641-004US, section 5.7.3.
1929 */
1930#define INTEL_6300_IOAPIC_ABAR 0x40
1931#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1932
1933static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1934{
1935 u16 pci_config_word;
1936
1937 if (noioapicquirk)
1938 return;
1939
1940 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1941 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1942 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1943
7506dc79 1944 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
fdcdaf6c 1945 dev->vendor, dev->device);
426b3b8d 1946}
f7625980
BH		 1947DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1948DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188 1949
82e1719c 1950/* Disable boot interrupts on HT-1000 */
77251188
OD		 1951#define BC_HT1000_FEATURE_REG 0x64
1952#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1953#define BC_HT1000_MAP_IDX 0xC00
1954#define BC_HT1000_MAP_DATA 0xC01
1955
1956static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1957{
1958 u32 pci_config_dword;
1959 u8 irq;
1960
1961 if (noioapicquirk)
1962 return;
1963
1964 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1965 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1966 BC_HT1000_PIC_REGS_ENABLE);
1967
1968 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1969 outb(irq, BC_HT1000_MAP_IDX);
1970 outb(0x00, BC_HT1000_MAP_DATA);
1971 }
1972
1973 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1974
7506dc79 1975 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
fdcdaf6c 1976 dev->vendor, dev->device);
77251188 1977}
f7625980
BH		 1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1979DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da 1980
82e1719c
BH		 1981/* Disable boot interrupts on AMD and ATI chipsets */
1982
542622da
OD		 1983/*
1984 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1985 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1986 * (due to an erratum).
1987 */
1988#define AMD_813X_MISC 0x40
1989#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1990#define AMD_813X_REV_B1 0x12
bbe19443 1991#define AMD_813X_REV_B2 0x13
542622da
OD		 1992
1993static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1994{
1995 u32 pci_config_dword;
1996
1997 if (noioapicquirk)
1998 return;
4fd8bdc5
SA		 1999 if ((dev->revision == AMD_813X_REV_B1) ||
2000 (dev->revision == AMD_813X_REV_B2))
bbe19443 2001 return;
542622da
OD		 2002
2003 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2004 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2005 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2006
7506dc79 2007 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
fdcdaf6c 2008 dev->vendor, dev->device);
542622da 2009}
4fd8bdc5
SA		 2010DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2011DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2013DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 2014
2015#define AMD_8111_PCI_IRQ_ROUTING 0x56
2016
2017static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2018{
2019 u16 pci_config_word;
2020
2021 if (noioapicquirk)
2022 return;
2023
2024 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2025 if (!pci_config_word) {
7506dc79 2026 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
227f0647 2027 dev->vendor, dev->device);
542622da
OD		 2028 return;
2029 }
2030 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
7506dc79 2031 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
fdcdaf6c 2032 dev->vendor, dev->device);
542622da 2033}
f7625980
BH		 2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2035DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 2036#endif /* CONFIG_X86_IO_APIC */
2037
33dced2e
SS		 2038/*
2039 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2040 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2041 * Re-allocate the region if needed...
2042 */
15856ad5 2043static void quirk_tc86c001_ide(struct pci_dev *dev)
33dced2e
SS		 2044{
2045 struct resource *r = &dev->resource[0];
2046
2047 if (r->start & 0x8) {
bd064f0a 2048 r->flags |= IORESOURCE_UNSET;
33dced2e
SS		 2049 r->start = 0;
2050 r->end = 0xf;
2051 }
2052}
2053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2054 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2055 quirk_tc86c001_ide);
2056
21c5fd97 2057/*
82e1719c 2058 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
21c5fd97
IA		 2059 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2060 * being read correctly if bit 7 of the base address is set.
2061 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2062 * Re-allocate the regions to a 256-byte boundary if necessary.
2063 */
193c0d68 2064static void quirk_plx_pci9050(struct pci_dev *dev)
21c5fd97
IA		 2065{
2066 unsigned int bar;
2067
2068 /* Fixed in revision 2 (PCI 9052). */
2069 if (dev->revision >= 2)
2070 return;
2071 for (bar = 0; bar <= 1; bar++)
2072 if (pci_resource_len(dev, bar) == 0x80 &&
2073 (pci_resource_start(dev, bar) & 0x80)) {
2074 struct resource *r = &dev->resource[bar];
7506dc79 2075 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
21c5fd97 2076 bar);
bd064f0a 2077 r->flags |= IORESOURCE_UNSET;
21c5fd97
IA		 2078 r->start = 0;
2079 r->end = 0xff;
2080 }
2081}
2082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2083 quirk_plx_pci9050);
2794bb28
IA		 2084/*
2085 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2086 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2087 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2088 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2089 *
2090 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2091 * driver.
2092 */
2093DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2094DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
21c5fd97 2095
15856ad5 2096static void quirk_netmos(struct pci_dev *dev)
1da177e4
LT		 2097{
2098 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2099 unsigned int num_serial = dev->subsystem_device & 0xf;
2100
2101 /*
2102 * These Netmos parts are multiport serial devices with optional
2103 * parallel ports. Even when parallel ports are present, they
2104 * are identified as class SERIAL, which means the serial driver
2105 * will claim them. To prevent this, mark them as class OTHER.
2106 * These combo devices should be claimed by parport_serial.
2107 *
2108 * The subdevice ID is of the form 0x00PS, where <P> is the number
2109 * of parallel ports and <S> is the number of serial ports.
2110 */
2111 switch (dev->device) {
4c9c1686
JS		 2112 case PCI_DEVICE_ID_NETMOS_9835:
2113 /* Well, this rule doesn't hold for the following 9835 device */
2114 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2115 dev->subsystem_device == 0x0299)
2116 return;
d6488ac1 2117 /* else: fall through */
1da177e4
LT		 2118 case PCI_DEVICE_ID_NETMOS_9735:
2119 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 2120 case PCI_DEVICE_ID_NETMOS_9845:
2121 case PCI_DEVICE_ID_NETMOS_9855:
08803efe 2122 if (num_parallel) {
7506dc79 2123 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1da177e4
LT		 2124 dev->device, num_parallel, num_serial);
2125 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2126 (dev->class & 0xff);
2127 }
2128 }
2129}
08803efe
YL		 2130DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2131 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1da177e4 2132
15856ad5 2133static void quirk_e100_interrupt(struct pci_dev *dev)
16a74744 2134{
e64aeccb 2135 u16 command, pmcsr;
16a74744
BH		 2136 u8 __iomem *csr;
2137 u8 cmd_hi;
2138
2139 switch (dev->device) {
2140 /* PCI IDs taken from drivers/net/e100.c */
2141 case 0x1029:
2142 case 0x1030 ... 0x1034:
2143 case 0x1038 ... 0x103E:
2144 case 0x1050 ... 0x1057:
2145 case 0x1059:
2146 case 0x1064 ... 0x106B:
2147 case 0x1091 ... 0x1095:
2148 case 0x1209:
2149 case 0x1229:
2150 case 0x2449:
2151 case 0x2459:
2152 case 0x245D:
2153 case 0x27DC:
2154 break;
2155 default:
2156 return;
2157 }
2158
2159 /*
2160 * Some firmware hands off the e100 with interrupts enabled,
2161 * which can cause a flood of interrupts if packets are
2162 * received before the driver attaches to the device. So
2163 * disable all e100 interrupts here. The driver will
2164 * re-enable them when it's ready.
2165 */
2166 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 2167
1bef7dc0 2168 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 2169 return;
2170
e64aeccb
IK		 2171 /*
2172 * Check that the device is in the D0 power state. If it's not,
2173 * there is no point to look any further.
2174 */
728cdb75
YW		 2175 if (dev->pm_cap) {
2176 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
e64aeccb
IK		 2177 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2178 return;
2179 }
2180
1bef7dc0
BH		 2181 /* Convert from PCI bus to resource space. */
2182 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 2183 if (!csr) {
7506dc79 2184 pci_warn(dev, "Can't map e100 registers\n");
16a74744
BH		 2185 return;
2186 }
2187
2188 cmd_hi = readb(csr + 3);
2189 if (cmd_hi == 0) {
7506dc79 2190 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
16a74744
BH		 2191 writeb(1, csr + 3);
2192 }
2193
2194 iounmap(csr);
2195}
4c5b28e2
YL		 2196DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2197 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
a5312e28 2198
649426ef
AD		 2199/*
2200 * The 82575 and 82598 may experience data corruption issues when transitioning
96291d56 2201 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
649426ef 2202 */
15856ad5 2203static void quirk_disable_aspm_l0s(struct pci_dev *dev)
649426ef 2204{
7506dc79 2205 pci_info(dev, "Disabling L0s\n");
649426ef
AD		 2206 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2207}
2208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2222
15856ad5 2223static void fixup_rev1_53c810(struct pci_dev *dev)
a5312e28 2224{
e6323e3c
BH		 2225 u32 class = dev->class;
2226
2227 /*
2228 * rev 1 ncr53c810 chips don't set the class at all which means
a5312e28
IK		 2229 * they don't get their resources remapped. Fix that here.
2230 */
e6323e3c
BH		 2231 if (class)
2232 return;
a5312e28 2233
e6323e3c 2234 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
7506dc79 2235 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
e6323e3c 2236 class, dev->class);
a5312e28
IK		 2237}
2238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2239
9d265124 2240/* Enable 1k I/O space granularity on the Intel P64H2 */
15856ad5 2241static void quirk_p64h2_1k_io(struct pci_dev *dev)
9d265124
DY		 2242{
2243 u16 en1k;
9d265124
DY		 2244
2245 pci_read_config_word(dev, 0x40, &en1k);
2246
2247 if (en1k & 0x200) {
7506dc79 2248 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2b28ae19 2249 dev->io_window_1k = 1;
9d265124
DY		 2250 }
2251}
82e1719c 2252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
9d265124 2253
82e1719c
BH		 2254/*
2255 * Under some circumstances, AER is not linked with extended capabilities.
cf34a8e0
BG		 2256 * Force it to be linked by setting the corresponding control bit in the
2257 * config space.
2258 */
1597cacb 2259static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 2260{
2261 uint8_t b;
82e1719c 2262
cf34a8e0
BG		 2263 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2264 if (!(b & 0x20)) {
2265 pci_write_config_byte(dev, 0xf41, b | 0x20);
7506dc79 2266 pci_info(dev, "Linking AER extended capability\n");
cf34a8e0
BG		 2267 }
2268 }
2269}
2270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2271 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 2272DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 2273 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 2274
15856ad5 2275static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
53a9bf42
TY		 2276{
2277 /*
2278 * Disable PCI Bus Parking and PCI Master read caching on CX700
2279 * which causes unspecified timing errors with a VT6212L on the PCI
ca846392
TY		 2280 * bus leading to USB2.0 packet loss.
2281 *
2282 * This quirk is only enabled if a second (on the external PCI bus)
2283 * VT6212L is found -- the CX700 core itself also contains a USB
2284 * host controller with the same PCI ID as the VT6212L.
53a9bf42
TY		 2285 */
2286
ca846392
TY		 2287 /* Count VT6212L instances */
2288 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2289 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
53a9bf42 2290 uint8_t b;
ca846392 2291
82e1719c
BH		 2292 /*
2293 * p should contain the first (internal) VT6212L -- see if we have
2294 * an external one by searching again.
2295 */
ca846392
TY		 2296 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2297 if (!p)
2298 return;
2299 pci_dev_put(p);
2300
53a9bf42
TY		 2301 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2302 if (b & 0x40) {
2303 /* Turn off PCI Bus Parking */
2304 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2305
7506dc79 2306 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
bc043274
TY		 2307 }
2308 }
2309
2310 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2311 if (b != 0) {
53a9bf42
TY		 2312 /* Turn off PCI Master read caching */
2313 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 2314
2315 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2316 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2317
2318 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2319 pci_write_config_byte(dev, 0x77, 0x0);
2320
7506dc79 2321 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2322 }
2323 }
2324}
ca846392 2325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
53a9bf42 2326
25e742b2 2327static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
0b471506
MC		 2328{
2329 u32 rev;
2330
2331 pci_read_config_dword(dev, 0xf4, &rev);
2332
2333 /* Only CAP the MRRS if the device is a 5719 A0 */
2334 if (rev == 0x05719000) {
2335 int readrq = pcie_get_readrq(dev);
2336 if (readrq > 2048)
2337 pcie_set_readrq(dev, 2048);
2338 }
2339}
0b471506
MC		 2340DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2341 PCI_DEVICE_ID_TIGON3_5719,
2342 quirk_brcm_5719_limit_mrrs);
2343
ce709f86
JM		 2344#ifdef CONFIG_PCIE_IPROC_PLATFORM
2345static void quirk_paxc_bridge(struct pci_dev *pdev)
2346{
82e1719c
BH		 2347 /*
2348 * The PCI config space is shared with the PAXC root port and the first
ce709f86
JM		 2349 * Ethernet device. So, we need to workaround this by telling the PCI
2350 * code that the bridge is not an Ethernet device.
2351 */
2352 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2353 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2354
82e1719c
BH		 2355 /*
2356 * MPSS is not being set properly (as it is currently 0). This is
ce709f86
JM		 2357 * because that area of the PCI config space is hard coded to zero, and
2358 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2359 * so that the MPS can be set to the real max value.
2360 */
2361 pdev->pcie_mpss = 2;
2362}
2363DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2364DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
b95e2cd0
RJ		 2365DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
2366DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
2367DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
ce709f86
JM		 2368#endif
2369
82e1719c
BH		 2370/*
2371 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2372 * hide device 6 which configures the overflow device access containing the
2373 * DRBs - this is where we expose device 6.
26c56dc0
MM		 2374 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2375 */
15856ad5 2376static void quirk_unhide_mch_dev6(struct pci_dev *dev)
26c56dc0
MM		 2377{
2378 u8 reg;
2379
2380 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
7506dc79 2381 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
26c56dc0
MM		 2382 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2383 }
2384}
26c56dc0
MM		 2385DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2386 quirk_unhide_mch_dev6);
2387DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2388 quirk_unhide_mch_dev6);
2389
3f79e107 2390#ifdef CONFIG_PCI_MSI
82e1719c
BH		 2391/*
2392 * Some chipsets do not support MSI. We cannot easily rely on setting
2393 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2394 * other buses controlled by the chipset even if Linux is not aware of it.
2395 * Instead of setting the flag on all buses in the machine, simply disable
2396 * MSI globally.
3f79e107 2397 */
15856ad5 2398static void quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2399{
88187dfa 2400 pci_no_msi();
7506dc79 2401 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2402}
ebdf7d39
TH		 2403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
549e1561 2409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
10b4ad1a 2410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
3f79e107
BG		 2411
2412/* Disable MSI on chipsets that are known to not support it */
15856ad5 2413static void quirk_disable_msi(struct pci_dev *dev)
3f79e107
BG		 2414{
2415 if (dev->subordinate) {
7506dc79 2416 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
3f79e107
BG		 2417 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2418 }
2419}
2420DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
134b3450 2421DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
9313ff45 2422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
6397c75c 2423
aff61369
CL		 2424/*
2425 * The APC bridge device in AMD 780 family northbridges has some random
2426 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2427 * we use the possible vendor/device IDs of the host bridge for the
2428 * declared quirk, and search for the APC bridge by slot number.
2429 */
15856ad5 2430static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
aff61369
CL		 2431{
2432 struct pci_dev *apc_bridge;
2433
2434 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2435 if (apc_bridge) {
2436 if (apc_bridge->device == 0x9602)
2437 quirk_disable_msi(apc_bridge);
2438 pci_dev_put(apc_bridge);
2439 }
2440}
2441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2443
82e1719c
BH		 2444/*
2445 * Go through the list of HyperTransport capabilities and return 1 if a HT
2446 * MSI capability is found and enabled.
2447 */
25e742b2 2448static int msi_ht_cap_enabled(struct pci_dev *dev)
6397c75c 2449{
fff905f3 2450 int pos, ttl = PCI_FIND_CAP_TTL;
7a380507
ME		 2451
2452 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2453 while (pos && ttl--) {
2454 u8 flags;
2455
2456 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
3c78bc61 2457 &flags) == 0) {
7506dc79 2458 pci_info(dev, "Found %s HT MSI Mapping\n",
7a380507 2459 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2460 "enabled" : "disabled");
7a380507 2461 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2462 }
7a380507
ME		 2463
2464 pos = pci_find_next_ht_capability(dev, pos,
2465 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2466 }
2467 return 0;
2468}
2469
82e1719c 2470/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
25e742b2 2471static void quirk_msi_ht_cap(struct pci_dev *dev)
6397c75c
BG		 2472{
2473 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
7506dc79 2474 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
6397c75c
BG		 2475 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2476 }
2477}
2478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2479 quirk_msi_ht_cap);
6bae1d96 2480
82e1719c
BH		 2481/*
2482 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2483 * if the MSI capability is set in any of these mappings.
6397c75c 2484 */
25e742b2 2485static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
6397c75c
BG		 2486{
2487 struct pci_dev *pdev;
2488
2489 if (!dev->subordinate)
2490 return;
2491
82e1719c
BH		 2492 /*
2493 * Check HT MSI cap on this chipset and the root one. A single one
2494 * having MSI is enough to be sure that MSI is supported.
6397c75c 2495 */
11f242f0 2496 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2497 if (!pdev)
2498 return;
0c875c28 2499 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
7506dc79 2500 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
6397c75c
BG		 2501 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2502 }
11f242f0 2503 pci_dev_put(pdev);
6397c75c
BG		 2504}
2505DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2506 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2507
415b6d0e 2508/* Force enable MSI mapping capability on HT bridges */
25e742b2 2509static void ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7 2510{
fff905f3 2511 int pos, ttl = PCI_FIND_CAP_TTL;
9dc625e7
PC		 2512
2513 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2514 while (pos && ttl--) {
2515 u8 flags;
2516
2517 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2518 &flags) == 0) {
7506dc79 2519 pci_info(dev, "Enabling HT MSI Mapping\n");
9dc625e7
PC		 2520
2521 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2522 flags | HT_MSI_FLAGS_ENABLE);
2523 }
2524 pos = pci_find_next_ht_capability(dev, pos,
2525 HT_CAPTYPE_MSI_MAPPING);
2526 }
2527}
415b6d0e
BH		 2528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2529 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2530 ht_enable_msi_mapping);
e0ae4f55
YL		 2531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2532 ht_enable_msi_mapping);
2533
82e1719c
BH		 2534/*
2535 * The P5N32-SLI motherboards from Asus have a problem with MSI
2536 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2537 * also affects other devices. As for now, turn off MSI for this device.
75e07fc3 2538 */
15856ad5 2539static void nvenet_msi_disable(struct pci_dev *dev)
75e07fc3 2540{
9251bac9
JD		 2541 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2542
2543 if (board_name &&
2544 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2545 strstr(board_name, "P5N32-E SLI"))) {
7506dc79 2546 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
75e07fc3
AP		 2547 dev->no_msi = 1;
2548 }
2549}
2550DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2551 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2552 nvenet_msi_disable);
2553
66db60ea 2554/*
f7625980
BH		 2555 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2556 * config register. This register controls the routing of legacy
2557 * interrupts from devices that route through the MCP55. If this register
2558 * is misprogrammed, interrupts are only sent to the BSP, unlike
2559 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2560 * having this register set properly prevents kdump from booting up
2561 * properly, so let's make sure that we have it set correctly.
2562 * Note that this is an undocumented register.
66db60ea 2563 */
15856ad5 2564static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
66db60ea
NH		 2565{
2566 u32 cfg;
2567
49c2fa08
NH		 2568 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2569 return;
2570
66db60ea
NH		 2571 pci_read_config_dword(dev, 0x74, &cfg);
2572
2573 if (cfg & ((1 << 2) | (1 << 15))) {
82e1719c 2574 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
66db60ea
NH		 2575 cfg &= ~((1 << 2) | (1 << 15));
2576 pci_write_config_dword(dev, 0x74, cfg);
2577 }
2578}
66db60ea
NH		 2579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2580 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2581 nvbridge_check_legacy_irq_routing);
66db60ea
NH		 2582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2583 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2584 nvbridge_check_legacy_irq_routing);
2585
25e742b2 2586static int ht_check_msi_mapping(struct pci_dev *dev)
de745306 2587{
fff905f3 2588 int pos, ttl = PCI_FIND_CAP_TTL;
de745306
YL		 2589 int found = 0;
2590
82e1719c 2591 /* Check if there is HT MSI cap or enabled on this device */
de745306
YL		 2592 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2593 while (pos && ttl--) {
2594 u8 flags;
2595
2596 if (found < 1)
2597 found = 1;
2598 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2599 &flags) == 0) {
2600 if (flags & HT_MSI_FLAGS_ENABLE) {
2601 if (found < 2) {
2602 found = 2;
2603 break;
2604 }
2605 }
2606 }
2607 pos = pci_find_next_ht_capability(dev, pos,
2608 HT_CAPTYPE_MSI_MAPPING);
2609 }
2610
2611 return found;
2612}
2613
25e742b2 2614static int host_bridge_with_leaf(struct pci_dev *host_bridge)
de745306
YL		 2615{
2616 struct pci_dev *dev;
2617 int pos;
2618 int i, dev_no;
2619 int found = 0;
2620
2621 dev_no = host_bridge->devfn >> 3;
2622 for (i = dev_no + 1; i < 0x20; i++) {
2623 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2624 if (!dev)
2625 continue;
2626
82e1719c 2627 /* found next host bridge? */
de745306
YL		 2628 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2629 if (pos != 0) {
2630 pci_dev_put(dev);
2631 break;
2632 }
2633
2634 if (ht_check_msi_mapping(dev)) {
2635 found = 1;
2636 pci_dev_put(dev);
2637 break;
2638 }
2639 pci_dev_put(dev);
2640 }
2641
2642 return found;
2643}
2644
eeafda70
YL		 2645#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2646#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2647
25e742b2 2648static int is_end_of_ht_chain(struct pci_dev *dev)
eeafda70
YL		 2649{
2650 int pos, ctrl_off;
2651 int end = 0;
2652 u16 flags, ctrl;
2653
2654 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2655
2656 if (!pos)
2657 goto out;
2658
2659 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2660
2661 ctrl_off = ((flags >> 10) & 1) ?
2662 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2663 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2664
2665 if (ctrl & (1 << 6))
2666 end = 1;
2667
2668out:
2669 return end;
2670}
2671
25e742b2 2672static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2673{
2674 struct pci_dev *host_bridge;
1dec6b05
YL		 2675 int pos;
2676 int i, dev_no;
2677 int found = 0;
2678
2679 dev_no = dev->devfn >> 3;
2680 for (i = dev_no; i >= 0; i--) {
2681 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2682 if (!host_bridge)
2683 continue;
2684
2685 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2686 if (pos != 0) {
2687 found = 1;
2688 break;
2689 }
2690 pci_dev_put(host_bridge);
2691 }
2692
2693 if (!found)
2694 return;
2695
eeafda70
YL		 2696 /* don't enable end_device/host_bridge with leaf directly here */
2697 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2698 host_bridge_with_leaf(host_bridge))
de745306
YL		 2699 goto out;
2700
1dec6b05
YL		 2701 /* root did that ! */
2702 if (msi_ht_cap_enabled(host_bridge))
2703 goto out;
2704
2705 ht_enable_msi_mapping(dev);
2706
2707out:
2708 pci_dev_put(host_bridge);
2709}
2710
25e742b2 2711static void ht_disable_msi_mapping(struct pci_dev *dev)
1dec6b05 2712{
fff905f3 2713 int pos, ttl = PCI_FIND_CAP_TTL;
1dec6b05
YL		 2714
2715 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2716 while (pos && ttl--) {
2717 u8 flags;
2718
2719 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2720 &flags) == 0) {
7506dc79 2721 pci_info(dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2722
2723 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2724 flags & ~HT_MSI_FLAGS_ENABLE);
2725 }
2726 pos = pci_find_next_ht_capability(dev, pos,
2727 HT_CAPTYPE_MSI_MAPPING);
2728 }
2729}
2730
25e742b2 2731static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2732{
2733 struct pci_dev *host_bridge;
2734 int pos;
2735 int found;
2736
3d2a5318
RW		 2737 if (!pci_msi_enabled())
2738 return;
2739
1dec6b05
YL		 2740 /* check if there is HT MSI cap or enabled on this device */
2741 found = ht_check_msi_mapping(dev);
2742
2743 /* no HT MSI CAP */
2744 if (found == 0)
2745 return;
9dc625e7
PC		 2746
2747 /*
2748 * HT MSI mapping should be disabled on devices that are below
2749 * a non-Hypertransport host bridge. Locate the host bridge...
2750 */
39c94652
SK		 2751 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2752 PCI_DEVFN(0, 0));
9dc625e7 2753 if (host_bridge == NULL) {
7506dc79 2754 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
9dc625e7
PC		 2755 return;
2756 }
2757
2758 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2759 if (pos != 0) {
2760 /* Host bridge is to HT */
1dec6b05
YL		 2761 if (found == 1) {
2762 /* it is not enabled, try to enable it */
de745306
YL		 2763 if (all)
2764 ht_enable_msi_mapping(dev);
2765 else
2766 nv_ht_enable_msi_mapping(dev);
1dec6b05 2767 }
dff3aef7 2768 goto out;
9dc625e7
PC		 2769 }
2770
1dec6b05
YL		 2771 /* HT MSI is not enabled */
2772 if (found == 1)
dff3aef7 2773 goto out;
9dc625e7 2774
1dec6b05
YL		 2775 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2776 ht_disable_msi_mapping(dev);
dff3aef7
MS		 2777
2778out:
2779 pci_dev_put(host_bridge);
9dc625e7 2780}
de745306 2781
25e742b2 2782static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
de745306
YL		 2783{
2784 return __nv_msi_ht_cap_quirk(dev, 1);
2785}
82e1719c
BH		 2786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2787DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
de745306 2788
25e742b2 2789static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
de745306
YL		 2790{
2791 return __nv_msi_ht_cap_quirk(dev, 0);
2792}
de745306 2793DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2794DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306 2795
15856ad5 2796static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
ba698ad4
DM		 2797{
2798 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2799}
82e1719c 2800
15856ad5 2801static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
4600c9d7
SH		 2802{
2803 struct pci_dev *p;
2804
82e1719c
BH		 2805 /*
2806 * SB700 MSI issue will be fixed at HW level from revision A21;
4600c9d7
SH		 2807 * we need check PCI REVISION ID of SMBus controller to get SB700
2808 * revision.
2809 */
2810 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2811 NULL);
2812 if (!p)
2813 return;
2814
2815 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2816 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2817 pci_dev_put(p);
2818}
82e1719c 2819
70588818
XH		 2820static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2821{
2822 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2823 if (dev->revision < 0x18) {
7506dc79 2824 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
70588818
XH		 2825 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2826 }
2827}
ba698ad4
DM		 2828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2829 PCI_DEVICE_ID_TIGON3_5780,
2830 quirk_msi_intx_disable_bug);
2831DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2832 PCI_DEVICE_ID_TIGON3_5780S,
2833 quirk_msi_intx_disable_bug);
2834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2835 PCI_DEVICE_ID_TIGON3_5714,
2836 quirk_msi_intx_disable_bug);
2837DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2838 PCI_DEVICE_ID_TIGON3_5714S,
2839 quirk_msi_intx_disable_bug);
2840DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2841 PCI_DEVICE_ID_TIGON3_5715,
2842 quirk_msi_intx_disable_bug);
2843DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2844 PCI_DEVICE_ID_TIGON3_5715S,
2845 quirk_msi_intx_disable_bug);
2846
bc38b411 2847DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2848 quirk_msi_intx_disable_ati_bug);
bc38b411 2849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2850 quirk_msi_intx_disable_ati_bug);
bc38b411 2851DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2852 quirk_msi_intx_disable_ati_bug);
bc38b411 2853DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2854 quirk_msi_intx_disable_ati_bug);
bc38b411 2855DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2856 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2857
2858DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2859 quirk_msi_intx_disable_bug);
2860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2861 quirk_msi_intx_disable_bug);
2862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2863 quirk_msi_intx_disable_bug);
2864
7cb6a291
HX		 2865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2866 quirk_msi_intx_disable_bug);
2867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2868 quirk_msi_intx_disable_bug);
2869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2870 quirk_msi_intx_disable_bug);
2871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2872 quirk_msi_intx_disable_bug);
2873DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2874 quirk_msi_intx_disable_bug);
2875DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2876 quirk_msi_intx_disable_bug);
70588818
XH		 2877DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2878 quirk_msi_intx_disable_qca_bug);
2879DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2880 quirk_msi_intx_disable_qca_bug);
2881DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2882 quirk_msi_intx_disable_qca_bug);
2883DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2884 quirk_msi_intx_disable_qca_bug);
2885DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2886 quirk_msi_intx_disable_qca_bug);
3f79e107 2887#endif /* CONFIG_PCI_MSI */
3d137310 2888
82e1719c
BH		 2889/*
2890 * Allow manual resource allocation for PCI hotplug bridges via
2891 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2892 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2893 * allocate resources when hotplug device is inserted and PCI bus is
2894 * rescanned.
3322340a 2895 */
15856ad5 2896static void quirk_hotplug_bridge(struct pci_dev *dev)
3322340a
FR		 2897{
2898 dev->is_hotplug_bridge = 1;
2899}
3322340a
FR		 2900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2901
03cd8f7e 2902/*
82e1719c
BH		 2903 * This is a quirk for the Ricoh MMC controller found as a part of some
2904 * multifunction chips.
2905 *
25985edc 2906 * This is very similar and based on the ricoh_mmc driver written by
03cd8f7e
ML		 2907 * Philip Langdale. Thank you for these magic sequences.
2908 *
82e1719c
BH		 2909 * These chips implement the four main memory card controllers (SD, MMC,
2910 * MS, xD) and one or both of CardBus or FireWire.
03cd8f7e 2911 *
82e1719c
BH		 2912 * It happens that they implement SD and MMC support as separate
2913 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
2914 * cards but the chip detects MMC cards in hardware and directs them to the
2915 * MMC controller - so the SDHCI driver never sees them.
03cd8f7e 2916 *
82e1719c
BH		 2917 * To get around this, we must disable the useless MMC controller. At that
2918 * point, the SDHCI controller will start seeing them. It seems to be the
2919 * case that the relevant PCI registers to deactivate the MMC controller
2920 * live on PCI function 0, which might be the CardBus controller or the
2921 * FireWire controller, depending on the particular chip in question
03cd8f7e
ML		 2922 *
2923 * This has to be done early, because as soon as we disable the MMC controller
82e1719c
BH		 2924 * other PCI functions shift up one level, e.g. function #2 becomes function
2925 * #1, and this will confuse the PCI core.
03cd8f7e 2926 */
03cd8f7e
ML		 2927#ifdef CONFIG_MMC_RICOH_MMC
2928static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2929{
03cd8f7e
ML		 2930 u8 write_enable;
2931 u8 write_target;
2932 u8 disable;
2933
82e1719c
BH		 2934 /*
2935 * Disable via CardBus interface
2936 *
2937 * This must be done via function #0
2938 */
03cd8f7e
ML		 2939 if (PCI_FUNC(dev->devfn))
2940 return;
2941
2942 pci_read_config_byte(dev, 0xB7, &disable);
2943 if (disable & 0x02)
2944 return;
2945
2946 pci_read_config_byte(dev, 0x8E, &write_enable);
2947 pci_write_config_byte(dev, 0x8E, 0xAA);
2948 pci_read_config_byte(dev, 0x8D, &write_target);
2949 pci_write_config_byte(dev, 0x8D, 0xB7);
2950 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2951 pci_write_config_byte(dev, 0x8E, write_enable);
2952 pci_write_config_byte(dev, 0x8D, write_target);
2953
82e1719c 2954 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
7506dc79 2955 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
03cd8f7e
ML		 2956}
2957DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2958DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2959
2960static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2961{
03cd8f7e
ML		 2962 u8 write_enable;
2963 u8 disable;
2964
82e1719c
BH		 2965 /*
2966 * Disable via FireWire interface
2967 *
2968 * This must be done via function #0
2969 */
03cd8f7e
ML		 2970 if (PCI_FUNC(dev->devfn))
2971 return;
15bed0f2 2972 /*
812089e0 2973 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
82e1719c
BH		 2974 * certain types of SD/MMC cards. Lowering the SD base clock
2975 * frequency from 200Mhz to 50Mhz fixes this issue.
15bed0f2
MI		 2976 *
2977 * 0x150 - SD2.0 mode enable for changing base clock
2978 * frequency to 50Mhz
2979 * 0xe1 - Base clock frequency
2980 * 0x32 - 50Mhz new clock frequency
2981 * 0xf9 - Key register for 0x150
2982 * 0xfc - key register for 0xe1
2983 */
812089e0
AL		 2984 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2985 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
15bed0f2
MI		 2986 pci_write_config_byte(dev, 0xf9, 0xfc);
2987 pci_write_config_byte(dev, 0x150, 0x10);
2988 pci_write_config_byte(dev, 0xf9, 0x00);
2989 pci_write_config_byte(dev, 0xfc, 0x01);
2990 pci_write_config_byte(dev, 0xe1, 0x32);
2991 pci_write_config_byte(dev, 0xfc, 0x00);
2992
7506dc79 2993 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
15bed0f2 2994 }
3e309cdf
JB		 2995
2996 pci_read_config_byte(dev, 0xCB, &disable);
2997
2998 if (disable & 0x02)
2999 return;
3000
3001 pci_read_config_byte(dev, 0xCA, &write_enable);
3002 pci_write_config_byte(dev, 0xCA, 0x57);
3003 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3004 pci_write_config_byte(dev, 0xCA, write_enable);
3005
82e1719c 3006 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
7506dc79 3007 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3e309cdf 3008
03cd8f7e
ML		 3009}
3010DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3011DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
812089e0
AL		 3012DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3013DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
be98ca65
MI		 3014DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3015DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
03cd8f7e
ML		 3016#endif /*CONFIG_MMC_RICOH_MMC*/
3017
d3f13810 3018#ifdef CONFIG_DMAR_TABLE
254e4200
SS		 3019#define VTUNCERRMSK_REG 0x1ac
3020#define VTD_MSK_SPEC_ERRORS (1 << 31)
3021/*
82e1719c
BH		 3022 * This is a quirk for masking VT-d spec-defined errors to platform error
3023 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
254e4200 3024 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
82e1719c 3025 * on the RAS config settings of the platform) when a VT-d fault happens.
254e4200
SS		 3026 * The resulting SMI caused the system to hang.
3027 *
82e1719c 3028 * VT-d spec-related errors are already handled by the VT-d OS code, so no
254e4200
SS		 3029 * need to report the same error through other channels.
3030 */
3031static void vtd_mask_spec_errors(struct pci_dev *dev)
3032{
3033 u32 word;
3034
3035 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3036 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3037}
3038DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3039DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3040#endif
03cd8f7e 3041
15856ad5 3042static void fixup_ti816x_class(struct pci_dev *dev)
63c44080 3043{
d1541dc9
BH		 3044 u32 class = dev->class;
3045
63c44080 3046 /* TI 816x devices do not have class code set when in PCIe boot mode */
d1541dc9 3047 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
7506dc79 3048 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
d1541dc9 3049 class, dev->class);
63c44080 3050}
40c96236 3051DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2b4aed1d 3052 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
63c44080 3053
82e1719c
BH		 3054/*
3055 * Some PCIe devices do not work reliably with the claimed maximum
a94d072b
BH		 3056 * payload size supported.
3057 */
15856ad5 3058static void fixup_mpss_256(struct pci_dev *dev)
a94d072b
BH		 3059{
3060 dev->pcie_mpss = 1; /* 256 bytes */
3061}
3062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3063 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3065 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3067 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3068
82e1719c
BH		 3069/*
3070 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
d387a8d6 3071 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
82e1719c 3072 * Since there is no way of knowing what the PCIe MPS on each fabric will be
d387a8d6
JM		 3073 * until all of the devices are discovered and buses walked, read completion
3074 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3075 * it is possible to hotplug a device with MPS of 256B.
3076 */
15856ad5 3077static void quirk_intel_mc_errata(struct pci_dev *dev)
d387a8d6
JM		 3078{
3079 int err;
3080 u16 rcc;
3081
27d868b5
KB		 3082 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3083 pcie_bus_config == PCIE_BUS_DEFAULT)
d387a8d6
JM		 3084 return;
3085
82e1719c
BH		 3086 /*
3087 * Intel erratum specifies bits to change but does not say what
3088 * they are. Keeping them magical until such time as the registers
3089 * and values can be explained.
d387a8d6
JM		 3090 */
3091 err = pci_read_config_word(dev, 0x48, &rcc);
3092 if (err) {
7506dc79 3093 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
d387a8d6
JM		 3094 return;
3095 }
3096
3097 if (!(rcc & (1 << 10)))
3098 return;
3099
3100 rcc &= ~(1 << 10);
3101
3102 err = pci_write_config_word(dev, 0x48, rcc);
3103 if (err) {
7506dc79 3104 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
d387a8d6
JM		 3105 return;
3106 }
3107
82e1719c 3108 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
d387a8d6
JM		 3109}
3110/* Intel 5000 series memory controllers and ports 2-7 */
3111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3114DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3121DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3125/* Intel 5100 series memory controllers and ports 2-7 */
3126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3129DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3133DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3134DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3137
12b03188 3138/*
82e1719c
BH		 3139 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3140 * To work around this, query the size it should be configured to by the
3141 * device and modify the resource end to correspond to this new size.
12b03188
JM		 3142 */
3143static void quirk_intel_ntb(struct pci_dev *dev)
3144{
3145 int rc;
3146 u8 val;
3147
3148 rc = pci_read_config_byte(dev, 0x00D0, &val);
3149 if (rc)
3150 return;
3151
3152 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3153
3154 rc = pci_read_config_byte(dev, 0x00D1, &val);
3155 if (rc)
3156 return;
3157
3158 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3159}
3160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3161DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3162
f67fd55f 3163/*
82e1719c
BH		 3164 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3165 * though no one is handling them (e.g., if the i915 driver is never
3166 * loaded). Additionally the interrupt destination is not set up properly
f67fd55f
TJ		 3167 * and the interrupt ends up -somewhere-.
3168 *
82e1719c
BH		 3169 * These spurious interrupts are "sticky" and the kernel disables the
3170 * (shared) interrupt line after 100,000+ generated interrupts.
f67fd55f 3171 *
82e1719c
BH		 3172 * Fix it by disabling the still enabled interrupts. This resolves crashes
3173 * often seen on monitor unplug.
f67fd55f
TJ		 3174 */
3175#define I915_DEIER_REG 0x4400c
15856ad5 3176static void disable_igfx_irq(struct pci_dev *dev)
f67fd55f
TJ		 3177{
3178 void __iomem *regs = pci_iomap(dev, 0, 0);
3179 if (regs == NULL) {
7506dc79 3180 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
f67fd55f
TJ		 3181 return;
3182 }
3183
3184 /* Check if any interrupt line is still enabled */
3185 if (readl(regs + I915_DEIER_REG) != 0) {
7506dc79 3186 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
f67fd55f
TJ		 3187
3188 writel(0, regs + I915_DEIER_REG);
3189 }
3190
3191 pci_iounmap(dev, regs);
3192}
d0c9606b
BM		 3193DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
f67fd55f 3196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
d0c9606b 3197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
f67fd55f 3198DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
7c82126a 3199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
f67fd55f 3200
b8cac70a
TB		 3201/*
3202 * PCI devices which are on Intel chips can skip the 10ms delay
3203 * before entering D3 mode.
3204 */
3205static void quirk_remove_d3_delay(struct pci_dev *dev)
3206{
3207 dev->d3_delay = 0;
3208}
cd3e2eb8 3209/* C600 Series devices do not need 10ms d3_delay */
b8cac70a 3210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
cd3e2eb8 3211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
b8cac70a 3212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
cd3e2eb8
AS		 3213/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
b8cac70a
TB		 3215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
cd3e2eb8
AS		 3217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
b8cac70a 3219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
cd3e2eb8
AS		 3220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
b8cac70a 3224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
4a118753
SK		 3225/* Intel Cherrytrail devices do not need 10ms d3_delay */
3226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
cd3e2eb8
AS		 3227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
4a118753 3229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
cd3e2eb8
AS		 3230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
4a118753
SK		 3232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
d76d2fe0 3235
fbebb9fd 3236/*
d76d2fe0 3237 * Some devices may pass our check in pci_intx_mask_supported() if
fbebb9fd
BH		 3238 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3239 * support this feature.
3240 */
15856ad5 3241static void quirk_broken_intx_masking(struct pci_dev *dev)
fbebb9fd
BH		 3242{
3243 dev->broken_intx_masking = 1;
3244}
b88214ce
NO		 3245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3246 quirk_broken_intx_masking);
3247DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3248 quirk_broken_intx_masking);
7c1efb68
BH		 3249DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3250 quirk_broken_intx_masking);
d76d2fe0 3251
3cb30b73
AW		 3252/*
3253 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3254 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3255 *
3256 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3257 */
b88214ce
NO		 3258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3259 quirk_broken_intx_masking);
fbebb9fd 3260
8bcf4525
AW		 3261/*
3262 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3263 * DisINTx can be set but the interrupt status bit is non-functional.
3264 */
82e1719c
BH		 3265DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3267DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3271DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
8bcf4525 3281
d76d2fe0
NO		 3282static u16 mellanox_broken_intx_devs[] = {
3283 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3284 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3285 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3286 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3287 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3288 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3289 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3290 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3291 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3292 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3293 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3294 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3295 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3296 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
d76d2fe0
NO		 3297};
3298
1600f625
NO		 3299#define CONNECTX_4_CURR_MAX_MINOR 99
3300#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3301
3302/*
3303 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3304 * If so, don't mark it as broken.
3305 * FW minor > 99 means older FW version format and no INTx masking support.
3306 * FW minor < 14 means new FW version format and no INTx masking support.
3307 */
d76d2fe0
NO		 3308static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3309{
1600f625
NO		 3310 __be32 __iomem *fw_ver;
3311 u16 fw_major;
3312 u16 fw_minor;
3313 u16 fw_subminor;
3314 u32 fw_maj_min;
3315 u32 fw_sub_min;
d76d2fe0
NO		 3316 int i;
3317
3318 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3319 if (pdev->device == mellanox_broken_intx_devs[i]) {
3320 pdev->broken_intx_masking = 1;
3321 return;
3322 }
3323 }
1600f625 3324
82e1719c
BH		 3325 /*
3326 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
1600f625
NO		 3327 * support so shouldn't be checked further
3328 */
3329 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3330 return;
3331
3332 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3333 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3334 return;
3335
3336 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3337 if (pci_enable_device_mem(pdev)) {
7506dc79 3338 pci_warn(pdev, "Can't enable device memory\n");
1600f625
NO		 3339 return;
3340 }
3341
3342 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3343 if (!fw_ver) {
7506dc79 3344 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
1600f625
NO		 3345 goto out;
3346 }
3347
3348 /* Reading from resource space should be 32b aligned */
3349 fw_maj_min = ioread32be(fw_ver);
3350 fw_sub_min = ioread32be(fw_ver + 1);
3351 fw_major = fw_maj_min & 0xffff;
3352 fw_minor = fw_maj_min >> 16;
3353 fw_subminor = fw_sub_min & 0xffff;
3354 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3355 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
7506dc79 3356 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
1600f625
NO		 3357 fw_major, fw_minor, fw_subminor, pdev->device ==
3358 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3359 pdev->broken_intx_masking = 1;
3360 }
3361
3362 iounmap(fw_ver);
3363
3364out:
3365 pci_disable_device(pdev);
d76d2fe0
NO		 3366}
3367DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3368 mellanox_check_broken_intx_masking);
8bcf4525 3369
c3e59ee4
AW		 3370static void quirk_no_bus_reset(struct pci_dev *dev)
3371{
3372 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3373}
3374
3375/*
9ac0108c
CB		 3376 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3377 * The device will throw a Link Down error on AER-capable systems and
3378 * regardless of AER, config space of the device is never accessible again
3379 * and typically causes the system to hang or reset when access is attempted.
c3e59ee4
AW		 3380 * http://www.spinics.net/lists/linux-pci/msg34797.html
3381 */
3382DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
9ac0108c
CB		 3383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
8e2e0317 3385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
c3e59ee4 3386
82215510
DD		 3387/*
3388 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3389 * reset when used with certain child devices. After the reset, config
3390 * accesses to the child may fail.
3391 */
3392DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3393
d84f3174
AW		 3394static void quirk_no_pm_reset(struct pci_dev *dev)
3395{
3396 /*
3397 * We can't do a bus reset on root bus devices, but an ineffective
3398 * PM reset may be better than nothing.
3399 */
3400 if (!pci_is_root_bus(dev->bus))
3401 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3402}
3403
3404/*
3405 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3406 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3407 * to have no effect on the device: it retains the framebuffer contents and
3408 * monitor sync. Advertising this support makes other layers, like VFIO,
3409 * assume pci_reset_function() is viable for this device. Mark it as
3410 * unavailable to skip it when testing reset methods.
3411 */
3412DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3413 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3414
19bf4d4f
LW		 3415/*
3416 * Thunderbolt controllers with broken MSI hotplug signaling:
3417 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3418 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3419 */
3420static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3421{
3422 if (pdev->is_hotplug_bridge &&
3423 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3424 pdev->revision <= 1))
3425 pdev->no_msi = 1;
3426}
3427DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3428 quirk_thunderbolt_hotplug_msi);
3429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3430 quirk_thunderbolt_hotplug_msi);
3431DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3432 quirk_thunderbolt_hotplug_msi);
3433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3434 quirk_thunderbolt_hotplug_msi);
3435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3436 quirk_thunderbolt_hotplug_msi);
3437
1df5172c
AN		 3438#ifdef CONFIG_ACPI
3439/*
3440 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3441 *
3442 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3443 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3444 * be present after resume if a device was plugged in before suspend.
3445 *
82e1719c
BH		 3446 * The Thunderbolt controller consists of a PCIe switch with downstream
3447 * bridges leading to the NHI and to the tunnel PCI bridges.
1df5172c
AN		 3448 *
3449 * This quirk cuts power to the whole chip. Therefore we have to apply it
3450 * during suspend_noirq of the upstream bridge.
3451 *
3452 * Power is automagically restored before resume. No action is needed.
3453 */
3454static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3455{
3456 acpi_handle bridge, SXIO, SXFP, SXLV;
3457
630b3aff 3458 if (!x86_apple_machine)
1df5172c
AN		 3459 return;
3460 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3461 return;
3462 bridge = ACPI_HANDLE(&dev->dev);
3463 if (!bridge)
3464 return;
82e1719c 3465
1df5172c
AN		 3466 /*
3467 * SXIO and SXLV are present only on machines requiring this quirk.
82e1719c
BH		 3468 * Thunderbolt bridges in external devices might have the same
3469 * device ID as those on the host, but they will not have the
3470 * associated ACPI methods. This implicitly checks that we are at
3471 * the right bridge.
1df5172c
AN		 3472 */
3473 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3474 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3475 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3476 return;
82e1719c 3477 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
1df5172c
AN		 3478
3479 /* magic sequence */
3480 acpi_execute_simple_method(SXIO, NULL, 1);
3481 acpi_execute_simple_method(SXFP, NULL, 0);
3482 msleep(300);
3483 acpi_execute_simple_method(SXLV, NULL, 0);
3484 acpi_execute_simple_method(SXIO, NULL, 0);
3485 acpi_execute_simple_method(SXLV, NULL, 0);
3486}
1d111406
LW		 3487DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3488 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1df5172c
AN		 3489 quirk_apple_poweroff_thunderbolt);
3490
3491/*
82e1719c 3492 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
1df5172c 3493 *
82e1719c 3494 * During suspend the Thunderbolt controller is reset and all PCI
1df5172c
AN		 3495 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3496 * during resume. We have to manually wait for the NHI since there is
3497 * no parent child relationship between the NHI and the tunneled
3498 * bridges.
3499 */
3500static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3501{
3502 struct pci_dev *sibling = NULL;
3503 struct pci_dev *nhi = NULL;
3504
630b3aff 3505 if (!x86_apple_machine)
1df5172c
AN		 3506 return;
3507 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3508 return;
82e1719c 3509
1df5172c 3510 /*
82e1719c
BH		 3511 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3512 * host controller and not on a Thunderbolt endpoint.
1df5172c
AN		 3513 */
3514 sibling = pci_get_slot(dev->bus, 0x0);
3515 if (sibling == dev)
3516 goto out; /* we are the downstream bridge to the NHI */
3517 if (!sibling || !sibling->subordinate)
3518 goto out;
3519 nhi = pci_get_slot(sibling->subordinate, 0x0);
3520 if (!nhi)
3521 goto out;
3522 if (nhi->vendor != PCI_VENDOR_ID_INTEL
19bf4d4f
LW		 3523 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3524 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
82a6a81c 3525 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
1d111406 3526 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
25eb7e5c 3527 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
1df5172c 3528 goto out;
82e1719c 3529 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
1df5172c
AN		 3530 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3531out:
3532 pci_dev_put(nhi);
3533 pci_dev_put(sibling);
3534}
19bf4d4f
LW		 3535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3536 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1df5172c 3537 quirk_apple_wait_for_thunderbolt);
1d111406
LW		 3538DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3539 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1df5172c 3540 quirk_apple_wait_for_thunderbolt);
82a6a81c
XG		 3541DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3542 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3543 quirk_apple_wait_for_thunderbolt);
1d111406
LW		 3544DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3545 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
1df5172c
AN		 3546 quirk_apple_wait_for_thunderbolt);
3547#endif
3548
b9c3b266 3549/*
4091fb95 3550 * Following are device-specific reset methods which can be used to
b9c3b266
DC		 3551 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3552 * not available.
3553 */
c763e7b5
DC		 3554static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3555{
76b57c67
BH		 3556 /*
3557 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3558 *
3559 * The 82599 supports FLR on VFs, but FLR support is reported only
3560 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
c8d8096a
CH		 3561 * Thus we must call pcie_flr() directly without first checking if it is
3562 * supported.
76b57c67 3563 */
c8d8096a
CH		 3564 if (!probe)
3565 pcie_flr(dev);
c763e7b5
DC		 3566 return 0;
3567}
3568
aba72ddc
VS		 3569#define SOUTH_CHICKEN2 0xc2004
3570#define PCH_PP_STATUS 0xc7200
3571#define PCH_PP_CONTROL 0xc7204
df558de1
XH		 3572#define MSG_CTL 0x45010
3573#define NSDE_PWR_STATE 0xd0100
3574#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3575
3576static int reset_ivb_igd(struct pci_dev *dev, int probe)
3577{
3578 void __iomem *mmio_base;
3579 unsigned long timeout;
3580 u32 val;
3581
3582 if (probe)
3583 return 0;
3584
3585 mmio_base = pci_iomap(dev, 0, 0);
3586 if (!mmio_base)
3587 return -ENOMEM;
3588
3589 iowrite32(0x00000002, mmio_base + MSG_CTL);
3590
3591 /*
3592 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3593 * driver loaded sets the right bits. However, this's a reset and
3594 * the bits have been set by i915 previously, so we clobber
3595 * SOUTH_CHICKEN2 register directly here.
3596 */
3597 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3598
3599 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3600 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3601
3602 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3603 do {
3604 val = ioread32(mmio_base + PCH_PP_STATUS);
3605 if ((val & 0xb0000000) == 0)
3606 goto reset_complete;
3607 msleep(10);
3608 } while (time_before(jiffies, timeout));
7506dc79 3609 pci_warn(dev, "timeout during reset\n");
df558de1
XH		 3610
3611reset_complete:
3612 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3613
3614 pci_iounmap(dev, mmio_base);
3615 return 0;
3616}
3617
82e1719c 3618/* Device-specific reset method for Chelsio T4-based adapters */
2c6217e0
CL		 3619static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3620{
3621 u16 old_command;
3622 u16 msix_flags;
3623
3624 /*
3625 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3626 * that we have no device-specific reset method.
3627 */
3628 if ((dev->device & 0xf000) != 0x4000)
3629 return -ENOTTY;
3630
3631 /*
3632 * If this is the "probe" phase, return 0 indicating that we can
3633 * reset this device.
3634 */
3635 if (probe)
3636 return 0;
3637
3638 /*
3639 * T4 can wedge if there are DMAs in flight within the chip and Bus
3640 * Master has been disabled. We need to have it on till the Function
3641 * Level Reset completes. (BUS_MASTER is disabled in
3642 * pci_reset_function()).
3643 */
3644 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3645 pci_write_config_word(dev, PCI_COMMAND,
3646 old_command | PCI_COMMAND_MASTER);
3647
3648 /*
3649 * Perform the actual device function reset, saving and restoring
3650 * configuration information around the reset.
3651 */
3652 pci_save_state(dev);
3653
3654 /*
3655 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3656 * are disabled when an MSI-X interrupt message needs to be delivered.
3657 * So we briefly re-enable MSI-X interrupts for the duration of the
3658 * FLR. The pci_restore_state() below will restore the original
3659 * MSI-X state.
3660 */
3661 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3662 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3663 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3664 msix_flags |
3665 PCI_MSIX_FLAGS_ENABLE |
3666 PCI_MSIX_FLAGS_MASKALL);
3667
48f52d1a 3668 pcie_flr(dev);
2c6217e0
CL		 3669
3670 /*
3671 * Restore the configuration information (BAR values, etc.) including
3672 * the original PCI Configuration Space Command word, and return
3673 * success.
3674 */
3675 pci_restore_state(dev);
3676 pci_write_config_word(dev, PCI_COMMAND, old_command);
3677 return 0;
3678}
3679
c763e7b5 3680#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
df558de1
XH		 3681#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3682#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
c763e7b5 3683
ffb08634
AW		 3684/*
3685 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3686 * FLR where config space reads from the device return -1. We seem to be
3687 * able to avoid this condition if we disable the NVMe controller prior to
3688 * FLR. This quirk is generic for any NVMe class device requiring similar
3689 * assistance to quiesce the device prior to FLR.
3690 *
3691 * NVMe specification: https://nvmexpress.org/resources/specifications/
3692 * Revision 1.0e:
3693 * Chapter 2: Required and optional PCI config registers
3694 * Chapter 3: NVMe control registers
3695 * Chapter 7.3: Reset behavior
3696 */
3697static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3698{
3699 void __iomem *bar;
3700 u16 cmd;
3701 u32 cfg;
3702
3703 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3704 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3705 return -ENOTTY;
3706
3707 if (probe)
3708 return 0;
3709
3710 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3711 if (!bar)
3712 return -ENOTTY;
3713
3714 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3715 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3716
3717 cfg = readl(bar + NVME_REG_CC);
3718
3719 /* Disable controller if enabled */
3720 if (cfg & NVME_CC_ENABLE) {
3721 u32 cap = readl(bar + NVME_REG_CAP);
3722 unsigned long timeout;
3723
3724 /*
3725 * Per nvme_disable_ctrl() skip shutdown notification as it
3726 * could complete commands to the admin queue. We only intend
3727 * to quiesce the device before reset.
3728 */
3729 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3730
3731 writel(cfg, bar + NVME_REG_CC);
3732
3733 /*
3734 * Some controllers require an additional delay here, see
3735 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3736 * supported by this quirk.
3737 */
3738
3739 /* Cap register provides max timeout in 500ms increments */
3740 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3741
3742 for (;;) {
3743 u32 status = readl(bar + NVME_REG_CSTS);
3744
3745 /* Ready status becomes zero on disable complete */
3746 if (!(status & NVME_CSTS_RDY))
3747 break;
3748
3749 msleep(100);
3750
3751 if (time_after(jiffies, timeout)) {
3752 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3753 break;
3754 }
3755 }
3756 }
3757
3758 pci_iounmap(dev, bar);
3759
3760 pcie_flr(dev);
3761
3762 return 0;
3763}
3764
51ba0945
AW		 3765/*
3766 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3767 * to change after NVMe enable if the driver starts interacting with the
3768 * device too soon after FLR. A 250ms delay after FLR has heuristically
3769 * proven to produce reliably working results for device assignment cases.
3770 */
3771static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3772{
3773 if (!pcie_has_flr(dev))
3774 return -ENOTTY;
3775
3776 if (probe)
3777 return 0;
3778
3779 pcie_flr(dev);
3780
3781 msleep(250);
3782
3783 return 0;
3784}
3785
5b889bf2 3786static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 3787 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3788 reset_intel_82599_sfp_virtfn },
df558de1
XH		 3789 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3790 reset_ivb_igd },
3791 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3792 reset_ivb_igd },
ffb08634 3793 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
51ba0945 3794 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
2c6217e0
CL		 3795 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3796 reset_chelsio_generic_dev },
b9c3b266
DC		 3797 { 0 }
3798};
5b889bf2 3799
df558de1
XH		 3800/*
3801 * These device-specific reset methods are here rather than in a driver
3802 * because when a host assigns a device to a guest VM, the host may need
3803 * to reset the device but probably doesn't have a driver for it.
3804 */
5b889bf2
RW		 3805int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3806{
df9d1e8a 3807 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 3808
3809 for (i = pci_dev_reset_methods; i->reset; i++) {
3810 if ((i->vendor == dev->vendor ||
3811 i->vendor == (u16)PCI_ANY_ID) &&
3812 (i->device == dev->device ||
3813 i->device == (u16)PCI_ANY_ID))
3814 return i->reset(dev, probe);
3815 }
3816
3817 return -ENOTTY;
3818}
12ea6cad 3819
ec637fb2
AW		 3820static void quirk_dma_func0_alias(struct pci_dev *dev)
3821{
f0af9593
BH		 3822 if (PCI_FUNC(dev->devfn) != 0)
3823 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
ec637fb2
AW		 3824}
3825
3826/*
3827 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3828 *
3829 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3830 */
3831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3833
cc346a47
AW		 3834static void quirk_dma_func1_alias(struct pci_dev *dev)
3835{
f0af9593
BH		 3836 if (PCI_FUNC(dev->devfn) != 1)
3837 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
cc346a47
AW		 3838}
3839
3840/*
3841 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3842 * SKUs function 1 is present and is a legacy IDE controller, in other
3843 * SKUs this function is not present, making this a ghost requester.
3844 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3845 */
247de694
SA		 3846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3847 quirk_dma_func1_alias);
cc346a47
AW		 3848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3849 quirk_dma_func1_alias);
aa008206
AW		 3850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3851 quirk_dma_func1_alias);
cc346a47
AW		 3852/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3854 quirk_dma_func1_alias);
3855/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3857 quirk_dma_func1_alias);
3858/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3860 quirk_dma_func1_alias);
00456b35
AS		 3861/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3863 quirk_dma_func1_alias);
7695e73f
BH		 3864/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
3865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
3866 quirk_dma_func1_alias);
cc346a47
AW		 3867/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3868DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3869 quirk_dma_func1_alias);
832e4e1f
TVC		 3870/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3872 quirk_dma_func1_alias);
cc346a47
AW		 3873/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3875 quirk_dma_func1_alias);
c2e0fb96
JC		 3876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3877 quirk_dma_func1_alias);
1903be82
HG		 3878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3879 quirk_dma_func1_alias);
cc346a47
AW		 3880/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3882 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3883 quirk_dma_func1_alias);
8b9b963e
TS		 3884/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3885DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3886 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3887 quirk_dma_func1_alias);
cc346a47 3888
d3d2ab43
AW		 3889/*
3890 * Some devices DMA with the wrong devfn, not just the wrong function.
3891 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3892 * the alias is "fixed" and independent of the device devfn.
3893 *
3894 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3895 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3896 * single device on the secondary bus. In reality, the single exposed
3897 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3898 * that provides a bridge to the internal bus of the I/O processor. The
3899 * controller supports private devices, which can be hidden from PCI config
3900 * space. In the case of the Adaptec 3405, a private device at 01.0
3901 * appears to be the DMA engine, which therefore needs to become a DMA
3902 * alias for the device.
3903 */
3904static const struct pci_device_id fixed_dma_alias_tbl[] = {
3905 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3906 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3907 .driver_data = PCI_DEVFN(1, 0) },
db83f87b
AW		 3908 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3909 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3910 .driver_data = PCI_DEVFN(1, 0) },
d3d2ab43
AW		 3911 { 0 }
3912};
3913
3914static void quirk_fixed_dma_alias(struct pci_dev *dev)
3915{
3916 const struct pci_device_id *id;
3917
3918 id = pci_match_id(fixed_dma_alias_tbl, dev);
48c83080 3919 if (id)
f0af9593 3920 pci_add_dma_alias(dev, id->driver_data);
d3d2ab43
AW		 3921}
3922
3923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3924
ebdb51eb
AW		 3925/*
3926 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3927 * using the wrong DMA alias for the device. Some of these devices can be
3928 * used as either forward or reverse bridges, so we need to test whether the
3929 * device is operating in the correct mode. We could probably apply this
3930 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3931 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3932 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3933 */
3934static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3935{
3936 if (!pci_is_root_bus(pdev->bus) &&
3937 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3938 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3939 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3940 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3941}
3942/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3944 quirk_use_pcie_bridge_dma_alias);
3945/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3946DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
98ca50db
AW		 3947/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3948DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
fce5d57e
JW		 3949/* ITE 8893 has the same problem as the 8892 */
3950DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
8ab4abbe
AW		 3951/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3952DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
ebdb51eb 3953
b1a928cd
JL		 3954/*
3955 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3956 * be added as aliases to the DMA device in order to allow buffer access
3957 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3958 * programmed in the EEPROM.
3959 */
3960static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3961{
3962 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3963 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3964 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3965}
3966DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3968
45a23293
J		 3969/*
3970 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
3971 * associated not at the root bus, but at a bridge below. This quirk avoids
3972 * generating invalid DMA aliases.
3973 */
3974static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
3975{
3976 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
3977}
3978DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
3979 quirk_bridge_cavm_thrx2_pcie_root);
3980DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
3981 quirk_bridge_cavm_thrx2_pcie_root);
3982
3657cebd
KHC		 3983/*
3984 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3985 * class code. Fix it.
3986 */
3987static void quirk_tw686x_class(struct pci_dev *pdev)
3988{
3989 u32 class = pdev->class;
3990
3991 /* Use "Multimedia controller" class */
3992 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
7506dc79 3993 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3657cebd
KHC		 3994 class, pdev->class);
3995}
2b4aed1d 3996DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3657cebd 3997 quirk_tw686x_class);
2b4aed1d 3998DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3657cebd 3999 quirk_tw686x_class);
2b4aed1d 4000DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3657cebd 4001 quirk_tw686x_class);
2b4aed1d 4002DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3657cebd
KHC		 4003 quirk_tw686x_class);
4004
a99b646a 4005/*
4006 * Some devices have problems with Transaction Layer Packets with the Relaxed
4007 * Ordering Attribute set. Such devices should mark themselves and other
82e1719c 4008 * device drivers should check before sending TLPs with RO set.
a99b646a 4009 */
4010static void quirk_relaxedordering_disable(struct pci_dev *dev)
4011{
4012 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
7506dc79 4013 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
a99b646a 4014}
4015
87e09cde 4016/*
4017 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
82e1719c 4018 * Complex have a Flow Control Credit issue which can cause performance
87e09cde 4019 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4020 */
4021DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4022 quirk_relaxedordering_disable);
4023DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4024 quirk_relaxedordering_disable);
4025DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4026 quirk_relaxedordering_disable);
4027DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4028 quirk_relaxedordering_disable);
4029DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4030 quirk_relaxedordering_disable);
4031DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4032 quirk_relaxedordering_disable);
4033DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4034 quirk_relaxedordering_disable);
4035DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4036 quirk_relaxedordering_disable);
4037DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4038 quirk_relaxedordering_disable);
4039DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4040 quirk_relaxedordering_disable);
4041DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4042 quirk_relaxedordering_disable);
4043DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4044 quirk_relaxedordering_disable);
4045DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4046 quirk_relaxedordering_disable);
4047DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4048 quirk_relaxedordering_disable);
4049DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4050 quirk_relaxedordering_disable);
4051DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4052 quirk_relaxedordering_disable);
4053DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4054 quirk_relaxedordering_disable);
4055DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4056 quirk_relaxedordering_disable);
4057DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4058 quirk_relaxedordering_disable);
4059DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4060 quirk_relaxedordering_disable);
4061DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4062 quirk_relaxedordering_disable);
4063DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4064 quirk_relaxedordering_disable);
4065DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4066 quirk_relaxedordering_disable);
4067DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4068 quirk_relaxedordering_disable);
4069DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4070 quirk_relaxedordering_disable);
4071DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4072 quirk_relaxedordering_disable);
4073DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4074 quirk_relaxedordering_disable);
4075DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4076 quirk_relaxedordering_disable);
4077
077fa19c 4078/*
82e1719c 4079 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
077fa19c 4080 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4081 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4082 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4083 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4084 * November 10, 2010). As a result, on this platform we can't use Relaxed
4085 * Ordering for Upstream TLPs.
4086 */
4087DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4088 quirk_relaxedordering_disable);
4089DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4090 quirk_relaxedordering_disable);
4091DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4092 quirk_relaxedordering_disable);
4093
c56d4450
HS		 4094/*
4095 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4096 * values for the Attribute as were supplied in the header of the
4097 * corresponding Request, except as explicitly allowed when IDO is used."
4098 *
4099 * If a non-compliant device generates a completion with a different
4100 * attribute than the request, the receiver may accept it (which itself
4101 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4102 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4103 * device access timeout.
4104 *
4105 * If the non-compliant device generates completions with zero attributes
4106 * (instead of copying the attributes from the request), we can work around
4107 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4108 * upstream devices so they always generate requests with zero attributes.
4109 *
4110 * This affects other devices under the same Root Port, but since these
4111 * attributes are performance hints, there should be no functional problem.
4112 *
4113 * Note that Configuration Space accesses are never supposed to have TLP
4114 * Attributes, so we're safe waiting till after any Configuration Space
4115 * accesses to do the Root Port fixup.
4116 */
4117static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4118{
4119 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4120
4121 if (!root_port) {
7506dc79 4122 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
c56d4450
HS		 4123 return;
4124 }
4125
7506dc79 4126 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
c56d4450
HS		 4127 dev_name(&pdev->dev));
4128 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4129 PCI_EXP_DEVCTL_RELAX_EN |
4130 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4131}
4132
4133/*
4134 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4135 * Completion it generates.
4136 */
4137static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4138{
4139 /*
4140 * This mask/compare operation selects for Physical Function 4 on a
4141 * T5. We only need to fix up the Root Port once for any of the
4142 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
82e1719c 4143 * 0x54xx so we use that one.
c56d4450
HS		 4144 */
4145 if ((pdev->device & 0xff00) == 0x5400)
4146 quirk_disable_root_port_attributes(pdev);
4147}
4148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4149 quirk_chelsio_T5_disable_root_port_attributes);
4150
15b100df
AW		 4151/*
4152 * AMD has indicated that the devices below do not support peer-to-peer
4153 * in any system where they are found in the southbridge with an AMD
4154 * IOMMU in the system. Multifunction devices that do not support
4155 * peer-to-peer between functions can claim to support a subset of ACS.
4156 * Such devices effectively enable request redirect (RR) and completion
4157 * redirect (CR) since all transactions are redirected to the upstream
4158 * root complex.
4159 *
4160 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4161 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4162 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4163 *
4164 * 1002:4385 SBx00 SMBus Controller
4165 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4166 * 1002:4383 SBx00 Azalia (Intel HDA)
4167 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4168 * 1002:4384 SBx00 PCI to PCI Bridge
4169 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3587e625
MR		 4170 *
4171 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4172 *
4173 * 1022:780f [AMD] FCH PCI Bridge
4174 * 1022:7809 [AMD] FCH USB OHCI Controller
15b100df
AW		 4175 */
4176static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4177{
4178#ifdef CONFIG_ACPI
4179 struct acpi_table_header *header = NULL;
4180 acpi_status status;
4181
4182 /* Targeting multifunction devices on the SB (appears on root bus) */
4183 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4184 return -ENODEV;
4185
4186 /* The IVRS table describes the AMD IOMMU */
4187 status = acpi_get_table("IVRS", 0, &header);
4188 if (ACPI_FAILURE(status))
4189 return -ENODEV;
4190
4191 /* Filter out flags not applicable to multifunction */
4192 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4193
4194 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4195#else
4196 return -ENODEV;
4197#endif
4198}
4199
f2ddaf8d
VL		 4200static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4201{
4202 /*
4203 * Effectively selects all downstream ports for whole ThunderX 1
4204 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4205 * bits of device ID are used to indicate which subdevice is used
4206 * within the SoC.
4207 */
4208 return (pci_is_pcie(dev) &&
4209 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4210 ((dev->device & 0xf800) == 0xa000));
4211}
4212
b404bcfb
MJ		 4213static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4214{
4215 /*
7f342678
VL		 4216 * Cavium root ports don't advertise an ACS capability. However,
4217 * the RTL internally implements similar protection as if ACS had
4218 * Request Redirection, Completion Redirection, Source Validation,
4219 * and Upstream Forwarding features enabled. Assert that the
4220 * hardware implements and enables equivalent ACS functionality for
4221 * these flags.
b404bcfb 4222 */
7f342678 4223 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
b404bcfb 4224
f2ddaf8d 4225 if (!pci_quirk_cavium_acs_match(dev))
b77d537d
MJ		 4226 return -ENOTTY;
4227
b404bcfb
MJ		 4228 return acs_flags ? 0 : 1;
4229}
4230
a0418aa2
FK		 4231static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4232{
4233 /*
82e1719c 4234 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
a0418aa2
FK		 4235 * transactions with others, allowing masking out these bits as if they
4236 * were unimplemented in the ACS capability.
4237 */
4238 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4239
4240 return acs_flags ? 0 : 1;
4241}
4242
d99321b6
AW		 4243/*
4244 * Many Intel PCH root ports do provide ACS-like features to disable peer
4245 * transactions and validate bus numbers in requests, but do not provide an
4246 * actual PCIe ACS capability. This is the list of device IDs known to fall
4247 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4248 */
4249static const u16 pci_quirk_intel_pch_acs_ids[] = {
4250 /* Ibexpeak PCH */
4251 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4252 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4253 /* Cougarpoint PCH */
4254 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4255 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4256 /* Pantherpoint PCH */
4257 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4258 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4259 /* Lynxpoint-H PCH */
4260 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4261 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4262 /* Lynxpoint-LP PCH */
4263 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4264 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4265 /* Wildcat PCH */
4266 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4267 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
1a30fd0d
AW		 4268 /* Patsburg (X79) PCH */
4269 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
78e88358
AW		 4270 /* Wellsburg (X99) PCH */
4271 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4272 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
dca230d1
AW		 4273 /* Lynx Point (9 series) PCH */
4274 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
d99321b6
AW		 4275};
4276
4277static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4278{
4279 int i;
4280
4281 /* Filter out a few obvious non-matches first */
4282 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4283 return false;
4284
4285 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4286 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4287 return true;
4288
4289 return false;
4290}
4291
4292#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4293
4294static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4295{
4296 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4297 INTEL_PCH_ACS_FLAGS : 0;
4298
4299 if (!pci_quirk_intel_pch_acs_match(dev))
4300 return -ENOTTY;
4301
4302 return acs_flags & ~flags ? 0 : 1;
4303}
4304
33be632b
SK		 4305/*
4306 * These QCOM root ports do provide ACS-like features to disable peer
4307 * transactions and validate bus numbers in requests, but do not provide an
4308 * actual PCIe ACS capability. Hardware supports source validation but it
4309 * will report the issue as Completer Abort instead of ACS Violation.
4310 * Hardware doesn't support peer-to-peer and each root port is a root
4311 * complex with unique segment numbers. It is not possible for one root
4312 * port to pass traffic to another root port. All PCIe transactions are
4313 * terminated inside the root port.
4314 */
4315static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4316{
4317 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4318 int ret = acs_flags & ~flags ? 0 : 1;
4319
7506dc79 4320 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
33be632b
SK		 4321
4322 return ret;
4323}
4324
1bf2bf22
AW		 4325/*
4326 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4327 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4328 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4329 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4330 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4331 * control register is at offset 8 instead of 6 and we should probably use
4332 * dword accesses to them. This applies to the following PCI Device IDs, as
4333 * found in volume 1 of the datasheet[2]:
4334 *
4335 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4336 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4337 *
4338 * N.B. This doesn't fix what lspci shows.
4339 *
7184f5b4
AW		 4340 * The 100 series chipset specification update includes this as errata #23[3].
4341 *
4342 * The 200 series chipset (Union Point) has the same bug according to the
4343 * specification update (Intel 200 Series Chipset Family Platform Controller
4344 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4345 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4346 * chipset include:
4347 *
4348 * 0xa290-0xa29f PCI Express Root port #{0-16}
4349 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4350 *
e8440f4b
AW		 4351 * Mobile chipsets are also affected, 7th & 8th Generation
4352 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4353 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4354 * Processor Family I/O for U Quad Core Platforms Specification Update,
4355 * August 2017, Revision 002, Document#: 334660-002)[6]
4356 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4357 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4358 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4359 *
4360 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4361 *
1bf2bf22
AW		 4362 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4363 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
7184f5b4
AW		 4364 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4365 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4366 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
e8440f4b
AW		 4367 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4368 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
1bf2bf22
AW		 4369 */
4370static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4371{
7184f5b4
AW		 4372 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4373 return false;
4374
4375 switch (dev->device) {
4376 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4377 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
e8440f4b 4378 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
7184f5b4
AW		 4379 return true;
4380 }
4381
4382 return false;
1bf2bf22
AW		 4383}
4384
4385#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4386
4387static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4388{
4389 int pos;
4390 u32 cap, ctrl;
4391
4392 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4393 return -ENOTTY;
4394
4395 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4396 if (!pos)
4397 return -ENOTTY;
4398
4399 /* see pci_acs_flags_enabled() */
4400 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4401 acs_flags &= (cap | PCI_ACS_EC);
4402
4403 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4404
4405 return acs_flags & ~ctrl ? 0 : 1;
4406}
4407
100ebb2c 4408static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
89b51cb5
AW		 4409{
4410 /*
4411 * SV, TB, and UF are not relevant to multifunction endpoints.
4412 *
100ebb2c
AW		 4413 * Multifunction devices are only required to implement RR, CR, and DT
4414 * in their ACS capability if they support peer-to-peer transactions.
4415 * Devices matching this quirk have been verified by the vendor to not
4416 * perform peer-to-peer with other functions, allowing us to mask out
4417 * these bits as if they were unimplemented in the ACS capability.
89b51cb5
AW		 4418 */
4419 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4420 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4421
4422 return acs_flags ? 0 : 1;
4423}
4424
ad805758
AW		 4425static const struct pci_dev_acs_enabled {
4426 u16 vendor;
4427 u16 device;
4428 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4429} pci_dev_acs_enabled[] = {
15b100df
AW		 4430 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4431 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4432 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4433 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4434 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4435 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3587e625
MR		 4436 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4437 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
100ebb2c
AW		 4438 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4439 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
9fad4012 4440 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
100ebb2c
AW		 4441 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4442 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4443 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4444 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4445 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4446 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4447 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4448 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4449 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4450 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4451 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4452 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4453 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4454 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4455 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4456 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4457 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4458 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4459 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4460 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
d748804f
AW		 4461 /* 82580 */
4462 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4463 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4464 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4465 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4466 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4467 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4468 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4469 /* 82576 */
4470 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4471 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4472 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4473 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4474 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4475 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4476 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4477 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4478 /* 82575 */
4479 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4480 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4481 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4482 /* I350 */
4483 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4484 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4485 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4486 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4487 /* 82571 (Quads omitted due to non-ACS switch) */
4488 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4489 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4490 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4491 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
95e16587
AW		 4492 /* I219 */
4493 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4494 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
33be632b 4495 /* QCOM QDF2xxx root ports */
333c8c12
BH		 4496 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4497 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
d748804f 4498 /* Intel PCH root ports */
d99321b6 4499 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
1bf2bf22 4500 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
6a3763d1
VV		 4501 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4502 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
b404bcfb
MJ		 4503 /* Cavium ThunderX */
4504 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
a0418aa2
FK		 4505 /* APM X-Gene */
4506 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4ef76ad0
FK		 4507 /* Ampere Computing */
4508 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4509 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4510 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4511 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4512 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4513 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4514 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4515 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
ad805758
AW		 4516 { 0 }
4517};
4518
4519int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4520{
4521 const struct pci_dev_acs_enabled *i;
4522 int ret;
4523
4524 /*
4525 * Allow devices that do not expose standard PCIe ACS capabilities
4526 * or control to indicate their support here. Multi-function express
4527 * devices which do not allow internal peer-to-peer between functions,
4528 * but do not implement PCIe ACS may wish to return true here.
4529 */
4530 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4531 if ((i->vendor == dev->vendor ||
4532 i->vendor == (u16)PCI_ANY_ID) &&
4533 (i->device == dev->device ||
4534 i->device == (u16)PCI_ANY_ID)) {
4535 ret = i->acs_enabled(dev, acs_flags);
4536 if (ret >= 0)
4537 return ret;
4538 }
4539 }
4540
4541 return -ENOTTY;
4542}
2c744244 4543
d99321b6
AW		 4544/* Config space offset of Root Complex Base Address register */
4545#define INTEL_LPC_RCBA_REG 0xf0
4546/* 31:14 RCBA address */
4547#define INTEL_LPC_RCBA_MASK 0xffffc000
4548/* RCBA Enable */
4549#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4550
4551/* Backbone Scratch Pad Register */
4552#define INTEL_BSPR_REG 0x1104
4553/* Backbone Peer Non-Posted Disable */
4554#define INTEL_BSPR_REG_BPNPD (1 << 8)
4555/* Backbone Peer Posted Disable */
4556#define INTEL_BSPR_REG_BPPD (1 << 9)
4557
4558/* Upstream Peer Decode Configuration Register */
4559#define INTEL_UPDCR_REG 0x1114
4560/* 5:0 Peer Decode Enable bits */
4561#define INTEL_UPDCR_REG_MASK 0x3f
4562
4563static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4564{
4565 u32 rcba, bspr, updcr;
4566 void __iomem *rcba_mem;
4567
4568 /*
4569 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4570 * are D28:F* and therefore get probed before LPC, thus we can't
82e1719c 4571 * use pci_get_slot()/pci_read_config_dword() here.
d99321b6
AW		 4572 */
4573 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4574 INTEL_LPC_RCBA_REG, &rcba);
4575 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4576 return -EINVAL;
4577
4578 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4579 PAGE_ALIGN(INTEL_UPDCR_REG));
4580 if (!rcba_mem)
4581 return -ENOMEM;
4582
4583 /*
4584 * The BSPR can disallow peer cycles, but it's set by soft strap and
4585 * therefore read-only. If both posted and non-posted peer cycles are
4586 * disallowed, we're ok. If either are allowed, then we need to use
4587 * the UPDCR to disable peer decodes for each port. This provides the
4588 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4589 */
4590 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4591 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4592 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4593 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4594 if (updcr & INTEL_UPDCR_REG_MASK) {
7506dc79 4595 pci_info(dev, "Disabling UPDCR peer decodes\n");
d99321b6
AW		 4596 updcr &= ~INTEL_UPDCR_REG_MASK;
4597 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4598 }
4599 }
4600
4601 iounmap(rcba_mem);
4602 return 0;
4603}
4604
4605/* Miscellaneous Port Configuration register */
4606#define INTEL_MPC_REG 0xd8
4607/* MPC: Invalid Receive Bus Number Check Enable */
4608#define INTEL_MPC_REG_IRBNCE (1 << 26)
4609
4610static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4611{
4612 u32 mpc;
4613
4614 /*
4615 * When enabled, the IRBNCE bit of the MPC register enables the
4616 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4617 * ensures that requester IDs fall within the bus number range
4618 * of the bridge. Enable if not already.
4619 */
4620 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4621 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
7506dc79 4622 pci_info(dev, "Enabling MPC IRBNCE\n");
d99321b6
AW		 4623 mpc |= INTEL_MPC_REG_IRBNCE;
4624 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4625 }
4626}
4627
4628static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4629{
4630 if (!pci_quirk_intel_pch_acs_match(dev))
4631 return -ENOTTY;
4632
4633 if (pci_quirk_enable_intel_lpc_acs(dev)) {
7506dc79 4634 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
d99321b6
AW		 4635 return 0;
4636 }
4637
4638 pci_quirk_enable_intel_rp_mpc_acs(dev);
4639
4640 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4641
7506dc79 4642 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
d99321b6
AW		 4643
4644 return 0;
4645}
4646
1bf2bf22
AW		 4647static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4648{
4649 int pos;
4650 u32 cap, ctrl;
4651
4652 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4653 return -ENOTTY;
4654
4655 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4656 if (!pos)
4657 return -ENOTTY;
4658
4659 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4660 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4661
4662 ctrl |= (cap & PCI_ACS_SV);
4663 ctrl |= (cap & PCI_ACS_RR);
4664 ctrl |= (cap & PCI_ACS_CR);
4665 ctrl |= (cap & PCI_ACS_UF);
4666
4667 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4668
7506dc79 4669 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
1bf2bf22
AW		 4670
4671 return 0;
4672}
4673
10dbc9fe
LG		 4674static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4675{
4676 int pos;
4677 u32 cap, ctrl;
4678
4679 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4680 return -ENOTTY;
4681
4682 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4683 if (!pos)
4684 return -ENOTTY;
4685
4686 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4687 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4688
4689 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
4690
4691 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4692
4693 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4694
4695 return 0;
4696}
4697
73c47dde 4698static const struct pci_dev_acs_ops {
2c744244
AW		 4699 u16 vendor;
4700 u16 device;
4701 int (*enable_acs)(struct pci_dev *dev);
73c47dde
LG		 4702 int (*disable_acs_redir)(struct pci_dev *dev);
4703} pci_dev_acs_ops[] = {
4704 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4705 .enable_acs = pci_quirk_enable_intel_pch_acs,
4706 },
4707 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4708 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
10dbc9fe 4709 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
73c47dde 4710 },
2c744244
AW		 4711};
4712
c1d61c9b 4713int pci_dev_specific_enable_acs(struct pci_dev *dev)
2c744244 4714{
73c47dde 4715 const struct pci_dev_acs_ops *p;
3b269185 4716 int i, ret;
2c744244 4717
73c47dde
LG		 4718 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4719 p = &pci_dev_acs_ops[i];
3b269185
LG		 4720 if ((p->vendor == dev->vendor ||
4721 p->vendor == (u16)PCI_ANY_ID) &&
4722 (p->device == dev->device ||
73c47dde
LG		 4723 p->device == (u16)PCI_ANY_ID) &&
4724 p->enable_acs) {
3b269185 4725 ret = p->enable_acs(dev);
2c744244 4726 if (ret >= 0)
73c47dde
LG		 4727 return ret;
4728 }
4729 }
2c744244 4730
73c47dde
LG		 4731 return -ENOTTY;
4732}
4733
4734int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
4735{
4736 const struct pci_dev_acs_ops *p;
4737 int i, ret;
4738
4739 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
4740 p = &pci_dev_acs_ops[i];
4741 if ((p->vendor == dev->vendor ||
4742 p->vendor == (u16)PCI_ANY_ID) &&
4743 (p->device == dev->device ||
4744 p->device == (u16)PCI_ANY_ID) &&
4745 p->disable_acs_redir) {
4746 ret = p->disable_acs_redir(dev);
2c744244 4747 if (ret >= 0)
c1d61c9b 4748 return ret;
2c744244
AW		 4749 }
4750 }
c1d61c9b
AW		 4751
4752 return -ENOTTY;
2c744244 4753}
3388a614
TS		 4754
4755/*
82e1719c 4756 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
3388a614
TS		 4757 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4758 * Next Capability pointer in the MSI Capability Structure should point to
4759 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4760 * the list.
4761 */
4762static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4763{
4764 int pos, i = 0;
4765 u8 next_cap;
4766 u16 reg16, *cap;
4767 struct pci_cap_saved_state *state;
4768
4769 /* Bail if the hardware bug is fixed */
4770 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4771 return;
4772
4773 /* Bail if MSI Capability Structure is not found for some reason */
4774 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4775 if (!pos)
4776 return;
4777
4778 /*
4779 * Bail if Next Capability pointer in the MSI Capability Structure
4780 * is not the expected incorrect 0x00.
4781 */
4782 pci_read_config_byte(pdev, pos + 1, &next_cap);
4783 if (next_cap)
4784 return;
4785
4786 /*
4787 * PCIe Capability Structure is expected to be at 0x50 and should
4788 * terminate the list (Next Capability pointer is 0x00). Verify
4789 * Capability Id and Next Capability pointer is as expected.
4790 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4791 * to correctly set kernel data structures which have already been
4792 * set incorrectly due to the hardware bug.
4793 */
4794 pos = 0x50;
4795 pci_read_config_word(pdev, pos, &reg16);
4796 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4797 u32 status;
4798#ifndef PCI_EXP_SAVE_REGS
4799#define PCI_EXP_SAVE_REGS 7
4800#endif
4801 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4802
4803 pdev->pcie_cap = pos;
4804 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4805 pdev->pcie_flags_reg = reg16;
4806 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4807 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4808
4809 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4810 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4811 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4812 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4813
4814 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4815 return;
4816
82e1719c 4817 /* Save PCIe cap */
3388a614
TS		 4818 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4819 if (!state)
4820 return;
4821
4822 state->cap.cap_nr = PCI_CAP_ID_EXP;
4823 state->cap.cap_extended = 0;
4824 state->cap.size = size;
4825 cap = (u16 *)&state->cap.data[0];
4826 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4827 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4828 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4829 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4830 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4831 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4832 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4833 hlist_add_head(&state->next, &pdev->saved_cap_space);
4834 }
4835}
4836DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
443b40ba 4837
82e1719c 4838/* FLR may cause some 82579 devices to hang */
f65fd1aa
SN		 4839static void quirk_intel_no_flr(struct pci_dev *dev)
4840{
4841 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4842}
4843DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4844DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
62ce94a7
SK		 4845
4846static void quirk_no_ext_tags(struct pci_dev *pdev)
4847{
4848 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4849
4850 if (!bridge)
4851 return;
4852
4853 bridge->no_ext_tags = 1;
7506dc79 4854 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
62ce94a7
SK		 4855
4856 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4857}
1b30dfd3 4858DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
62ce94a7 4859DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
1b30dfd3 4860DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
62ce94a7
SK		 4861DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
4862DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
1b30dfd3
SK		 4863DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
4864DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
cf2d8041 4865
9b44b0b0
JR		 4866#ifdef CONFIG_PCI_ATS
4867/*
4868 * Some devices have a broken ATS implementation causing IOMMU stalls.
4869 * Don't use ATS for those devices.
4870 */
4871static void quirk_no_ats(struct pci_dev *pdev)
4872{
7506dc79 4873 pci_info(pdev, "disabling ATS (broken on this device)\n");
9b44b0b0
JR		 4874 pdev->ats_cap = 0;
4875}
4876
4877/* AMD Stoney platform GPU */
4878DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
4879#endif /* CONFIG_PCI_ATS */
06dc4ee5
HZ		 4880
4881/* Freescale PCIe doesn't support MSI in RC mode */
4882static void quirk_fsl_no_msi(struct pci_dev *pdev)
4883{
4884 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
4885 pdev->no_msi = 1;
4886}
4887DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
07f4f97d
LW		 4888
4889/*
4890 * GPUs with integrated HDA controller for streaming audio to attached displays
4891 * need a device link from the HDA controller (consumer) to the GPU (supplier)
4892 * so that the GPU is powered up whenever the HDA controller is accessed.
4893 * The GPU and HDA controller are functions 0 and 1 of the same PCI device.
4894 * The device link stays in place until shutdown (or removal of the PCI device
4895 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller
4896 * to prevent it from permanently keeping the GPU awake.
4897 */
4898static void quirk_gpu_hda(struct pci_dev *hda)
4899{
4900 struct pci_dev *gpu;
4901
4902 if (PCI_FUNC(hda->devfn) != 1)
4903 return;
4904
4905 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus),
4906 hda->bus->number,
4907 PCI_DEVFN(PCI_SLOT(hda->devfn), 0));
4908 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) {
4909 pci_dev_put(gpu);
4910 return;
4911 }
4912
4913 if (!device_link_add(&hda->dev, &gpu->dev,
4914 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
4915 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu));
4916
4917 pm_runtime_allow(&hda->dev);
4918 pci_dev_put(gpu);
4919}
4920DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
4921 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4922DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
4923 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4924DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
4925 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
aa667c64
JP		 4926
4927/*
4928 * Some IDT switches incorrectly flag an ACS Source Validation error on
4929 * completions for config read requests even though PCIe r4.0, sec
4930 * 6.12.1.1, says that completions are never affected by ACS Source
4931 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
4932 *
4933 * Item #36 - Downstream port applies ACS Source Validation to Completions
4934 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
4935 * completions are never affected by ACS Source Validation. However,
4936 * completions received by a downstream port of the PCIe switch from a
4937 * device that has not yet captured a PCIe bus number are incorrectly
4938 * dropped by ACS Source Validation by the switch downstream port.
4939 *
4940 * The workaround suggested by IDT is to issue a config write to the
4941 * downstream device before issuing the first config read. This allows the
4942 * downstream device to capture its bus and device numbers (see PCIe r4.0,
4943 * sec 2.2.9), thus avoiding the ACS error on the completion.
4944 *
4945 * However, we don't know when the device is ready to accept the config
4946 * write, so we do config reads until we receive a non-Config Request Retry
4947 * Status, then do the config write.
4948 *
4949 * To avoid hitting the erratum when doing the config reads, we disable ACS
4950 * SV around this process.
4951 */
4952int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
4953{
4954 int pos;
4955 u16 ctrl = 0;
4956 bool found;
4957 struct pci_dev *bridge = bus->self;
4958
4959 pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
4960
4961 /* Disable ACS SV before initial config reads */
4962 if (pos) {
4963 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
4964 if (ctrl & PCI_ACS_SV)
4965 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
4966 ctrl & ~PCI_ACS_SV);
4967 }
4968
4969 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
4970
4971 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
4972 if (found)
4973 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
4974
4975 /* Re-enable ACS_SV if it was previously enabled */
4976 if (ctrl & PCI_ACS_SV)
4977 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
4978
4979 return found;
4980}
e7aaf90f 4981
ad281ecf
DM		 4982/*
4983 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
4984 * NT endpoints via the internal switch fabric. These IDs replace the
4985 * originating requestor ID TLPs which access host memory on peer NTB
4986 * ports. Therefore, all proxy IDs must be aliased to the NTB device
4987 * to permit access when the IOMMU is turned on.
4988 */
4989static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
4990{
4991 void __iomem *mmio;
4992 struct ntb_info_regs __iomem *mmio_ntb;
4993 struct ntb_ctrl_regs __iomem *mmio_ctrl;
ad281ecf
DM		 4994 u64 partition_map;
4995 u8 partition;
4996 int pp;
4997
4998 if (pci_enable_device(pdev)) {
4999 pci_err(pdev, "Cannot enable Switchtec device\n");
5000 return;
5001 }
5002
5003 mmio = pci_iomap(pdev, 0, 0);
5004 if (mmio == NULL) {
5005 pci_disable_device(pdev);
5006 pci_err(pdev, "Cannot iomap Switchtec device\n");
5007 return;
5008 }
5009
5010 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5011
5012 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5013 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
ad281ecf
DM		 5014
5015 partition = ioread8(&mmio_ntb->partition_id);
5016
5017 partition_map = ioread32(&mmio_ntb->ep_map);
5018 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5019 partition_map &= ~(1ULL << partition);
5020
5021 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5022 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5023 u32 table_sz = 0;
5024 int te;
5025
5026 if (!(partition_map & (1ULL << pp)))
5027 continue;
5028
5029 pci_dbg(pdev, "Processing partition %d\n", pp);
5030
5031 mmio_peer_ctrl = &mmio_ctrl[pp];
5032
5033 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5034 if (!table_sz) {
5035 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5036 continue;
5037 }
5038
5039 if (table_sz > 512) {
5040 pci_warn(pdev,
5041 "Invalid Switchtec partition %d table_sz %d\n",
5042 pp, table_sz);
5043 continue;
5044 }
5045
5046 for (te = 0; te < table_sz; te++) {
5047 u32 rid_entry;
5048 u8 devfn;
5049
5050 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5051 devfn = (rid_entry >> 1) & 0xFF;
5052 pci_dbg(pdev,
5053 "Aliasing Partition %d Proxy ID %02x.%d\n",
5054 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5055 pci_add_dma_alias(pdev, devfn);
5056 }
5057 }
5058
5059 pci_iounmap(pdev, mmio);
5060 pci_disable_device(pdev);
5061}
01d5d7fa 5062#define SWITCHTEC_QUIRK(vid) \
742bbe1e
LG		 5063 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5064 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
01d5d7fa
LG		 5065
5066SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5067SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5068SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5069SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5070SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5071SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5072SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5073SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5074SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5075SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5076SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5077SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5078SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5079SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5080SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5081SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5082SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5083SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5084SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5085SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5086SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5087SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5088SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5089SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5090SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5091SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5092SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5093SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5094SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5095SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
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