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ASoC: wm_adsp: Handle old .bin files
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93
MB		 23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/jack.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include <linux/mfd/arizona/registers.h>
33
34#include "wm_adsp.h"
35
36#define adsp_crit(_dsp, fmt, ...) \
37 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
38#define adsp_err(_dsp, fmt, ...) \
39 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40#define adsp_warn(_dsp, fmt, ...) \
41 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_info(_dsp, fmt, ...) \
43 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_dbg(_dsp, fmt, ...) \
45 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46
47#define ADSP1_CONTROL_1 0x00
48#define ADSP1_CONTROL_2 0x02
49#define ADSP1_CONTROL_3 0x03
50#define ADSP1_CONTROL_4 0x04
51#define ADSP1_CONTROL_5 0x06
52#define ADSP1_CONTROL_6 0x07
53#define ADSP1_CONTROL_7 0x08
54#define ADSP1_CONTROL_8 0x09
55#define ADSP1_CONTROL_9 0x0A
56#define ADSP1_CONTROL_10 0x0B
57#define ADSP1_CONTROL_11 0x0C
58#define ADSP1_CONTROL_12 0x0D
59#define ADSP1_CONTROL_13 0x0F
60#define ADSP1_CONTROL_14 0x10
61#define ADSP1_CONTROL_15 0x11
62#define ADSP1_CONTROL_16 0x12
63#define ADSP1_CONTROL_17 0x13
64#define ADSP1_CONTROL_18 0x14
65#define ADSP1_CONTROL_19 0x16
66#define ADSP1_CONTROL_20 0x17
67#define ADSP1_CONTROL_21 0x18
68#define ADSP1_CONTROL_22 0x1A
69#define ADSP1_CONTROL_23 0x1B
70#define ADSP1_CONTROL_24 0x1C
71#define ADSP1_CONTROL_25 0x1E
72#define ADSP1_CONTROL_26 0x20
73#define ADSP1_CONTROL_27 0x21
74#define ADSP1_CONTROL_28 0x22
75#define ADSP1_CONTROL_29 0x23
76#define ADSP1_CONTROL_30 0x24
77#define ADSP1_CONTROL_31 0x26
78
79/*
80 * ADSP1 Control 19
81 */
82#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85
86
87/*
88 * ADSP1 Control 30
89 */
90#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
91#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
95#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
98#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
99#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
102#define ADSP1_START 0x0001 /* DSP1_START */
103#define ADSP1_START_MASK 0x0001 /* DSP1_START */
104#define ADSP1_START_SHIFT 0 /* DSP1_START */
105#define ADSP1_START_WIDTH 1 /* DSP1_START */
106
94e205bf
CR		 107/*
108 * ADSP1 Control 31
109 */
110#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
111#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
113
2d30b575
MB		 114#define ADSP2_CONTROL 0x0
115#define ADSP2_CLOCKING 0x1
116#define ADSP2_STATUS1 0x4
117#define ADSP2_WDMA_CONFIG_1 0x30
118#define ADSP2_WDMA_CONFIG_2 0x31
119#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93
MB		 120
121/*
122 * ADSP2 Control
123 */
124
125#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
126#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
127#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
128#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
129#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
130#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
131#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
132#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
133#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
134#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
135#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
136#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
137#define ADSP2_START 0x0001 /* DSP1_START */
138#define ADSP2_START_MASK 0x0001 /* DSP1_START */
139#define ADSP2_START_SHIFT 0 /* DSP1_START */
140#define ADSP2_START_WIDTH 1 /* DSP1_START */
141
973838a0
MB		 142/*
143 * ADSP2 clocking
144 */
145#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
146#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
147#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
148
2159ad93
MB		 149/*
150 * ADSP2 Status 1
151 */
152#define ADSP2_RAM_RDY 0x0001
153#define ADSP2_RAM_RDY_MASK 0x0001
154#define ADSP2_RAM_RDY_SHIFT 0
155#define ADSP2_RAM_RDY_WIDTH 1
156
cf17c83c
MB		 157struct wm_adsp_buf {
158 struct list_head list;
159 void *buf;
160};
161
162static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
163 struct list_head *list)
164{
165 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
166
167 if (buf == NULL)
168 return NULL;
169
170 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
171 if (!buf->buf) {
172 kfree(buf);
173 return NULL;
174 }
175
176 if (list)
177 list_add_tail(&buf->list, list);
178
179 return buf;
180}
181
182static void wm_adsp_buf_free(struct list_head *list)
183{
184 while (!list_empty(list)) {
185 struct wm_adsp_buf *buf = list_first_entry(list,
186 struct wm_adsp_buf,
187 list);
188 list_del(&buf->list);
189 kfree(buf->buf);
190 kfree(buf);
191 }
192}
193
36e8fe99 194#define WM_ADSP_NUM_FW 4
1023dbd9
MB		 195
196static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
36e8fe99 197 "MBC/VSS", "Tx", "Tx Speaker", "Rx ANC"
1023dbd9
MB		 198};
199
200static struct {
201 const char *file;
202} wm_adsp_fw[WM_ADSP_NUM_FW] = {
203 { .file = "mbc-vss" },
204 { .file = "tx" },
36e8fe99 205 { .file = "tx-spk" },
1023dbd9
MB		 206 { .file = "rx-anc" },
207};
208
209static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
210 struct snd_ctl_elem_value *ucontrol)
211{
212 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
213 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
214 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
215
216 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
217
218 return 0;
219}
220
221static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
222 struct snd_ctl_elem_value *ucontrol)
223{
224 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
225 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
226 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
227
228 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
229 return 0;
230
231 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
232 return -EINVAL;
233
234 if (adsp[e->shift_l].running)
235 return -EBUSY;
236
31522764 237 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9
MB		 238
239 return 0;
240}
241
242static const struct soc_enum wm_adsp_fw_enum[] = {
243 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
244 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
245 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
246 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
247};
248
249const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
250 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
251 wm_adsp_fw_get, wm_adsp_fw_put),
252 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
253 wm_adsp_fw_get, wm_adsp_fw_put),
254 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
255 wm_adsp_fw_get, wm_adsp_fw_put),
256 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
257 wm_adsp_fw_get, wm_adsp_fw_put),
258};
259EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 260
261static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
262 int type)
263{
264 int i;
265
266 for (i = 0; i < dsp->num_mems; i++)
267 if (dsp->mem[i].type == type)
268 return &dsp->mem[i];
269
270 return NULL;
271}
272
45b9ee72
MB		 273static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
274 unsigned int offset)
275{
276 switch (region->type) {
277 case WMFW_ADSP1_PM:
278 return region->base + (offset * 3);
279 case WMFW_ADSP1_DM:
280 return region->base + (offset * 2);
281 case WMFW_ADSP2_XM:
282 return region->base + (offset * 2);
283 case WMFW_ADSP2_YM:
284 return region->base + (offset * 2);
285 case WMFW_ADSP1_ZM:
286 return region->base + (offset * 2);
287 default:
288 WARN_ON(NULL != "Unknown memory region type");
289 return offset;
290 }
291}
292
2159ad93
MB		 293static int wm_adsp_load(struct wm_adsp *dsp)
294{
cf17c83c 295 LIST_HEAD(buf_list);
2159ad93
MB		 296 const struct firmware *firmware;
297 struct regmap *regmap = dsp->regmap;
298 unsigned int pos = 0;
299 const struct wmfw_header *header;
300 const struct wmfw_adsp1_sizes *adsp1_sizes;
301 const struct wmfw_adsp2_sizes *adsp2_sizes;
302 const struct wmfw_footer *footer;
303 const struct wmfw_region *region;
304 const struct wm_adsp_region *mem;
305 const char *region_name;
306 char *file, *text;
cf17c83c 307 struct wm_adsp_buf *buf;
2159ad93
MB		 308 unsigned int reg;
309 int regions = 0;
310 int ret, offset, type, sizes;
311
312 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
313 if (file == NULL)
314 return -ENOMEM;
315
1023dbd9
MB		 316 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
317 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 318 file[PAGE_SIZE - 1] = '\0';
319
320 ret = request_firmware(&firmware, file, dsp->dev);
321 if (ret != 0) {
322 adsp_err(dsp, "Failed to request '%s'\n", file);
323 goto out;
324 }
325 ret = -EINVAL;
326
327 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
328 if (pos >= firmware->size) {
329 adsp_err(dsp, "%s: file too short, %zu bytes\n",
330 file, firmware->size);
331 goto out_fw;
332 }
333
334 header = (void*)&firmware->data[0];
335
336 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
337 adsp_err(dsp, "%s: invalid magic\n", file);
338 goto out_fw;
339 }
340
341 if (header->ver != 0) {
342 adsp_err(dsp, "%s: unknown file format %d\n",
343 file, header->ver);
344 goto out_fw;
345 }
346
347 if (header->core != dsp->type) {
348 adsp_err(dsp, "%s: invalid core %d != %d\n",
349 file, header->core, dsp->type);
350 goto out_fw;
351 }
352
353 switch (dsp->type) {
354 case WMFW_ADSP1:
355 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
356 adsp1_sizes = (void *)&(header[1]);
357 footer = (void *)&(adsp1_sizes[1]);
358 sizes = sizeof(*adsp1_sizes);
359
360 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
361 file, le32_to_cpu(adsp1_sizes->dm),
362 le32_to_cpu(adsp1_sizes->pm),
363 le32_to_cpu(adsp1_sizes->zm));
364 break;
365
366 case WMFW_ADSP2:
367 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
368 adsp2_sizes = (void *)&(header[1]);
369 footer = (void *)&(adsp2_sizes[1]);
370 sizes = sizeof(*adsp2_sizes);
371
372 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
373 file, le32_to_cpu(adsp2_sizes->xm),
374 le32_to_cpu(adsp2_sizes->ym),
375 le32_to_cpu(adsp2_sizes->pm),
376 le32_to_cpu(adsp2_sizes->zm));
377 break;
378
379 default:
380 BUG_ON(NULL == "Unknown DSP type");
381 goto out_fw;
382 }
383
384 if (le32_to_cpu(header->len) != sizeof(*header) +
385 sizes + sizeof(*footer)) {
386 adsp_err(dsp, "%s: unexpected header length %d\n",
387 file, le32_to_cpu(header->len));
388 goto out_fw;
389 }
390
391 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
392 le64_to_cpu(footer->timestamp));
393
394 while (pos < firmware->size &&
395 pos - firmware->size > sizeof(*region)) {
396 region = (void *)&(firmware->data[pos]);
397 region_name = "Unknown";
398 reg = 0;
399 text = NULL;
400 offset = le32_to_cpu(region->offset) & 0xffffff;
401 type = be32_to_cpu(region->type) & 0xff;
402 mem = wm_adsp_find_region(dsp, type);
403
404 switch (type) {
405 case WMFW_NAME_TEXT:
406 region_name = "Firmware name";
407 text = kzalloc(le32_to_cpu(region->len) + 1,
408 GFP_KERNEL);
409 break;
410 case WMFW_INFO_TEXT:
411 region_name = "Information";
412 text = kzalloc(le32_to_cpu(region->len) + 1,
413 GFP_KERNEL);
414 break;
415 case WMFW_ABSOLUTE:
416 region_name = "Absolute";
417 reg = offset;
418 break;
419 case WMFW_ADSP1_PM:
420 BUG_ON(!mem);
421 region_name = "PM";
45b9ee72 422 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 423 break;
424 case WMFW_ADSP1_DM:
425 BUG_ON(!mem);
426 region_name = "DM";
45b9ee72 427 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 428 break;
429 case WMFW_ADSP2_XM:
430 BUG_ON(!mem);
431 region_name = "XM";
45b9ee72 432 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 433 break;
434 case WMFW_ADSP2_YM:
435 BUG_ON(!mem);
436 region_name = "YM";
45b9ee72 437 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 438 break;
439 case WMFW_ADSP1_ZM:
440 BUG_ON(!mem);
441 region_name = "ZM";
45b9ee72 442 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 443 break;
444 default:
445 adsp_warn(dsp,
446 "%s.%d: Unknown region type %x at %d(%x)\n",
447 file, regions, type, pos, pos);
448 break;
449 }
450
451 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
452 regions, le32_to_cpu(region->len), offset,
453 region_name);
454
455 if (text) {
456 memcpy(text, region->data, le32_to_cpu(region->len));
457 adsp_info(dsp, "%s: %s\n", file, text);
458 kfree(text);
459 }
460
461 if (reg) {
cf17c83c
MB		 462 buf = wm_adsp_buf_alloc(region->data,
463 le32_to_cpu(region->len),
464 &buf_list);
a76fefab
MB		 465 if (!buf) {
466 adsp_err(dsp, "Out of memory\n");
467 return -ENOMEM;
468 }
469
cf17c83c
MB		 470 ret = regmap_raw_write_async(regmap, reg, buf->buf,
471 le32_to_cpu(region->len));
2159ad93
MB		 472 if (ret != 0) {
473 adsp_err(dsp,
474 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
475 file, regions,
476 le32_to_cpu(region->len), offset,
477 region_name, ret);
478 goto out_fw;
479 }
480 }
481
482 pos += le32_to_cpu(region->len) + sizeof(*region);
483 regions++;
484 }
cf17c83c
MB		 485
486 ret = regmap_async_complete(regmap);
487 if (ret != 0) {
488 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
489 goto out_fw;
490 }
491
2159ad93
MB		 492 if (pos > firmware->size)
493 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
494 file, regions, pos - firmware->size);
495
496out_fw:
cf17c83c
MB		 497 regmap_async_complete(regmap);
498 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 499 release_firmware(firmware);
500out:
501 kfree(file);
502
503 return ret;
504}
505
db40517c
MB		 506static int wm_adsp_setup_algs(struct wm_adsp *dsp)
507{
508 struct regmap *regmap = dsp->regmap;
509 struct wmfw_adsp1_id_hdr adsp1_id;
510 struct wmfw_adsp2_id_hdr adsp2_id;
511 struct wmfw_adsp1_alg_hdr *adsp1_alg;
512 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 513 void *alg, *buf;
471f4885 514 struct wm_adsp_alg_region *region;
db40517c
MB		 515 const struct wm_adsp_region *mem;
516 unsigned int pos, term;
d62f4bc6 517 size_t algs, buf_size;
db40517c
MB		 518 __be32 val;
519 int i, ret;
520
521 switch (dsp->type) {
522 case WMFW_ADSP1:
523 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
524 break;
525 case WMFW_ADSP2:
526 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
527 break;
528 default:
529 mem = NULL;
530 break;
531 }
532
533 if (mem == NULL) {
534 BUG_ON(mem != NULL);
535 return -EINVAL;
536 }
537
538 switch (dsp->type) {
539 case WMFW_ADSP1:
540 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
541 sizeof(adsp1_id));
542 if (ret != 0) {
543 adsp_err(dsp, "Failed to read algorithm info: %d\n",
544 ret);
545 return ret;
546 }
547
d62f4bc6
MB		 548 buf = &adsp1_id;
549 buf_size = sizeof(adsp1_id);
550
db40517c 551 algs = be32_to_cpu(adsp1_id.algs);
f395a218 552 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
db40517c 553 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
f395a218 554 dsp->fw_id,
db40517c
MB		 555 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
556 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
557 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
558 algs);
559
560 pos = sizeof(adsp1_id) / 2;
561 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
562 break;
563
564 case WMFW_ADSP2:
565 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
566 sizeof(adsp2_id));
567 if (ret != 0) {
568 adsp_err(dsp, "Failed to read algorithm info: %d\n",
569 ret);
570 return ret;
571 }
572
d62f4bc6
MB		 573 buf = &adsp2_id;
574 buf_size = sizeof(adsp2_id);
575
db40517c 576 algs = be32_to_cpu(adsp2_id.algs);
f395a218 577 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
db40517c 578 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
f395a218 579 dsp->fw_id,
db40517c
MB		 580 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
581 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
582 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
583 algs);
584
585 pos = sizeof(adsp2_id) / 2;
586 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
587 break;
588
589 default:
590 BUG_ON(NULL == "Unknown DSP type");
591 return -EINVAL;
592 }
593
594 if (algs == 0) {
595 adsp_err(dsp, "No algorithms\n");
596 return -EINVAL;
597 }
598
d62f4bc6
MB		 599 if (algs > 1024) {
600 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
601 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
602 buf, buf_size);
603 return -EINVAL;
604 }
605
db40517c
MB		 606 /* Read the terminator first to validate the length */
607 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
608 if (ret != 0) {
609 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
610 ret);
611 return ret;
612 }
613
614 if (be32_to_cpu(val) != 0xbedead)
615 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
616 term, be32_to_cpu(val));
617
f2a93e2a 618 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
db40517c
MB		 619 if (!alg)
620 return -ENOMEM;
621
622 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
623 if (ret != 0) {
624 adsp_err(dsp, "Failed to read algorithm list: %d\n",
625 ret);
626 goto out;
627 }
628
629 adsp1_alg = alg;
630 adsp2_alg = alg;
631
632 for (i = 0; i < algs; i++) {
633 switch (dsp->type) {
634 case WMFW_ADSP1:
471f4885 635 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
db40517c
MB		 636 i, be32_to_cpu(adsp1_alg[i].alg.id),
637 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
638 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 639 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
640 be32_to_cpu(adsp1_alg[i].dm),
641 be32_to_cpu(adsp1_alg[i].zm));
642
7480800e
MB		 643 region = kzalloc(sizeof(*region), GFP_KERNEL);
644 if (!region)
645 return -ENOMEM;
646 region->type = WMFW_ADSP1_DM;
647 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
648 region->base = be32_to_cpu(adsp1_alg[i].dm);
649 list_add_tail(&region->list, &dsp->alg_regions);
471f4885 650
7480800e
MB		 651 region = kzalloc(sizeof(*region), GFP_KERNEL);
652 if (!region)
653 return -ENOMEM;
654 region->type = WMFW_ADSP1_ZM;
655 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
656 region->base = be32_to_cpu(adsp1_alg[i].zm);
657 list_add_tail(&region->list, &dsp->alg_regions);
db40517c
MB		 658 break;
659
660 case WMFW_ADSP2:
471f4885
MB		 661 adsp_info(dsp,
662 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
db40517c
MB		 663 i, be32_to_cpu(adsp2_alg[i].alg.id),
664 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
665 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
471f4885
MB		 666 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
667 be32_to_cpu(adsp2_alg[i].xm),
668 be32_to_cpu(adsp2_alg[i].ym),
669 be32_to_cpu(adsp2_alg[i].zm));
670
7480800e
MB		 671 region = kzalloc(sizeof(*region), GFP_KERNEL);
672 if (!region)
673 return -ENOMEM;
674 region->type = WMFW_ADSP2_XM;
675 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
676 region->base = be32_to_cpu(adsp2_alg[i].xm);
677 list_add_tail(&region->list, &dsp->alg_regions);
471f4885 678
7480800e
MB		 679 region = kzalloc(sizeof(*region), GFP_KERNEL);
680 if (!region)
681 return -ENOMEM;
682 region->type = WMFW_ADSP2_YM;
683 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
684 region->base = be32_to_cpu(adsp2_alg[i].ym);
685 list_add_tail(&region->list, &dsp->alg_regions);
471f4885 686
7480800e
MB		 687 region = kzalloc(sizeof(*region), GFP_KERNEL);
688 if (!region)
689 return -ENOMEM;
690 region->type = WMFW_ADSP2_ZM;
691 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
692 region->base = be32_to_cpu(adsp2_alg[i].zm);
693 list_add_tail(&region->list, &dsp->alg_regions);
db40517c
MB		 694 break;
695 }
696 }
697
698out:
699 kfree(alg);
700 return ret;
701}
702
2159ad93
MB		 703static int wm_adsp_load_coeff(struct wm_adsp *dsp)
704{
cf17c83c 705 LIST_HEAD(buf_list);
2159ad93
MB		 706 struct regmap *regmap = dsp->regmap;
707 struct wmfw_coeff_hdr *hdr;
708 struct wmfw_coeff_item *blk;
709 const struct firmware *firmware;
471f4885
MB		 710 const struct wm_adsp_region *mem;
711 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 712 const char *region_name;
713 int ret, pos, blocks, type, offset, reg;
714 char *file;
cf17c83c 715 struct wm_adsp_buf *buf;
bdaacea3 716 int tmp;
2159ad93
MB		 717
718 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
719 if (file == NULL)
720 return -ENOMEM;
721
1023dbd9
MB		 722 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
723 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 724 file[PAGE_SIZE - 1] = '\0';
725
726 ret = request_firmware(&firmware, file, dsp->dev);
727 if (ret != 0) {
728 adsp_warn(dsp, "Failed to request '%s'\n", file);
729 ret = 0;
730 goto out;
731 }
732 ret = -EINVAL;
733
734 if (sizeof(*hdr) >= firmware->size) {
735 adsp_err(dsp, "%s: file too short, %zu bytes\n",
736 file, firmware->size);
737 goto out_fw;
738 }
739
740 hdr = (void*)&firmware->data[0];
741 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
742 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 743 goto out_fw;
2159ad93
MB		 744 }
745
c712326d
MB		 746 switch (be32_to_cpu(hdr->rev) & 0xff) {
747 case 1:
748 break;
749 default:
750 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
751 file, be32_to_cpu(hdr->rev) & 0xff);
752 ret = -EINVAL;
753 goto out_fw;
754 }
755
2159ad93
MB		 756 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
757 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
758 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
759 le32_to_cpu(hdr->ver) & 0xff);
760
761 pos = le32_to_cpu(hdr->len);
762
763 blocks = 0;
764 while (pos < firmware->size &&
765 pos - firmware->size > sizeof(*blk)) {
766 blk = (void*)(&firmware->data[pos]);
767
c712326d
MB		 768 type = le16_to_cpu(blk->type);
769 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 770
771 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
772 file, blocks, le32_to_cpu(blk->id),
773 (le32_to_cpu(blk->ver) >> 16) & 0xff,
774 (le32_to_cpu(blk->ver) >> 8) & 0xff,
775 le32_to_cpu(blk->ver) & 0xff);
776 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
777 file, blocks, le32_to_cpu(blk->len), offset, type);
778
779 reg = 0;
780 region_name = "Unknown";
781 switch (type) {
c712326d
MB		 782 case (WMFW_NAME_TEXT << 8):
783 case (WMFW_INFO_TEXT << 8):
2159ad93 784 break;
c712326d 785 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 786 /*
787 * Old files may use this for global
788 * coefficients.
789 */
790 if (le32_to_cpu(blk->id) == dsp->fw_id &&
791 offset == 0) {
792 region_name = "global coefficients";
793 mem = wm_adsp_find_region(dsp, type);
794 if (!mem) {
795 adsp_err(dsp, "No ZM\n");
796 break;
797 }
798 reg = wm_adsp_region_to_reg(mem, 0);
799
800 } else {
801 region_name = "register";
802 reg = offset;
803 }
2159ad93 804 break;
471f4885
MB		 805
806 case WMFW_ADSP1_DM:
807 case WMFW_ADSP1_ZM:
808 case WMFW_ADSP2_XM:
809 case WMFW_ADSP2_YM:
810 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
811 file, blocks, le32_to_cpu(blk->len),
812 type, le32_to_cpu(blk->id));
813
814 mem = wm_adsp_find_region(dsp, type);
815 if (!mem) {
816 adsp_err(dsp, "No base for region %x\n", type);
817 break;
818 }
819
820 reg = 0;
821 list_for_each_entry(alg_region,
822 &dsp->alg_regions, list) {
823 if (le32_to_cpu(blk->id) == alg_region->alg &&
824 type == alg_region->type) {
338c5188 825 reg = alg_region->base;
471f4885
MB		 826 reg = wm_adsp_region_to_reg(mem,
827 reg);
338c5188 828 reg += offset;
471f4885
MB		 829 }
830 }
831
832 if (reg == 0)
833 adsp_err(dsp, "No %x for algorithm %x\n",
834 type, le32_to_cpu(blk->id));
835 break;
836
2159ad93 837 default:
25c62f7e
MB		 838 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
839 file, blocks, type, pos);
2159ad93
MB		 840 break;
841 }
842
843 if (reg) {
cf17c83c
MB		 844 buf = wm_adsp_buf_alloc(blk->data,
845 le32_to_cpu(blk->len),
846 &buf_list);
a76fefab
MB		 847 if (!buf) {
848 adsp_err(dsp, "Out of memory\n");
849 return -ENOMEM;
850 }
851
20da6d5a
MB		 852 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
853 file, blocks, le32_to_cpu(blk->len),
854 reg);
cf17c83c
MB		 855 ret = regmap_raw_write_async(regmap, reg, buf->buf,
856 le32_to_cpu(blk->len));
2159ad93
MB		 857 if (ret != 0) {
858 adsp_err(dsp,
859 "%s.%d: Failed to write to %x in %s\n",
860 file, blocks, reg, region_name);
861 }
862 }
863
bdaacea3
CR		 864 tmp = le32_to_cpu(blk->len) % 4;
865 if (tmp)
866 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
867 else
868 pos += le32_to_cpu(blk->len) + sizeof(*blk);
869
2159ad93
MB		 870 blocks++;
871 }
872
cf17c83c
MB		 873 ret = regmap_async_complete(regmap);
874 if (ret != 0)
875 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
876
2159ad93
MB		 877 if (pos > firmware->size)
878 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
879 file, blocks, pos - firmware->size);
880
881out_fw:
882 release_firmware(firmware);
cf17c83c 883 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 884out:
885 kfree(file);
886 return 0;
887}
888
5e7a7a22
MB		 889int wm_adsp1_init(struct wm_adsp *adsp)
890{
891 INIT_LIST_HEAD(&adsp->alg_regions);
892
893 return 0;
894}
895EXPORT_SYMBOL_GPL(wm_adsp1_init);
896
2159ad93
MB		 897int wm_adsp1_event(struct snd_soc_dapm_widget *w,
898 struct snd_kcontrol *kcontrol,
899 int event)
900{
901 struct snd_soc_codec *codec = w->codec;
902 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
903 struct wm_adsp *dsp = &dsps[w->shift];
904 int ret;
94e205bf 905 int val;
2159ad93
MB		 906
907 switch (event) {
908 case SND_SOC_DAPM_POST_PMU:
909 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
910 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
911
94e205bf
CR		 912 /*
913 * For simplicity set the DSP clock rate to be the
914 * SYSCLK rate rather than making it configurable.
915 */
916 if(dsp->sysclk_reg) {
917 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
918 if (ret != 0) {
919 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
920 ret);
921 return ret;
922 }
923
924 val = (val & dsp->sysclk_mask)
925 >> dsp->sysclk_shift;
926
927 ret = regmap_update_bits(dsp->regmap,
928 dsp->base + ADSP1_CONTROL_31,
929 ADSP1_CLK_SEL_MASK, val);
930 if (ret != 0) {
931 adsp_err(dsp, "Failed to set clock rate: %d\n",
932 ret);
933 return ret;
934 }
935 }
936
2159ad93
MB		 937 ret = wm_adsp_load(dsp);
938 if (ret != 0)
939 goto err;
940
db40517c
MB		 941 ret = wm_adsp_setup_algs(dsp);
942 if (ret != 0)
943 goto err;
944
2159ad93
MB		 945 ret = wm_adsp_load_coeff(dsp);
946 if (ret != 0)
947 goto err;
948
949 /* Start the core running */
950 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
951 ADSP1_CORE_ENA | ADSP1_START,
952 ADSP1_CORE_ENA | ADSP1_START);
953 break;
954
955 case SND_SOC_DAPM_PRE_PMD:
956 /* Halt the core */
957 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
958 ADSP1_CORE_ENA | ADSP1_START, 0);
959
960 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
961 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
962
963 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
964 ADSP1_SYS_ENA, 0);
965 break;
966
967 default:
968 break;
969 }
970
971 return 0;
972
973err:
974 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
975 ADSP1_SYS_ENA, 0);
976 return ret;
977}
978EXPORT_SYMBOL_GPL(wm_adsp1_event);
979
980static int wm_adsp2_ena(struct wm_adsp *dsp)
981{
982 unsigned int val;
983 int ret, count;
984
985 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
986 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
987 if (ret != 0)
988 return ret;
989
990 /* Wait for the RAM to start, should be near instantaneous */
991 count = 0;
992 do {
993 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
994 &val);
995 if (ret != 0)
996 return ret;
997 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
998
999 if (!(val & ADSP2_RAM_RDY)) {
1000 adsp_err(dsp, "Failed to start DSP RAM\n");
1001 return -EBUSY;
1002 }
1003
1004 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1005 adsp_info(dsp, "RAM ready after %d polls\n", count);
1006
1007 return 0;
1008}
1009
1010int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1011 struct snd_kcontrol *kcontrol, int event)
1012{
1013 struct snd_soc_codec *codec = w->codec;
1014 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1015 struct wm_adsp *dsp = &dsps[w->shift];
471f4885 1016 struct wm_adsp_alg_region *alg_region;
973838a0 1017 unsigned int val;
2159ad93
MB		 1018 int ret;
1019
1020 switch (event) {
1021 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 1022 /*
1023 * For simplicity set the DSP clock rate to be the
1024 * SYSCLK rate rather than making it configurable.
1025 */
1026 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1027 if (ret != 0) {
1028 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1029 ret);
1030 return ret;
1031 }
1032 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1033 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1034
1035 ret = regmap_update_bits(dsp->regmap,
1036 dsp->base + ADSP2_CLOCKING,
1037 ADSP2_CLK_SEL_MASK, val);
1038 if (ret != 0) {
1039 adsp_err(dsp, "Failed to set clock rate: %d\n",
1040 ret);
1041 return ret;
1042 }
1043
973838a0
MB		 1044 if (dsp->dvfs) {
1045 ret = regmap_read(dsp->regmap,
1046 dsp->base + ADSP2_CLOCKING, &val);
1047 if (ret != 0) {
1048 dev_err(dsp->dev,
1049 "Failed to read clocking: %d\n", ret);
1050 return ret;
1051 }
1052
25c6fdb0 1053 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 1054 ret = regulator_enable(dsp->dvfs);
1055 if (ret != 0) {
1056 dev_err(dsp->dev,
1057 "Failed to enable supply: %d\n",
1058 ret);
1059 return ret;
1060 }
1061
1062 ret = regulator_set_voltage(dsp->dvfs,
1063 1800000,
1064 1800000);
1065 if (ret != 0) {
1066 dev_err(dsp->dev,
1067 "Failed to raise supply: %d\n",
1068 ret);
1069 return ret;
1070 }
1071 }
1072 }
1073
2159ad93
MB		 1074 ret = wm_adsp2_ena(dsp);
1075 if (ret != 0)
1076 return ret;
1077
1078 ret = wm_adsp_load(dsp);
1079 if (ret != 0)
1080 goto err;
1081
db40517c
MB		 1082 ret = wm_adsp_setup_algs(dsp);
1083 if (ret != 0)
1084 goto err;
1085
2159ad93
MB		 1086 ret = wm_adsp_load_coeff(dsp);
1087 if (ret != 0)
1088 goto err;
1089
1090 ret = regmap_update_bits(dsp->regmap,
1091 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1092 ADSP2_CORE_ENA | ADSP2_START,
1093 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 1094 if (ret != 0)
1095 goto err;
1023dbd9
MB		 1096
1097 dsp->running = true;
2159ad93
MB		 1098 break;
1099
1100 case SND_SOC_DAPM_PRE_PMD:
1023dbd9
MB		 1101 dsp->running = false;
1102
2159ad93 1103 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 1104 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1105 ADSP2_START, 0);
973838a0 1106
2d30b575
MB		 1107 /* Make sure DMAs are quiesced */
1108 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1109 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1110 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1111
973838a0
MB		 1112 if (dsp->dvfs) {
1113 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1114 1800000);
1115 if (ret != 0)
1116 dev_warn(dsp->dev,
1117 "Failed to lower supply: %d\n",
1118 ret);
1119
1120 ret = regulator_disable(dsp->dvfs);
1121 if (ret != 0)
1122 dev_err(dsp->dev,
1123 "Failed to enable supply: %d\n",
1124 ret);
1125 }
471f4885
MB		 1126
1127 while (!list_empty(&dsp->alg_regions)) {
1128 alg_region = list_first_entry(&dsp->alg_regions,
1129 struct wm_adsp_alg_region,
1130 list);
1131 list_del(&alg_region->list);
1132 kfree(alg_region);
1133 }
2159ad93
MB		 1134 break;
1135
1136 default:
1137 break;
1138 }
1139
1140 return 0;
1141err:
1142 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 1143 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 1144 return ret;
1145}
1146EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 1147
1148int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1149{
1150 int ret;
1151
10a2b662
MB		 1152 /*
1153 * Disable the DSP memory by default when in reset for a small
1154 * power saving.
1155 */
1156 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1157 ADSP2_MEM_ENA, 0);
1158 if (ret != 0) {
1159 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1160 return ret;
1161 }
1162
471f4885
MB		 1163 INIT_LIST_HEAD(&adsp->alg_regions);
1164
973838a0
MB		 1165 if (dvfs) {
1166 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1167 if (IS_ERR(adsp->dvfs)) {
1168 ret = PTR_ERR(adsp->dvfs);
1169 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
1170 return ret;
1171 }
1172
1173 ret = regulator_enable(adsp->dvfs);
1174 if (ret != 0) {
1175 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1176 ret);
1177 return ret;
1178 }
1179
1180 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1181 if (ret != 0) {
1182 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1183 ret);
1184 return ret;
1185 }
1186
1187 ret = regulator_disable(adsp->dvfs);
1188 if (ret != 0) {
1189 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1190 ret);
1191 return ret;
1192 }
1193 }
1194
1195 return 0;
1196}
1197EXPORT_SYMBOL_GPL(wm_adsp2_init);
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