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x86/cpu: Sanitize FAM6_ATOM naming
[linux.git] / arch / x86 / events / intel / core.c
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a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
aacfbe6a 15#include <linux/nmi.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7 18#include <asm/hardirq.h>
ef5f9f47 19#include <asm/intel-family.h>
de0428a7
KW		 20#include <asm/apic.h>
21
27f6d22b 22#include "../perf_event.h"
a7e3ed1e 23
f22f54f4 24/*
b622d644 25 * Intel PerfMon, used on Core and later.
f22f54f4 26 */
ec75a716 27static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 28{
c3b7cdf1
PE		 29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 37};
38
5c543e3c 39static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 40{
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
47 EVENT_CONSTRAINT_END
48};
49
5c543e3c 50static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 51{
b622d644
PZ		 52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
65 EVENT_CONSTRAINT_END
66};
67
5c543e3c 68static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 69{
b622d644
PZ		 70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
81 EVENT_CONSTRAINT_END
82};
83
5c543e3c 84static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 85{
53ad0447
YZ		 86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 89 EVENT_EXTRA_END
90};
91
5c543e3c 92static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 93{
b622d644
PZ		 94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 101 EVENT_CONSTRAINT_END
102};
103
5c543e3c 104static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 105{
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c 118
9010ae4a
SE		 119 /*
120 * When HT is off these events can only run on the bottom 4 counters
121 * When HT is on, they are impacted by the HT bug and require EXCL access
122 */
93fcf72c
MD		 123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
127
b06b3d49
LM		 128 EVENT_CONSTRAINT_END
129};
130
69943182
SE		 131static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
132{
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c 146
9010ae4a
SE		 147 /*
148 * When HT is off these events can only run on the bottom 4 counters
149 * When HT is on, they are impacted by the HT bug and require EXCL access
150 */
93fcf72c
MD		 151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
155
69943182
SE		 156 EVENT_CONSTRAINT_END
157};
158
5c543e3c 159static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 160{
53ad0447
YZ		 161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 165 EVENT_EXTRA_END
166};
167
0af3ac1f
AK		 168static struct event_constraint intel_v1_event_constraints[] __read_mostly =
169{
170 EVENT_CONSTRAINT_END
171};
172
5c543e3c 173static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 174{
b622d644
PZ		 175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 178 EVENT_CONSTRAINT_END
179};
180
1fa64180
YZ		 181static struct event_constraint intel_slm_event_constraints[] __read_mostly =
182{
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
186 EVENT_CONSTRAINT_END
187};
188
20f36278 189static struct event_constraint intel_skl_event_constraints[] = {
9a92e16f
AK		 190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
9010ae4a
SE		 194
195 /*
196 * when HT is off, these can only run on the bottom 4 counters
197 */
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
203
9a92e16f
AK		 204 EVENT_CONSTRAINT_END
205};
206
1e7b9390 207static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
9c489fce
LO		 208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
1e7b9390
HC		 210 EVENT_EXTRA_END
211};
212
ee89cbc2 213static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 218 EVENT_EXTRA_END
219};
220
221static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 226 EVENT_EXTRA_END
227};
228
9a92e16f
AK		 229static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
dfe1f3cb
AK		 233 /*
234 * Note the low 8 bits eventsel code is not a continuous field, containing
235 * some #GPing bits. These are masked out.
236 */
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
9a92e16f
AK		 238 EVENT_EXTRA_END
239};
240
7f2ee91f
IM		 241EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
242EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
243EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee 244
20f36278 245static struct attribute *nhm_events_attrs[] = {
f20093ee
SE		 246 EVENT_PTR(mem_ld_nhm),
247 NULL,
248};
249
a39fcae7
AK		 250/*
251 * topdown events for Intel Core CPUs.
252 *
253 * The events are all in slots, which is a free slot in a 4 wide
254 * pipeline. Some events are already reported in slots, for cycle
255 * events we multiply by the pipeline width (4).
256 *
257 * With Hyper Threading on, topdown metrics are either summed or averaged
258 * between the threads of a core: (count_t0 + count_t1).
259 *
260 * For the average case the metric is always scaled to pipeline width,
261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
262 */
263
264EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
267EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
268EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
269 "event=0xe,umask=0x1"); /* uops_issued.any */
270EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
272EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
274EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
277EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
278 "4", "2");
279
20f36278 280static struct attribute *snb_events_attrs[] = {
f20093ee 281 EVENT_PTR(mem_ld_snb),
9ad64c0f 282 EVENT_PTR(mem_st_snb),
a39fcae7
AK		 283 EVENT_PTR(td_slots_issued),
284 EVENT_PTR(td_slots_retired),
285 EVENT_PTR(td_fetch_bubbles),
286 EVENT_PTR(td_total_slots),
287 EVENT_PTR(td_total_slots_scale),
288 EVENT_PTR(td_recovery_bubbles),
289 EVENT_PTR(td_recovery_bubbles_scale),
f20093ee
SE		 290 NULL,
291};
292
3a632cb2
AK		 293static struct event_constraint intel_hsw_event_constraints[] = {
294 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
295 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
296 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
e0fbac1c 297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
3a632cb2
AK		 298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
300 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 302 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 304 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c 306
9010ae4a
SE		 307 /*
308 * When HT is off these events can only run on the bottom 4 counters
309 * When HT is on, they are impacted by the HT bug and require EXCL access
310 */
93fcf72c
MD		 311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
315
3a632cb2
AK		 316 EVENT_CONSTRAINT_END
317};
318
20f36278 319static struct event_constraint intel_bdw_event_constraints[] = {
91f1b705
AK		 320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
322 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
b7883a1c 324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
9010ae4a
SE		 325 /*
326 * when HT is off, these can only run on the bottom 4 counters
327 */
328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
91f1b705
AK		 332 EVENT_CONSTRAINT_END
333};
334
f22f54f4
PZ		 335static u64 intel_pmu_event_map(int hw_event)
336{
337 return intel_perfmon_event_map[hw_event];
338}
339
9a92e16f
AK		 340/*
341 * Notes on the events:
342 * - data reads do not include code reads (comparable to earlier tables)
343 * - data counts include speculative execution (except L1 write, dtlb, bpu)
344 * - remote node access includes remote memory, remote cache, remote mmio.
345 * - prefetches are not included in the counts.
346 * - icache miss does not include decoded icache
347 */
348
349#define SKL_DEMAND_DATA_RD BIT_ULL(0)
350#define SKL_DEMAND_RFO BIT_ULL(1)
351#define SKL_ANY_RESPONSE BIT_ULL(16)
352#define SKL_SUPPLIER_NONE BIT_ULL(17)
353#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
354#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
355#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
356#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
357#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
360 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
361#define SKL_SPL_HIT BIT_ULL(30)
362#define SKL_SNOOP_NONE BIT_ULL(31)
363#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
364#define SKL_SNOOP_MISS BIT_ULL(33)
365#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
366#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
367#define SKL_SNOOP_HITM BIT_ULL(36)
368#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
369#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
373#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
374#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
377 SKL_SNOOP_HITM|SKL_SPL_HIT)
378#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
379#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
380#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
382 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
383
384static __initconst const u64 skl_hw_cache_event_ids
385 [PERF_COUNT_HW_CACHE_MAX]
386 [PERF_COUNT_HW_CACHE_OP_MAX]
387 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
388{
389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
393 },
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS) ] = 0x0,
397 },
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
401 },
402 },
403 [ C(L1I ) ] = {
404 [ C(OP_READ) ] = {
405 [ C(RESULT_ACCESS) ] = 0x0,
406 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
407 },
408 [ C(OP_WRITE) ] = {
409 [ C(RESULT_ACCESS) ] = -1,
410 [ C(RESULT_MISS) ] = -1,
411 },
412 [ C(OP_PREFETCH) ] = {
413 [ C(RESULT_ACCESS) ] = 0x0,
414 [ C(RESULT_MISS) ] = 0x0,
415 },
416 },
417 [ C(LL ) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
420 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
421 },
422 [ C(OP_WRITE) ] = {
423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
425 },
426 [ C(OP_PREFETCH) ] = {
427 [ C(RESULT_ACCESS) ] = 0x0,
428 [ C(RESULT_MISS) ] = 0x0,
429 },
430 },
431 [ C(DTLB) ] = {
432 [ C(OP_READ) ] = {
433 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
fb3a5055 434 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
9a92e16f
AK		 435 },
436 [ C(OP_WRITE) ] = {
437 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
fb3a5055 438 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
9a92e16f
AK		 439 },
440 [ C(OP_PREFETCH) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x0,
443 },
444 },
445 [ C(ITLB) ] = {
446 [ C(OP_READ) ] = {
447 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
448 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
449 },
450 [ C(OP_WRITE) ] = {
451 [ C(RESULT_ACCESS) ] = -1,
452 [ C(RESULT_MISS) ] = -1,
453 },
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 },
459 [ C(BPU ) ] = {
460 [ C(OP_READ) ] = {
461 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
462 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
463 },
464 [ C(OP_WRITE) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
467 },
468 [ C(OP_PREFETCH) ] = {
469 [ C(RESULT_ACCESS) ] = -1,
470 [ C(RESULT_MISS) ] = -1,
471 },
472 },
473 [ C(NODE) ] = {
474 [ C(OP_READ) ] = {
475 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
476 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
477 },
478 [ C(OP_WRITE) ] = {
479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
481 },
482 [ C(OP_PREFETCH) ] = {
483 [ C(RESULT_ACCESS) ] = 0x0,
484 [ C(RESULT_MISS) ] = 0x0,
485 },
486 },
487};
488
489static __initconst const u64 skl_hw_cache_extra_regs
490 [PERF_COUNT_HW_CACHE_MAX]
491 [PERF_COUNT_HW_CACHE_OP_MAX]
492 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
493{
494 [ C(LL ) ] = {
495 [ C(OP_READ) ] = {
496 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
497 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
498 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
499 SKL_L3_MISS|SKL_ANY_SNOOP|
500 SKL_SUPPLIER_NONE,
501 },
502 [ C(OP_WRITE) ] = {
503 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
504 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
505 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
506 SKL_L3_MISS|SKL_ANY_SNOOP|
507 SKL_SUPPLIER_NONE,
508 },
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
512 },
513 },
514 [ C(NODE) ] = {
515 [ C(OP_READ) ] = {
516 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
517 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
518 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
519 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
520 },
521 [ C(OP_WRITE) ] = {
522 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
523 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
524 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
525 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x0,
529 [ C(RESULT_MISS) ] = 0x0,
530 },
531 },
532};
533
74e6543f
YZ		 534#define SNB_DMND_DATA_RD (1ULL << 0)
535#define SNB_DMND_RFO (1ULL << 1)
536#define SNB_DMND_IFETCH (1ULL << 2)
537#define SNB_DMND_WB (1ULL << 3)
538#define SNB_PF_DATA_RD (1ULL << 4)
539#define SNB_PF_RFO (1ULL << 5)
540#define SNB_PF_IFETCH (1ULL << 6)
541#define SNB_LLC_DATA_RD (1ULL << 7)
542#define SNB_LLC_RFO (1ULL << 8)
543#define SNB_LLC_IFETCH (1ULL << 9)
544#define SNB_BUS_LOCKS (1ULL << 10)
545#define SNB_STRM_ST (1ULL << 11)
546#define SNB_OTHER (1ULL << 15)
547#define SNB_RESP_ANY (1ULL << 16)
548#define SNB_NO_SUPP (1ULL << 17)
549#define SNB_LLC_HITM (1ULL << 18)
550#define SNB_LLC_HITE (1ULL << 19)
551#define SNB_LLC_HITS (1ULL << 20)
552#define SNB_LLC_HITF (1ULL << 21)
553#define SNB_LOCAL (1ULL << 22)
554#define SNB_REMOTE (0xffULL << 23)
555#define SNB_SNP_NONE (1ULL << 31)
556#define SNB_SNP_NOT_NEEDED (1ULL << 32)
557#define SNB_SNP_MISS (1ULL << 33)
558#define SNB_NO_FWD (1ULL << 34)
559#define SNB_SNP_FWD (1ULL << 35)
560#define SNB_HITM (1ULL << 36)
561#define SNB_NON_DRAM (1ULL << 37)
562
563#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
564#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
565#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
566
567#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
569 SNB_HITM)
570
571#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
572#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
573
574#define SNB_L3_ACCESS SNB_RESP_ANY
575#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
576
577static __initconst const u64 snb_hw_cache_extra_regs
578 [PERF_COUNT_HW_CACHE_MAX]
579 [PERF_COUNT_HW_CACHE_OP_MAX]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
581{
582 [ C(LL ) ] = {
583 [ C(OP_READ) ] = {
584 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
585 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
586 },
587 [ C(OP_WRITE) ] = {
588 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
589 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
590 },
591 [ C(OP_PREFETCH) ] = {
592 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
593 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
594 },
595 },
596 [ C(NODE) ] = {
597 [ C(OP_READ) ] = {
598 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
599 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
600 },
601 [ C(OP_WRITE) ] = {
602 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
603 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
604 },
605 [ C(OP_PREFETCH) ] = {
606 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
607 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
608 },
609 },
610};
611
b06b3d49
LM		 612static __initconst const u64 snb_hw_cache_event_ids
613 [PERF_COUNT_HW_CACHE_MAX]
614 [PERF_COUNT_HW_CACHE_OP_MAX]
615 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
616{
617 [ C(L1D) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
620 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
621 },
622 [ C(OP_WRITE) ] = {
623 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
624 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
625 },
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
629 },
630 },
631 [ C(L1I ) ] = {
632 [ C(OP_READ) ] = {
633 [ C(RESULT_ACCESS) ] = 0x0,
634 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
635 },
636 [ C(OP_WRITE) ] = {
637 [ C(RESULT_ACCESS) ] = -1,
638 [ C(RESULT_MISS) ] = -1,
639 },
640 [ C(OP_PREFETCH) ] = {
641 [ C(RESULT_ACCESS) ] = 0x0,
642 [ C(RESULT_MISS) ] = 0x0,
643 },
644 },
645 [ C(LL ) ] = {
b06b3d49 646 [ C(OP_READ) ] = {
63b6a675 647 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 648 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 649 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
650 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 651 },
652 [ C(OP_WRITE) ] = {
63b6a675 653 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 654 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 655 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
656 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 657 },
658 [ C(OP_PREFETCH) ] = {
63b6a675 659 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 660 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 661 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
662 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 663 },
664 },
665 [ C(DTLB) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
668 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
672 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x0,
677 },
678 },
679 [ C(ITLB) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
682 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = -1,
686 [ C(RESULT_MISS) ] = -1,
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
691 },
692 },
693 [ C(BPU ) ] = {
694 [ C(OP_READ) ] = {
695 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
696 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
697 },
698 [ C(OP_WRITE) ] = {
699 [ C(RESULT_ACCESS) ] = -1,
700 [ C(RESULT_MISS) ] = -1,
701 },
702 [ C(OP_PREFETCH) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
705 },
706 },
89d6c0b5
PZ		 707 [ C(NODE) ] = {
708 [ C(OP_READ) ] = {
74e6543f
YZ		 709 [ C(RESULT_ACCESS) ] = 0x01b7,
710 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 711 },
712 [ C(OP_WRITE) ] = {
74e6543f
YZ		 713 [ C(RESULT_ACCESS) ] = 0x01b7,
714 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 715 },
716 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 717 [ C(RESULT_ACCESS) ] = 0x01b7,
718 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 719 },
720 },
721
b06b3d49
LM		 722};
723
0f1b5ca2
AK		 724/*
725 * Notes on the events:
726 * - data reads do not include code reads (comparable to earlier tables)
727 * - data counts include speculative execution (except L1 write, dtlb, bpu)
728 * - remote node access includes remote memory, remote cache, remote mmio.
729 * - prefetches are not included in the counts because they are not
730 * reliably counted.
731 */
732
733#define HSW_DEMAND_DATA_RD BIT_ULL(0)
734#define HSW_DEMAND_RFO BIT_ULL(1)
735#define HSW_ANY_RESPONSE BIT_ULL(16)
736#define HSW_SUPPLIER_NONE BIT_ULL(17)
737#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
738#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
739#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
740#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
741#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
743 HSW_L3_MISS_REMOTE_HOP2P)
744#define HSW_SNOOP_NONE BIT_ULL(31)
745#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
746#define HSW_SNOOP_MISS BIT_ULL(33)
747#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
748#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
749#define HSW_SNOOP_HITM BIT_ULL(36)
750#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
751#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
755#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
756#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
757#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
758#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
760#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
761
91f1b705
AK		 762#define BDW_L3_MISS_LOCAL BIT(26)
763#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
765 HSW_L3_MISS_REMOTE_HOP2P)
766
767
0f1b5ca2
AK		 768static __initconst const u64 hsw_hw_cache_event_ids
769 [PERF_COUNT_HW_CACHE_MAX]
770 [PERF_COUNT_HW_CACHE_OP_MAX]
771 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
772{
773 [ C(L1D ) ] = {
774 [ C(OP_READ) ] = {
775 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
776 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
777 },
778 [ C(OP_WRITE) ] = {
779 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
780 [ C(RESULT_MISS) ] = 0x0,
781 },
782 [ C(OP_PREFETCH) ] = {
783 [ C(RESULT_ACCESS) ] = 0x0,
784 [ C(RESULT_MISS) ] = 0x0,
785 },
786 },
787 [ C(L1I ) ] = {
788 [ C(OP_READ) ] = {
789 [ C(RESULT_ACCESS) ] = 0x0,
790 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
791 },
792 [ C(OP_WRITE) ] = {
793 [ C(RESULT_ACCESS) ] = -1,
794 [ C(RESULT_MISS) ] = -1,
795 },
796 [ C(OP_PREFETCH) ] = {
797 [ C(RESULT_ACCESS) ] = 0x0,
798 [ C(RESULT_MISS) ] = 0x0,
799 },
800 },
801 [ C(LL ) ] = {
802 [ C(OP_READ) ] = {
803 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
804 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
805 },
806 [ C(OP_WRITE) ] = {
807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
809 },
810 [ C(OP_PREFETCH) ] = {
811 [ C(RESULT_ACCESS) ] = 0x0,
812 [ C(RESULT_MISS) ] = 0x0,
813 },
814 },
815 [ C(DTLB) ] = {
816 [ C(OP_READ) ] = {
817 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
818 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
822 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
823 },
824 [ C(OP_PREFETCH) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x0,
827 },
828 },
829 [ C(ITLB) ] = {
830 [ C(OP_READ) ] = {
831 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
832 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = -1,
836 [ C(RESULT_MISS) ] = -1,
837 },
838 [ C(OP_PREFETCH) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 },
843 [ C(BPU ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
846 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = -1,
850 [ C(RESULT_MISS) ] = -1,
851 },
852 [ C(OP_PREFETCH) ] = {
853 [ C(RESULT_ACCESS) ] = -1,
854 [ C(RESULT_MISS) ] = -1,
855 },
856 },
857 [ C(NODE) ] = {
858 [ C(OP_READ) ] = {
859 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
860 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
861 },
862 [ C(OP_WRITE) ] = {
863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
865 },
866 [ C(OP_PREFETCH) ] = {
867 [ C(RESULT_ACCESS) ] = 0x0,
868 [ C(RESULT_MISS) ] = 0x0,
869 },
870 },
871};
872
873static __initconst const u64 hsw_hw_cache_extra_regs
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877{
878 [ C(LL ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
881 HSW_LLC_ACCESS,
882 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
883 HSW_L3_MISS|HSW_ANY_SNOOP,
884 },
885 [ C(OP_WRITE) ] = {
886 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
887 HSW_LLC_ACCESS,
888 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
889 HSW_L3_MISS|HSW_ANY_SNOOP,
890 },
891 [ C(OP_PREFETCH) ] = {
892 [ C(RESULT_ACCESS) ] = 0x0,
893 [ C(RESULT_MISS) ] = 0x0,
894 },
895 },
896 [ C(NODE) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
899 HSW_L3_MISS_LOCAL_DRAM|
900 HSW_SNOOP_DRAM,
901 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
902 HSW_L3_MISS_REMOTE|
903 HSW_SNOOP_DRAM,
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
907 HSW_L3_MISS_LOCAL_DRAM|
908 HSW_SNOOP_DRAM,
909 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
910 HSW_L3_MISS_REMOTE|
911 HSW_SNOOP_DRAM,
912 },
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = 0x0,
915 [ C(RESULT_MISS) ] = 0x0,
916 },
917 },
918};
919
caaa8be3 920static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 921 [PERF_COUNT_HW_CACHE_MAX]
922 [PERF_COUNT_HW_CACHE_OP_MAX]
923 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
924{
925 [ C(L1D) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
929 },
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
932 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
933 },
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
936 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
937 },
938 },
939 [ C(L1I ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
942 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
943 },
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
947 },
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = 0x0,
950 [ C(RESULT_MISS) ] = 0x0,
951 },
952 },
953 [ C(LL ) ] = {
954 [ C(OP_READ) ] = {
63b6a675 955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 956 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
958 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 959 },
e994d7d2
AK		 960 /*
961 * Use RFO, not WRITEBACK, because a write miss would typically occur
962 * on RFO.
963 */
f22f54f4 964 [ C(OP_WRITE) ] = {
63b6a675
PZ		 965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 968 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 969 },
970 [ C(OP_PREFETCH) ] = {
63b6a675 971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 972 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
984 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
89d6c0b5
PZ		 1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
f22f54f4
PZ		 1033};
1034
e994d7d2 1035/*
63b6a675
PZ		 1036 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1037 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 1038 */
1039
63b6a675
PZ		 1040#define NHM_DMND_DATA_RD (1 << 0)
1041#define NHM_DMND_RFO (1 << 1)
1042#define NHM_DMND_IFETCH (1 << 2)
1043#define NHM_DMND_WB (1 << 3)
1044#define NHM_PF_DATA_RD (1 << 4)
1045#define NHM_PF_DATA_RFO (1 << 5)
1046#define NHM_PF_IFETCH (1 << 6)
1047#define NHM_OFFCORE_OTHER (1 << 7)
1048#define NHM_UNCORE_HIT (1 << 8)
1049#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1050#define NHM_OTHER_CORE_HITM (1 << 10)
1051 /* reserved */
1052#define NHM_REMOTE_CACHE_FWD (1 << 12)
1053#define NHM_REMOTE_DRAM (1 << 13)
1054#define NHM_LOCAL_DRAM (1 << 14)
1055#define NHM_NON_DRAM (1 << 15)
1056
87e24f4b
PZ		 1057#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1058#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 1059
1060#define NHM_DMND_READ (NHM_DMND_DATA_RD)
1061#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1062#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1063
1064#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 1065#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 1066#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 1067
1068static __initconst const u64 nehalem_hw_cache_extra_regs
1069 [PERF_COUNT_HW_CACHE_MAX]
1070 [PERF_COUNT_HW_CACHE_OP_MAX]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1072{
1073 [ C(LL ) ] = {
1074 [ C(OP_READ) ] = {
63b6a675
PZ		 1075 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1076 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 1077 },
1078 [ C(OP_WRITE) ] = {
63b6a675
PZ		 1079 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1080 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 1081 },
1082 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 1083 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1084 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 1085 },
89d6c0b5
PZ		 1086 },
1087 [ C(NODE) ] = {
1088 [ C(OP_READ) ] = {
87e24f4b
PZ		 1089 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1090 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 1091 },
1092 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 1093 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1094 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 1095 },
1096 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 1097 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1098 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 1099 },
1100 },
e994d7d2
AK		 1101};
1102
caaa8be3 1103static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 1104 [PERF_COUNT_HW_CACHE_MAX]
1105 [PERF_COUNT_HW_CACHE_OP_MAX]
1106 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1107{
1108 [ C(L1D) ] = {
1109 [ C(OP_READ) ] = {
f4929bd3
PZ		 1110 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1111 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 1112 },
1113 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 1114 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1115 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 1116 },
1117 [ C(OP_PREFETCH) ] = {
1118 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1119 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1120 },
1121 },
1122 [ C(L1I ) ] = {
1123 [ C(OP_READ) ] = {
1124 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1125 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1126 },
1127 [ C(OP_WRITE) ] = {
1128 [ C(RESULT_ACCESS) ] = -1,
1129 [ C(RESULT_MISS) ] = -1,
1130 },
1131 [ C(OP_PREFETCH) ] = {
1132 [ C(RESULT_ACCESS) ] = 0x0,
1133 [ C(RESULT_MISS) ] = 0x0,
1134 },
1135 },
1136 [ C(LL ) ] = {
1137 [ C(OP_READ) ] = {
e994d7d2
AK		 1138 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1141 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 1142 },
e994d7d2
AK		 1143 /*
1144 * Use RFO, not WRITEBACK, because a write miss would typically occur
1145 * on RFO.
1146 */
f22f54f4 1147 [ C(OP_WRITE) ] = {
e994d7d2
AK		 1148 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1149 [ C(RESULT_ACCESS) ] = 0x01b7,
1150 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1151 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1152 },
1153 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 1154 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1155 [ C(RESULT_ACCESS) ] = 0x01b7,
1156 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1157 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1158 },
1159 },
1160 [ C(DTLB) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1163 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1164 },
1165 [ C(OP_WRITE) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1167 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1168 },
1169 [ C(OP_PREFETCH) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0,
1171 [ C(RESULT_MISS) ] = 0x0,
1172 },
1173 },
1174 [ C(ITLB) ] = {
1175 [ C(OP_READ) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1177 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1178 },
1179 [ C(OP_WRITE) ] = {
1180 [ C(RESULT_ACCESS) ] = -1,
1181 [ C(RESULT_MISS) ] = -1,
1182 },
1183 [ C(OP_PREFETCH) ] = {
1184 [ C(RESULT_ACCESS) ] = -1,
1185 [ C(RESULT_MISS) ] = -1,
1186 },
1187 },
1188 [ C(BPU ) ] = {
1189 [ C(OP_READ) ] = {
1190 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1191 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1192 },
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = -1,
1195 [ C(RESULT_MISS) ] = -1,
1196 },
1197 [ C(OP_PREFETCH) ] = {
1198 [ C(RESULT_ACCESS) ] = -1,
1199 [ C(RESULT_MISS) ] = -1,
1200 },
1201 },
89d6c0b5
PZ		 1202 [ C(NODE) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x01b7,
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x01b7,
1209 [ C(RESULT_MISS) ] = 0x01b7,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01b7,
1213 [ C(RESULT_MISS) ] = 0x01b7,
1214 },
1215 },
f22f54f4
PZ		 1216};
1217
caaa8be3 1218static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 1219 [PERF_COUNT_HW_CACHE_MAX]
1220 [PERF_COUNT_HW_CACHE_OP_MAX]
1221 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1222{
1223 [ C(L1D) ] = {
1224 [ C(OP_READ) ] = {
1225 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1226 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1227 },
1228 [ C(OP_WRITE) ] = {
1229 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1230 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1231 },
1232 [ C(OP_PREFETCH) ] = {
1233 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1234 [ C(RESULT_MISS) ] = 0,
1235 },
1236 },
1237 [ C(L1I ) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1240 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = -1,
1244 [ C(RESULT_MISS) ] = -1,
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0,
1248 [ C(RESULT_MISS) ] = 0,
1249 },
1250 },
1251 [ C(LL ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1254 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1258 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0,
1262 [ C(RESULT_MISS) ] = 0,
1263 },
1264 },
1265 [ C(DTLB) ] = {
1266 [ C(OP_READ) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1268 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1269 },
1270 [ C(OP_WRITE) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1272 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1273 },
1274 [ C(OP_PREFETCH) ] = {
1275 [ C(RESULT_ACCESS) ] = 0,
1276 [ C(RESULT_MISS) ] = 0,
1277 },
1278 },
1279 [ C(ITLB) ] = {
1280 [ C(OP_READ) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1282 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1283 },
1284 [ C(OP_WRITE) ] = {
1285 [ C(RESULT_ACCESS) ] = -1,
1286 [ C(RESULT_MISS) ] = -1,
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 },
1293 [ C(BPU ) ] = {
1294 [ C(OP_READ) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1296 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1297 },
1298 [ C(OP_WRITE) ] = {
1299 [ C(RESULT_ACCESS) ] = -1,
1300 [ C(RESULT_MISS) ] = -1,
1301 },
1302 [ C(OP_PREFETCH) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 },
1307};
1308
caaa8be3 1309static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1310 [PERF_COUNT_HW_CACHE_MAX]
1311 [PERF_COUNT_HW_CACHE_OP_MAX]
1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1313{
1314 [ C(L1D) ] = {
1315 [ C(OP_READ) ] = {
1316 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1317 [ C(RESULT_MISS) ] = 0,
1318 },
1319 [ C(OP_WRITE) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1321 [ C(RESULT_MISS) ] = 0,
1322 },
1323 [ C(OP_PREFETCH) ] = {
1324 [ C(RESULT_ACCESS) ] = 0x0,
1325 [ C(RESULT_MISS) ] = 0,
1326 },
1327 },
1328 [ C(L1I ) ] = {
1329 [ C(OP_READ) ] = {
1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1332 },
1333 [ C(OP_WRITE) ] = {
1334 [ C(RESULT_ACCESS) ] = -1,
1335 [ C(RESULT_MISS) ] = -1,
1336 },
1337 [ C(OP_PREFETCH) ] = {
1338 [ C(RESULT_ACCESS) ] = 0,
1339 [ C(RESULT_MISS) ] = 0,
1340 },
1341 },
1342 [ C(LL ) ] = {
1343 [ C(OP_READ) ] = {
1344 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1345 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1346 },
1347 [ C(OP_WRITE) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1349 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1350 },
1351 [ C(OP_PREFETCH) ] = {
1352 [ C(RESULT_ACCESS) ] = 0,
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 },
1356 [ C(DTLB) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1359 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1363 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = 0,
1367 [ C(RESULT_MISS) ] = 0,
1368 },
1369 },
1370 [ C(ITLB) ] = {
1371 [ C(OP_READ) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1373 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1374 },
1375 [ C(OP_WRITE) ] = {
1376 [ C(RESULT_ACCESS) ] = -1,
1377 [ C(RESULT_MISS) ] = -1,
1378 },
1379 [ C(OP_PREFETCH) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 },
1384 [ C(BPU ) ] = {
1385 [ C(OP_READ) ] = {
1386 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1387 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1388 },
1389 [ C(OP_WRITE) ] = {
1390 [ C(RESULT_ACCESS) ] = -1,
1391 [ C(RESULT_MISS) ] = -1,
1392 },
1393 [ C(OP_PREFETCH) ] = {
1394 [ C(RESULT_ACCESS) ] = -1,
1395 [ C(RESULT_MISS) ] = -1,
1396 },
1397 },
1398};
1399
eb12b8ec
AK		 1400EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1401EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1402/* no_alloc_cycles.not_delivered */
1403EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1404 "event=0xca,umask=0x50");
1405EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1406/* uops_retired.all */
1407EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1408 "event=0xc2,umask=0x10");
1409/* uops_retired.all */
1410EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1411 "event=0xc2,umask=0x10");
1412
1413static struct attribute *slm_events_attrs[] = {
1414 EVENT_PTR(td_total_slots_slm),
1415 EVENT_PTR(td_total_slots_scale_slm),
1416 EVENT_PTR(td_fetch_bubbles_slm),
1417 EVENT_PTR(td_fetch_bubbles_scale_slm),
1418 EVENT_PTR(td_slots_issued_slm),
1419 EVENT_PTR(td_slots_retired_slm),
1420 NULL
1421};
1422
1fa64180
YZ		 1423static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1424{
1425 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1 1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
ae3f011f 1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1fa64180
YZ		 1428 EVENT_EXTRA_END
1429};
1430
1431#define SLM_DMND_READ SNB_DMND_DATA_RD
1432#define SLM_DMND_WRITE SNB_DMND_RFO
1433#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1434
1435#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1436#define SLM_LLC_ACCESS SNB_RESP_ANY
1437#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1438
1439static __initconst const u64 slm_hw_cache_extra_regs
1440 [PERF_COUNT_HW_CACHE_MAX]
1441 [PERF_COUNT_HW_CACHE_OP_MAX]
1442 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1443{
1444 [ C(LL ) ] = {
1445 [ C(OP_READ) ] = {
1446 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1447 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1448 },
1449 [ C(OP_WRITE) ] = {
1450 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1451 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1452 },
1453 [ C(OP_PREFETCH) ] = {
1454 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1455 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1456 },
1457 },
1458};
1459
1460static __initconst const u64 slm_hw_cache_event_ids
1461 [PERF_COUNT_HW_CACHE_MAX]
1462 [PERF_COUNT_HW_CACHE_OP_MAX]
1463 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1464{
1465 [ C(L1D) ] = {
1466 [ C(OP_READ) ] = {
1467 [ C(RESULT_ACCESS) ] = 0,
1468 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1469 },
1470 [ C(OP_WRITE) ] = {
1471 [ C(RESULT_ACCESS) ] = 0,
1472 [ C(RESULT_MISS) ] = 0,
1473 },
1474 [ C(OP_PREFETCH) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1477 },
1478 },
1479 [ C(L1I ) ] = {
1480 [ C(OP_READ) ] = {
1481 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1482 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1483 },
1484 [ C(OP_WRITE) ] = {
1485 [ C(RESULT_ACCESS) ] = -1,
1486 [ C(RESULT_MISS) ] = -1,
1487 },
1488 [ C(OP_PREFETCH) ] = {
1489 [ C(RESULT_ACCESS) ] = 0,
1490 [ C(RESULT_MISS) ] = 0,
1491 },
1492 },
1493 [ C(LL ) ] = {
1494 [ C(OP_READ) ] = {
1495 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1496 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1497 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1498 },
1499 [ C(OP_WRITE) ] = {
1500 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1501 [ C(RESULT_ACCESS) ] = 0x01b7,
1502 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1503 [ C(RESULT_MISS) ] = 0x01b7,
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1507 [ C(RESULT_ACCESS) ] = 0x01b7,
1508 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1509 [ C(RESULT_MISS) ] = 0x01b7,
1510 },
1511 },
1512 [ C(DTLB) ] = {
1513 [ C(OP_READ) ] = {
1514 [ C(RESULT_ACCESS) ] = 0,
1515 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1516 },
1517 [ C(OP_WRITE) ] = {
1518 [ C(RESULT_ACCESS) ] = 0,
1519 [ C(RESULT_MISS) ] = 0,
1520 },
1521 [ C(OP_PREFETCH) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 },
1526 [ C(ITLB) ] = {
1527 [ C(OP_READ) ] = {
1528 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1529 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1530 },
1531 [ C(OP_WRITE) ] = {
1532 [ C(RESULT_ACCESS) ] = -1,
1533 [ C(RESULT_MISS) ] = -1,
1534 },
1535 [ C(OP_PREFETCH) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 },
1540 [ C(BPU ) ] = {
1541 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1543 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1544 },
1545 [ C(OP_WRITE) ] = {
1546 [ C(RESULT_ACCESS) ] = -1,
1547 [ C(RESULT_MISS) ] = -1,
1548 },
1549 [ C(OP_PREFETCH) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 },
1554};
1555
ed827adb
KL		 1556EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1557EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1558/* UOPS_NOT_DELIVERED.ANY */
1559EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1560/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1561EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1562/* UOPS_RETIRED.ANY */
1563EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1564/* UOPS_ISSUED.ANY */
1565EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1566
1567static struct attribute *glm_events_attrs[] = {
1568 EVENT_PTR(td_total_slots_glm),
1569 EVENT_PTR(td_total_slots_scale_glm),
1570 EVENT_PTR(td_fetch_bubbles_glm),
1571 EVENT_PTR(td_recovery_bubbles_glm),
1572 EVENT_PTR(td_slots_issued_glm),
1573 EVENT_PTR(td_slots_retired_glm),
1574 NULL
1575};
1576
8b92c3a7
KL		 1577static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1578 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1579 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1580 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1581 EVENT_EXTRA_END
1582};
1583
1584#define GLM_DEMAND_DATA_RD BIT_ULL(0)
1585#define GLM_DEMAND_RFO BIT_ULL(1)
1586#define GLM_ANY_RESPONSE BIT_ULL(16)
1587#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1588#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1589#define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1590#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1591#define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1592#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1593#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1594
1595static __initconst const u64 glm_hw_cache_event_ids
1596 [PERF_COUNT_HW_CACHE_MAX]
1597 [PERF_COUNT_HW_CACHE_OP_MAX]
1598 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1599 [C(L1D)] = {
1600 [C(OP_READ)] = {
1601 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1602 [C(RESULT_MISS)] = 0x0,
1603 },
1604 [C(OP_WRITE)] = {
1605 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1606 [C(RESULT_MISS)] = 0x0,
1607 },
1608 [C(OP_PREFETCH)] = {
1609 [C(RESULT_ACCESS)] = 0x0,
1610 [C(RESULT_MISS)] = 0x0,
1611 },
1612 },
1613 [C(L1I)] = {
1614 [C(OP_READ)] = {
1615 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1616 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1617 },
1618 [C(OP_WRITE)] = {
1619 [C(RESULT_ACCESS)] = -1,
1620 [C(RESULT_MISS)] = -1,
1621 },
1622 [C(OP_PREFETCH)] = {
1623 [C(RESULT_ACCESS)] = 0x0,
1624 [C(RESULT_MISS)] = 0x0,
1625 },
1626 },
1627 [C(LL)] = {
1628 [C(OP_READ)] = {
1629 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1630 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1631 },
1632 [C(OP_WRITE)] = {
1633 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1634 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1635 },
1636 [C(OP_PREFETCH)] = {
1637 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1638 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1639 },
1640 },
1641 [C(DTLB)] = {
1642 [C(OP_READ)] = {
1643 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1644 [C(RESULT_MISS)] = 0x0,
1645 },
1646 [C(OP_WRITE)] = {
1647 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1648 [C(RESULT_MISS)] = 0x0,
1649 },
1650 [C(OP_PREFETCH)] = {
1651 [C(RESULT_ACCESS)] = 0x0,
1652 [C(RESULT_MISS)] = 0x0,
1653 },
1654 },
1655 [C(ITLB)] = {
1656 [C(OP_READ)] = {
1657 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1658 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1659 },
1660 [C(OP_WRITE)] = {
1661 [C(RESULT_ACCESS)] = -1,
1662 [C(RESULT_MISS)] = -1,
1663 },
1664 [C(OP_PREFETCH)] = {
1665 [C(RESULT_ACCESS)] = -1,
1666 [C(RESULT_MISS)] = -1,
1667 },
1668 },
1669 [C(BPU)] = {
1670 [C(OP_READ)] = {
1671 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1672 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1673 },
1674 [C(OP_WRITE)] = {
1675 [C(RESULT_ACCESS)] = -1,
1676 [C(RESULT_MISS)] = -1,
1677 },
1678 [C(OP_PREFETCH)] = {
1679 [C(RESULT_ACCESS)] = -1,
1680 [C(RESULT_MISS)] = -1,
1681 },
1682 },
1683};
1684
1685static __initconst const u64 glm_hw_cache_extra_regs
1686 [PERF_COUNT_HW_CACHE_MAX]
1687 [PERF_COUNT_HW_CACHE_OP_MAX]
1688 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1689 [C(LL)] = {
1690 [C(OP_READ)] = {
1691 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1692 GLM_LLC_ACCESS,
1693 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1694 GLM_LLC_MISS,
1695 },
1696 [C(OP_WRITE)] = {
1697 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1698 GLM_LLC_ACCESS,
1699 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1700 GLM_LLC_MISS,
1701 },
1702 [C(OP_PREFETCH)] = {
1703 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1704 GLM_LLC_ACCESS,
1705 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1706 GLM_LLC_MISS,
1707 },
1708 },
1709};
1710
dd0b06b5
KL		 1711static __initconst const u64 glp_hw_cache_event_ids
1712 [PERF_COUNT_HW_CACHE_MAX]
1713 [PERF_COUNT_HW_CACHE_OP_MAX]
1714 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1715 [C(L1D)] = {
1716 [C(OP_READ)] = {
1717 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1718 [C(RESULT_MISS)] = 0x0,
1719 },
1720 [C(OP_WRITE)] = {
1721 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1722 [C(RESULT_MISS)] = 0x0,
1723 },
1724 [C(OP_PREFETCH)] = {
1725 [C(RESULT_ACCESS)] = 0x0,
1726 [C(RESULT_MISS)] = 0x0,
1727 },
1728 },
1729 [C(L1I)] = {
1730 [C(OP_READ)] = {
1731 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1732 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1733 },
1734 [C(OP_WRITE)] = {
1735 [C(RESULT_ACCESS)] = -1,
1736 [C(RESULT_MISS)] = -1,
1737 },
1738 [C(OP_PREFETCH)] = {
1739 [C(RESULT_ACCESS)] = 0x0,
1740 [C(RESULT_MISS)] = 0x0,
1741 },
1742 },
1743 [C(LL)] = {
1744 [C(OP_READ)] = {
1745 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1746 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1747 },
1748 [C(OP_WRITE)] = {
1749 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1750 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1751 },
1752 [C(OP_PREFETCH)] = {
1753 [C(RESULT_ACCESS)] = 0x0,
1754 [C(RESULT_MISS)] = 0x0,
1755 },
1756 },
1757 [C(DTLB)] = {
1758 [C(OP_READ)] = {
1759 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1760 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1761 },
1762 [C(OP_WRITE)] = {
1763 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1764 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1765 },
1766 [C(OP_PREFETCH)] = {
1767 [C(RESULT_ACCESS)] = 0x0,
1768 [C(RESULT_MISS)] = 0x0,
1769 },
1770 },
1771 [C(ITLB)] = {
1772 [C(OP_READ)] = {
1773 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1774 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1775 },
1776 [C(OP_WRITE)] = {
1777 [C(RESULT_ACCESS)] = -1,
1778 [C(RESULT_MISS)] = -1,
1779 },
1780 [C(OP_PREFETCH)] = {
1781 [C(RESULT_ACCESS)] = -1,
1782 [C(RESULT_MISS)] = -1,
1783 },
1784 },
1785 [C(BPU)] = {
1786 [C(OP_READ)] = {
1787 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1788 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1789 },
1790 [C(OP_WRITE)] = {
1791 [C(RESULT_ACCESS)] = -1,
1792 [C(RESULT_MISS)] = -1,
1793 },
1794 [C(OP_PREFETCH)] = {
1795 [C(RESULT_ACCESS)] = -1,
1796 [C(RESULT_MISS)] = -1,
1797 },
1798 },
1799};
1800
1801static __initconst const u64 glp_hw_cache_extra_regs
1802 [PERF_COUNT_HW_CACHE_MAX]
1803 [PERF_COUNT_HW_CACHE_OP_MAX]
1804 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1805 [C(LL)] = {
1806 [C(OP_READ)] = {
1807 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1808 GLM_LLC_ACCESS,
1809 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1810 GLM_LLC_MISS,
1811 },
1812 [C(OP_WRITE)] = {
1813 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1814 GLM_LLC_ACCESS,
1815 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1816 GLM_LLC_MISS,
1817 },
1818 [C(OP_PREFETCH)] = {
1819 [C(RESULT_ACCESS)] = 0x0,
1820 [C(RESULT_MISS)] = 0x0,
1821 },
1822 },
1823};
1824
1e7b9390
HC		 1825#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1826#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1827#define KNL_MCDRAM_LOCAL BIT_ULL(21)
1828#define KNL_MCDRAM_FAR BIT_ULL(22)
1829#define KNL_DDR_LOCAL BIT_ULL(23)
1830#define KNL_DDR_FAR BIT_ULL(24)
1831#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1832 KNL_DDR_LOCAL | KNL_DDR_FAR)
1833#define KNL_L2_READ SLM_DMND_READ
1834#define KNL_L2_WRITE SLM_DMND_WRITE
1835#define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1836#define KNL_L2_ACCESS SLM_LLC_ACCESS
1837#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1838 KNL_DRAM_ANY | SNB_SNP_ANY | \
1839 SNB_NON_DRAM)
1840
1841static __initconst const u64 knl_hw_cache_extra_regs
1842 [PERF_COUNT_HW_CACHE_MAX]
1843 [PERF_COUNT_HW_CACHE_OP_MAX]
1844 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1845 [C(LL)] = {
1846 [C(OP_READ)] = {
1847 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1848 [C(RESULT_MISS)] = 0,
1849 },
1850 [C(OP_WRITE)] = {
1851 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1852 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1853 },
1854 [C(OP_PREFETCH)] = {
1855 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1856 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1857 },
1858 },
1859};
1860
1a78d937 1861/*
c3d266c8
KL		 1862 * Used from PMIs where the LBRs are already disabled.
1863 *
1864 * This function could be called consecutively. It is required to remain in
1865 * disabled state if called consecutively.
1866 *
1867 * During consecutive calls, the same disable value will be written to related
cecf6235
AS		 1868 * registers, so the PMU state remains unchanged.
1869 *
1870 * intel_bts events don't coexist with intel PMU's BTS events because of
1871 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1872 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1a78d937
AK		 1873 */
1874static void __intel_pmu_disable_all(void)
f22f54f4 1875{
89cbc767 1876 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1877
1878 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1879
15c7ad51 1880 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1881 intel_pmu_disable_bts();
ca037701
PZ		 1882
1883 intel_pmu_pebs_disable_all();
1a78d937
AK		 1884}
1885
1886static void intel_pmu_disable_all(void)
1887{
1888 __intel_pmu_disable_all();
caff2bef 1889 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1890}
1891
1a78d937 1892static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1893{
89cbc767 1894 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1895
d329527e 1896 intel_pmu_pebs_enable_all();
1a78d937 1897 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1898 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1899 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1900
15c7ad51 1901 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1902 struct perf_event *event =
15c7ad51 1903 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1904
1905 if (WARN_ON_ONCE(!event))
1906 return;
1907
1908 intel_pmu_enable_bts(event->hw.config);
cecf6235 1909 }
f22f54f4
PZ		 1910}
1911
1a78d937
AK		 1912static void intel_pmu_enable_all(int added)
1913{
1914 __intel_pmu_enable_all(added, false);
1915}
1916
11164cd4
PZ		 1917/*
1918 * Workaround for:
1919 * Intel Errata AAK100 (model 26)
1920 * Intel Errata AAP53 (model 30)
40b91cd1 1921 * Intel Errata BD53 (model 44)
11164cd4 1922 *
351af072
ZY		 1923 * The official story:
1924 * These chips need to be 'reset' when adding counters by programming the
1925 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1926 * in sequence on the same PMC or on different PMCs.
1927 *
1928 * In practise it appears some of these events do in fact count, and
1929 * we need to programm all 4 events.
11164cd4 1930 */
351af072 1931static void intel_pmu_nhm_workaround(void)
11164cd4 1932{
89cbc767 1933 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1934 static const unsigned long nhm_magic[4] = {
1935 0x4300B5,
1936 0x4300D2,
1937 0x4300B1,
1938 0x4300B1
1939 };
1940 struct perf_event *event;
1941 int i;
11164cd4 1942
351af072
ZY		 1943 /*
1944 * The Errata requires below steps:
1945 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1946 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1947 * the corresponding PMCx;
1948 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1949 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1950 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1951 */
11164cd4 1952
351af072
ZY		 1953 /*
1954 * The real steps we choose are a little different from above.
1955 * A) To reduce MSR operations, we don't run step 1) as they
1956 * are already cleared before this function is called;
1957 * B) Call x86_perf_event_update to save PMCx before configuring
1958 * PERFEVTSELx with magic number;
1959 * C) With step 5), we do clear only when the PERFEVTSELx is
1960 * not used currently.
1961 * D) Call x86_perf_event_set_period to restore PMCx;
1962 */
11164cd4 1963
351af072
ZY		 1964 /* We always operate 4 pairs of PERF Counters */
1965 for (i = 0; i < 4; i++) {
1966 event = cpuc->events[i];
1967 if (event)
1968 x86_perf_event_update(event);
1969 }
11164cd4 1970
351af072
ZY		 1971 for (i = 0; i < 4; i++) {
1972 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1973 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1974 }
1975
1976 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1977 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1978
351af072
ZY		 1979 for (i = 0; i < 4; i++) {
1980 event = cpuc->events[i];
1981
1982 if (event) {
1983 x86_perf_event_set_period(event);
31fa58af 1984 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1985 ARCH_PERFMON_EVENTSEL_ENABLE);
1986 } else
1987 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1988 }
351af072
ZY		 1989}
1990
1991static void intel_pmu_nhm_enable_all(int added)
1992{
1993 if (added)
1994 intel_pmu_nhm_workaround();
11164cd4
PZ		 1995 intel_pmu_enable_all(added);
1996}
1997
af3bdb99
AK		 1998static void enable_counter_freeze(void)
1999{
2000 update_debugctlmsr(get_debugctlmsr() |
2001 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2002}
2003
2004static void disable_counter_freeze(void)
2005{
2006 update_debugctlmsr(get_debugctlmsr() &
2007 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2008}
2009
f22f54f4
PZ		 2010static inline u64 intel_pmu_get_status(void)
2011{
2012 u64 status;
2013
2014 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2015
2016 return status;
2017}
2018
2019static inline void intel_pmu_ack_status(u64 ack)
2020{
2021 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2022}
2023
ca037701 2024static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 2025{
15c7ad51 2026 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 2027 u64 ctrl_val, mask;
2028
2029 mask = 0xfULL << (idx * 4);
2030
2031 rdmsrl(hwc->config_base, ctrl_val);
2032 ctrl_val &= ~mask;
7645a24c 2033 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 2034}
2035
2b9e344d
PZ		 2036static inline bool event_is_checkpointed(struct perf_event *event)
2037{
2038 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2039}
2040
ca037701 2041static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 2042{
aff3d91a 2043 struct hw_perf_event *hwc = &event->hw;
89cbc767 2044 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 2045
15c7ad51 2046 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 2047 intel_pmu_disable_bts();
2048 intel_pmu_drain_bts_buffer();
2049 return;
2050 }
2051
144d31e6
GN		 2052 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
2053 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 2054 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 2055
4f08b625
KL		 2056 if (unlikely(event->attr.precise_ip))
2057 intel_pmu_pebs_disable(event);
2058
f22f54f4 2059 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 2060 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 2061 return;
2062 }
2063
aff3d91a 2064 x86_pmu_disable_event(event);
f22f54f4
PZ		 2065}
2066
68f7082f
PZ		 2067static void intel_pmu_del_event(struct perf_event *event)
2068{
2069 if (needs_branch_stack(event))
2070 intel_pmu_lbr_del(event);
2071 if (event->attr.precise_ip)
2072 intel_pmu_pebs_del(event);
2073}
2074
ceb90d9e
KL		 2075static void intel_pmu_read_event(struct perf_event *event)
2076{
2077 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2078 intel_pmu_auto_reload_read(event);
2079 else
2080 x86_perf_event_update(event);
2081}
2082
4f08b625 2083static void intel_pmu_enable_fixed(struct perf_event *event)
f22f54f4 2084{
4f08b625 2085 struct hw_perf_event *hwc = &event->hw;
15c7ad51 2086 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
4f08b625 2087 u64 ctrl_val, mask, bits = 0;
f22f54f4
PZ		 2088
2089 /*
4f08b625 2090 * Enable IRQ generation (0x8), if not PEBS,
f22f54f4
PZ		 2091 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2092 * if requested:
2093 */
4f08b625
KL		 2094 if (!event->attr.precise_ip)
2095 bits |= 0x8;
f22f54f4
PZ		 2096 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2097 bits |= 0x2;
2098 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2099 bits |= 0x1;
2100
2101 /*
2102 * ANY bit is supported in v3 and up
2103 */
2104 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2105 bits |= 0x4;
2106
2107 bits <<= (idx * 4);
2108 mask = 0xfULL << (idx * 4);
2109
2110 rdmsrl(hwc->config_base, ctrl_val);
2111 ctrl_val &= ~mask;
2112 ctrl_val |= bits;
7645a24c 2113 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 2114}
2115
aff3d91a 2116static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 2117{
aff3d91a 2118 struct hw_perf_event *hwc = &event->hw;
89cbc767 2119 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 2120
15c7ad51 2121 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 2122 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 2123 return;
2124
2125 intel_pmu_enable_bts(hwc->config);
2126 return;
2127 }
2128
144d31e6
GN		 2129 if (event->attr.exclude_host)
2130 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
2131 if (event->attr.exclude_guest)
2132 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
2133
2b9e344d
PZ		 2134 if (unlikely(event_is_checkpointed(event)))
2135 cpuc->intel_cp_status |= (1ull << hwc->idx);
2136
4f08b625
KL		 2137 if (unlikely(event->attr.precise_ip))
2138 intel_pmu_pebs_enable(event);
2139
f22f54f4 2140 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
4f08b625 2141 intel_pmu_enable_fixed(event);
f22f54f4
PZ		 2142 return;
2143 }
2144
31fa58af 2145 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 2146}
2147
68f7082f
PZ		 2148static void intel_pmu_add_event(struct perf_event *event)
2149{
2150 if (event->attr.precise_ip)
2151 intel_pmu_pebs_add(event);
2152 if (needs_branch_stack(event))
2153 intel_pmu_lbr_add(event);
2154}
2155
f22f54f4
PZ		 2156/*
2157 * Save and restart an expired event. Called by NMI contexts,
2158 * so it has to be careful about preempting normal event ops:
2159 */
de0428a7 2160int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 2161{
cc2ad4ba 2162 x86_perf_event_update(event);
2dbf0116
AK		 2163 /*
2164 * For a checkpointed counter always reset back to 0. This
2165 * avoids a situation where the counter overflows, aborts the
2166 * transaction and is then set back to shortly before the
2167 * overflow, and overflows and aborts again.
2168 */
2169 if (unlikely(event_is_checkpointed(event))) {
2170 /* No race with NMIs because the counter should not be armed */
2171 wrmsrl(event->hw.event_base, 0);
2172 local64_set(&event->hw.prev_count, 0);
2173 }
cc2ad4ba 2174 return x86_perf_event_set_period(event);
f22f54f4
PZ		 2175}
2176
2177static void intel_pmu_reset(void)
2178{
0a3aee0d 2179 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 2180 unsigned long flags;
2181 int idx;
2182
948b1bb8 2183 if (!x86_pmu.num_counters)
f22f54f4
PZ		 2184 return;
2185
2186 local_irq_save(flags);
2187
c767a54b 2188 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 2189
948b1bb8 2190 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 2191 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2192 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 2193 }
948b1bb8 2194 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 2195 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 2196
f22f54f4
PZ		 2197 if (ds)
2198 ds->bts_index = ds->bts_buffer_base;
2199
8882edf7
AK		 2200 /* Ack all overflows and disable fixed counters */
2201 if (x86_pmu.version >= 2) {
2202 intel_pmu_ack_status(intel_pmu_get_status());
2203 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2204 }
2205
2206 /* Reset LBRs and LBR freezing */
2207 if (x86_pmu.lbr_nr) {
2208 update_debugctlmsr(get_debugctlmsr() &
2209 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2210 }
2211
f22f54f4
PZ		 2212 local_irq_restore(flags);
2213}
2214
ba12d20e 2215static int handle_pmi_common(struct pt_regs *regs, u64 status)
f22f54f4
PZ		 2216{
2217 struct perf_sample_data data;
ba12d20e
KL		 2218 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2219 int bit;
2220 int handled = 0;
f22f54f4
PZ		 2221
2222 inc_irq_stat(apic_perf_irqs);
ca037701 2223
b292d7a1 2224 /*
d8020bee
AK		 2225 * Ignore a range of extra bits in status that do not indicate
2226 * overflow by themselves.
b292d7a1 2227 */
d8020bee
AK		 2228 status &= ~(GLOBAL_STATUS_COND_CHG |
2229 GLOBAL_STATUS_ASIF |
2230 GLOBAL_STATUS_LBRS_FROZEN);
2231 if (!status)
ba12d20e 2232 return 0;
daa864b8
SE		 2233 /*
2234 * In case multiple PEBS events are sampled at the same time,
2235 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2236 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2237 * having their bits set in the status register. This is a sign
2238 * that there was at least one PEBS record pending at the time
2239 * of the PMU interrupt. PEBS counters must only be processed
2240 * via the drain_pebs() calls and not via the regular sample
2241 * processing loop coming after that the function, otherwise
2242 * phony regular samples may be generated in the sampling buffer
2243 * not marked with the EXACT tag. Another possibility is to have
2244 * one PEBS event and at least one non-PEBS event whic hoverflows
2245 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2246 * not be set, yet the overflow status bit for the PEBS counter will
2247 * be on Skylake.
2248 *
2249 * To avoid this problem, we systematically ignore the PEBS-enabled
2250 * counters from the GLOBAL_STATUS mask and we always process PEBS
2251 * events via drain_pebs().
2252 */
ec71a398
KL		 2253 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2254 status &= ~cpuc->pebs_enabled;
2255 else
2256 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
b292d7a1 2257
ca037701
PZ		 2258 /*
2259 * PEBS overflow sets bit 62 in the global status register
2260 */
de725dec
PZ		 2261 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2262 handled++;
ca037701 2263 x86_pmu.drain_pebs(regs);
8077eca0 2264 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
de725dec 2265 }
ca037701 2266
52ca9ced
AS		 2267 /*
2268 * Intel PT
2269 */
2270 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2271 handled++;
2272 intel_pt_interrupt();
2273 }
2274
2dbf0116 2275 /*
2b9e344d
PZ		 2276 * Checkpointed counters can lead to 'spurious' PMIs because the
2277 * rollback caused by the PMI will have cleared the overflow status
2278 * bit. Therefore always force probe these counters.
2dbf0116 2279 */
2b9e344d 2280 status |= cpuc->intel_cp_status;
2dbf0116 2281
984b3f57 2282 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 2283 struct perf_event *event = cpuc->events[bit];
2284
de725dec
PZ		 2285 handled++;
2286
f22f54f4
PZ		 2287 if (!test_bit(bit, cpuc->active_mask))
2288 continue;
2289
2290 if (!intel_pmu_save_and_restart(event))
2291 continue;
2292
fd0d000b 2293 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 2294
60ce0fbd
SE		 2295 if (has_branch_stack(event))
2296 data.br_stack = &cpuc->lbr_stack;
2297
a8b0ca17 2298 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 2299 x86_pmu_stop(event, 0);
f22f54f4
PZ		 2300 }
2301
ba12d20e
KL		 2302 return handled;
2303}
2304
af3bdb99
AK		 2305static bool disable_counter_freezing;
2306static int __init intel_perf_counter_freezing_setup(char *s)
2307{
2308 disable_counter_freezing = true;
2309 pr_info("Intel PMU Counter freezing feature disabled\n");
2310 return 1;
2311}
2312__setup("disable_counter_freezing", intel_perf_counter_freezing_setup);
2313
2314/*
2315 * Simplified handler for Arch Perfmon v4:
2316 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2317 * This is done automatically on PMU ack.
2318 * - Ack the PMU only after the APIC.
2319 */
2320
2321static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2322{
2323 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2324 int handled = 0;
2325 bool bts = false;
2326 u64 status;
2327 int pmu_enabled = cpuc->enabled;
2328 int loops = 0;
2329
2330 /* PMU has been disabled because of counter freezing */
2331 cpuc->enabled = 0;
2332 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2333 bts = true;
2334 intel_bts_disable_local();
2335 handled = intel_pmu_drain_bts_buffer();
2336 handled += intel_bts_interrupt();
2337 }
2338 status = intel_pmu_get_status();
2339 if (!status)
2340 goto done;
2341again:
2342 intel_pmu_lbr_read();
2343 if (++loops > 100) {
2344 static bool warned;
2345
2346 if (!warned) {
2347 WARN(1, "perfevents: irq loop stuck!\n");
2348 perf_event_print_debug();
2349 warned = true;
2350 }
2351 intel_pmu_reset();
2352 goto done;
2353 }
2354
2355
2356 handled += handle_pmi_common(regs, status);
2357done:
2358 /* Ack the PMI in the APIC */
2359 apic_write(APIC_LVTPC, APIC_DM_NMI);
2360
2361 /*
2362 * The counters start counting immediately while ack the status.
2363 * Make it as close as possible to IRET. This avoids bogus
2364 * freezing on Skylake CPUs.
2365 */
2366 if (status) {
2367 intel_pmu_ack_status(status);
2368 } else {
2369 /*
2370 * CPU may issues two PMIs very close to each other.
2371 * When the PMI handler services the first one, the
2372 * GLOBAL_STATUS is already updated to reflect both.
2373 * When it IRETs, the second PMI is immediately
2374 * handled and it sees clear status. At the meantime,
2375 * there may be a third PMI, because the freezing bit
2376 * isn't set since the ack in first PMI handlers.
2377 * Double check if there is more work to be done.
2378 */
2379 status = intel_pmu_get_status();
2380 if (status)
2381 goto again;
2382 }
2383
2384 if (bts)
2385 intel_bts_enable_local();
2386 cpuc->enabled = pmu_enabled;
2387 return handled;
2388}
2389
ba12d20e
KL		 2390/*
2391 * This handler is triggered by the local APIC, so the APIC IRQ handling
2392 * rules apply:
2393 */
2394static int intel_pmu_handle_irq(struct pt_regs *regs)
2395{
2396 struct cpu_hw_events *cpuc;
2397 int loops;
2398 u64 status;
2399 int handled;
2400 int pmu_enabled;
2401
2402 cpuc = this_cpu_ptr(&cpu_hw_events);
2403
2404 /*
2405 * Save the PMU state.
2406 * It needs to be restored when leaving the handler.
2407 */
2408 pmu_enabled = cpuc->enabled;
2409 /*
2410 * No known reason to not always do late ACK,
2411 * but just in case do it opt-in.
2412 */
2413 if (!x86_pmu.late_ack)
2414 apic_write(APIC_LVTPC, APIC_DM_NMI);
2415 intel_bts_disable_local();
2416 cpuc->enabled = 0;
2417 __intel_pmu_disable_all();
2418 handled = intel_pmu_drain_bts_buffer();
2419 handled += intel_bts_interrupt();
2420 status = intel_pmu_get_status();
2421 if (!status)
2422 goto done;
2423
2424 loops = 0;
2425again:
2426 intel_pmu_lbr_read();
2427 intel_pmu_ack_status(status);
2428 if (++loops > 100) {
2429 static bool warned;
2430
2431 if (!warned) {
2432 WARN(1, "perfevents: irq loop stuck!\n");
2433 perf_event_print_debug();
2434 warned = true;
2435 }
2436 intel_pmu_reset();
2437 goto done;
2438 }
2439
2440 handled += handle_pmi_common(regs, status);
2441
f22f54f4
PZ		 2442 /*
2443 * Repeat if there is more work to be done:
2444 */
2445 status = intel_pmu_get_status();
2446 if (status)
2447 goto again;
2448
3fb2b8dd 2449done:
c3d266c8 2450 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
82d71ed0
KL		 2451 cpuc->enabled = pmu_enabled;
2452 if (pmu_enabled)
c3d266c8 2453 __intel_pmu_enable_all(0, true);
cecf6235 2454 intel_bts_enable_local();
c3d266c8 2455
72db5596
AK		 2456 /*
2457 * Only unmask the NMI after the overflow counters
2458 * have been reset. This avoids spurious NMIs on
2459 * Haswell CPUs.
2460 */
2461 if (x86_pmu.late_ack)
2462 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 2463 return handled;
f22f54f4
PZ		 2464}
2465
f22f54f4 2466static struct event_constraint *
ca037701 2467intel_bts_constraints(struct perf_event *event)
f22f54f4 2468{
ca037701
PZ		 2469 struct hw_perf_event *hwc = &event->hw;
2470 unsigned int hw_event, bts_event;
f22f54f4 2471
18a073a3
PZ		 2472 if (event->attr.freq)
2473 return NULL;
2474
ca037701
PZ		 2475 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2476 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 2477
ca037701 2478 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 2479 return &bts_constraint;
ca037701 2480
f22f54f4
PZ		 2481 return NULL;
2482}
2483
ae3f011f 2484static int intel_alt_er(int idx, u64 config)
b79e8941 2485{
e01d8718
PZ		 2486 int alt_idx = idx;
2487
9a5e3fb5 2488 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 2489 return idx;
b79e8941 2490
5a425294 2491 if (idx == EXTRA_REG_RSP_0)
ae3f011f 2492 alt_idx = EXTRA_REG_RSP_1;
5a425294
PZ		 2493
2494 if (idx == EXTRA_REG_RSP_1)
ae3f011f 2495 alt_idx = EXTRA_REG_RSP_0;
5a425294 2496
ae3f011f
KL		 2497 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2498 return idx;
2499
2500 return alt_idx;
5a425294
PZ		 2501}
2502
2503static void intel_fixup_er(struct perf_event *event, int idx)
2504{
2505 event->hw.extra_reg.idx = idx;
2506
2507 if (idx == EXTRA_REG_RSP_0) {
b79e8941 2508 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2509 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 2510 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 2511 } else if (idx == EXTRA_REG_RSP_1) {
2512 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2513 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 2514 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 2515 }
b79e8941
PZ		 2516}
2517
efc9f05d
SE		 2518/*
2519 * manage allocation of shared extra msr for certain events
2520 *
2521 * sharing can be:
2522 * per-cpu: to be shared between the various events on a single PMU
2523 * per-core: per-cpu + shared by HT threads
2524 */
a7e3ed1e 2525static struct event_constraint *
efc9f05d 2526__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 2527 struct perf_event *event,
2528 struct hw_perf_event_extra *reg)
a7e3ed1e 2529{
efc9f05d 2530 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 2531 struct er_account *era;
cd8a38d3 2532 unsigned long flags;
5a425294 2533 int idx = reg->idx;
a7e3ed1e 2534
5a425294
PZ		 2535 /*
2536 * reg->alloc can be set due to existing state, so for fake cpuc we
2537 * need to ignore this, otherwise we might fail to allocate proper fake
2538 * state for this extra reg constraint. Also see the comment below.
2539 */
2540 if (reg->alloc && !cpuc->is_fake)
b36817e8 2541 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 2542
b79e8941 2543again:
5a425294 2544 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 2545 /*
2546 * we use spin_lock_irqsave() to avoid lockdep issues when
2547 * passing a fake cpuc
2548 */
2549 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 2550
2551 if (!atomic_read(&era->ref) || era->config == reg->config) {
2552
5a425294
PZ		 2553 /*
2554 * If its a fake cpuc -- as per validate_{group,event}() we
2555 * shouldn't touch event state and we can avoid doing so
2556 * since both will only call get_event_constraints() once
2557 * on each event, this avoids the need for reg->alloc.
2558 *
2559 * Not doing the ER fixup will only result in era->reg being
2560 * wrong, but since we won't actually try and program hardware
2561 * this isn't a problem either.
2562 */
2563 if (!cpuc->is_fake) {
2564 if (idx != reg->idx)
2565 intel_fixup_er(event, idx);
2566
2567 /*
2568 * x86_schedule_events() can call get_event_constraints()
2569 * multiple times on events in the case of incremental
2570 * scheduling(). reg->alloc ensures we only do the ER
2571 * allocation once.
2572 */
2573 reg->alloc = 1;
2574 }
2575
efc9f05d
SE		 2576 /* lock in msr value */
2577 era->config = reg->config;
2578 era->reg = reg->reg;
2579
2580 /* one more user */
2581 atomic_inc(&era->ref);
2582
a7e3ed1e 2583 /*
b36817e8
SE		 2584 * need to call x86_get_event_constraint()
2585 * to check if associated event has constraints
a7e3ed1e 2586 */
b36817e8 2587 c = NULL;
5a425294 2588 } else {
ae3f011f 2589 idx = intel_alt_er(idx, reg->config);
5a425294
PZ		 2590 if (idx != reg->idx) {
2591 raw_spin_unlock_irqrestore(&era->lock, flags);
2592 goto again;
2593 }
a7e3ed1e 2594 }
cd8a38d3 2595 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 2596
efc9f05d
SE		 2597 return c;
2598}
2599
2600static void
2601__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2602 struct hw_perf_event_extra *reg)
2603{
2604 struct er_account *era;
2605
2606 /*
5a425294
PZ		 2607 * Only put constraint if extra reg was actually allocated. Also takes
2608 * care of event which do not use an extra shared reg.
2609 *
2610 * Also, if this is a fake cpuc we shouldn't touch any event state
2611 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2612 * either since it'll be thrown out.
efc9f05d 2613 */
5a425294 2614 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 2615 return;
2616
2617 era = &cpuc->shared_regs->regs[reg->idx];
2618
2619 /* one fewer user */
2620 atomic_dec(&era->ref);
2621
2622 /* allocate again next time */
2623 reg->alloc = 0;
2624}
2625
2626static struct event_constraint *
2627intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2628 struct perf_event *event)
2629{
b36817e8
SE		 2630 struct event_constraint *c = NULL, *d;
2631 struct hw_perf_event_extra *xreg, *breg;
2632
2633 xreg = &event->hw.extra_reg;
2634 if (xreg->idx != EXTRA_REG_NONE) {
2635 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2636 if (c == &emptyconstraint)
2637 return c;
2638 }
2639 breg = &event->hw.branch_reg;
2640 if (breg->idx != EXTRA_REG_NONE) {
2641 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2642 if (d == &emptyconstraint) {
2643 __intel_shared_reg_put_constraints(cpuc, xreg);
2644 c = d;
2645 }
2646 }
efc9f05d 2647 return c;
a7e3ed1e
AK		 2648}
2649
de0428a7 2650struct event_constraint *
79cba822
SE		 2651x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2652 struct perf_event *event)
de0428a7
KW		 2653{
2654 struct event_constraint *c;
2655
2656 if (x86_pmu.event_constraints) {
2657 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 2658 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 2659 event->hw.flags |= c->flags;
de0428a7 2660 return c;
9fac2cf3 2661 }
de0428a7
KW		 2662 }
2663 }
2664
2665 return &unconstrained;
2666}
2667
f22f54f4 2668static struct event_constraint *
e979121b 2669__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 2670 struct perf_event *event)
f22f54f4
PZ		 2671{
2672 struct event_constraint *c;
2673
ca037701
PZ		 2674 c = intel_bts_constraints(event);
2675 if (c)
2676 return c;
2677
687805e4 2678 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 2679 if (c)
2680 return c;
2681
687805e4 2682 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 2683 if (c)
2684 return c;
2685
79cba822 2686 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 2687}
2688
e979121b
MD		 2689static void
2690intel_start_scheduling(struct cpu_hw_events *cpuc)
2691{
2692 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2693 struct intel_excl_states *xl;
e979121b 2694 int tid = cpuc->excl_thread_id;
e979121b
MD		 2695
2696 /*
2697 * nothing needed if in group validation mode
2698 */
b37609c3 2699 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 2700 return;
b37609c3 2701
e979121b
MD		 2702 /*
2703 * no exclusion needed
2704 */
17186ccd 2705 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2706 return;
2707
e979121b
MD		 2708 xl = &excl_cntrs->states[tid];
2709
2710 xl->sched_started = true;
e979121b
MD		 2711 /*
2712 * lock shared state until we are done scheduling
2713 * in stop_event_scheduling()
2714 * makes scheduling appear as a transaction
2715 */
e979121b 2716 raw_spin_lock(&excl_cntrs->lock);
e979121b
MD		 2717}
2718
0c41e756
PZ		 2719static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2720{
2721 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2722 struct event_constraint *c = cpuc->event_constraint[idx];
2723 struct intel_excl_states *xl;
2724 int tid = cpuc->excl_thread_id;
2725
2726 if (cpuc->is_fake || !is_ht_workaround_enabled())
2727 return;
2728
2729 if (WARN_ON_ONCE(!excl_cntrs))
2730 return;
2731
2732 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2733 return;
2734
2735 xl = &excl_cntrs->states[tid];
2736
2737 lockdep_assert_held(&excl_cntrs->lock);
2738
1fe684e3 2739 if (c->flags & PERF_X86_EVENT_EXCL)
43ef205b 2740 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1fe684e3 2741 else
43ef205b 2742 xl->state[cntr] = INTEL_EXCL_SHARED;
0c41e756
PZ		 2743}
2744
e979121b
MD		 2745static void
2746intel_stop_scheduling(struct cpu_hw_events *cpuc)
2747{
2748 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2749 struct intel_excl_states *xl;
e979121b 2750 int tid = cpuc->excl_thread_id;
e979121b
MD		 2751
2752 /*
2753 * nothing needed if in group validation mode
2754 */
b37609c3 2755 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 2756 return;
2757 /*
2758 * no exclusion needed
2759 */
17186ccd 2760 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2761 return;
2762
e979121b
MD		 2763 xl = &excl_cntrs->states[tid];
2764
e979121b
MD		 2765 xl->sched_started = false;
2766 /*
2767 * release shared state lock (acquired in intel_start_scheduling())
2768 */
2769 raw_spin_unlock(&excl_cntrs->lock);
2770}
2771
2772static struct event_constraint *
2773intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2774 int idx, struct event_constraint *c)
2775{
e979121b 2776 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2777 struct intel_excl_states *xlo;
e979121b 2778 int tid = cpuc->excl_thread_id;
1c565833 2779 int is_excl, i;
e979121b
MD		 2780
2781 /*
2782 * validating a group does not require
2783 * enforcing cross-thread exclusion
2784 */
b37609c3
SE		 2785 if (cpuc->is_fake || !is_ht_workaround_enabled())
2786 return c;
2787
2788 /*
2789 * no exclusion needed
2790 */
17186ccd 2791 if (WARN_ON_ONCE(!excl_cntrs))
e979121b 2792 return c;
e979121b 2793
e979121b
MD		 2794 /*
2795 * because we modify the constraint, we need
2796 * to make a copy. Static constraints come
2797 * from static const tables.
2798 *
2799 * only needed when constraint has not yet
2800 * been cloned (marked dynamic)
2801 */
2802 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
aaf932e8 2803 struct event_constraint *cx;
e979121b 2804
e979121b
MD		 2805 /*
2806 * grab pre-allocated constraint entry
2807 */
2808 cx = &cpuc->constraint_list[idx];
2809
2810 /*
2811 * initialize dynamic constraint
2812 * with static constraint
2813 */
aaf932e8 2814 *cx = *c;
e979121b
MD		 2815
2816 /*
2817 * mark constraint as dynamic, so we
2818 * can free it later on
2819 */
2820 cx->flags |= PERF_X86_EVENT_DYNAMIC;
aaf932e8 2821 c = cx;
e979121b
MD		 2822 }
2823
2824 /*
2825 * From here on, the constraint is dynamic.
2826 * Either it was just allocated above, or it
2827 * was allocated during a earlier invocation
2828 * of this function
2829 */
2830
1c565833
PZ		 2831 /*
2832 * state of sibling HT
2833 */
2834 xlo = &excl_cntrs->states[tid ^ 1];
2835
2836 /*
2837 * event requires exclusive counter access
2838 * across HT threads
2839 */
2840 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2841 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2842 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2843 if (!cpuc->n_excl++)
2844 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2845 }
2846
e979121b
MD		 2847 /*
2848 * Modify static constraint with current dynamic
2849 * state of thread
2850 *
2851 * EXCLUSIVE: sibling counter measuring exclusive event
2852 * SHARED : sibling counter measuring non-exclusive event
2853 * UNUSED : sibling counter unused
2854 */
aaf932e8 2855 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
e979121b
MD		 2856 /*
2857 * exclusive event in sibling counter
2858 * our corresponding counter cannot be used
2859 * regardless of our event
2860 */
1c565833 2861 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
aaf932e8 2862 __clear_bit(i, c->idxmsk);
e979121b
MD		 2863 /*
2864 * if measuring an exclusive event, sibling
2865 * measuring non-exclusive, then counter cannot
2866 * be used
2867 */
1c565833 2868 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
aaf932e8 2869 __clear_bit(i, c->idxmsk);
e979121b
MD		 2870 }
2871
2872 /*
2873 * recompute actual bit weight for scheduling algorithm
2874 */
aaf932e8 2875 c->weight = hweight64(c->idxmsk64);
e979121b
MD		 2876
2877 /*
2878 * if we return an empty mask, then switch
2879 * back to static empty constraint to avoid
2880 * the cost of freeing later on
2881 */
aaf932e8
PZ		 2882 if (c->weight == 0)
2883 c = &emptyconstraint;
e979121b 2884
aaf932e8 2885 return c;
e979121b
MD		 2886}
2887
2888static struct event_constraint *
2889intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2890 struct perf_event *event)
2891{
ebfb4988 2892 struct event_constraint *c1 = NULL;
a90738c2 2893 struct event_constraint *c2;
e979121b 2894
ebfb4988
PZ		 2895 if (idx >= 0) /* fake does < 0 */
2896 c1 = cpuc->event_constraint[idx];
2897
e979121b
MD		 2898 /*
2899 * first time only
2900 * - static constraint: no change across incremental scheduling calls
2901 * - dynamic constraint: handled by intel_get_excl_constraints()
2902 */
a90738c2
SE		 2903 c2 = __intel_get_event_constraints(cpuc, idx, event);
2904 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2905 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2906 c1->weight = c2->weight;
2907 c2 = c1;
2908 }
e979121b
MD		 2909
2910 if (cpuc->excl_cntrs)
a90738c2 2911 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2912
a90738c2 2913 return c2;
e979121b
MD		 2914}
2915
2916static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2917 struct perf_event *event)
2918{
2919 struct hw_perf_event *hwc = &event->hw;
2920 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
e979121b 2921 int tid = cpuc->excl_thread_id;
1c565833 2922 struct intel_excl_states *xl;
e979121b
MD		 2923
2924 /*
2925 * nothing needed if in group validation mode
2926 */
2927 if (cpuc->is_fake)
2928 return;
2929
17186ccd 2930 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2931 return;
2932
cc1790cf
PZ		 2933 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2934 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2935 if (!--cpuc->n_excl)
2936 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2937 }
e979121b
MD		 2938
2939 /*
ba040653
PZ		 2940 * If event was actually assigned, then mark the counter state as
2941 * unused now.
e979121b 2942 */
ba040653
PZ		 2943 if (hwc->idx >= 0) {
2944 xl = &excl_cntrs->states[tid];
2945
2946 /*
2947 * put_constraint may be called from x86_schedule_events()
2948 * which already has the lock held so here make locking
2949 * conditional.
2950 */
2951 if (!xl->sched_started)
2952 raw_spin_lock(&excl_cntrs->lock);
e979121b 2953
1c565833 2954 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
e979121b 2955
ba040653
PZ		 2956 if (!xl->sched_started)
2957 raw_spin_unlock(&excl_cntrs->lock);
2958 }
e979121b
MD		 2959}
2960
efc9f05d
SE		 2961static void
2962intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2963 struct perf_event *event)
2964{
efc9f05d 2965 struct hw_perf_event_extra *reg;
a7e3ed1e 2966
efc9f05d
SE		 2967 reg = &event->hw.extra_reg;
2968 if (reg->idx != EXTRA_REG_NONE)
2969 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2970
2971 reg = &event->hw.branch_reg;
2972 if (reg->idx != EXTRA_REG_NONE)
2973 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2974}
a7e3ed1e 2975
efc9f05d
SE		 2976static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2977 struct perf_event *event)
2978{
2979 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2980
2981 /*
2982 * is PMU has exclusive counter restrictions, then
2983 * all events are subject to and must call the
2984 * put_excl_constraints() routine
2985 */
b371b594 2986 if (cpuc->excl_cntrs)
e979121b 2987 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2988}
2989
0780c927 2990static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2991{
0780c927 2992 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2993 /*
2994 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2995 * (0x003c) so that we can use it with PEBS.
2996 *
2997 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2998 * PEBS capable. However we can use INST_RETIRED.ANY_P
2999 * (0x00c0), which is a PEBS capable event, to get the same
3000 * count.
3001 *
3002 * INST_RETIRED.ANY_P counts the number of cycles that retires
3003 * CNTMASK instructions. By setting CNTMASK to a value (16)
3004 * larger than the maximum number of instructions that can be
3005 * retired per cycle (4) and then inverting the condition, we
3006 * count all cycles that retire 16 or less instructions, which
3007 * is every cycle.
3008 *
3009 * Thereby we gain a PEBS capable cycle counter.
3010 */
f9b4eeb8
PZ		 3011 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3012
0780c927
PZ		 3013 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3014 event->hw.config = alt_config;
3015 }
3016}
3017
3018static void intel_pebs_aliases_snb(struct perf_event *event)
3019{
3020 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3021 /*
3022 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3023 * (0x003c) so that we can use it with PEBS.
3024 *
3025 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3026 * PEBS capable. However we can use UOPS_RETIRED.ALL
3027 * (0x01c2), which is a PEBS capable event, to get the same
3028 * count.
3029 *
3030 * UOPS_RETIRED.ALL counts the number of cycles that retires
3031 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3032 * larger than the maximum number of micro-ops that can be
3033 * retired per cycle (4) and then inverting the condition, we
3034 * count all cycles that retire 16 or less micro-ops, which
3035 * is every cycle.
3036 *
3037 * Thereby we gain a PEBS capable cycle counter.
3038 */
3039 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 3040
3041 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3042 event->hw.config = alt_config;
3043 }
0780c927
PZ		 3044}
3045
72469764
AK		 3046static void intel_pebs_aliases_precdist(struct perf_event *event)
3047{
3048 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3049 /*
3050 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3051 * (0x003c) so that we can use it with PEBS.
3052 *
3053 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3054 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3055 * (0x01c0), which is a PEBS capable event, to get the same
3056 * count.
3057 *
3058 * The PREC_DIST event has special support to minimize sample
3059 * shadowing effects. One drawback is that it can be
3060 * only programmed on counter 1, but that seems like an
3061 * acceptable trade off.
3062 */
3063 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3064
3065 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3066 event->hw.config = alt_config;
3067 }
3068}
3069
3070static void intel_pebs_aliases_ivb(struct perf_event *event)
3071{
3072 if (event->attr.precise_ip < 3)
3073 return intel_pebs_aliases_snb(event);
3074 return intel_pebs_aliases_precdist(event);
3075}
3076
3077static void intel_pebs_aliases_skl(struct perf_event *event)
3078{
3079 if (event->attr.precise_ip < 3)
3080 return intel_pebs_aliases_core2(event);
3081 return intel_pebs_aliases_precdist(event);
3082}
3083
174afc3e 3084static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
a7b58d21 3085{
174afc3e 3086 unsigned long flags = x86_pmu.large_pebs_flags;
a7b58d21
AK		 3087
3088 if (event->attr.use_clockid)
3089 flags &= ~PERF_SAMPLE_TIME;
a47ba4d7
AK		 3090 if (!event->attr.exclude_kernel)
3091 flags &= ~PERF_SAMPLE_REGS_USER;
3092 if (event->attr.sample_regs_user & ~PEBS_REGS)
3093 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
a7b58d21
AK		 3094 return flags;
3095}
3096
0780c927
PZ		 3097static int intel_pmu_hw_config(struct perf_event *event)
3098{
3099 int ret = x86_pmu_hw_config(event);
3100
3101 if (ret)
3102 return ret;
3103
851559e3 3104 if (event->attr.precise_ip) {
3569c0d7 3105 if (!event->attr.freq) {
851559e3 3106 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
a7b58d21 3107 if (!(event->attr.sample_type &
174afc3e
KL		 3108 ~intel_pmu_large_pebs_flags(event)))
3109 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3569c0d7 3110 }
851559e3
YZ		 3111 if (x86_pmu.pebs_aliases)
3112 x86_pmu.pebs_aliases(event);
6cbc304f
PZ		 3113
3114 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3115 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
851559e3 3116 }
7639dae0 3117
a46a2300 3118 if (needs_branch_stack(event)) {
60ce0fbd
SE		 3119 ret = intel_pmu_setup_lbr_filter(event);
3120 if (ret)
3121 return ret;
48070342
AS		 3122
3123 /*
3124 * BTS is set up earlier in this path, so don't account twice
3125 */
3126 if (!intel_pmu_has_bts(event)) {
3127 /* disallow lbr if conflicting events are present */
3128 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3129 return -EBUSY;
3130
3131 event->destroy = hw_perf_lbr_event_destroy;
3132 }
60ce0fbd
SE		 3133 }
3134
b4cdc5c2
PZ		 3135 if (event->attr.type != PERF_TYPE_RAW)
3136 return 0;
3137
3138 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3139 return 0;
3140
3141 if (x86_pmu.version < 3)
3142 return -EINVAL;
3143
3144 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
3145 return -EACCES;
3146
3147 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3148
3149 return 0;
3150}
3151
144d31e6
GN		 3152struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3153{
3154 if (x86_pmu.guest_get_msrs)
3155 return x86_pmu.guest_get_msrs(nr);
3156 *nr = 0;
3157 return NULL;
3158}
3159EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3160
3161static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3162{
89cbc767 3163 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 3164 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3165
3166 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3167 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3168 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 3169 /*
3170 * If PMU counter has PEBS enabled it is not enough to disable counter
3171 * on a guest entry since PEBS memory write can overshoot guest entry
3172 * and corrupt guest memory. Disabling PEBS solves the problem.
3173 */
3174 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3175 arr[1].host = cpuc->pebs_enabled;
3176 arr[1].guest = 0;
144d31e6 3177
26a4f3c0 3178 *nr = 2;
144d31e6
GN		 3179 return arr;
3180}
3181
3182static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3183{
89cbc767 3184 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 3185 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3186 int idx;
3187
3188 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3189 struct perf_event *event = cpuc->events[idx];
3190
3191 arr[idx].msr = x86_pmu_config_addr(idx);
3192 arr[idx].host = arr[idx].guest = 0;
3193
3194 if (!test_bit(idx, cpuc->active_mask))
3195 continue;
3196
3197 arr[idx].host = arr[idx].guest =
3198 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3199
3200 if (event->attr.exclude_host)
3201 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3202 else if (event->attr.exclude_guest)
3203 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3204 }
3205
3206 *nr = x86_pmu.num_counters;
3207 return arr;
3208}
3209
3210static void core_pmu_enable_event(struct perf_event *event)
3211{
3212 if (!event->attr.exclude_host)
3213 x86_pmu_enable_event(event);
3214}
3215
3216static void core_pmu_enable_all(int added)
3217{
89cbc767 3218 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 3219 int idx;
3220
3221 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3222 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3223
3224 if (!test_bit(idx, cpuc->active_mask) ||
3225 cpuc->events[idx]->attr.exclude_host)
3226 continue;
3227
3228 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3229 }
3230}
3231
3a632cb2
AK		 3232static int hsw_hw_config(struct perf_event *event)
3233{
3234 int ret = intel_pmu_hw_config(event);
3235
3236 if (ret)
3237 return ret;
3238 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3239 return 0;
3240 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3241
3242 /*
3243 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3244 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3245 * this combination.
3246 */
3247 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3248 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3249 event->attr.precise_ip > 0))
3250 return -EOPNOTSUPP;
3251
2dbf0116
AK		 3252 if (event_is_checkpointed(event)) {
3253 /*
3254 * Sampling of checkpointed events can cause situations where
3255 * the CPU constantly aborts because of a overflow, which is
3256 * then checkpointed back and ignored. Forbid checkpointing
3257 * for sampling.
3258 *
3259 * But still allow a long sampling period, so that perf stat
3260 * from KVM works.
3261 */
3262 if (event->attr.sample_period > 0 &&
3263 event->attr.sample_period < 0x7fffffff)
3264 return -EOPNOTSUPP;
3265 }
3a632cb2
AK		 3266 return 0;
3267}
3268
dd0b06b5
KL		 3269static struct event_constraint counter0_constraint =
3270 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3271
3a632cb2
AK		 3272static struct event_constraint counter2_constraint =
3273 EVENT_CONSTRAINT(0, 0x4, 0);
3274
3275static struct event_constraint *
79cba822
SE		 3276hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3277 struct perf_event *event)
3a632cb2 3278{
79cba822
SE		 3279 struct event_constraint *c;
3280
3281 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 3282
3283 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3284 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3285 if (c->idxmsk64 & (1U << 2))
3286 return &counter2_constraint;
3287 return &emptyconstraint;
3288 }
3289
3290 return c;
3291}
3292
dd0b06b5
KL		 3293static struct event_constraint *
3294glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3295 struct perf_event *event)
3296{
3297 struct event_constraint *c;
3298
3299 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3300 if (event->attr.precise_ip == 3)
3301 return &counter0_constraint;
3302
3303 c = intel_get_event_constraints(cpuc, idx, event);
3304
3305 return c;
3306}
3307
294fe0f5
AK		 3308/*
3309 * Broadwell:
3310 *
3311 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3312 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3313 * the two to enforce a minimum period of 128 (the smallest value that has bits
3314 * 0-5 cleared and >= 100).
3315 *
3316 * Because of how the code in x86_perf_event_set_period() works, the truncation
3317 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3318 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3319 *
3320 * Therefore the effective (average) period matches the requested period,
3321 * despite coarser hardware granularity.
3322 */
f605cfca 3323static u64 bdw_limit_period(struct perf_event *event, u64 left)
294fe0f5
AK		 3324{
3325 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3326 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3327 if (left < 128)
3328 left = 128;
e5ea9b54 3329 left &= ~0x3fULL;
294fe0f5
AK		 3330 }
3331 return left;
3332}
3333
641cc938
JO		 3334PMU_FORMAT_ATTR(event, "config:0-7" );
3335PMU_FORMAT_ATTR(umask, "config:8-15" );
3336PMU_FORMAT_ATTR(edge, "config:18" );
3337PMU_FORMAT_ATTR(pc, "config:19" );
3338PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3339PMU_FORMAT_ATTR(inv, "config:23" );
3340PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 3341PMU_FORMAT_ATTR(in_tx, "config:32");
3342PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 3343
3344static struct attribute *intel_arch_formats_attr[] = {
3345 &format_attr_event.attr,
3346 &format_attr_umask.attr,
3347 &format_attr_edge.attr,
3348 &format_attr_pc.attr,
3349 &format_attr_inv.attr,
3350 &format_attr_cmask.attr,
3351 NULL,
3352};
3353
0bf79d44
JO		 3354ssize_t intel_event_sysfs_show(char *page, u64 config)
3355{
3356 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3357
3358 return x86_event_sysfs_show(page, config, event);
3359}
3360
de0428a7 3361struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 3362{
3363 struct intel_shared_regs *regs;
3364 int i;
3365
3366 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3367 GFP_KERNEL, cpu_to_node(cpu));
3368 if (regs) {
3369 /*
3370 * initialize the locks to keep lockdep happy
3371 */
3372 for (i = 0; i < EXTRA_REG_MAX; i++)
3373 raw_spin_lock_init(&regs->regs[i].lock);
3374
3375 regs->core_id = -1;
3376 }
3377 return regs;
3378}
3379
6f6539ca
MD		 3380static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3381{
3382 struct intel_excl_cntrs *c;
6f6539ca
MD		 3383
3384 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3385 GFP_KERNEL, cpu_to_node(cpu));
3386 if (c) {
3387 raw_spin_lock_init(&c->lock);
6f6539ca
MD		 3388 c->core_id = -1;
3389 }
3390 return c;
3391}
3392
a7e3ed1e
AK		 3393static int intel_pmu_cpu_prepare(int cpu)
3394{
3395 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3396
6f6539ca
MD		 3397 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3398 cpuc->shared_regs = allocate_shared_regs(cpu);
3399 if (!cpuc->shared_regs)
dbc72b7a 3400 goto err;
6f6539ca 3401 }
69092624 3402
6f6539ca
MD		 3403 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3404 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3405
3406 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3407 if (!cpuc->constraint_list)
dbc72b7a 3408 goto err_shared_regs;
6f6539ca
MD		 3409
3410 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
dbc72b7a
PZ		 3411 if (!cpuc->excl_cntrs)
3412 goto err_constraint_list;
3413
6f6539ca
MD		 3414 cpuc->excl_thread_id = 0;
3415 }
a7e3ed1e 3416
95ca792c 3417 return 0;
dbc72b7a
PZ		 3418
3419err_constraint_list:
3420 kfree(cpuc->constraint_list);
3421 cpuc->constraint_list = NULL;
3422
3423err_shared_regs:
3424 kfree(cpuc->shared_regs);
3425 cpuc->shared_regs = NULL;
3426
3427err:
95ca792c 3428 return -ENOMEM;
a7e3ed1e
AK		 3429}
3430
6089327f
KL		 3431static void flip_smm_bit(void *data)
3432{
3433 unsigned long set = *(unsigned long *)data;
3434
3435 if (set > 0) {
3436 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
3437 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3438 } else {
3439 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
3440 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3441 }
3442}
3443
74846d35
PZ		 3444static void intel_pmu_cpu_starting(int cpu)
3445{
a7e3ed1e
AK		 3446 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3447 int core_id = topology_core_id(cpu);
3448 int i;
3449
69092624
LM		 3450 init_debug_store_on_cpu(cpu);
3451 /*
3452 * Deal with CPUs that don't clear their LBRs on power-up.
3453 */
3454 intel_pmu_lbr_reset();
3455
b36817e8
SE		 3456 cpuc->lbr_sel = NULL;
3457
4e949e9b
KL		 3458 if (x86_pmu.version > 1)
3459 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
6089327f 3460
af3bdb99
AK		 3461 if (x86_pmu.counter_freezing)
3462 enable_counter_freeze();
3463
b36817e8 3464 if (!cpuc->shared_regs)
69092624
LM		 3465 return;
3466
9a5e3fb5 3467 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
06931e62 3468 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
b36817e8 3469 struct intel_shared_regs *pc;
a7e3ed1e 3470
b36817e8
SE		 3471 pc = per_cpu(cpu_hw_events, i).shared_regs;
3472 if (pc && pc->core_id == core_id) {
8f04b853 3473 cpuc->kfree_on_online[0] = cpuc->shared_regs;
b36817e8
SE		 3474 cpuc->shared_regs = pc;
3475 break;
3476 }
a7e3ed1e 3477 }
b36817e8
SE		 3478 cpuc->shared_regs->core_id = core_id;
3479 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 3480 }
3481
b36817e8
SE		 3482 if (x86_pmu.lbr_sel_map)
3483 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 3484
3485 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
06931e62 3486 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4e71de79 3487 struct cpu_hw_events *sibling;
6f6539ca
MD		 3488 struct intel_excl_cntrs *c;
3489
4e71de79
ZC		 3490 sibling = &per_cpu(cpu_hw_events, i);
3491 c = sibling->excl_cntrs;
6f6539ca
MD		 3492 if (c && c->core_id == core_id) {
3493 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3494 cpuc->excl_cntrs = c;
4e71de79
ZC		 3495 if (!sibling->excl_thread_id)
3496 cpuc->excl_thread_id = 1;
6f6539ca
MD		 3497 break;
3498 }
3499 }
3500 cpuc->excl_cntrs->core_id = core_id;
3501 cpuc->excl_cntrs->refcnt++;
3502 }
74846d35
PZ		 3503}
3504
b37609c3 3505static void free_excl_cntrs(int cpu)
74846d35 3506{
a7e3ed1e 3507 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 3508 struct intel_excl_cntrs *c;
a7e3ed1e 3509
6f6539ca
MD		 3510 c = cpuc->excl_cntrs;
3511 if (c) {
3512 if (c->core_id == -1 || --c->refcnt == 0)
3513 kfree(c);
3514 cpuc->excl_cntrs = NULL;
3515 kfree(cpuc->constraint_list);
3516 cpuc->constraint_list = NULL;
3517 }
b37609c3 3518}
a7e3ed1e 3519
b37609c3
SE		 3520static void intel_pmu_cpu_dying(int cpu)
3521{
3522 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3523 struct intel_shared_regs *pc;
3524
3525 pc = cpuc->shared_regs;
3526 if (pc) {
3527 if (pc->core_id == -1 || --pc->refcnt == 0)
3528 kfree(pc);
3529 cpuc->shared_regs = NULL;
e979121b
MD		 3530 }
3531
b37609c3
SE		 3532 free_excl_cntrs(cpu);
3533
74846d35 3534 fini_debug_store_on_cpu(cpu);
af3bdb99
AK		 3535
3536 if (x86_pmu.counter_freezing)
3537 disable_counter_freeze();
74846d35
PZ		 3538}
3539
9c964efa
YZ		 3540static void intel_pmu_sched_task(struct perf_event_context *ctx,
3541 bool sched_in)
3542{
df6c3db8
JO		 3543 intel_pmu_pebs_sched_task(ctx, sched_in);
3544 intel_pmu_lbr_sched_task(ctx, sched_in);
9c964efa
YZ		 3545}
3546
641cc938
JO		 3547PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3548
a63fcab4
SE		 3549PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3550
d0dc8494
AK		 3551PMU_FORMAT_ATTR(frontend, "config1:0-23");
3552
641cc938
JO		 3553static struct attribute *intel_arch3_formats_attr[] = {
3554 &format_attr_event.attr,
3555 &format_attr_umask.attr,
3556 &format_attr_edge.attr,
3557 &format_attr_pc.attr,
3558 &format_attr_any.attr,
3559 &format_attr_inv.attr,
3560 &format_attr_cmask.attr,
a5df70c3
AK		 3561 NULL,
3562};
3563
3564static struct attribute *hsw_format_attr[] = {
3a632cb2
AK		 3565 &format_attr_in_tx.attr,
3566 &format_attr_in_tx_cp.attr,
a5df70c3
AK		 3567 &format_attr_offcore_rsp.attr,
3568 &format_attr_ldlat.attr,
3569 NULL
3570};
641cc938 3571
a5df70c3
AK		 3572static struct attribute *nhm_format_attr[] = {
3573 &format_attr_offcore_rsp.attr,
3574 &format_attr_ldlat.attr,
3575 NULL
3576};
3577
3578static struct attribute *slm_format_attr[] = {
3579 &format_attr_offcore_rsp.attr,
3580 NULL
641cc938
JO		 3581};
3582
d0dc8494
AK		 3583static struct attribute *skl_format_attr[] = {
3584 &format_attr_frontend.attr,
3585 NULL,
3586};
3587
3b6e0421
JO		 3588static __initconst const struct x86_pmu core_pmu = {
3589 .name = "core",
3590 .handle_irq = x86_pmu_handle_irq,
3591 .disable_all = x86_pmu_disable_all,
3592 .enable_all = core_pmu_enable_all,
3593 .enable = core_pmu_enable_event,
3594 .disable = x86_pmu_disable_event,
3595 .hw_config = x86_pmu_hw_config,
3596 .schedule_events = x86_schedule_events,
3597 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3598 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3599 .event_map = intel_pmu_event_map,
3600 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3601 .apic = 1,
174afc3e 3602 .large_pebs_flags = LARGE_PEBS_FLAGS,
a7b58d21 3603
3b6e0421
JO		 3604 /*
3605 * Intel PMCs cannot be accessed sanely above 32-bit width,
3606 * so we install an artificial 1<<31 period regardless of
3607 * the generic event period:
3608 */
3609 .max_period = (1ULL<<31) - 1,
3610 .get_event_constraints = intel_get_event_constraints,
3611 .put_event_constraints = intel_put_event_constraints,
3612 .event_constraints = intel_core_event_constraints,
3613 .guest_get_msrs = core_guest_get_msrs,
3614 .format_attrs = intel_arch_formats_attr,
3615 .events_sysfs_show = intel_event_sysfs_show,
3616
3617 /*
3618 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3619 * together with PMU version 1 and thus be using core_pmu with
3620 * shared_regs. We need following callbacks here to allocate
3621 * it properly.
3622 */
3623 .cpu_prepare = intel_pmu_cpu_prepare,
3624 .cpu_starting = intel_pmu_cpu_starting,
3625 .cpu_dying = intel_pmu_cpu_dying,
3626};
3627
4e949e9b
KL		 3628static struct attribute *intel_pmu_attrs[];
3629
caaa8be3 3630static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 3631 .name = "Intel",
3632 .handle_irq = intel_pmu_handle_irq,
3633 .disable_all = intel_pmu_disable_all,
3634 .enable_all = intel_pmu_enable_all,
3635 .enable = intel_pmu_enable_event,
3636 .disable = intel_pmu_disable_event,
68f7082f
PZ		 3637 .add = intel_pmu_add_event,
3638 .del = intel_pmu_del_event,
ceb90d9e 3639 .read = intel_pmu_read_event,
b4cdc5c2 3640 .hw_config = intel_pmu_hw_config,
a072738e 3641 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 3642 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3643 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3644 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 3645 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3646 .apic = 1,
174afc3e 3647 .large_pebs_flags = LARGE_PEBS_FLAGS,
f22f54f4
PZ		 3648 /*
3649 * Intel PMCs cannot be accessed sanely above 32 bit width,
3650 * so we install an artificial 1<<31 period regardless of
3651 * the generic event period:
3652 */
3653 .max_period = (1ULL << 31) - 1,
3f6da390 3654 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 3655 .put_event_constraints = intel_put_event_constraints,
0780c927 3656 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 3657
641cc938 3658 .format_attrs = intel_arch3_formats_attr,
0bf79d44 3659 .events_sysfs_show = intel_event_sysfs_show,
641cc938 3660
4e949e9b
KL		 3661 .attrs = intel_pmu_attrs,
3662
a7e3ed1e 3663 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 3664 .cpu_starting = intel_pmu_cpu_starting,
3665 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 3666 .guest_get_msrs = intel_guest_get_msrs,
9c964efa 3667 .sched_task = intel_pmu_sched_task,
f22f54f4
PZ		 3668};
3669
c1d6f42f 3670static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 3671{
3672 /*
3673 * PEBS is unreliable due to:
3674 *
3675 * AJ67 - PEBS may experience CPL leaks
3676 * AJ68 - PEBS PMI may be delayed by one event
3677 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3678 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3679 *
3680 * AJ67 could be worked around by restricting the OS/USR flags.
3681 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3682 *
3683 * AJ106 could possibly be worked around by not allowing LBR
3684 * usage from PEBS, including the fixup.
3685 * AJ68 could possibly be worked around by always programming
ec75a716 3686 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 3687 *
3688 * But taken together it might just make sense to not enable PEBS on
3689 * these chips.
3690 */
c767a54b 3691 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 3692 x86_pmu.pebs = 0;
3693 x86_pmu.pebs_constraints = NULL;
3694}
3695
c93dc84c
PZ		 3696static int intel_snb_pebs_broken(int cpu)
3697{
3698 u32 rev = UINT_MAX; /* default to broken for unknown models */
3699
3700 switch (cpu_data(cpu).x86_model) {
ef5f9f47 3701 case INTEL_FAM6_SANDYBRIDGE:
c93dc84c
PZ		 3702 rev = 0x28;
3703 break;
3704
ef5f9f47 3705 case INTEL_FAM6_SANDYBRIDGE_X:
b399151c 3706 switch (cpu_data(cpu).x86_stepping) {
c93dc84c
PZ		 3707 case 6: rev = 0x618; break;
3708 case 7: rev = 0x70c; break;
3709 }
3710 }
3711
3712 return (cpu_data(cpu).microcode < rev);
3713}
3714
3715static void intel_snb_check_microcode(void)
3716{
3717 int pebs_broken = 0;
3718 int cpu;
3719
c93dc84c
PZ		 3720 for_each_online_cpu(cpu) {
3721 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3722 break;
3723 }
c93dc84c
PZ		 3724
3725 if (pebs_broken == x86_pmu.pebs_broken)
3726 return;
3727
3728 /*
3729 * Serialized by the microcode lock..
3730 */
3731 if (x86_pmu.pebs_broken) {
3732 pr_info("PEBS enabled due to microcode update\n");
3733 x86_pmu.pebs_broken = 0;
3734 } else {
3735 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3736 x86_pmu.pebs_broken = 1;
3737 }
3738}
3739
19fc9ddd
DCC		 3740static bool is_lbr_from(unsigned long msr)
3741{
3742 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
3743
3744 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
3745}
3746
338b522c
KL		 3747/*
3748 * Under certain circumstances, access certain MSR may cause #GP.
3749 * The function tests if the input MSR can be safely accessed.
3750 */
3751static bool check_msr(unsigned long msr, u64 mask)
3752{
3753 u64 val_old, val_new, val_tmp;
3754
3755 /*
3756 * Read the current value, change it and read it back to see if it
3757 * matches, this is needed to detect certain hardware emulators
3758 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3759 */
3760 if (rdmsrl_safe(msr, &val_old))
3761 return false;
3762
3763 /*
3764 * Only change the bits which can be updated by wrmsrl.
3765 */
3766 val_tmp = val_old ^ mask;
19fc9ddd
DCC		 3767
3768 if (is_lbr_from(msr))
3769 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
3770
338b522c
KL		 3771 if (wrmsrl_safe(msr, val_tmp) ||
3772 rdmsrl_safe(msr, &val_new))
3773 return false;
3774
19fc9ddd
DCC		 3775 /*
3776 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
3777 * should equal rdmsrl()'s even with the quirk.
3778 */
338b522c
KL		 3779 if (val_new != val_tmp)
3780 return false;
3781
19fc9ddd
DCC		 3782 if (is_lbr_from(msr))
3783 val_old = lbr_from_signext_quirk_wr(val_old);
3784
338b522c
KL		 3785 /* Here it's sure that the MSR can be safely accessed.
3786 * Restore the old value and return.
3787 */
3788 wrmsrl(msr, val_old);
3789
3790 return true;
3791}
3792
c1d6f42f 3793static __init void intel_sandybridge_quirk(void)
6a600a8b 3794{
c93dc84c 3795 x86_pmu.check_microcode = intel_snb_check_microcode;
1ba143a5 3796 cpus_read_lock();
c93dc84c 3797 intel_snb_check_microcode();
1ba143a5 3798 cpus_read_unlock();
6a600a8b
PZ		 3799}
3800
c1d6f42f
PZ		 3801static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3802 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3803 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3804 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3805 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3806 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3807 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3808 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 3809};
3810
c1d6f42f
PZ		 3811static __init void intel_arch_events_quirk(void)
3812{
3813 int bit;
3814
3815 /* disable event that reported as not presend by cpuid */
3816 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3817 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 3818 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3819 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 3820 }
3821}
3822
3823static __init void intel_nehalem_quirk(void)
3824{
3825 union cpuid10_ebx ebx;
3826
3827 ebx.full = x86_pmu.events_maskl;
3828 if (ebx.split.no_branch_misses_retired) {
3829 /*
3830 * Erratum AAJ80 detected, we work it around by using
3831 * the BR_MISP_EXEC.ANY event. This will over-count
3832 * branch-misses, but it's still much better than the
3833 * architectural event which is often completely bogus:
3834 */
3835 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3836 ebx.split.no_branch_misses_retired = 0;
3837 x86_pmu.events_maskl = ebx.full;
c767a54b 3838 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 3839 }
3840}
3841
93fcf72c
MD		 3842/*
3843 * enable software workaround for errata:
3844 * SNB: BJ122
3845 * IVB: BV98
3846 * HSW: HSD29
3847 *
3848 * Only needed when HT is enabled. However detecting
b37609c3
SE		 3849 * if HT is enabled is difficult (model specific). So instead,
3850 * we enable the workaround in the early boot, and verify if
3851 * it is needed in a later initcall phase once we have valid
3852 * topology information to check if HT is actually enabled
93fcf72c
MD		 3853 */
3854static __init void intel_ht_bug(void)
3855{
b37609c3 3856 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c 3857
93fcf72c 3858 x86_pmu.start_scheduling = intel_start_scheduling;
0c41e756 3859 x86_pmu.commit_scheduling = intel_commit_scheduling;
93fcf72c 3860 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 3861}
3862
7f2ee91f
IM		 3863EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3864EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 3865
4b2c4f1f 3866/* Haswell special events */
7f2ee91f
IM		 3867EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3868EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3869EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3870EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3871EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3872EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3873EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3874EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3875EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3876EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3877EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3878EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 3879
f9134f36 3880static struct attribute *hsw_events_attrs[] = {
58ba4d5a
AK		 3881 EVENT_PTR(mem_ld_hsw),
3882 EVENT_PTR(mem_st_hsw),
3883 EVENT_PTR(td_slots_issued),
3884 EVENT_PTR(td_slots_retired),
3885 EVENT_PTR(td_fetch_bubbles),
3886 EVENT_PTR(td_total_slots),
3887 EVENT_PTR(td_total_slots_scale),
3888 EVENT_PTR(td_recovery_bubbles),
3889 EVENT_PTR(td_recovery_bubbles_scale),
3890 NULL
3891};
3892
3893static struct attribute *hsw_tsx_events_attrs[] = {
4b2c4f1f
AK		 3894 EVENT_PTR(tx_start),
3895 EVENT_PTR(tx_commit),
3896 EVENT_PTR(tx_abort),
3897 EVENT_PTR(tx_capacity),
3898 EVENT_PTR(tx_conflict),
3899 EVENT_PTR(el_start),
3900 EVENT_PTR(el_commit),
3901 EVENT_PTR(el_abort),
3902 EVENT_PTR(el_capacity),
3903 EVENT_PTR(el_conflict),
3904 EVENT_PTR(cycles_t),
3905 EVENT_PTR(cycles_ct),
f9134f36
AK		 3906 NULL
3907};
3908
58ba4d5a
AK		 3909static __init struct attribute **get_hsw_events_attrs(void)
3910{
3911 return boot_cpu_has(X86_FEATURE_RTM) ?
3912 merge_attr(hsw_events_attrs, hsw_tsx_events_attrs) :
3913 hsw_events_attrs;
3914}
3915
6089327f
KL		 3916static ssize_t freeze_on_smi_show(struct device *cdev,
3917 struct device_attribute *attr,
3918 char *buf)
3919{
3920 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
3921}
3922
3923static DEFINE_MUTEX(freeze_on_smi_mutex);
3924
3925static ssize_t freeze_on_smi_store(struct device *cdev,
3926 struct device_attribute *attr,
3927 const char *buf, size_t count)
3928{
3929 unsigned long val;
3930 ssize_t ret;
3931
3932 ret = kstrtoul(buf, 0, &val);
3933 if (ret)
3934 return ret;
3935
3936 if (val > 1)
3937 return -EINVAL;
3938
3939 mutex_lock(&freeze_on_smi_mutex);
3940
3941 if (x86_pmu.attr_freeze_on_smi == val)
3942 goto done;
3943
3944 x86_pmu.attr_freeze_on_smi = val;
3945
3946 get_online_cpus();
3947 on_each_cpu(flip_smm_bit, &val, 1);
3948 put_online_cpus();
3949done:
3950 mutex_unlock(&freeze_on_smi_mutex);
3951
3952 return count;
3953}
3954
3955static DEVICE_ATTR_RW(freeze_on_smi);
3956
b00233b5
AK		 3957static ssize_t branches_show(struct device *cdev,
3958 struct device_attribute *attr,
3959 char *buf)
3960{
3961 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
3962}
3963
3964static DEVICE_ATTR_RO(branches);
3965
3966static struct attribute *lbr_attrs[] = {
3967 &dev_attr_branches.attr,
3968 NULL
3969};
3970
3971static char pmu_name_str[30];
3972
3973static ssize_t pmu_name_show(struct device *cdev,
3974 struct device_attribute *attr,
3975 char *buf)
3976{
3977 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
3978}
3979
3980static DEVICE_ATTR_RO(pmu_name);
3981
b00233b5 3982static struct attribute *intel_pmu_caps_attrs[] = {
5da382eb
PZ		 3983 &dev_attr_pmu_name.attr,
3984 NULL
b00233b5
AK		 3985};
3986
6089327f
KL		 3987static struct attribute *intel_pmu_attrs[] = {
3988 &dev_attr_freeze_on_smi.attr,
3989 NULL,
3990};
3991
de0428a7 3992__init int intel_pmu_init(void)
f22f54f4 3993{
7ad1437d
TG		 3994 struct attribute **extra_attr = NULL;
3995 struct attribute **to_free = NULL;
f22f54f4
PZ		 3996 union cpuid10_edx edx;
3997 union cpuid10_eax eax;
ffb871bc 3998 union cpuid10_ebx ebx;
a1eac7ac 3999 struct event_constraint *c;
f22f54f4 4000 unsigned int unused;
338b522c
KL		 4001 struct extra_reg *er;
4002 int version, i;
b00233b5 4003 char *name;
f22f54f4
PZ		 4004
4005 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 4006 switch (boot_cpu_data.x86) {
4007 case 0x6:
4008 return p6_pmu_init();
e717bf4e
VW		 4009 case 0xb:
4010 return knc_pmu_init();
a072738e
CG		 4011 case 0xf:
4012 return p4_pmu_init();
4013 }
f22f54f4 4014 return -ENODEV;
f22f54f4
PZ		 4015 }
4016
4017 /*
4018 * Check whether the Architectural PerfMon supports
4019 * Branch Misses Retired hw_event or not.
4020 */
ffb871bc
GN		 4021 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4022 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 4023 return -ENODEV;
4024
4025 version = eax.split.version_id;
4026 if (version < 2)
4027 x86_pmu = core_pmu;
4028 else
4029 x86_pmu = intel_pmu;
4030
4031 x86_pmu.version = version;
948b1bb8
RR		 4032 x86_pmu.num_counters = eax.split.num_counters;
4033 x86_pmu.cntval_bits = eax.split.bit_width;
4034 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 4035
c1d6f42f
PZ		 4036 x86_pmu.events_maskl = ebx.full;
4037 x86_pmu.events_mask_len = eax.split.mask_length;
4038
70ab7003
AK		 4039 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4040
f22f54f4
PZ		 4041 /*
4042 * Quirk: v2 perfmon does not report fixed-purpose events, so
f92b7604 4043 * assume at least 3 events, when not running in a hypervisor:
f22f54f4 4044 */
f92b7604
IP		 4045 if (version > 1) {
4046 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4047
4048 x86_pmu.num_counters_fixed =
4049 max((int)edx.split.num_counters_fixed, assume);
4050 }
f22f54f4 4051
af3bdb99
AK		 4052 if (version >= 4)
4053 x86_pmu.counter_freezing = !disable_counter_freezing;
4054
c9b08884 4055 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 4056 u64 capabilities;
4057
4058 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4059 x86_pmu.intel_cap.capabilities = capabilities;
4060 }
4061
ca037701
PZ		 4062 intel_ds_init();
4063
c1d6f42f
PZ		 4064 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
4065
f22f54f4
PZ		 4066 /*
4067 * Install the hw-cache-events table:
4068 */
4069 switch (boot_cpu_data.x86_model) {
ef5f9f47 4070 case INTEL_FAM6_CORE_YONAH:
f22f54f4 4071 pr_cont("Core events, ");
b00233b5 4072 name = "core";
f22f54f4
PZ		 4073 break;
4074
ef5f9f47 4075 case INTEL_FAM6_CORE2_MEROM:
c1d6f42f 4076 x86_add_quirk(intel_clovertown_quirk);
ef5f9f47
DH		 4077 case INTEL_FAM6_CORE2_MEROM_L:
4078 case INTEL_FAM6_CORE2_PENRYN:
4079 case INTEL_FAM6_CORE2_DUNNINGTON:
f22f54f4
PZ		 4080 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
4081 sizeof(hw_cache_event_ids));
4082
caff2bef
PZ		 4083 intel_pmu_lbr_init_core();
4084
f22f54f4 4085 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 4086 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4 4087 pr_cont("Core2 events, ");
b00233b5 4088 name = "core2";
f22f54f4
PZ		 4089 break;
4090
ef5f9f47
DH		 4091 case INTEL_FAM6_NEHALEM:
4092 case INTEL_FAM6_NEHALEM_EP:
4093 case INTEL_FAM6_NEHALEM_EX:
f22f54f4
PZ		 4094 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
4095 sizeof(hw_cache_event_ids));
e994d7d2
AK		 4096 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4097 sizeof(hw_cache_extra_regs));
f22f54f4 4098
caff2bef
PZ		 4099 intel_pmu_lbr_init_nhm();
4100
f22f54f4 4101 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 4102 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 4103 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 4104 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 4105
f20093ee
SE		 4106 x86_pmu.cpu_events = nhm_events_attrs;
4107
91fc4cc0 4108 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 4109 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4110 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 4111 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 4112 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4113 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 4114
e17dc653 4115 intel_pmu_pebs_data_source_nhm();
c1d6f42f 4116 x86_add_quirk(intel_nehalem_quirk);
95298355 4117 x86_pmu.pebs_no_tlb = 1;
a5df70c3 4118 extra_attr = nhm_format_attr;
ec75a716 4119
11164cd4 4120 pr_cont("Nehalem events, ");
b00233b5 4121 name = "nehalem";
f22f54f4 4122 break;
caff2bef 4123
f2c4db1b
PZ		 4124 case INTEL_FAM6_ATOM_BONNELL:
4125 case INTEL_FAM6_ATOM_BONNELL_MID:
4126 case INTEL_FAM6_ATOM_SALTWELL:
4127 case INTEL_FAM6_ATOM_SALTWELL_MID:
4128 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
f22f54f4
PZ		 4129 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
4130 sizeof(hw_cache_event_ids));
4131
caff2bef
PZ		 4132 intel_pmu_lbr_init_atom();
4133
f22f54f4 4134 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 4135 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
673d188b 4136 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
f22f54f4 4137 pr_cont("Atom events, ");
b00233b5 4138 name = "bonnell";
f22f54f4
PZ		 4139 break;
4140
f2c4db1b
PZ		 4141 case INTEL_FAM6_ATOM_SILVERMONT:
4142 case INTEL_FAM6_ATOM_SILVERMONT_X:
4143 case INTEL_FAM6_ATOM_SILVERMONT_MID:
ef5f9f47 4144 case INTEL_FAM6_ATOM_AIRMONT:
f2c4db1b 4145 case INTEL_FAM6_ATOM_AIRMONT_MID:
1fa64180
YZ		 4146 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
4147 sizeof(hw_cache_event_ids));
4148 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
4149 sizeof(hw_cache_extra_regs));
4150
f21d5adc 4151 intel_pmu_lbr_init_slm();
1fa64180
YZ		 4152
4153 x86_pmu.event_constraints = intel_slm_event_constraints;
4154 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4155 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 4156 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
eb12b8ec 4157 x86_pmu.cpu_events = slm_events_attrs;
a5df70c3 4158 extra_attr = slm_format_attr;
1fa64180 4159 pr_cont("Silvermont events, ");
b00233b5 4160 name = "silvermont";
1fa64180
YZ		 4161 break;
4162
ef5f9f47 4163 case INTEL_FAM6_ATOM_GOLDMONT:
f2c4db1b 4164 case INTEL_FAM6_ATOM_GOLDMONT_X:
8b92c3a7
KL		 4165 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
4166 sizeof(hw_cache_event_ids));
4167 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
4168 sizeof(hw_cache_extra_regs));
4169
4170 intel_pmu_lbr_init_skl();
4171
4172 x86_pmu.event_constraints = intel_slm_event_constraints;
4173 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
4174 x86_pmu.extra_regs = intel_glm_extra_regs;
4175 /*
4176 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4177 * for precise cycles.
4178 * :pp is identical to :ppp
4179 */
4180 x86_pmu.pebs_aliases = NULL;
4181 x86_pmu.pebs_prec_dist = true;
ccbebba4 4182 x86_pmu.lbr_pt_coexist = true;
8b92c3a7 4183 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
ed827adb 4184 x86_pmu.cpu_events = glm_events_attrs;
a5df70c3 4185 extra_attr = slm_format_attr;
8b92c3a7 4186 pr_cont("Goldmont events, ");
b00233b5 4187 name = "goldmont";
8b92c3a7
KL		 4188 break;
4189
f2c4db1b 4190 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
dd0b06b5
KL		 4191 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4192 sizeof(hw_cache_event_ids));
4193 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
4194 sizeof(hw_cache_extra_regs));
4195
4196 intel_pmu_lbr_init_skl();
4197
4198 x86_pmu.event_constraints = intel_slm_event_constraints;
dd0b06b5
KL		 4199 x86_pmu.extra_regs = intel_glm_extra_regs;
4200 /*
4201 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
4202 * for precise cycles.
4203 */
4204 x86_pmu.pebs_aliases = NULL;
4205 x86_pmu.pebs_prec_dist = true;
4206 x86_pmu.lbr_pt_coexist = true;
4207 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
a38b0ba1 4208 x86_pmu.flags |= PMU_FL_PEBS_ALL;
dd0b06b5
KL		 4209 x86_pmu.get_event_constraints = glp_get_event_constraints;
4210 x86_pmu.cpu_events = glm_events_attrs;
4211 /* Goldmont Plus has 4-wide pipeline */
4212 event_attr_td_total_slots_scale_glm.event_str = "4";
a5df70c3 4213 extra_attr = slm_format_attr;
dd0b06b5 4214 pr_cont("Goldmont plus events, ");
b00233b5 4215 name = "goldmont_plus";
dd0b06b5
KL		 4216 break;
4217
ef5f9f47
DH		 4218 case INTEL_FAM6_WESTMERE:
4219 case INTEL_FAM6_WESTMERE_EP:
4220 case INTEL_FAM6_WESTMERE_EX:
f22f54f4
PZ		 4221 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
4222 sizeof(hw_cache_event_ids));
e994d7d2
AK		 4223 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4224 sizeof(hw_cache_extra_regs));
f22f54f4 4225
caff2bef
PZ		 4226 intel_pmu_lbr_init_nhm();
4227
f22f54f4 4228 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 4229 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 4230 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 4231 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 4232 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 4233
f20093ee
SE		 4234 x86_pmu.cpu_events = nhm_events_attrs;
4235
30112039 4236 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 4237 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4238 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 4239 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 4240 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4241 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 4242
e17dc653 4243 intel_pmu_pebs_data_source_nhm();
a5df70c3 4244 extra_attr = nhm_format_attr;
f22f54f4 4245 pr_cont("Westmere events, ");
b00233b5 4246 name = "westmere";
f22f54f4 4247 break;
b622d644 4248
ef5f9f47
DH		 4249 case INTEL_FAM6_SANDYBRIDGE:
4250 case INTEL_FAM6_SANDYBRIDGE_X:
47a8863d 4251 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 4252 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 4253 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4254 sizeof(hw_cache_event_ids));
74e6543f
YZ		 4255 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4256 sizeof(hw_cache_extra_regs));
b06b3d49 4257
c5cc2cd9 4258 intel_pmu_lbr_init_snb();
b06b3d49
LM		 4259
4260 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 4261 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 4262 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
ef5f9f47 4263 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
f1923820
SE		 4264 x86_pmu.extra_regs = intel_snbep_extra_regs;
4265 else
4266 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 4267
4268
ee89cbc2 4269 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 4270 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4271 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 4272
f20093ee
SE		 4273 x86_pmu.cpu_events = snb_events_attrs;
4274
e04d1b23 4275 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 4276 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4277 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 4278 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 4279 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4280 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 4281
a5df70c3
AK		 4282 extra_attr = nhm_format_attr;
4283
b06b3d49 4284 pr_cont("SandyBridge events, ");
b00233b5 4285 name = "sandybridge";
b06b3d49 4286 break;
0f7c29ce 4287
ef5f9f47
DH		 4288 case INTEL_FAM6_IVYBRIDGE:
4289 case INTEL_FAM6_IVYBRIDGE_X:
93fcf72c 4290 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 4291 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4292 sizeof(hw_cache_event_ids));
1996388e
VW		 4293 /* dTLB-load-misses on IVB is different than SNB */
4294 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
4295
20a36e39
SE		 4296 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4297 sizeof(hw_cache_extra_regs));
4298
4299 intel_pmu_lbr_init_snb();
4300
69943182 4301 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39 4302 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
72469764
AK		 4303 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4304 x86_pmu.pebs_prec_dist = true;
ef5f9f47 4305 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
f1923820
SE		 4306 x86_pmu.extra_regs = intel_snbep_extra_regs;
4307 else
4308 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 4309 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 4310 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4311 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 4312
f20093ee
SE		 4313 x86_pmu.cpu_events = snb_events_attrs;
4314
20a36e39
SE		 4315 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
4316 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4317 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4318
a5df70c3
AK		 4319 extra_attr = nhm_format_attr;
4320
20a36e39 4321 pr_cont("IvyBridge events, ");
b00233b5 4322 name = "ivybridge";
20a36e39
SE		 4323 break;
4324
b06b3d49 4325
ef5f9f47
DH		 4326 case INTEL_FAM6_HASWELL_CORE:
4327 case INTEL_FAM6_HASWELL_X:
4328 case INTEL_FAM6_HASWELL_ULT:
4329 case INTEL_FAM6_HASWELL_GT3E:
93fcf72c 4330 x86_add_quirk(intel_ht_bug);
72db5596 4331 x86_pmu.late_ack = true;
0f1b5ca2
AK		 4332 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4333 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 4334
e9d7f7cd 4335 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 4336
4337 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 4338 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 4339 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 4340 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4341 x86_pmu.pebs_prec_dist = true;
3a632cb2 4342 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 4343 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4344 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 4345
4346 x86_pmu.hw_config = hsw_hw_config;
4347 x86_pmu.get_event_constraints = hsw_get_event_constraints;
58ba4d5a 4348 x86_pmu.cpu_events = get_hsw_events_attrs();
b7af41a1 4349 x86_pmu.lbr_double_abort = true;
a5df70c3
AK		 4350 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4351 hsw_format_attr : nhm_format_attr;
3a632cb2 4352 pr_cont("Haswell events, ");
b00233b5 4353 name = "haswell";
3a632cb2
AK		 4354 break;
4355
ef5f9f47
DH		 4356 case INTEL_FAM6_BROADWELL_CORE:
4357 case INTEL_FAM6_BROADWELL_XEON_D:
4358 case INTEL_FAM6_BROADWELL_GT3E:
4359 case INTEL_FAM6_BROADWELL_X:
91f1b705
AK		 4360 x86_pmu.late_ack = true;
4361 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4362 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4363
4364 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
4365 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
4366 BDW_L3_MISS|HSW_SNOOP_DRAM;
4367 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
4368 HSW_SNOOP_DRAM;
4369 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
4370 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4371 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
4372 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4373
78d504bc 4374 intel_pmu_lbr_init_hsw();
91f1b705
AK		 4375
4376 x86_pmu.event_constraints = intel_bdw_event_constraints;
b3e62463 4377 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
91f1b705 4378 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 4379 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4380 x86_pmu.pebs_prec_dist = true;
91f1b705 4381 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 4382 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4383 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 4384
4385 x86_pmu.hw_config = hsw_hw_config;
4386 x86_pmu.get_event_constraints = hsw_get_event_constraints;
58ba4d5a 4387 x86_pmu.cpu_events = get_hsw_events_attrs();
294fe0f5 4388 x86_pmu.limit_period = bdw_limit_period;
a5df70c3
AK		 4389 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4390 hsw_format_attr : nhm_format_attr;
91f1b705 4391 pr_cont("Broadwell events, ");
b00233b5 4392 name = "broadwell";
91f1b705
AK		 4393 break;
4394
ef5f9f47 4395 case INTEL_FAM6_XEON_PHI_KNL:
608284bf 4396 case INTEL_FAM6_XEON_PHI_KNM:
1e7b9390
HC		 4397 memcpy(hw_cache_event_ids,
4398 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4399 memcpy(hw_cache_extra_regs,
4400 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4401 intel_pmu_lbr_init_knl();
4402
4403 x86_pmu.event_constraints = intel_slm_event_constraints;
4404 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4405 x86_pmu.extra_regs = intel_knl_extra_regs;
4406
4407 /* all extra regs are per-cpu when HT is on */
4408 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4409 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
a5df70c3 4410 extra_attr = slm_format_attr;
608284bf 4411 pr_cont("Knights Landing/Mill events, ");
b00233b5 4412 name = "knights-landing";
1e7b9390
HC		 4413 break;
4414
ef5f9f47
DH		 4415 case INTEL_FAM6_SKYLAKE_MOBILE:
4416 case INTEL_FAM6_SKYLAKE_DESKTOP:
4417 case INTEL_FAM6_SKYLAKE_X:
4418 case INTEL_FAM6_KABYLAKE_MOBILE:
4419 case INTEL_FAM6_KABYLAKE_DESKTOP:
9a92e16f
AK		 4420 x86_pmu.late_ack = true;
4421 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4422 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4423 intel_pmu_lbr_init_skl();
4424
a39fcae7
AK		 4425 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
4426 event_attr_td_recovery_bubbles.event_str_noht =
4427 "event=0xd,umask=0x1,cmask=1";
4428 event_attr_td_recovery_bubbles.event_str_ht =
4429 "event=0xd,umask=0x1,cmask=1,any=1";
4430
9a92e16f
AK		 4431 x86_pmu.event_constraints = intel_skl_event_constraints;
4432 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
4433 x86_pmu.extra_regs = intel_skl_extra_regs;
72469764
AK		 4434 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
4435 x86_pmu.pebs_prec_dist = true;
9a92e16f
AK		 4436 /* all extra regs are per-cpu when HT is on */
4437 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4438 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4439
4440 x86_pmu.hw_config = hsw_hw_config;
4441 x86_pmu.get_event_constraints = hsw_get_event_constraints;
a5df70c3
AK		 4442 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4443 hsw_format_attr : nhm_format_attr;
4444 extra_attr = merge_attr(extra_attr, skl_format_attr);
7ad1437d 4445 to_free = extra_attr;
58ba4d5a 4446 x86_pmu.cpu_events = get_hsw_events_attrs();
6ae5fa61
AK		 4447 intel_pmu_pebs_data_source_skl(
4448 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
9a92e16f 4449 pr_cont("Skylake events, ");
b00233b5 4450 name = "skylake";
9a92e16f
AK		 4451 break;
4452
f22f54f4 4453 default:
0af3ac1f
AK		 4454 switch (x86_pmu.version) {
4455 case 1:
4456 x86_pmu.event_constraints = intel_v1_event_constraints;
4457 pr_cont("generic architected perfmon v1, ");
b00233b5 4458 name = "generic_arch_v1";
0af3ac1f
AK		 4459 break;
4460 default:
4461 /*
4462 * default constraints for v2 and up
4463 */
4464 x86_pmu.event_constraints = intel_gen_event_constraints;
4465 pr_cont("generic architected perfmon, ");
b00233b5 4466 name = "generic_arch_v2+";
0af3ac1f
AK		 4467 break;
4468 }
f22f54f4 4469 }
ffb871bc 4470
b00233b5
AK		 4471 snprintf(pmu_name_str, sizeof pmu_name_str, "%s", name);
4472
a5df70c3
AK		 4473 if (version >= 2 && extra_attr) {
4474 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
4475 extra_attr);
4476 WARN_ON(!x86_pmu.format_attrs);
4477 }
4478
a1eac7ac
RR		 4479 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
4480 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4481 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
4482 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
4483 }
ad5013d5 4484 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac
RR		 4485
4486 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
4487 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
4488 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
4489 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
4490 }
4491
4492 x86_pmu.intel_ctrl |=
4493 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
4494
4495 if (x86_pmu.event_constraints) {
4496 /*
4497 * event on fixed counter2 (REF_CYCLES) only works on this
4498 * counter, so do not extend mask to generic counters
4499 */
4500 for_each_event_constraint(c, x86_pmu.event_constraints) {
2c33645d
PI		 4501 if (c->cmask == FIXED_EVENT_FLAGS
4502 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
4503 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac 4504 }
2c33645d 4505 c->idxmsk64 &=
6d6f2833 4506 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
2c33645d 4507 c->weight = hweight64(c->idxmsk64);
a1eac7ac
RR		 4508 }
4509 }
4510
338b522c
KL		 4511 /*
4512 * Access LBR MSR may cause #GP under certain circumstances.
4513 * E.g. KVM doesn't support LBR MSR
4514 * Check all LBT MSR here.
4515 * Disable LBR access if any LBR MSRs can not be accessed.
4516 */
4517 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
4518 x86_pmu.lbr_nr = 0;
4519 for (i = 0; i < x86_pmu.lbr_nr; i++) {
4520 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
4521 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
4522 x86_pmu.lbr_nr = 0;
4523 }
4524
b00233b5
AK		 4525 x86_pmu.caps_attrs = intel_pmu_caps_attrs;
4526
4527 if (x86_pmu.lbr_nr) {
4528 x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs);
f09509b9 4529 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
b00233b5
AK		 4530 }
4531
338b522c
KL		 4532 /*
4533 * Access extra MSR may cause #GP under certain circumstances.
4534 * E.g. KVM doesn't support offcore event
4535 * Check all extra_regs here.
4536 */
4537 if (x86_pmu.extra_regs) {
4538 for (er = x86_pmu.extra_regs; er->msr; er++) {
8c4fe709 4539 er->extra_msr_access = check_msr(er->msr, 0x11UL);
338b522c
KL		 4540 /* Disable LBR select mapping */
4541 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
4542 x86_pmu.lbr_sel_map = NULL;
4543 }
4544 }
4545
069e0c3c
AK		 4546 /* Support full width counters using alternative MSR range */
4547 if (x86_pmu.intel_cap.full_width_write) {
7f612a7f 4548 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
069e0c3c
AK		 4549 x86_pmu.perfctr = MSR_IA32_PMC0;
4550 pr_cont("full-width counters, ");
4551 }
4552
af3bdb99
AK		 4553 /*
4554 * For arch perfmon 4 use counter freezing to avoid
4555 * several MSR accesses in the PMI.
4556 */
4557 if (x86_pmu.counter_freezing)
4558 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
4559
7ad1437d 4560 kfree(to_free);
f22f54f4
PZ		 4561 return 0;
4562}
b37609c3
SE		 4563
4564/*
4565 * HT bug: phase 2 init
4566 * Called once we have valid topology information to check
4567 * whether or not HT is enabled
4568 * If HT is off, then we disable the workaround
4569 */
4570static __init int fixup_ht_bug(void)
4571{
030ba6cd 4572 int c;
b37609c3
SE		 4573 /*
4574 * problem not present on this CPU model, nothing to do
4575 */
4576 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
4577 return 0;
4578
030ba6cd 4579 if (topology_max_smt_threads() > 1) {
b37609c3
SE		 4580 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4581 return 0;
4582 }
4583
2406e3b1
PZ		 4584 cpus_read_lock();
4585
4586 hardlockup_detector_perf_stop();
b37609c3
SE		 4587
4588 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
4589
b37609c3 4590 x86_pmu.start_scheduling = NULL;
0c41e756 4591 x86_pmu.commit_scheduling = NULL;
b37609c3
SE		 4592 x86_pmu.stop_scheduling = NULL;
4593
2406e3b1 4594 hardlockup_detector_perf_restart();
b37609c3 4595
1ba143a5 4596 for_each_online_cpu(c)
b37609c3 4597 free_excl_cntrs(c);
b37609c3 4598
1ba143a5 4599 cpus_read_unlock();
b37609c3
SE		 4600 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4601 return 0;
4602}
4603subsys_initcall(fixup_ht_bug)
Empty description
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