[linux.git] / drivers / pci / setup-bus.c

/*
 *	drivers/pci/setup-bus.c
 *
 * Extruded from code written by
 *      Dave Rusling ([email protected])
 *      David Mosberger ([email protected])
 *	David Miller ([email protected])
 *
 * Support routines for initializing a PCI subsystem.
 */

/*
 * Nov 2000, Ivan Kokshaysky <[email protected]>
 *	     PCI-PCI bridges cleanup, sorted resource allocation.
 * Feb 2002, Ivan Kokshaysky <[email protected]>
 *	     Converted to allocation in 3 passes, which gives
 *	     tighter packing. Prefetchable range support.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>


#define DEBUG_CONFIG 1
#if DEBUG_CONFIG
#define DBG(x...)     printk(x)
#else
#define DBG(x...)
#endif

static void pbus_assign_resources_sorted(struct pci_bus *bus)
{
	struct pci_dev *dev;
	struct resource *res;
	struct resource_list head, *list, *tmp;
	int idx;

	head.next = NULL;
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 class = dev->class >> 8;

		/* Don't touch classless devices or host bridges or ioapics.  */
		if (class == PCI_CLASS_NOT_DEFINED ||
		    class == PCI_CLASS_BRIDGE_HOST)
			continue;

		/* Don't touch ioapic devices already enabled by firmware */
		if (class == PCI_CLASS_SYSTEM_PIC) {
			u16 command;
			pci_read_config_word(dev, PCI_COMMAND, &command);
			if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
				continue;
		}

		pdev_sort_resources(dev, &head);
	}

	for (list = head.next; list;) {
		res = list->res;
		idx = res - &list->dev->resource[0];
		if (pci_assign_resource(list->dev, idx)) {
			res->start = 0;
			res->end = 0;
			res->flags = 0;
		}
		tmp = list;
		list = list->next;
		kfree(tmp);
	}
}

void pci_setup_cardbus(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct pci_bus_region region;

	printk("PCI: Bus %d, cardbus bridge: %s\n",
		bus->number, pci_name(bridge));

	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	if (bus->resource[0]->flags & IORESOURCE_IO) {
		/*
		 * The IO resource is allocated a range twice as large as it
		 * would normally need.  This allows us to set both IO regs.
		 */
		printk("  IO window: %08lx-%08lx\n",
			region.start, region.end);
		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	if (bus->resource[1]->flags & IORESOURCE_IO) {
		printk("  IO window: %08lx-%08lx\n",
			region.start, region.end);
		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	if (bus->resource[2]->flags & IORESOURCE_MEM) {
		printk("  PREFETCH window: %08lx-%08lx\n",
			region.start, region.end);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
	if (bus->resource[3]->flags & IORESOURCE_MEM) {
		printk("  MEM window: %08lx-%08lx\n",
			region.start, region.end);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
					region.end);
	}
}
EXPORT_SYMBOL(pci_setup_cardbus);

/* Initialize bridges with base/limit values we have collected.
   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
   requires that if there is no I/O ports or memory behind the
   bridge, corresponding range must be turned off by writing base
   value greater than limit to the bridge's base/limit registers.

   Note: care must be taken when updating I/O base/limit registers
   of bridges which support 32-bit I/O. This update requires two
   config space writes, so it's quite possible that an I/O window of
   the bridge will have some undesirable address (e.g. 0) after the
   first write. Ditto 64-bit prefetchable MMIO.  */
static void __devinit
pci_setup_bridge(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct pci_bus_region region;
	u32 l, io_upper16;

	DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));

	/* Set up the top and bottom of the PCI I/O segment for this bus. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	if (bus->resource[0]->flags & IORESOURCE_IO) {
		pci_read_config_dword(bridge, PCI_IO_BASE, &l);
		l &= 0xffff0000;
		l |= (region.start >> 8) & 0x00f0;
		l |= region.end & 0xf000;
		/* Set up upper 16 bits of I/O base/limit. */
		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
		DBG(KERN_INFO "  IO window: %04lx-%04lx\n",
				region.start, region.end);
	}
	else {
		/* Clear upper 16 bits of I/O base/limit. */
		io_upper16 = 0;
		l = 0x00f0;
		DBG(KERN_INFO "  IO window: disabled.\n");
	}
	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	/* Update lower 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE, l);
	/* Update upper 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);

	/* Set up the top and bottom of the PCI Memory segment
	   for this bus. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	if (bus->resource[1]->flags & IORESOURCE_MEM) {
		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
		DBG(KERN_INFO "  MEM window: %08lx-%08lx\n",
				region.start, region.end);
	}
	else {
		l = 0x0000fff0;
		DBG(KERN_INFO "  MEM window: disabled.\n");
	}
	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);

	/* Clear out the upper 32 bits of PREF limit.
	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	   disables PREF range, which is ok. */
	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);

	/* Set up PREF base/limit. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
		DBG(KERN_INFO "  PREFETCH window: %08lx-%08lx\n",
				region.start, region.end);
	}
	else {
		l = 0x0000fff0;
		DBG(KERN_INFO "  PREFETCH window: disabled.\n");
	}
	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);

	/* Clear out the upper 32 bits of PREF base. */
	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);

	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
}

/* Check whether the bridge supports optional I/O and
   prefetchable memory ranges. If not, the respective
   base/limit registers must be read-only and read as 0. */
static void pci_bridge_check_ranges(struct pci_bus *bus)
{
	u16 io;
	u32 pmem;
	struct pci_dev *bridge = bus->self;
	struct resource *b_res;

	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	b_res[1].flags |= IORESOURCE_MEM;

	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	if (!io) {
		pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
		pci_read_config_word(bridge, PCI_IO_BASE, &io);
 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 	}
 	if (io)
		b_res[0].flags |= IORESOURCE_IO;
	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
	    disconnect boundary by one PCI data phase.
	    Workaround: do not use prefetching on this device. */
	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
		return;
	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	if (!pmem) {
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
					       0xfff0fff0);
		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	}
	if (pmem)
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
}

/* Helper function for sizing routines: find first available
   bus resource of a given type. Note: we intentionally skip
   the bus resources which have already been assigned (that is,
   have non-NULL parent resource). */
static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
{
	int i;
	struct resource *r;
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
		r = bus->resource[i];
		if (r == &ioport_resource || r == &iomem_resource)
			continue;
		if (r && (r->flags & type_mask) == type && !r->parent)
			return r;
	}
	return NULL;
}

/* Sizing the IO windows of the PCI-PCI bridge is trivial,
   since these windows have 4K granularity and the IO ranges
   of non-bridge PCI devices are limited to 256 bytes.
   We must be careful with the ISA aliasing though. */
static void pbus_size_io(struct pci_bus *bus)
{
	struct pci_dev *dev;
	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
	unsigned long size = 0, size1 = 0;

	if (!b_res)
 		return;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			unsigned long r_size;

			if (r->parent || !(r->flags & IORESOURCE_IO))
				continue;
			r_size = r->end - r->start + 1;

			if (r_size < 0x400)
				/* Might be re-aligned for ISA */
				size += r_size;
			else
				size1 += r_size;
		}
	}
/* To be fixed in 2.5: we should have sort of HAVE_ISA
   flag in the struct pci_bus. */
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
	size = (size & 0xff) + ((size & ~0xffUL) << 2);
#endif
	size = ALIGN(size + size1, 4096);
	if (!size) {
		b_res->flags = 0;
		return;
	}
	/* Alignment of the IO window is always 4K */
	b_res->start = 4096;
	b_res->end = b_res->start + size - 1;
}

/* Calculate the size of the bus and minimal alignment which
   guarantees that all child resources fit in this size. */
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
{
	struct pci_dev *dev;
	unsigned long min_align, align, size;
	unsigned long aligns[12];	/* Alignments from 1Mb to 2Gb */
	int order, max_order;
	struct resource *b_res = find_free_bus_resource(bus, type);

	if (!b_res)
		return 0;

	memset(aligns, 0, sizeof(aligns));
	max_order = 0;
	size = 0;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;
		
		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			unsigned long r_size;

			if (r->parent || (r->flags & mask) != type)
				continue;
			r_size = r->end - r->start + 1;
			/* For bridges size != alignment */
			align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
			order = __ffs(align) - 20;
			if (order > 11) {
				printk(KERN_WARNING "PCI: region %s/%d "
				       "too large: %llx-%llx\n",
					pci_name(dev), i,
					(unsigned long long)r->start,
					(unsigned long long)r->end);
				r->flags = 0;
				continue;
			}
			size += r_size;
			if (order < 0)
				order = 0;
			/* Exclude ranges with size > align from
			   calculation of the alignment. */
			if (r_size == align)
				aligns[order] += align;
			if (order > max_order)
				max_order = order;
		}
	}

	align = 0;
	min_align = 0;
	for (order = 0; order <= max_order; order++) {
		unsigned long align1 = 1UL << (order + 20);

		if (!align)
			min_align = align1;
		else if (ALIGN(align + min_align, min_align) < align1)
			min_align = align1 >> 1;
		align += aligns[order];
	}
	size = ALIGN(size, min_align);
	if (!size) {
		b_res->flags = 0;
		return 1;
	}
	b_res->start = min_align;
	b_res->end = size + min_align - 1;
	return 1;
}

static void __devinit
pci_bus_size_cardbus(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	u16 ctrl;

	/*
	 * Reserve some resources for CardBus.  We reserve
	 * a fixed amount of bus space for CardBus bridges.
	 */
	b_res[0].start = pci_cardbus_io_size;
	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
	b_res[0].flags |= IORESOURCE_IO;

	b_res[1].start = pci_cardbus_io_size;
	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
	b_res[1].flags |= IORESOURCE_IO;

	/*
	 * Check whether prefetchable memory is supported
	 * by this bridge.
	 */
	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	}

	/*
	 * If we have prefetchable memory support, allocate
	 * two regions.  Otherwise, allocate one region of
	 * twice the size.
	 */
	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
		b_res[2].start = pci_cardbus_mem_size;
		b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;

		b_res[3].start = pci_cardbus_mem_size;
		b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
		b_res[3].flags |= IORESOURCE_MEM;
	} else {
		b_res[3].start = pci_cardbus_mem_size * 2;
		b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
		b_res[3].flags |= IORESOURCE_MEM;
	}
}

void pci_bus_size_bridges(struct pci_bus *bus)
{
	struct pci_dev *dev;
	unsigned long mask, prefmask;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		struct pci_bus *b = dev->subordinate;
		if (!b)
			continue;

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_bus_size_cardbus(b);
			break;

		case PCI_CLASS_BRIDGE_PCI:
		default:
			pci_bus_size_bridges(b);
			break;
		}
	}

	/* The root bus? */
	if (!bus->self)
		return;

	switch (bus->self->class >> 8) {
	case PCI_CLASS_BRIDGE_CARDBUS:
		/* don't size cardbuses yet. */
		break;

	case PCI_CLASS_BRIDGE_PCI:
		/* don't size subtractive decoding (transparent)
		 * PCI-to-PCI bridges */
		if (bus->self->transparent)
			break;
		pci_bridge_check_ranges(bus);
		/* fall through */
	default:
		pbus_size_io(bus);
		/* If the bridge supports prefetchable range, size it
		   separately. If it doesn't, or its prefetchable window
		   has already been allocated by arch code, try
		   non-prefetchable range for both types of PCI memory
		   resources. */
		mask = IORESOURCE_MEM;
		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
		if (pbus_size_mem(bus, prefmask, prefmask))
			mask = prefmask; /* Success, size non-prefetch only. */
		pbus_size_mem(bus, mask, IORESOURCE_MEM);
		break;
	}
}
EXPORT_SYMBOL(pci_bus_size_bridges);

void pci_bus_assign_resources(struct pci_bus *bus)
{
	struct pci_bus *b;
	struct pci_dev *dev;

	pbus_assign_resources_sorted(bus);

	list_for_each_entry(dev, &bus->devices, bus_list) {
		b = dev->subordinate;
		if (!b)
			continue;

		pci_bus_assign_resources(b);

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_PCI:
			pci_setup_bridge(b);
			break;

		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_setup_cardbus(b);
			break;

		default:
			printk(KERN_INFO "PCI: not setting up bridge %s "
			       "for bus %d\n", pci_name(dev), b->number);
			break;
		}
	}
}
EXPORT_SYMBOL(pci_bus_assign_resources);

void __init
pci_assign_unassigned_resources(void)
{
	struct pci_bus *bus;

	/* Depth first, calculate sizes and alignments of all
	   subordinate buses. */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_size_bridges(bus);
	}
	/* Depth last, allocate resources and update the hardware. */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_assign_resources(bus);
		pci_enable_bridges(bus);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-bus.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling ([email protected])
	6	* David Mosberger ([email protected])
	7	* David Miller ([email protected])
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/*
	13	* Nov 2000, Ivan Kokshaysky <[email protected]>
	14	* PCI-PCI bridges cleanup, sorted resource allocation.
	15	* Feb 2002, Ivan Kokshaysky <[email protected]>
	16	* Converted to allocation in 3 passes, which gives
	17	* tighter packing. Prefetchable range support.
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/errno.h>
	25	#include <linux/ioport.h>
	26	#include <linux/cache.h>
	27	#include <linux/slab.h>
	28
	29
	30	#define DEBUG_CONFIG 1
	31	#if DEBUG_CONFIG
	32	#define DBG(x...) printk(x)
	33	#else
	34	#define DBG(x...)
	35	#endif
	36
96bde06a	37	static void pbus_assign_resources_sorted(struct pci_bus *bus)
1da177e4 LT	38	{
	39	struct pci_dev *dev;
	40	struct resource *res;
	41	struct resource_list head, list, tmp;
	42	int idx;
	43
1da177e4 LT	44	head.next = NULL;
	45	list_for_each_entry(dev, &bus->devices, bus_list) {
	46	u16 class = dev->class >> 8;
	47
9bded00b	48	/* Don't touch classless devices or host bridges or ioapics. */
1da177e4	49	if (class == PCI_CLASS_NOT_DEFINED \|\|
23186279	50	class == PCI_CLASS_BRIDGE_HOST)
1da177e4 LT	51	continue;
1da177e4 LT	52
9bded00b	53	/* Don't touch ioapic devices already enabled by firmware */
23186279	54	if (class == PCI_CLASS_SYSTEM_PIC) {
9bded00b KK	55	u16 command;
	56	pci_read_config_word(dev, PCI_COMMAND, &command);
	57	if (command & (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY))
23186279 ST	58	continue;
	59	}
	60
1da177e4 LT	61	pdev_sort_resources(dev, &head);
	62	}
	63
	64	for (list = head.next; list;) {
	65	res = list->res;
	66	idx = res - &list->dev->resource[0];
542df5de RS	67	if (pci_assign_resource(list->dev, idx)) {
542df5de RS	68	res->start = 0;
960b8466	69	res->end = 0;
542df5de RS	70	res->flags = 0;
542df5de RS	71	}
1da177e4 LT	72	tmp = list;
	73	list = list->next;
	74	kfree(tmp);
	75	}
	76	}
	77
b3743fa4	78	void pci_setup_cardbus(struct pci_bus *bus)
1da177e4 LT	79	{
	80	struct pci_dev *bridge = bus->self;
	81	struct pci_bus_region region;
	82
	83	printk("PCI: Bus %d, cardbus bridge: %s\n",
	84	bus->number, pci_name(bridge));
	85
	86	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	87	if (bus->resource[0]->flags & IORESOURCE_IO) {
	88	/*
	89	* The IO resource is allocated a range twice as large as it
	90	* would normally need. This allows us to set both IO regs.
	91	*/
	92	printk(" IO window: %08lx-%08lx\n",
	93	region.start, region.end);
	94	pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
	95	region.start);
	96	pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
	97	region.end);
	98	}
	99
	100	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	101	if (bus->resource[1]->flags & IORESOURCE_IO) {
	102	printk(" IO window: %08lx-%08lx\n",
	103	region.start, region.end);
	104	pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
	105	region.start);
	106	pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
	107	region.end);
	108	}
	109
	110	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	111	if (bus->resource[2]->flags & IORESOURCE_MEM) {
	112	printk(" PREFETCH window: %08lx-%08lx\n",
	113	region.start, region.end);
	114	pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
	115	region.start);
	116	pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
	117	region.end);
	118	}
	119
	120	pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
	121	if (bus->resource[3]->flags & IORESOURCE_MEM) {
	122	printk(" MEM window: %08lx-%08lx\n",
	123	region.start, region.end);
	124	pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
	125	region.start);
	126	pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
	127	region.end);
	128	}
	129	}
b3743fa4	130	EXPORT_SYMBOL(pci_setup_cardbus);
1da177e4 LT	131
	132	/* Initialize bridges with base/limit values we have collected.
	133	PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
	134	requires that if there is no I/O ports or memory behind the
	135	bridge, corresponding range must be turned off by writing base
	136	value greater than limit to the bridge's base/limit registers.
	137
	138	Note: care must be taken when updating I/O base/limit registers
	139	of bridges which support 32-bit I/O. This update requires two
	140	config space writes, so it's quite possible that an I/O window of
	141	the bridge will have some undesirable address (e.g. 0) after the
	142	first write. Ditto 64-bit prefetchable MMIO. */
	143	static void __devinit
	144	pci_setup_bridge(struct pci_bus *bus)
	145	{
	146	struct pci_dev *bridge = bus->self;
	147	struct pci_bus_region region;
	148	u32 l, io_upper16;
	149
	150	DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
	151
	152	/* Set up the top and bottom of the PCI I/O segment for this bus. */
	153	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	154	if (bus->resource[0]->flags & IORESOURCE_IO) {
	155	pci_read_config_dword(bridge, PCI_IO_BASE, &l);
	156	l &= 0xffff0000;
	157	l \|= (region.start >> 8) & 0x00f0;
	158	l \|= region.end & 0xf000;
	159	/* Set up upper 16 bits of I/O base/limit. */
	160	io_upper16 = (region.end & 0xffff0000) \| (region.start >> 16);
	161	DBG(KERN_INFO " IO window: %04lx-%04lx\n",
	162	region.start, region.end);
	163	}
	164	else {
	165	/* Clear upper 16 bits of I/O base/limit. */
	166	io_upper16 = 0;
	167	l = 0x00f0;
	168	DBG(KERN_INFO " IO window: disabled.\n");
	169	}
	170	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	171	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	172	/* Update lower 16 bits of I/O base/limit. */
	173	pci_write_config_dword(bridge, PCI_IO_BASE, l);
	174	/* Update upper 16 bits of I/O base/limit. */
	175	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
	176
	177	/* Set up the top and bottom of the PCI Memory segment
	178	for this bus. */
	179	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	180	if (bus->resource[1]->flags & IORESOURCE_MEM) {
	181	l = (region.start >> 16) & 0xfff0;
	182	l \|= region.end & 0xfff00000;
	183	DBG(KERN_INFO " MEM window: %08lx-%08lx\n",
	184	region.start, region.end);
	185	}
	186	else {
	187	l = 0x0000fff0;
	188	DBG(KERN_INFO " MEM window: disabled.\n");
	189	}
	190	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
	191
	192	/* Clear out the upper 32 bits of PREF limit.
	193	If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	194	disables PREF range, which is ok. */
195	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
196
197	/* Set up PREF base/limit. */
198	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
199	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
200	l = (region.start >> 16) & 0xfff0;
201	l \|= region.end & 0xfff00000;
202	DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n",
203	region.start, region.end);
204	}
205	else {
206	l = 0x0000fff0;
207	DBG(KERN_INFO " PREFETCH window: disabled.\n");
208	}
209	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
210
211	/* Clear out the upper 32 bits of PREF base. */
212	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
213
214	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
215	}
216
217	/* Check whether the bridge supports optional I/O and
218	prefetchable memory ranges. If not, the respective
219	base/limit registers must be read-only and read as 0. */
96bde06a	220	static void pci_bridge_check_ranges(struct pci_bus *bus)
1da177e4 LT	221	{
	222	u16 io;
	223	u32 pmem;
	224	struct pci_dev *bridge = bus->self;
	225	struct resource *b_res;
	226
	227	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	228	b_res[1].flags \|= IORESOURCE_MEM;
	229
	230	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	231	if (!io) {
	232	pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
	233	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	234	pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
	235	}
	236	if (io)
	237	b_res[0].flags \|= IORESOURCE_IO;
	238	/* DECchip 21050 pass 2 errata: the bridge may miss an address
	239	disconnect boundary by one PCI data phase.
	240	Workaround: do not use prefetching on this device. */
	241	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
	242	return;
	243	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	244	if (!pmem) {
	245	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
	246	0xfff0fff0);
	247	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	248	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	249	}
	250	if (pmem)
	251	b_res[2].flags \|= IORESOURCE_MEM \| IORESOURCE_PREFETCH;
	252	}
	253
	254	/* Helper function for sizing routines: find first available
	255	bus resource of a given type. Note: we intentionally skip
	256	the bus resources which have already been assigned (that is,
	257	have non-NULL parent resource). */
96bde06a	258	static struct resource find_free_bus_resource(struct pci_bus bus, unsigned long type)
1da177e4 LT	259	{
	260	int i;
	261	struct resource *r;
	262	unsigned long type_mask = IORESOURCE_IO \| IORESOURCE_MEM \|
	263	IORESOURCE_PREFETCH;
	264
	265	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
	266	r = bus->resource[i];
299de034 IK	267	if (r == &ioport_resource \|\| r == &iomem_resource)
299de034 IK	268	continue;
1da177e4 LT	269	if (r && (r->flags & type_mask) == type && !r->parent)
	270	return r;
	271	}
	272	return NULL;
	273	}
	274
	275	/* Sizing the IO windows of the PCI-PCI bridge is trivial,
	276	since these windows have 4K granularity and the IO ranges
	277	of non-bridge PCI devices are limited to 256 bytes.
	278	We must be careful with the ISA aliasing though. */
96bde06a	279	static void pbus_size_io(struct pci_bus *bus)
1da177e4 LT	280	{
	281	struct pci_dev *dev;
	282	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
	283	unsigned long size = 0, size1 = 0;
	284
	285	if (!b_res)
	286	return;
	287
	288	list_for_each_entry(dev, &bus->devices, bus_list) {
	289	int i;
	290
	291	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	292	struct resource *r = &dev->resource[i];
	293	unsigned long r_size;
	294
	295	if (r->parent \|\| !(r->flags & IORESOURCE_IO))
	296	continue;
	297	r_size = r->end - r->start + 1;
	298
	299	if (r_size < 0x400)
	300	/* Might be re-aligned for ISA */
	301	size += r_size;
	302	else
	303	size1 += r_size;
	304	}
	305	}
	306	/* To be fixed in 2.5: we should have sort of HAVE_ISA
	307	flag in the struct pci_bus. */
	308	#if defined(CONFIG_ISA) \|\| defined(CONFIG_EISA)
	309	size = (size & 0xff) + ((size & ~0xffUL) << 2);
	310	#endif
6f6f8c2f	311	size = ALIGN(size + size1, 4096);
1da177e4 LT	312	if (!size) {
	313	b_res->flags = 0;
	314	return;
	315	}
	316	/* Alignment of the IO window is always 4K */
	317	b_res->start = 4096;
	318	b_res->end = b_res->start + size - 1;
	319	}
	320
	321	/* Calculate the size of the bus and minimal alignment which
	322	guarantees that all child resources fit in this size. */
96bde06a	323	static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
1da177e4 LT	324	{
	325	struct pci_dev *dev;
	326	unsigned long min_align, align, size;
	327	unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
	328	int order, max_order;
	329	struct resource *b_res = find_free_bus_resource(bus, type);
	330
	331	if (!b_res)
	332	return 0;
	333
	334	memset(aligns, 0, sizeof(aligns));
	335	max_order = 0;
	336	size = 0;
	337
	338	list_for_each_entry(dev, &bus->devices, bus_list) {
	339	int i;
	340
	341	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	342	struct resource *r = &dev->resource[i];
	343	unsigned long r_size;
	344
	345	if (r->parent \|\| (r->flags & mask) != type)
	346	continue;
	347	r_size = r->end - r->start + 1;
	348	/* For bridges size != alignment */
	349	align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
	350	order = __ffs(align) - 20;
	351	if (order > 11) {
	352	printk(KERN_WARNING "PCI: region %s/%d "
1396a8c3 GKH	353	"too large: %llx-%llx\n",
	354	pci_name(dev), i,
	355	(unsigned long long)r->start,
	356	(unsigned long long)r->end);
1da177e4 LT	357	r->flags = 0;
	358	continue;
	359	}
	360	size += r_size;
	361	if (order < 0)
	362	order = 0;
	363	/* Exclude ranges with size > align from
	364	calculation of the alignment. */
	365	if (r_size == align)
	366	aligns[order] += align;
	367	if (order > max_order)
	368	max_order = order;
	369	}
	370	}
	371
	372	align = 0;
	373	min_align = 0;
	374	for (order = 0; order <= max_order; order++) {
	375	unsigned long align1 = 1UL << (order + 20);
	376
	377	if (!align)
	378	min_align = align1;
6f6f8c2f	379	else if (ALIGN(align + min_align, min_align) < align1)
1da177e4 LT	380	min_align = align1 >> 1;
	381	align += aligns[order];
	382	}
6f6f8c2f	383	size = ALIGN(size, min_align);
1da177e4 LT	384	if (!size) {
	385	b_res->flags = 0;
	386	return 1;
	387	}
	388	b_res->start = min_align;
	389	b_res->end = size + min_align - 1;
	390	return 1;
	391	}
	392
	393	static void __devinit
	394	pci_bus_size_cardbus(struct pci_bus *bus)
	395	{
	396	struct pci_dev *bridge = bus->self;
	397	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	398	u16 ctrl;
	399
	400	/*
	401	* Reserve some resources for CardBus. We reserve
	402	* a fixed amount of bus space for CardBus bridges.
	403	*/
4516a618 AN	404	b_res[0].start = pci_cardbus_io_size;
4516a618 AN	405	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1da177e4 LT	406	b_res[0].flags \|= IORESOURCE_IO;
1da177e4 LT	407
4516a618 AN	408	b_res[1].start = pci_cardbus_io_size;
4516a618 AN	409	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1da177e4 LT	410	b_res[1].flags \|= IORESOURCE_IO;
	411
	412	/*
	413	* Check whether prefetchable memory is supported
	414	* by this bridge.
	415	*/
	416	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	417	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
	418	ctrl \|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
	419	pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
	420	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	421	}
	422
	423	/*
	424	* If we have prefetchable memory support, allocate
	425	* two regions. Otherwise, allocate one region of
	426	* twice the size.
	427	*/
	428	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
4516a618 AN	429	b_res[2].start = pci_cardbus_mem_size;
4516a618 AN	430	b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1da177e4 LT	431	b_res[2].flags \|= IORESOURCE_MEM \| IORESOURCE_PREFETCH;
1da177e4 LT	432
4516a618 AN	433	b_res[3].start = pci_cardbus_mem_size;
4516a618 AN	434	b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
1da177e4 LT	435	b_res[3].flags \|= IORESOURCE_MEM;
1da177e4 LT	436	} else {
4516a618 AN	437	b_res[3].start = pci_cardbus_mem_size * 2;
4516a618 AN	438	b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
1da177e4 LT	439	b_res[3].flags \|= IORESOURCE_MEM;
	440	}
	441	}
	442
96bde06a	443	void pci_bus_size_bridges(struct pci_bus *bus)
1da177e4 LT	444	{
	445	struct pci_dev *dev;
	446	unsigned long mask, prefmask;
	447
	448	list_for_each_entry(dev, &bus->devices, bus_list) {
	449	struct pci_bus *b = dev->subordinate;
	450	if (!b)
	451	continue;
	452
	453	switch (dev->class >> 8) {
	454	case PCI_CLASS_BRIDGE_CARDBUS:
	455	pci_bus_size_cardbus(b);
	456	break;
	457
	458	case PCI_CLASS_BRIDGE_PCI:
	459	default:
	460	pci_bus_size_bridges(b);
	461	break;
	462	}
	463	}
	464
	465	/* The root bus? */
	466	if (!bus->self)
	467	return;
	468
	469	switch (bus->self->class >> 8) {
	470	case PCI_CLASS_BRIDGE_CARDBUS:
	471	/* don't size cardbuses yet. */
	472	break;
	473
	474	case PCI_CLASS_BRIDGE_PCI:
8fa5913d GH	475	/* don't size subtractive decoding (transparent)
	476	* PCI-to-PCI bridges */
	477	if (bus->self->transparent)
	478	break;
1da177e4	479	pci_bridge_check_ranges(bus);
8fa5913d	480	/* fall through */
1da177e4 LT	481	default:
	482	pbus_size_io(bus);
	483	/* If the bridge supports prefetchable range, size it
	484	separately. If it doesn't, or its prefetchable window
	485	has already been allocated by arch code, try
	486	non-prefetchable range for both types of PCI memory
	487	resources. */
	488	mask = IORESOURCE_MEM;
	489	prefmask = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
	490	if (pbus_size_mem(bus, prefmask, prefmask))
	491	mask = prefmask; /* Success, size non-prefetch only. */
	492	pbus_size_mem(bus, mask, IORESOURCE_MEM);
	493	break;
	494	}
	495	}
	496	EXPORT_SYMBOL(pci_bus_size_bridges);
	497
96bde06a	498	void pci_bus_assign_resources(struct pci_bus *bus)
1da177e4 LT	499	{
	500	struct pci_bus *b;
	501	struct pci_dev *dev;
	502
	503	pbus_assign_resources_sorted(bus);
	504
1da177e4 LT	505	list_for_each_entry(dev, &bus->devices, bus_list) {
	506	b = dev->subordinate;
	507	if (!b)
	508	continue;
	509
	510	pci_bus_assign_resources(b);
	511
	512	switch (dev->class >> 8) {
	513	case PCI_CLASS_BRIDGE_PCI:
	514	pci_setup_bridge(b);
	515	break;
	516
	517	case PCI_CLASS_BRIDGE_CARDBUS:
	518	pci_setup_cardbus(b);
	519	break;
	520
	521	default:
	522	printk(KERN_INFO "PCI: not setting up bridge %s "
	523	"for bus %d\n", pci_name(dev), b->number);
	524	break;
	525	}
	526	}
	527	}
	528	EXPORT_SYMBOL(pci_bus_assign_resources);
	529
	530	void __init
	531	pci_assign_unassigned_resources(void)
	532	{
	533	struct pci_bus *bus;
	534
	535	/* Depth first, calculate sizes and alignments of all
	536	subordinate buses. */
	537	list_for_each_entry(bus, &pci_root_buses, node) {
	538	pci_bus_size_bridges(bus);
	539	}
	540	/* Depth last, allocate resources and update the hardware. */
	541	list_for_each_entry(bus, &pci_root_buses, node) {
	542	pci_bus_assign_resources(bus);
	543	pci_enable_bridges(bus);
	544	}
	545	}